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[AArch64][SVE] Instcombine SDIV to ASRD
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Authored by MattDevereau on Dec 9 2021, 7:39 AM.

Details

Summary

Instcombine SDIV to ASRD when the third operand of SDIV is a power of 2

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Event Timeline

MattDevereau created this revision.Dec 9 2021, 7:39 AM
MattDevereau requested review of this revision.Dec 9 2021, 7:39 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 9 2021, 7:39 AM

rename intr -> ASRD

To match the equivalent functionality in D113281, can you also add support for signed divides by negative powers or two?

peterwaller-arm added inline comments.Dec 9 2021, 8:06 AM
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
1025

nit. I think the name 'instCombineSVESDiv' would be in keeping with the other functions in this file.

1038

nit. Extraneous blank.

1047

nit. Suggest extracting the constant as its own variable to make 'CreateIntrinsic' a bit tidier.

MattDevereau marked 3 inline comments as done.

Added negation of ASRD if the splat exponent is negative

Force int32 type and add i64 tests

peterwaller-arm accepted this revision.Dec 13 2021, 7:16 AM

LGTM with a nit.

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
1040

I think this would be better called Divisor.

This revision is now accepted and ready to land.Dec 13 2021, 7:16 AM

Just a couple of things to consider before committing.

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
1034–1035

FYI: If you use dyn_cast_or_null<ConstantInt>(SplatValue) you can remove this extra check.

1044

You shouldn't need this as the exponent cannot be negative and the intrinsic it's passed to (aarch64_sve_asrd) does not support this operand being negative either.

1052

As above.

This revision was landed with ongoing or failed builds.Dec 14 2021, 7:58 AM
This revision was automatically updated to reflect the committed changes.