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[PowerPC] Fix 32bit vector insert instructions for ISA3.1

Authored by lei on Nov 12 2021, 1:17 PM.



The platform independent ISD::INSERT_VECTOR_ELT take a element index,
but vins* instructions take a byte index. Update 32bit td patterns for
vector insert to handle the element index accordingly.

Since vector insert for non constant index are supported in
ISA3.1, there is no need to use platform specific ISD node,
PPCISD::VECINSERT. Update td pattern to directly use

Diff Detail

Event Timeline

lei created this revision.Nov 12 2021, 1:17 PM
lei requested review of this revision.Nov 12 2021, 1:17 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 12 2021, 1:17 PM
jsji added a reviewer: Restricted Project.Nov 12 2021, 1:39 PM

Please rebase. Does not apply cleanly to ToT.


s/integer vectors and float vectors/all vectors

nemanjai accepted this revision.Nov 15 2021, 5:59 AM

LGTM other than minor nits.


Why did you pull this out of the block above? The Predicates seem to be exactly the same.

This revision is now accepted and ready to land.Nov 15 2021, 5:59 AM
lei added inline comments.Nov 15 2021, 9:20 AM

It's because of the complexity. For vector insert double, the original pattern generated:

lfd f0, 0(r5)
xxmrghd v2, v2, vs0

seem to be better then forcing it to use VINSDRX

ld r3, 0(r5)
li r4, 0
vinsdrx v2, r4, r3
nemanjai added inline comments.Nov 15 2021, 9:27 AM

I realize that we want to add the AddedComplexity but that should be orthogonal to Predicates


let Predicates = [IsISA3_1, HasVSX, IsLittleEndian] in {
  // defs
  let AddedComplexity = 400 in {
    // defs with the same predicates plus added complexity
lei added inline comments.Nov 15 2021, 10:10 AM

You are right, I don't know why I thought it needed to be separate! Will update that before commit!

lei updated this revision to Diff 387320.Nov 15 2021, 10:31 AM

address review comments

This revision was automatically updated to reflect the committed changes.