[AMDGPU] Use shift for b64 mov

[sebastian-ne]

Summary

There is no v_mov_b64, but a v_lshlrev_b64 can accomplish the same by
shifting a 64-bit register by 0.

[foad]

Interesting. I see you're doing this when expanding V_MOV_B64_PSEUDO, but I don't really understand when we use V_MOV_B64_PSEUDO in the first place. copyPhysReg() does not generate it, instead it copies the logic from here to emit V_PK_MOV_B32. So does that mean you need to add your V_LSHLREV_B64_e64 code to copyPhysReg too?

[arsenm]

64-bit shifts were quarter rate instructions last I checked, so this is slower

[foad]

In D113778#3127658, @arsenm wrote:

64-bit shifts were quarter rate instructions last I checked, so this is slower

The Write64Bit definitions in SISchedule.td suggest they are half rate on most subtargets and full rate on gfx90a.

[arsenm]

In D113778#3127670, @foad wrote:

In D113778#3127658, @arsenm wrote:

64-bit shifts were quarter rate instructions last I checked, so this is slower

The Write64Bit definitions in SISchedule.td suggest they are half rate on most subtargets and full rate on gfx90a.

I think that's probably wrong. Comments in performShlCombine for example say it's quarter rate

[sebastian-ne]

In D113778#3127676, @arsenm wrote:

In D113778#3127670, @foad wrote:

In D113778#3127658, @arsenm wrote:

64-bit shifts were quarter rate instructions last I checked, so this is slower

The Write64Bit definitions in SISchedule.td suggest they are half rate on most subtargets and full rate on gfx90a.

I think that's probably wrong. Comments in performShlCombine for example say it's quarter rate

It seems to be quarter rate (or something slow) on gfx9, full rate on gfx90a and half rate on gfx10?
Then it would be worth using on gfx90a and gfx10+.

[rampitec]

In D113778#3127677, @sebastian-ne wrote:

In D113778#3127676, @arsenm wrote:

In D113778#3127670, @foad wrote:

In D113778#3127658, @arsenm wrote:

64-bit shifts were quarter rate instructions last I checked, so this is slower

The Write64Bit definitions in SISchedule.td suggest they are half rate on most subtargets and full rate on gfx90a.

I think that's probably wrong. Comments in performShlCombine for example say it's quarter rate

It seems to be quarter rate (or something slow) on gfx9, full rate on gfx90a and half rate on gfx10?
Then it would be worth using on gfx90a and gfx10+.

You do not need this on gfx90a because there is pk_mov. It is arguably the same performance as 2 moves on gfx10.

[rampitec]

In D113778#3127656, @foad wrote:

Interesting. I see you're doing this when expanding V_MOV_B64_PSEUDO, but I don't really understand when we use V_MOV_B64_PSEUDO in the first place. copyPhysReg() does not generate it, instead it copies the logic from here to emit V_PK_MOV_B32. So does that mean you need to add your V_LSHLREV_B64_e64 code to copyPhysReg too?

Pseudo was created to deal with 64 bit immediates and fold these. It is not needed that late.

[critson]

For GFX10, I don't think this is worth doing unless V_LSHLREV_B64 is full rate.
2x V_MOV_B32 in VOP1 takes the same space as V_LSHLREV_B64 in VOP3.

[rampitec]

In D113778#3130490, @critson wrote:

For GFX10, I don't think this is worth doing unless V_LSHLREV_B64 is full rate.
2x V_MOV_B32 in VOP1 takes the same space as V_LSHLREV_B64 in VOP3.

I think this is right. It can also be scheduled apart leaving room for something else to be scheduled in between. A 64 bit shift is rarely beneficial in general if you can get away without it.

[sebastian-ne]

Those are good arguments, thanks for your thoughts.

llvm/lib/Target/AMDGPU/GCNSubtarget.h

public:
   bool hasImageStoreD16Bug() const { return HasImageStoreD16Bug; }
 
   bool hasImageGather4D16Bug() const { return HasImageGather4D16Bug; }
 
   bool hasNSAEncoding() const { return HasNSAEncoding; }
 
   unsigned getNSAMaxSize() const { return NSAMaxSize; }
 
+  bool hasGFX8Insts() const { return GFX8Insts; }
+
   bool hasGFX10_AEncoding() const {
     return GFX10_AEncoding;
   }
 
   bool hasGFX10_BEncoding() const {
     return GFX10_BEncoding;
   }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

if (SrcOp.isImm()) {
           .addReg(SrcOp.getReg())
           .addImm(SISrcMods::OP_SEL_0 | SISrcMods::OP_SEL_1) // src1_mod
           .addReg(SrcOp.getReg())
           .addImm(0)  // op_sel_lo
           .addImm(0)  // op_sel_hi
           .addImm(0)  // neg_lo
           .addImm(0)  // neg_hi
           .addImm(0); // clamp
+      } else if (ST.hasGFX8Insts()) {
+        BuildMI(MBB, MI, DL, get(AMDGPU::V_LSHLREV_B64_e64), Dst)
+            .addImm(0) // shift width
+            .addReg(SrcOp.getReg());
       } else {
         BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
           .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
           .addReg(Dst, RegState::Implicit | RegState::Define);
         BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
           .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
           .addReg(Dst, RegState::Implicit | RegState::Define);
       }

llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir

 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX900 %s
 # RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass postrapseudos -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX90A %s
 
 # GCN-LABEL: name: v_mov_b64_from_vgpr
-# GFX900: $vgpr0 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1
-# GFX900: $vgpr1 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1
+# GFX900: $vgpr0_vgpr1 = V_LSHLREV_B64_e64 0, $vgpr2_vgpr3, implicit $exec
 # GFX90A: $vgpr0_vgpr1 = V_PK_MOV_B32 8, $vgpr2_vgpr3, 12, $vgpr2_vgpr3, 0, 0, 0, 0, 0, implicit $exec
 name: v_mov_b64_from_vgpr
 body: |
   bb.0:
     $vgpr0_vgpr1 = V_MOV_B64_PSEUDO $vgpr2_vgpr3, implicit $exec
 ...
 
 # GCN-LABEL: name: v_mov_b64_from_sgpr
-# GFX900: $vgpr0 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit-def $vgpr0_vgpr1
-# GFX900: $vgpr1 = V_MOV_B32_e32 $sgpr3, implicit $exec, implicit-def $vgpr0_vgpr1
+# GFX900: $vgpr0_vgpr1 = V_LSHLREV_B64_e64 0, $sgpr2_sgpr3, implicit $exec
 # GFX90A: $vgpr0_vgpr1 = V_PK_MOV_B32 8, $sgpr2_sgpr3, 12, $sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec
 name: v_mov_b64_from_sgpr
 body: |
   bb.0:
     $vgpr0_vgpr1 = V_MOV_B64_PSEUDO $sgpr2_sgpr3, implicit $exec
 ...
 
 # GCN-LABEL: name: v_mov_b64_from_sext_inline_imm

llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

 ; GFX9-O0-NEXT:    s_mov_b32 s35, s9
 ; GFX9-O0-NEXT:    ; kill: def $sgpr30_sgpr31 killed $sgpr34_sgpr35
 ; GFX9-O0-NEXT:    s_mov_b64 s[30:31], 0
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v0, s34
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v1, s35
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v10, v1
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v9, v0
 ; GFX9-O0-NEXT:    s_not_b64 exec, exec
-; GFX9-O0-NEXT:    v_mov_b32_e32 v9, s30
-; GFX9-O0-NEXT:    v_mov_b32_e32 v10, s31
+; GFX9-O0-NEXT:    v_lshlrev_b64 v[9:10], 0, s[30:31]
 ; GFX9-O0-NEXT:    s_not_b64 exec, exec
 ; GFX9-O0-NEXT:    s_or_saveexec_b64 s[30:31], -1
 ; GFX9-O0-NEXT:    v_writelane_b32 v11, s30, 6
 ; GFX9-O0-NEXT:    v_writelane_b32 v11, s31, 7
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v2, v9
 ; GFX9-O0-NEXT:    s_mov_b32 s30, 32
 ; GFX9-O0-NEXT:    ; implicit-def: $sgpr34_sgpr35
 ; GFX9-O0-NEXT:    v_lshrrev_b64 v[3:4], s30, v[9:10]

 ; GFX9-O0-NEXT:    v_readlane_b32 s31, v11, 1
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v3, v1
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v4, v9
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v5, v10
 ; GFX9-O0-NEXT:    v_add_co_u32_e64 v2, s[40:41], v2, v4
 ; GFX9-O0-NEXT:    v_addc_co_u32_e64 v3, s[40:41], v3, v5, s[40:41]
 ; GFX9-O0-NEXT:    s_mov_b64 exec, s[34:35]
-; GFX9-O0-NEXT:    v_mov_b32_e32 v0, v2
-; GFX9-O0-NEXT:    v_mov_b32_e32 v1, v3
+; GFX9-O0-NEXT:    v_lshlrev_b64 v[0:1], 0, v[2:3]
 ; GFX9-O0-NEXT:    s_mov_b32 s34, 0
 ; GFX9-O0-NEXT:    buffer_store_dwordx2 v[0:1], off, s[36:39], s34 offset:4
 ; GFX9-O0-NEXT:    s_add_i32 s32, s32, 0xfffff400
 ; GFX9-O0-NEXT:    v_readlane_b32 s33, v11, 8
 ; GFX9-O0-NEXT:    s_or_saveexec_b64 s[34:35], -1
 ; GFX9-O0-NEXT:    buffer_load_dword v11, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
 ; GFX9-O0-NEXT:    s_nop 0
 ; GFX9-O0-NEXT:    buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload

 ; GFX9-O3-NEXT:    v_mov_b32_e32 v1, v7
 ; GFX9-O3-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-O3-NEXT:    s_swappc_b64 s[30:31], s[30:31]
 ; GFX9-O3-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-O3-NEXT:    v_mov_b32_e32 v3, v1
 ; GFX9-O3-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v6
 ; GFX9-O3-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v7, vcc
 ; GFX9-O3-NEXT:    s_mov_b64 exec, s[34:35]
-; GFX9-O3-NEXT:    v_mov_b32_e32 v0, v2
-; GFX9-O3-NEXT:    v_mov_b32_e32 v1, v3
-; GFX9-O3-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0 offset:4
+; GFX9-O3-NEXT:    v_lshlrev_b64 v[0:1], 0, v[2:3]
 ; GFX9-O3-NEXT:    s_addk_i32 s32, 0xf800
+; GFX9-O3-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0 offset:4
 ; GFX9-O3-NEXT:    s_mov_b32 s33, s38
 ; GFX9-O3-NEXT:    s_or_saveexec_b64 s[30:31], -1
 ; GFX9-O3-NEXT:    buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
 ; GFX9-O3-NEXT:    s_nop 0
 ; GFX9-O3-NEXT:    buffer_load_dword v7, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
 ; GFX9-O3-NEXT:    s_nop 0
 ; GFX9-O3-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
 ; GFX9-O3-NEXT:    buffer_load_dword v3, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload

 ; GFX9-O0-NEXT:    v_mov_b32_e32 v6, v7
 ; GFX9-O0-NEXT:    s_mov_b32 s35, 0x7fffffff
 ; GFX9-O0-NEXT:    s_mov_b32 s40, -1
 ; GFX9-O0-NEXT:    ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41
 ; GFX9-O0-NEXT:    s_mov_b32 s41, s35
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v1, v5
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v2, v6
 ; GFX9-O0-NEXT:    s_not_b64 exec, exec
-; GFX9-O0-NEXT:    v_mov_b32_e32 v1, s40
-; GFX9-O0-NEXT:    v_mov_b32_e32 v2, s41
+; GFX9-O0-NEXT:    v_lshlrev_b64 v[1:2], 0, s[40:41]
 ; GFX9-O0-NEXT:    s_not_b64 exec, exec
-; GFX9-O0-NEXT:    v_mov_b32_e32 v8, v1
-; GFX9-O0-NEXT:    v_mov_b32_e32 v9, v2
+; GFX9-O0-NEXT:    v_lshlrev_b64 v[8:9], 0, v[1:2]
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v7, v13
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v5, v12
 ; GFX9-O0-NEXT:    ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v6, v7
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v1, v5
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v2, v6
 ; GFX9-O0-NEXT:    s_not_b64 exec, exec
-; GFX9-O0-NEXT:    v_mov_b32_e32 v1, s40
-; GFX9-O0-NEXT:    v_mov_b32_e32 v2, s41
+; GFX9-O0-NEXT:    v_lshlrev_b64 v[1:2], 0, s[40:41]
 ; GFX9-O0-NEXT:    s_not_b64 exec, exec
-; GFX9-O0-NEXT:    v_mov_b32_e32 v6, v1
-; GFX9-O0-NEXT:    v_mov_b32_e32 v7, v2
+; GFX9-O0-NEXT:    v_lshlrev_b64 v[6:7], 0, v[1:2]
 ; GFX9-O0-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v1, v3
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v2, v4
 ; GFX9-O0-NEXT:    s_not_b64 exec, exec
-; GFX9-O0-NEXT:    v_mov_b32_e32 v1, s40
-; GFX9-O0-NEXT:    v_mov_b32_e32 v2, s41
+; GFX9-O0-NEXT:    v_lshlrev_b64 v[1:2], 0, s[40:41]
 ; GFX9-O0-NEXT:    s_not_b64 exec, exec
-; GFX9-O0-NEXT:    v_mov_b32_e32 v3, v1
-; GFX9-O0-NEXT:    v_mov_b32_e32 v4, v2
+; GFX9-O0-NEXT:    v_lshlrev_b64 v[3:4], 0, v[1:2]
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v11, v9
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v5, v8
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v9, v7
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v10, v6
 ; GFX9-O0-NEXT:    ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6_vgpr7_vgpr8 killed $exec
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v6, v11
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v7, v10
 ; GFX9-O0-NEXT:    v_mov_b32_e32 v8, v9

 ; GFX9-O3-NEXT:    s_mov_b64 exec, s[34:35]
 ; GFX9-O3-NEXT:    v_lshlrev_b32_e32 v0, 5, v0
 ; GFX9-O3-NEXT:    buffer_load_dwordx4 v[1:4], v0, s[4:7], 0 offen
 ; GFX9-O3-NEXT:    buffer_load_dwordx2 v[5:6], v0, s[4:7], 0 offen offset:16
 ; GFX9-O3-NEXT:    s_mov_b32 s34, -1
 ; GFX9-O3-NEXT:    s_brev_b32 s35, -2
 ; GFX9-O3-NEXT:    s_not_b64 exec, exec
 ; GFX9-O3-NEXT:    s_waitcnt vmcnt(1)
-; GFX9-O3-NEXT:    v_mov_b32_e32 v1, s34
-; GFX9-O3-NEXT:    v_mov_b32_e32 v2, s35
+; GFX9-O3-NEXT:    v_lshlrev_b64 v[1:2], 0, s[34:35]
 ; GFX9-O3-NEXT:    s_not_b64 exec, exec
 ; GFX9-O3-NEXT:    s_not_b64 exec, exec
-; GFX9-O3-NEXT:    v_mov_b32_e32 v3, s34
-; GFX9-O3-NEXT:    v_mov_b32_e32 v4, s35
+; GFX9-O3-NEXT:    v_lshlrev_b64 v[3:4], 0, s[34:35]
 ; GFX9-O3-NEXT:    s_not_b64 exec, exec
 ; GFX9-O3-NEXT:    s_not_b64 exec, exec
 ; GFX9-O3-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-O3-NEXT:    v_mov_b32_e32 v5, s34
-; GFX9-O3-NEXT:    v_mov_b32_e32 v6, s35
+; GFX9-O3-NEXT:    v_lshlrev_b64 v[5:6], 0, s[34:35]
 ; GFX9-O3-NEXT:    s_not_b64 exec, exec
-; GFX9-O3-NEXT:    v_mov_b32_e32 v7, v1
-; GFX9-O3-NEXT:    v_mov_b32_e32 v9, v3
-; GFX9-O3-NEXT:    v_mov_b32_e32 v8, v2
-; GFX9-O3-NEXT:    v_mov_b32_e32 v10, v4
-; GFX9-O3-NEXT:    v_mov_b32_e32 v11, v5
-; GFX9-O3-NEXT:    v_mov_b32_e32 v12, v6
+; GFX9-O3-NEXT:    v_lshlrev_b64 v[7:8], 0, v[1:2]
+; GFX9-O3-NEXT:    v_lshlrev_b64 v[9:10], 0, v[3:4]
+; GFX9-O3-NEXT:    v_lshlrev_b64 v[11:12], 0, v[5:6]
 ; GFX9-O3-NEXT:    buffer_store_dwordx4 v[7:10], v0, s[4:7], 0 offen
 ; GFX9-O3-NEXT:    buffer_store_dwordx2 v[11:12], v0, s[4:7], 0 offen offset:16
 ; GFX9-O3-NEXT:    s_or_saveexec_b64 s[34:35], -1
 ; GFX9-O3-NEXT:    buffer_load_dword v1, off, s[0:3], s32 ; 4-byte Folded Reload
 ; GFX9-O3-NEXT:    s_nop 0
 ; GFX9-O3-NEXT:    buffer_load_dword v2, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
 ; GFX9-O3-NEXT:    s_nop 0
 ; GFX9-O3-NEXT:    buffer_load_dword v3, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload

llvm/test/CodeGen/AMDGPU/wwm-reserved.ll

define i64 @called_i64(i64 %a) noinline {
   %sub = sub i64 %mul, %add
   ret i64 %sub
 }
 
 ; GFX9-LABEL: {{^}}call_i64:
 define amdgpu_kernel void @call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) {
 ; GFX9: s_load_dwordx2 s{{\[}}[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]{{\]}}
 
-; GFX9-O0: s_mov_b64 s{{\[}}[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]{{\]}}, 0{{$}}
+; GFX9-O0: s_mov_b64 s[[ZERO:\[[0-9:]+\]]], 0{{$}}
 ; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]]
 ; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]]
 ; GFX9-O0-DAG: v_mov_b32_e32 v10, v1
 ; GFX9-O0-DAG: v_mov_b32_e32 v9, v0
 
 ; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]]
 ; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]]
 
 ; GFX9: s_not_b64 exec, exec
-; GFX9-O0-NEXT: v_mov_b32_e32 v9, s[[ZERO_LO]]
-; GFX9-O0-NEXT: v_mov_b32_e32 v10, s[[ZERO_HI]]
+; GFX9-O0-NEXT: v_lshlrev_b64 v[9:10], 0, s[[ZERO]]
 ; GFX9-O3-NEXT: v_mov_b32_e32 v6, 0
 ; GFX9-O3-NEXT: v_mov_b32_e32 v7, 0
 ; GFX9-NEXT: s_not_b64 exec, exec
   %tmp107 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %arg, i64 0)
 ; GFX9: s_swappc_b64
   %tmp134 = call i64 @called_i64(i64 %tmp107)
   %tmp136 = add i64 %tmp134, %tmp107
   %tmp137 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp136)
define i64 @strict_wwm_called_i64(i64 %a) noinline {
   %sub = sub i64 %mul, %add
   ret i64 %sub
 }
 
 ; GFX9-LABEL: {{^}}strict_wwm_call_i64:
 define amdgpu_kernel void @strict_wwm_call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) {
 ; GFX9: s_load_dwordx2 s{{\[}}[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]{{\]}}
 
-; GFX9-O0: s_mov_b64 s{{\[}}[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]{{\]}}, 0{{$}}
+; GFX9-O0: s_mov_b64 s[[ZERO:\[[0-9:]+\]]], 0{{$}}
 ; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]]
 ; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]]
 ; GFX9-O0-DAG: v_mov_b32_e32 v10, v1
 ; GFX9-O0-DAG: v_mov_b32_e32 v9, v0
 
 ; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]]
 ; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]]
 
 ; GFX9: s_not_b64 exec, exec
-; GFX9-O0-NEXT: v_mov_b32_e32 v9, s[[ZERO_LO]]
-; GFX9-O0-NEXT: v_mov_b32_e32 v10, s[[ZERO_HI]]
+; GFX9-O0-NEXT: v_lshlrev_b64 v[9:10], 0, s[[ZERO]]
 ; GFX9-O3-NEXT: v_mov_b32_e32 v6, 0
 ; GFX9-O3-NEXT: v_mov_b32_e32 v7, 0
 ; GFX9-NEXT: s_not_b64 exec, exec
   %tmp107 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %arg, i64 0)
 ; GFX9: s_swappc_b64
   %tmp134 = call i64 @strict_wwm_called_i64(i64 %tmp107)
   %tmp136 = add i64 %tmp134, %tmp107
   %tmp137 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp136)