[TwoAddressInstructionPass] Update existing physreg live intervals

[foad]

Summary

In TwoAddressInstructionPass::processTiedPairs with
-early-live-intervals, update any preexisting physreg live intervals,
as well as virtreg live intervals. By default (without
-precompute-phys-liveness) physreg live intervals only exist for
registers that are live-in to some basic block.

[foad]

Fix was pushed prematurely by mistake, so I reverted it.

[arsenm]

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

1555–1557

Having to repeat the code everywhere for virtual and physregs is pretty annoying

llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

#endif
     MachineBasicBlock::iterator PrevMI = MI;
     --PrevMI;
     DistanceMap.insert(std::make_pair(&*PrevMI, Dist));
     DistanceMap[MI] = ++Dist;
 
     if (LIS) {
       LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
 
+      SlotIndex endIdx =
+          LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
       if (RegA.isVirtual()) {
         LiveInterval &LI = LIS->getInterval(RegA);
         VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
-        SlotIndex endIdx =
-            LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
-        LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
+        LI.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));
         for (auto &S : LI.subranges()) {
           VNI = S.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
-          S.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
+          S.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));
+        }
+      } else {
+        for (MCRegUnitIterator Unit(RegA, TRI); Unit.isValid(); ++Unit) {
+          if (LiveRange *LR = LIS->getCachedRegUnit(*Unit)) {
+            VNInfo *VNI =
+                LR->getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
+            LR->addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));
+          }
         }
       }
     }
 
     LLVM_DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
 
     MachineOperand &MO = MI->getOperand(SrcIdx);
     assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&

llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll

 ; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s
+; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 -early-live-intervals < %s | FileCheck %s
 
 %struct.twofloat = type { float, float }
 %struct.twodouble = type { double, double }
 
 ; Check support for returning a float in GPR with soft float ABI
 define arm_aapcscc float @zerobits_float_soft() #0 {
 ; CHECK-LABEL: zerobits_float_soft
 ; CHECK: mov r0, #0

llvm/test/CodeGen/Thumb/emergency-spill-slot.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s | FileCheck %s
+; RUN: llc -early-live-intervals < %s | FileCheck %s
 target triple = "thumbv6m-unknown-unknown-eabi"
 
 define void @vla_emergency_spill(i32 %n) {
 ; CHECK-LABEL: vla_emergency_spill:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
 ; CHECK-NEXT:    .setfp r7, sp, #12

llvm/test/CodeGen/X86/inline-asm-A-constraint.ll

 ; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-- -early-live-intervals < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64--"
 
 ; Function Attrs: nounwind uwtable
 define { i64, i64 } @foo(i8* %ptr, i128* nocapture readonly %src, i128* nocapture readonly %dst) local_unnamed_addr #0 {
 entry:
   %0 = load i128, i128* %dst, align 16, !tbaa !1