[AMDGPU] Fix setcc combine for i128

[sebastian-ne]

Summary

The combine asserted if constants could not be represented as uint64_t.
Use APInts to fix this.

[foad]

Looks OK to me.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

if (VT == MVT::i32 && LHS.getOpcode() == ISD::SIGN_EXTEND &&
                            DAG.getConstant(-1, SL, MVT::i1));
       if ((CRHS->isAllOnes() &&
            (CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
           (CRHS->isZero() &&
            (CC == ISD::SETNE || CC == ISD::SETUGT || CC == ISD::SETLT)))
         return LHS.getOperand(0);
     }
 
-    uint64_t CRHSVal = CRHS->getZExtValue();
+    const APInt &CRHSVal = CRHS->getAPIntValue();
     if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
         LHS.getOpcode() == ISD::SELECT &&
         isa<ConstantSDNode>(LHS.getOperand(1)) &&
         isa<ConstantSDNode>(LHS.getOperand(2)) &&
         LHS.getConstantOperandVal(1) != LHS.getConstantOperandVal(2) &&
         isBoolSGPR(LHS.getOperand(0))) {
       // Given CT != FT:
       // setcc (select cc, CT, CF), CF, eq => xor cc, -1
       // setcc (select cc, CT, CF), CF, ne => cc
       // setcc (select cc, CT, CF), CT, ne => xor cc, -1
       // setcc (select cc, CT, CF), CT, eq => cc
-      uint64_t CT = LHS.getConstantOperandVal(1);
-      uint64_t CF = LHS.getConstantOperandVal(2);
+      const APInt &CT = LHS.getConstantOperandAPInt(1);
+      const APInt &CF = LHS.getConstantOperandAPInt(2);
 
       if ((CF == CRHSVal && CC == ISD::SETEQ) ||
           (CT == CRHSVal && CC == ISD::SETNE))
         return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
                            DAG.getConstant(-1, SL, MVT::i1));
       if ((CF == CRHSVal && CC == ISD::SETNE) ||
           (CT == CRHSVal && CC == ISD::SETEQ))
         return LHS.getOperand(0);

llvm/test/CodeGen/AMDGPU/setcc64.ll

 define amdgpu_kernel void @i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) #0 {
 entry:
   %tmp0 = icmp sle i64 %a, %b
   %tmp1 = sext i1 %tmp0 to i32
   store i32 %tmp1, i32 addrspace(1)* %out
   ret void
 }
 
+; GCN-LABEL: {{^}}i128_sle:
+; GCN: v_cmp_le_u64
+; GCN: v_cmp_le_i64
+; SI: v_cmp_eq_u64
+; VI: s_cmp_eq_u64
+define amdgpu_kernel void @i128_sle(i32 addrspace(1)* %out, i128 %a, i128 %b) #0 {
+entry:
+  %tmp0 = icmp sle i128 %a, %b
+  %tmp1 = sext i1 %tmp0 to i32
+  store i32 %tmp1, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}i128_eq_const:
+; SI: v_cmp_eq_u64
+; VI: s_cmp_eq_u64
+define amdgpu_kernel void @i128_eq_const(i32 addrspace(1)* %out, i128 %a) #0 {
+entry:
+  %tmp0 = icmp eq i128 %a, 85070591730234615865843651857942052992
+  %tmp1 = sext i1 %tmp0 to i32
+  store i32 %tmp1, i32 addrspace(1)* %out
+  ret void
+}
+
 attributes #0 = { nounwind }