[x86] add special-case lowering for usubsat for pre-SSE4

[spatel]

Summary

usubsat X, SMIN --> (X ^ SMIN) & (X s>> BW-1)

This would be a regression with D112085 where we combine to usubsat more aggressively, so avoid that by matching the special-case where we are subtracting SMIN (signmask):
https://alive2.llvm.org/ce/z/4_3gBD

[RKSimon]

LGTM

llvm/test/CodeGen/X86/psubus.ll

31–32

Please can you add a comment explaining the fold:

; usubsat X, (1 << (BW-1)) --> (X ^ (1 << (BW-1))) & (ashr X, (BW-1))

llvm/lib/Target/X86/X86ISelLowering.cpp

if (VT == MVT::v32i16 || VT == MVT::v64i8 ||
     return splitVectorIntBinary(Op, DAG);
   }
 
   // Avoid the generic expansion with min/max if we don't have pminu*/pmaxu*.
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   EVT SetCCResultType =
       TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
 
+  unsigned BitWidth = VT.getScalarSizeInBits();
   if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) {
+    // Handle a special-case with a bit-hack instead of cmp+select:
+    // usubsat X, SMIN --> (X ^ SMIN) & (X s>> BW-1)
+    ConstantSDNode *C = isConstOrConstSplat(Y, true);
+    if (C && C->getAPIntValue().isSignMask()) {
+      SDValue SignMask = DAG.getConstant(C->getAPIntValue(), DL, VT);
+      SDValue ShiftAmt = DAG.getConstant(BitWidth - 1, DL, VT);
+      SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, SignMask);
+      SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShiftAmt);
+      return DAG.getNode(ISD::AND, DL, VT, Xor, Sra);
+    }
+
     // usubsat X, Y --> (X >u Y) ? X - Y : 0
     SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, X, Y);
     SDValue Cmp = DAG.getSetCC(DL, SetCCResultType, X, Y, ISD::SETUGT);
     // TODO: Move this to DAGCombiner?
     if (SetCCResultType == VT &&
         DAG.ComputeNumSignBits(Cmp) == VT.getScalarSizeInBits())
       return DAG.getNode(ISD::AND, DL, VT, Cmp, Sub);
     return DAG.getSelect(DL, VT, Cmp, Sub, DAG.getConstant(0, DL, VT));
   }
 
   if ((Opcode == ISD::SADDSAT || Opcode == ISD::SSUBSAT) &&
       (!VT.isVector() || VT == MVT::v2i64)) {
-    unsigned BitWidth = VT.getScalarSizeInBits();
     APInt MinVal = APInt::getSignedMinValue(BitWidth);
     APInt MaxVal = APInt::getSignedMaxValue(BitWidth);
     SDValue Zero = DAG.getConstant(0, DL, VT);
     SDValue Result =
         DAG.getNode(Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::SSUBO, DL,
                     DAG.getVTList(VT, SetCCResultType), X, Y);
     SDValue SumDiff = Result.getValue(0);
     SDValue Overflow = Result.getValue(1);

llvm/test/CodeGen/X86/psubus.ll

 ; AVX-NEXT:    retq
 vector.ph:
   %0 = icmp slt <8 x i16> %x, zeroinitializer
   %1 = xor <8 x i16> %x, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
   %res = select <8 x i1> %0, <8 x i16> %1, <8 x i16> zeroinitializer
   ret <8 x i16> %res
 }
 
 ; This is logically equivalent to the above.
+; usubsat X, (1 << (BW-1)) <--> (X ^ (1 << (BW-1))) & (ashr X, (BW-1))
 
 define <8 x i16> @ashr_xor_and(<8 x i16> %x) nounwind {
 ; SSE-LABEL: ashr_xor_and:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    movdqa %xmm0, %xmm1
 ; SSE-NEXT:    psraw $15, %xmm1
 ; SSE-NEXT:    pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE-NEXT:    pand %xmm1, %xmm0

 ; AVX512-NEXT:    vpternlogd $72, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
 ; AVX512-NEXT:    retq
   %signsplat = ashr <4 x i32> %x, <i32 undef, i32 31, i32 31, i32 31>
   %flipsign = xor <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
   %res = and <4 x i32> %flipsign, %signsplat
   ret <4 x i32> %res
 }
 
+; usubsat X, (1 << (BW-1)) <--> (X ^ (1 << (BW-1))) & (ashr X, (BW-1))
+
 define <4 x i32> @usubsat_custom(<4 x i32> %x) nounwind {
 ; SSE2OR3-LABEL: usubsat_custom:
 ; SSE2OR3:       # %bb.0:
-; SSE2OR3-NEXT:    movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; SSE2OR3-NEXT:    pxor %xmm0, %xmm1
-; SSE2OR3-NEXT:    pxor %xmm2, %xmm2
-; SSE2OR3-NEXT:    pcmpgtd %xmm2, %xmm1
-; SSE2OR3-NEXT:    psubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2OR3-NEXT:    movdqa %xmm0, %xmm1
+; SSE2OR3-NEXT:    psrad $31, %xmm1
+; SSE2OR3-NEXT:    pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
 ; SSE2OR3-NEXT:    pand %xmm1, %xmm0
 ; SSE2OR3-NEXT:    retq
 ;
 ; SSE41-LABEL: usubsat_custom:
 ; SSE41:       # %bb.0:
 ; SSE41-NEXT:    movdqa {{.*#+}} xmm1 = <2147483648,2147483648,2147483648,u>
 ; SSE41-NEXT:    pmaxud %xmm1, %xmm0
 ; SSE41-NEXT:    psubd %xmm1, %xmm0