[X86] Use CMOVNS for abs instead of CMOVGE.

[craig.topper]

Summary

CMOVGE reads SF and OF. CMOVNS only reads SF. This matches with
other recent changes to use a single flag where possible. It also
matches gcc codegen.

I believe this technically changes whether the conditioanl move happens
on INT_MIN, but for INT_MIN both registers are the same so it doesn't
matter.

[RKSimon]

LGTM - cheers

llvm/lib/Target/X86/X86ISelLowering.cpp

static SDValue LowerABS(SDValue Op, const X86Subtarget &Subtarget,
   MVT VT = Op.getSimpleValueType();
   if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) {
     // Since X86 does not have CMOV for 8-bit integer, we don't convert
     // 8-bit integer abs to NEG and CMOV.
     SDLoc DL(Op);
     SDValue N0 = Op.getOperand(0);
     SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
                               DAG.getConstant(0, DL, VT), N0);
-    SDValue Ops[] = {N0, Neg, DAG.getTargetConstant(X86::COND_GE, DL, MVT::i8),
+    SDValue Ops[] = {N0, Neg, DAG.getTargetConstant(X86::COND_NS, DL, MVT::i8),
                      SDValue(Neg.getNode(), 1)};
     return DAG.getNode(X86ISD::CMOV, DL, VT, Ops);
   }
 
   // ABS(vXi64 X) --> VPBLENDVPD(X, 0-X, X).
   if ((VT == MVT::v2i64 || VT == MVT::v4i64) && Subtarget.hasSSE41()) {
     SDLoc DL(Op);
     SDValue Src = Op.getOperand(0);

llvm/test/CodeGen/X86/abs.ll

; X86-NEXT:    retl
   ret i8 %r
 }
 
 define i16 @test_i16(i16 %a) nounwind {
 ; X64-LABEL: test_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negw %ax
-; X64-NEXT:    cmovlw %di, %ax
+; X64-NEXT:    cmovsw %di, %ax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i16:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negw %ax
-; X86-NEXT:    cmovlw %cx, %ax
+; X86-NEXT:    cmovsw %cx, %ax
 ; X86-NEXT:    retl
   %r = call i16 @llvm.abs.i16(i16 %a, i1 false)
   ret i16 %r
 }
 
 define i24 @test_i24(i24 %a) nounwind {
 ; X64-LABEL: test_i24:
 ; X64:       # %bb.0:
 ; X64-NEXT:    shll $8, %edi
 ; X64-NEXT:    sarl $8, %edi
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i24:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    shll $8, %ecx
 ; X86-NEXT:    sarl $8, %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    cmovsl %ecx, %eax
 ; X86-NEXT:    retl
   %r = call i24 @llvm.abs.i24(i24 %a, i1 false)
   ret i24 %r
 }
 
 define i32 @test_i32(i32 %a) nounwind {
 ; X64-LABEL: test_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    cmovsl %ecx, %eax
 ; X86-NEXT:    retl
   %r = call i32 @llvm.abs.i32(i32 %a, i1 false)
   ret i32 %r
 }
 
 define i64 @test_i64(i64 %a) nounwind {
 ; X64-LABEL: test_i64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    negq %rax
-; X64-NEXT:    cmovlq %rdi, %rax
+; X64-NEXT:    cmovsq %rdi, %rax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    sarl $31, %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
; X86-NEXT:    retl $4
   ret i128 %r
 }
 
 define <1 x i32> @test_v1i32(<1 x i32> %a) nounwind {
 ; X64-LABEL: test_v1i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_v1i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    cmovsl %ecx, %eax
 ; X86-NEXT:    retl
   %r = call <1 x i32> @llvm.abs.v1i32(<1 x i32> %a, i1 false)
   ret <1 x i32> %r
 }
 
 define <2 x i32> @test_v2i32(<2 x i32> %a) nounwind {
 ; SSE-LABEL: test_v2i32:
 ; SSE:       # %bb.0:

 ; AVX-NEXT:    retq
 ;
 ; X86-LABEL: test_v2i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %edx, %eax
+; X86-NEXT:    cmovsl %edx, %eax
 ; X86-NEXT:    movl %ecx, %edx
 ; X86-NEXT:    negl %edx
-; X86-NEXT:    cmovll %ecx, %edx
+; X86-NEXT:    cmovsl %ecx, %edx
 ; X86-NEXT:    retl
   %r = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 false)
   ret <2 x i32> %r
 }
 
 define <3 x i32> @test_v3i32(<3 x i32> %a) nounwind {
 ; SSE-LABEL: test_v3i32:
 ; SSE:       # %bb.0:

 ; X86-LABEL: test_v3i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %edx, %eax
+; X86-NEXT:    cmovsl %edx, %eax
 ; X86-NEXT:    movl %ecx, %edx
 ; X86-NEXT:    negl %edx
-; X86-NEXT:    cmovll %ecx, %edx
+; X86-NEXT:    cmovsl %ecx, %edx
 ; X86-NEXT:    movl %esi, %ecx
 ; X86-NEXT:    negl %ecx
-; X86-NEXT:    cmovll %esi, %ecx
+; X86-NEXT:    cmovsl %esi, %ecx
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    retl
   %r = call <3 x i32> @llvm.abs.v3i32(<3 x i32> %a, i1 false)
   ret <3 x i32> %r
 }
 
 define <4 x i32> @test_v4i32(<4 x i32> %a) nounwind {
 ; SSE-LABEL: test_v4i32:

 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X86-NEXT:    movl %ebx, %edx
 ; X86-NEXT:    negl %edx
-; X86-NEXT:    cmovll %ebx, %edx
+; X86-NEXT:    cmovsl %ebx, %edx
 ; X86-NEXT:    movl %edi, %ebx
 ; X86-NEXT:    negl %ebx
-; X86-NEXT:    cmovll %edi, %ebx
+; X86-NEXT:    cmovsl %edi, %ebx
 ; X86-NEXT:    movl %esi, %edi
 ; X86-NEXT:    negl %edi
-; X86-NEXT:    cmovll %esi, %edi
+; X86-NEXT:    cmovsl %esi, %edi
 ; X86-NEXT:    movl %ecx, %esi
 ; X86-NEXT:    negl %esi
-; X86-NEXT:    cmovll %ecx, %esi
+; X86-NEXT:    cmovsl %ecx, %esi
 ; X86-NEXT:    movl %esi, 12(%eax)
 ; X86-NEXT:    movl %edi, 8(%eax)
 ; X86-NEXT:    movl %ebx, 4(%eax)
 ; X86-NEXT:    movl %edx, (%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    popl %ebx
 ; X86-NEXT:    retl $4

 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ebp
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    negl %ecx
-; X86-NEXT:    cmovll %edx, %ecx
+; X86-NEXT:    cmovsl %edx, %ecx
 ; X86-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; X86-NEXT:    movl %esi, %ecx
 ; X86-NEXT:    negl %ecx
-; X86-NEXT:    cmovll %esi, %ecx
+; X86-NEXT:    cmovsl %esi, %ecx
 ; X86-NEXT:    movl %ecx, (%esp) # 4-byte Spill
 ; X86-NEXT:    movl %ebx, %esi
 ; X86-NEXT:    negl %esi
-; X86-NEXT:    cmovll %ebx, %esi
+; X86-NEXT:    cmovsl %ebx, %esi
 ; X86-NEXT:    movl %ebp, %ebx
 ; X86-NEXT:    negl %ebx
-; X86-NEXT:    cmovll %ebp, %ebx
+; X86-NEXT:    cmovsl %ebp, %ebx
 ; X86-NEXT:    movl %edi, %ebp
 ; X86-NEXT:    negl %ebp
-; X86-NEXT:    cmovll %edi, %ebp
+; X86-NEXT:    cmovsl %edi, %ebp
 ; X86-NEXT:    movl %eax, %edi
 ; X86-NEXT:    negl %edi
-; X86-NEXT:    cmovll %eax, %edi
+; X86-NEXT:    cmovsl %eax, %edi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negl %eax
-; X86-NEXT:    cmovll %ecx, %eax
+; X86-NEXT:    cmovsl %ecx, %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    negl %ecx
-; X86-NEXT:    cmovll %edx, %ecx
+; X86-NEXT:    cmovsl %edx, %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %ecx, 28(%edx)
 ; X86-NEXT:    movl %eax, 24(%edx)
 ; X86-NEXT:    movl %edi, 20(%edx)
 ; X86-NEXT:    movl %ebp, 16(%edx)
 ; X86-NEXT:    movl %ebx, 12(%edx)
 ; X86-NEXT:    movl %esi, 8(%edx)
 ; X86-NEXT:    movl (%esp), %eax # 4-byte Reload

 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %edi
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ebp
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ebx
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %esi
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    negw %cx
-; X86-NEXT:    cmovlw %dx, %cx
+; X86-NEXT:    cmovsw %dx, %cx
 ; X86-NEXT:    movw %cx, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
 ; X86-NEXT:    movl %esi, %ecx
 ; X86-NEXT:    negw %cx
-; X86-NEXT:    cmovlw %si, %cx
+; X86-NEXT:    cmovsw %si, %cx
 ; X86-NEXT:    movw %cx, (%esp) # 2-byte Spill
 ; X86-NEXT:    movl %ebx, %esi
 ; X86-NEXT:    negw %si
-; X86-NEXT:    cmovlw %bx, %si
+; X86-NEXT:    cmovsw %bx, %si
 ; X86-NEXT:    movl %ebp, %ebx
 ; X86-NEXT:    negw %bx
-; X86-NEXT:    cmovlw %bp, %bx
+; X86-NEXT:    cmovsw %bp, %bx
 ; X86-NEXT:    movl %edi, %ebp
 ; X86-NEXT:    negw %bp
-; X86-NEXT:    cmovlw %di, %bp
+; X86-NEXT:    cmovsw %di, %bp
 ; X86-NEXT:    movl %eax, %edi
 ; X86-NEXT:    negw %di
-; X86-NEXT:    cmovlw %ax, %di
+; X86-NEXT:    cmovsw %ax, %di
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    negw %ax
-; X86-NEXT:    cmovlw %cx, %ax
+; X86-NEXT:    cmovsw %cx, %ax
 ; X86-NEXT:    movzwl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    negw %cx
-; X86-NEXT:    cmovlw %dx, %cx
+; X86-NEXT:    cmovsw %dx, %cx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movw %cx, 14(%edx)
 ; X86-NEXT:    movw %ax, 12(%edx)
 ; X86-NEXT:    movw %di, 10(%edx)
 ; X86-NEXT:    movw %bp, 8(%edx)
 ; X86-NEXT:    movw %bx, 6(%edx)
 ; X86-NEXT:    movw %si, 4(%edx)
 ; X86-NEXT:    movzwl (%esp), %eax # 2-byte Folded Reload

llvm/test/CodeGen/X86/combine-abs.ll

 }
 
 ; fold (abs (abs x)) -> (abs x)
 define i32 @combine_i32_abs_abs(i32 %a) {
 ; CHECK-LABEL: combine_i32_abs_abs:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    negl %eax
-; CHECK-NEXT:    cmovll %edi, %eax
+; CHECK-NEXT:    cmovsl %edi, %eax
 ; CHECK-NEXT:    retq
   %n1 = sub i32 zeroinitializer, %a
   %b1 = icmp slt i32 %a, zeroinitializer
   %a1 = select i1 %b1, i32 %n1, i32 %a
   %n2 = sub i32 zeroinitializer, %a1
   %b2 = icmp sgt i32 %a1, zeroinitializer
   %a2 = select i1 %b2, i32 %a1, i32 %n2
   ret i32 %a2

llvm/test/CodeGen/X86/iabs.ll

 ; X86-NO-CMOV-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NO-CMOV-NEXT:    retl
 ;
 ; X86-CMOV-LABEL: test_i16:
 ; X86-CMOV:       # %bb.0:
 ; X86-CMOV-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-CMOV-NEXT:    movl %ecx, %eax
 ; X86-CMOV-NEXT:    negw %ax
-; X86-CMOV-NEXT:    cmovlw %cx, %ax
+; X86-CMOV-NEXT:    cmovsw %cx, %ax
 ; X86-CMOV-NEXT:    retl
 ;
 ; X64-LABEL: test_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negw %ax
-; X64-NEXT:    cmovlw %di, %ax
+; X64-NEXT:    cmovsw %di, %ax
 ; X64-NEXT:    retq
   %tmp1neg = sub i16 0, %a
   %b = icmp sgt i16 %a, -1
   %abs = select i1 %b, i16 %a, i16 %tmp1neg
   ret i16 %abs
 }
 
 define i32 @test_i32(i32 %a) nounwind {
 ; X86-NO-CMOV-LABEL: test_i32:
 ; X86-NO-CMOV:       # %bb.0:
 ; X86-NO-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NO-CMOV-NEXT:    movl %eax, %ecx
 ; X86-NO-CMOV-NEXT:    sarl $31, %ecx
 ; X86-NO-CMOV-NEXT:    addl %ecx, %eax
 ; X86-NO-CMOV-NEXT:    xorl %ecx, %eax
 ; X86-NO-CMOV-NEXT:    retl
 ;
 ; X86-CMOV-LABEL: test_i32:
 ; X86-CMOV:       # %bb.0:
 ; X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-CMOV-NEXT:    movl %ecx, %eax
 ; X86-CMOV-NEXT:    negl %eax
-; X86-CMOV-NEXT:    cmovll %ecx, %eax
+; X86-CMOV-NEXT:    cmovsl %ecx, %eax
 ; X86-CMOV-NEXT:    retl
 ;
 ; X64-LABEL: test_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
   %tmp1neg = sub i32 0, %a
   %b = icmp sgt i32 %a, -1
   %abs = select i1 %b, i32 %a, i32 %tmp1neg
   ret i32 %abs
 }
 
 define i64 @test_i64(i64 %a) nounwind {
 ; X86-LABEL: test_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    sarl $31, %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    addl %ecx, %eax
 ; X86-NEXT:    adcl %ecx, %edx
 ; X86-NEXT:    xorl %ecx, %edx
 ; X86-NEXT:    xorl %ecx, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_i64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    negq %rax
-; X64-NEXT:    cmovlq %rdi, %rax
+; X64-NEXT:    cmovsq %rdi, %rax
 ; X64-NEXT:    retq
   %tmp1neg = sub i64 0, %a
   %b = icmp sgt i64 %a, -1
   %abs = select i1 %b, i64 %a, i64 %tmp1neg
   ret i64 %abs
 }
 
 define i128 @test_i128(i128 %a) nounwind {

llvm/test/CodeGen/X86/neg-abs.ll

 ; X86-NEXT:    subl %ecx, %eax
 ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: neg_abs_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negw %ax
-; X64-NEXT:    cmovlw %di, %ax
+; X64-NEXT:    cmovsw %di, %ax
 ; X64-NEXT:    negl %eax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
   %neg = sub nsw i16 0, %abs
   ret i16 %neg
 }
 
 define i32 @neg_abs_i32(i32 %x) nounwind {
 ; X86-LABEL: neg_abs_i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    sarl $31, %eax
 ; X86-NEXT:    xorl %eax, %ecx
 ; X86-NEXT:    subl %ecx, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: neg_abs_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    negl %eax
 ; X64-NEXT:    retq
   %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
   %neg = sub nsw i32 0, %abs
   ret i32 %neg
 }
 
 define i64 @neg_abs_i64(i64 %x) nounwind {

 ; X86-NEXT:    sbbl %ecx, %edx
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: neg_abs_i64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    negq %rax
-; X64-NEXT:    cmovlq %rdi, %rax
+; X64-NEXT:    cmovsq %rdi, %rax
 ; X64-NEXT:    negq %rax
 ; X64-NEXT:    retq
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
   %neg = sub nsw i64 0, %abs
   ret i64 %neg
 }
 
 define i128 @neg_abs_i128(i128 %x) nounwind {

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected

 ; X86-NO-CMOV-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NO-CMOV-NEXT:    retl
 ;
 ; X86-CMOV-LABEL: test_i16:
 ; X86-CMOV:       # %bb.0:
 ; X86-CMOV-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
 ; X86-CMOV-NEXT:    movl %ecx, %eax
 ; X86-CMOV-NEXT:    negw %ax
-; X86-CMOV-NEXT:    cmovlw %cx, %ax
+; X86-CMOV-NEXT:    cmovsw %cx, %ax
 ; X86-CMOV-NEXT:    retl
 ;
 ; X64-LABEL: test_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negw %ax
-; X64-NEXT:    cmovlw %di, %ax
+; X64-NEXT:    cmovsw %di, %ax
 ; X64-NEXT:    retq
   %tmp1neg = sub i16 0, %a
   %b = icmp sgt i16 %a, -1
   %abs = select i1 %b, i16 %a, i16 %tmp1neg
   ret i16 %abs
 }
 
 define i32 @test_i32(i32 %a) nounwind {
 ; X86-NO-CMOV-LABEL: test_i32:
 ; X86-NO-CMOV:       # %bb.0:
 ; X86-NO-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NO-CMOV-NEXT:    movl %eax, %ecx
 ; X86-NO-CMOV-NEXT:    sarl $31, %ecx
 ; X86-NO-CMOV-NEXT:    addl %ecx, %eax
 ; X86-NO-CMOV-NEXT:    xorl %ecx, %eax
 ; X86-NO-CMOV-NEXT:    retl
 ;
 ; X86-CMOV-LABEL: test_i32:
 ; X86-CMOV:       # %bb.0:
 ; X86-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-CMOV-NEXT:    movl %ecx, %eax
 ; X86-CMOV-NEXT:    negl %eax
-; X86-CMOV-NEXT:    cmovll %ecx, %eax
+; X86-CMOV-NEXT:    cmovsl %ecx, %eax
 ; X86-CMOV-NEXT:    retl
 ;
 ; X64-LABEL: test_i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    negl %eax
-; X64-NEXT:    cmovll %edi, %eax
+; X64-NEXT:    cmovsl %edi, %eax
 ; X64-NEXT:    retq
   %tmp1neg = sub i32 0, %a
   %b = icmp sgt i32 %a, -1
   %abs = select i1 %b, i32 %a, i32 %tmp1neg
   ret i32 %abs
 }
 
 define i64 @test_i64(i64 %a) nounwind {
 ; X86-LABEL: test_i64:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl %edx, %ecx
 ; X86-NEXT:    sarl $31, %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    addl %ecx, %eax
 ; X86-NEXT:    adcl %ecx, %edx
 ; X86-NEXT:    xorl %ecx, %edx
 ; X86-NEXT:    xorl %ecx, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_i64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    negq %rax
-; X64-NEXT:    cmovlq %rdi, %rax
+; X64-NEXT:    cmovsq %rdi, %rax
 ; X64-NEXT:    retq
   %tmp1neg = sub i64 0, %a
   %b = icmp sgt i64 %a, -1
   %abs = select i1 %b, i64 %a, i64 %tmp1neg
   ret i64 %abs
 }