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Differential D111606

[mlir][Vector] NFC - Add test to exercise lowering of vector.transfer to scf
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Authored by nicolasvasilache on Oct 12 2021, 12:05 AM.

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springerm
dcaballe
ftynse
ThomasRaoux
aartbik
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rG0c74b12a2e81: [mlir][Vector] NFC - Add test to exercise lowering of vector.transfer to scf
Summary

This revision also renames and moves some tests around.

Diff Detail

Event Timeline

nicolasvasilache created this revision.Oct 12 2021, 12:05 AM
Herald added subscribers: wenzhicui, wrengr, Chia-hungDuan and 18 others. · View Herald TranscriptOct 12 2021, 12:05 AM
nicolasvasilache requested review of this revision.Oct 12 2021, 12:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 12 2021, 12:05 AM
Herald added a subscriber: stephenneuendorffer. · View Herald Transcript
Harbormaster completed remote builds in B128275: Diff 378893.Oct 12 2021, 12:05 AM
nicolasvasilache updated this revision to Diff 378984.Oct 12 2021, 5:37 AM

Fix test.

This revision was not accepted when it landed; it landed in state Needs Review.Oct 12 2021, 5:38 AM
This revision was landed with ongoing or failed builds.
Closed by commit rG0c74b12a2e81: [mlir][Vector] NFC - Add test to exercise lowering of vector.transfer to scf (authored by nicolasvasilache). · Explain Why
This revision was automatically updated to reflect the committed changes.
nicolasvasilache added a commit: rG0c74b12a2e81: [mlir][Vector] NFC - Add test to exercise lowering of vector.transfer to scf.
gysit added a subscriber: gysit.Oct 12 2021, 5:39 AM
gysit added inline comments.
mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
21

nit: is this test intentionally disabled?

Harbormaster completed remote builds in B128340: Diff 378984.Oct 12 2021, 5:53 AM
nicolasvasilache marked an inline comment as done.Oct 12 2021, 5:57 AM
nicolasvasilache added inline comments.
mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir
21

fixed in 0a7f81a4518ef88d897322985483c2dd48fa577e

Revision Contents

PathSize
mlir/
test/
Conversion/
VectorToSCF/
vector-to-scf.mlir
vector-to-loops.mlir
26 lines
Conversion/
VectorToSCF/
Dialect/
Vector/
vector-to-scf-mask-and-permutation-map.mlir
vector-transfer-lowering-to-scf.mlir
Dialect/
Vector/
vector-transfer-to-vector-load-store.mlir
vector-transfer-lowering.mlir
2 lines

Diff 378985

mlir/test/Conversion/VectorToSCF/vector-to-loops.mlir

  • This file was moved to mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir.

mlir/test/Conversion/VectorToSCF/vector-to-scf-mask-and-permutation-map.mlir

  • This file was moved from mlir/test/Dialect/Vector/vector-transfer-lowering-to-scf.mlir.
The contents of this file were not changed.

mlir/test/Conversion/VectorToSCF/vector-to-scf.mlir

  • This file was moved from mlir/test/Conversion/VectorToSCF/vector-to-loops.mlir.
// RUN: mlir-opt %s -convert-vector-to-scf -split-input-file -allow-unregistered-dialect | FileCheck %s // RUN: mlir-opt %s -convert-vector-to-scf -split-input-file -allow-unregistered-dialect | FileCheck %s
// RUN: mlir-opt %s -convert-vector-to-scf=full-unroll=true -split-input-file -allow-unregistered-dialect | FileCheck %s --check-prefix=FULL-UNROLL // RUN: mlir-opt %s -convert-vector-to-scf=full-unroll=true -split-input-file -allow-unregistered-dialect | FileCheck %s --check-prefix=FULL-UNROLL
// CHECK-LABEL: func @vector_transfer_ops_0d(
// CHECK-SAME: %[[MEM:.*]]: memref<f32>) {
func @vector_transfer_ops_0d(%M: memref<f32>) {
%f0 = constant 0.0 : f32
// CHECK: %[[V0:.*]] = constant dense<0{{.*}}> : vector<1xf32>
// CHECK: %[[R0:.*]] = scf.for %[[I:.*]] = {{.*}} iter_args(%[[V0_ITER:.*]] = %[[V0]]) -> (vector<1xf32>) {
// CHECK: %[[IDX:.*]] = index_cast %[[I]] : index to i32
// CHECK: %[[S:.*]] = memref.load %[[MEM]][] : memref<f32>
// CHECK: %[[R_ITER:.*]] = vector.insertelement %[[S]], %[[V0_ITER]][%[[IDX]] : i32] : vector<1xf32>
// CHECK: scf.yield %[[R_ITER]] : vector<1xf32>
%0 = vector.transfer_read %M[], %f0 {permutation_map = affine_map<()->(0)>} :
memref<f32>, vector<1xf32>
// C-HECK: scf.for %[[J:.*]] = %{{.*}}
// C-HECK: %[[JDX:.*]] = index_cast %[[J]] : index to i32
// C-HECK: %[[SS:.*]] = vector.extractelement %[[R0]][%[[JDX]] : i32] : vector<1xf32>
// C-HECK: memref.store %[[SS]], %[[MEM]][] : memref<f32>
gysitUnsubmitted
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nit: is this test intentionally disabled?

gysit: nit: is this test intentionally disabled?
nicolasvasilacheAuthorUnsubmitted
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fixed in 0a7f81a4518ef88d897322985483c2dd48fa577e

nicolasvasilache: fixed in 0a7f81a4518ef88d897322985483c2dd48fa577e
vector.transfer_write %0, %M[] {permutation_map = affine_map<()->(0)>} :
vector<1xf32>, memref<f32>
return
}
// -----
// CHECK-LABEL: func @materialize_read_1d() { // CHECK-LABEL: func @materialize_read_1d() {
func @materialize_read_1d() { func @materialize_read_1d() {
%f0 = constant 0.0: f32 %f0 = constant 0.0: f32
%A = memref.alloc () : memref<7x42xf32> %A = memref.alloc () : memref<7x42xf32>
affine.for %i0 = 0 to 7 step 4 { affine.for %i0 = 0 to 7 step 4 {
affine.for %i1 = 0 to 42 step 4 { affine.for %i1 = 0 to 42 step 4 {
%f1 = vector.transfer_read %A[%i0, %i1], %f0 {permutation_map = affine_map<(d0, d1) -> (d0)>} : memref<7x42xf32>, vector<4xf32> %f1 = vector.transfer_read %A[%i0, %i1], %f0 {permutation_map = affine_map<(d0, d1) -> (d0)>} : memref<7x42xf32>, vector<4xf32>
%ip1 = affine.apply affine_map<(d0) -> (d0 + 1)> (%i1) %ip1 = affine.apply affine_map<(d0) -> (d0 + 1)> (%i1)
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mlir/test/Dialect/Vector/vector-transfer-lowering-to-scf.mlir

  • This file was moved to mlir/test/Conversion/VectorToSCF/vector-to-scf-mask-and-permutation-map.mlir.

mlir/test/Dialect/Vector/vector-transfer-lowering.mlir

  • This file was moved to mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir.

mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir

  • This file was moved from mlir/test/Dialect/Vector/vector-transfer-lowering.mlir.
// RUN: mlir-opt %s -test-vector-transfer-lowering-patterns -canonicalize -split-input-file | FileCheck %s // RUN: mlir-opt %s -test-vector-transfer-lowering-patterns -canonicalize -split-input-file | FileCheck %s
// CHECK-LABEL: func @vector_transfer_ops_0d( // CHECK-LABEL: func @vector_transfer_ops_0d(
// CHECK-SAME: %[[MEM:.*]]: memref<f32>) { // CHECK-SAME: %[[MEM:.*]]: memref<f32>) {
func @vector_transfer_ops_0d(%M: memref<f32>) { func @vector_transfer_ops_0d(%M: memref<f32>) {
%f0 = constant 0.0 : f32 %f0 = constant 0.0 : f32
// CHECK-NEXT: %[[V:.*]] = memref.load %[[MEM]][] : memref<f32> // CHECK-NEXT: %[[V:.*]] = memref.load %[[MEM]][] : memref<f32>
%0 = vector.transfer_read %M[], %f0 {permutation_map = affine_map<()->(0)>} : %0 = vector.transfer_read %M[], %f0 {permutation_map = affine_map<()->(0)>} :
memref<f32>, vector<1xf32> memref<f32>, vector<1xf32>
// CHECK-NEXT: memref.store %[[V]], %[[MEM]][] : memref<f32> // CHECK-NEXT: memref.store %[[V]], %[[MEM]][] : memref<f32>
vector.transfer_write %0, %M[] {permutation_map = affine_map<()->(0)>} : vector.transfer_write %0, %M[] {permutation_map = affine_map<()->(0)>} :
vector<1xf32>, memref<f32> vector<1xf32>, memref<f32>
return return
} }
// ----- // -----
// transfer_read/write are lowered to vector.load/store // transfer_read/write are lowered to vector.load/store
// CHECK-LABEL: func @transfer_to_load( // CHECK-LABEL: func @transfer_to_load(
// CHECK-SAME: %[[MEM:.*]]: memref<8x8xf32>, // CHECK-SAME: %[[MEM:.*]]: memref<8x8xf32>,
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