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[OpenMP] Simplify all stores in the device code
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Authored by jdoerfert on Sep 17 2021, 12:57 PM.

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jhuber6
ggeorgakoudis
tianshilei1992
uenoku
sstefan1
baziotis

Commits

rG3e0c512ce6ce: [OpenMP] Simplify all stores in the device code

Summary

Similar to loads, we want to be aggressive when it comes to store
simplification. Not everything in LLVM handles dead stores well when
address space casts are involved, we can simply ask the Attributor to do
it for us though.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

jdoerfert created this revision.Sep 17 2021, 12:57 PM

Herald added a reviewer: uenoku. · View Herald TranscriptSep 17 2021, 12:57 PM

Herald added subscribers: ormris, uenoku, guansong and 3 others. · View Herald Transcript

jdoerfert requested review of this revision.Sep 17 2021, 12:57 PM

Herald added a reviewer: sstefan1. · View Herald TranscriptSep 17 2021, 12:57 PM

Herald added a reviewer: baziotis. · View Herald Transcript

Herald added a project: Restricted Project. · View Herald Transcript

Herald added subscribers: llvm-commits, sstefan1. · View Herald Transcript

Harbormaster completed remote builds in B124466: Diff 373315.Sep 17 2021, 3:17 PM

LGTM.

llvm/test/Transforms/OpenMP/spmdization.ll
1873–1874	Can we do further? Since the store to this variable is removed, its value now is meaningless. We don't have to pass it to the function call below, and we can remove the argument for the callee, and we don't need to allocate this variable.

This revision is now accepted and ready to land.Sep 20 2021, 11:36 AM

jdoerfert added inline comments.Sep 20 2021, 12:31 PM

llvm/test/Transforms/OpenMP/spmdization.ll
1873–1874	Will happen eventually.

This revision was landed with ongoing or failed builds.Dec 28 2021, 10:21 PM

Closed by commit rG3e0c512ce6ce: [OpenMP] Simplify all stores in the device code (authored by jdoerfert). · Explain Why

This revision was automatically updated to reflect the committed changes.

jdoerfert added a commit: rG3e0c512ce6ce: [OpenMP] Simplify all stores in the device code.

Revision Contents

Path

Size

llvm/

lib/

Transforms/

IPO/

OpenMPOpt.cpp

2 lines

test/

Transforms/

OpenMP/

custom_state_machines.ll

144 lines

spmdization.ll

50 lines

spmdization_guarding_two_reaching_kernels.ll

3 lines

Diff 396482

llvm/lib/Transforms/IPO/OpenMPOpt.cpp

Show First 20 Lines • Show All 4,503 Lines • ▼ Show 20 Lines	for (auto *F : SCC) {
if (!DisableOpenMPOptDeglobalization)		if (!DisableOpenMPOptDeglobalization)
A.getOrCreateAAFor<AAHeapToStack>(IRPosition::function(*F));		A.getOrCreateAAFor<AAHeapToStack>(IRPosition::function(*F));

for (auto &I : instructions(*F)) {		for (auto &I : instructions(*F)) {
if (auto *LI = dyn_cast<LoadInst>(&I)) {		if (auto *LI = dyn_cast<LoadInst>(&I)) {
bool UsedAssumedInformation = false;		bool UsedAssumedInformation = false;
A.getAssumedSimplified(IRPosition::value(LI), / AA */ nullptr,		A.getAssumedSimplified(IRPosition::value(LI), / AA */ nullptr,
UsedAssumedInformation);		UsedAssumedInformation);
		} else if (auto *SI = dyn_cast<StoreInst>(&I)) {
		A.getOrCreateAAFor<AAIsDead>(IRPosition::value(*SI));
}		}
}		}
}		}
}		}

const char AAICVTracker::ID = 0;		const char AAICVTracker::ID = 0;
const char AAKernelInfo::ID = 0;		const char AAKernelInfo::ID = 0;
const char AAExecutionDomain::ID = 0;		const char AAExecutionDomain::ID = 0;
▲ Show 20 Lines • Show All 389 Lines • Show Last 20 Lines

llvm/test/Transforms/OpenMP/custom_state_machines.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 995 Lines • ▼ Show 20 Lines
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3
	; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: call void @p1() #[[ATTR10]]			; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline nounwind			; AMDGPU: Function Attrs: convergent noinline nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized			; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
	; AMDGPU-SAME: () #[[ATTR1]] {			; AMDGPU-SAME: () #[[ATTR1]] {
	▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__8			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__8
	; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: call void @p1() #[[ATTR10]]			; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__11			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__11
	; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: call void @p1() #[[ATTR10]]			; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
	▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__14			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__14
	; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: call void @p1() #[[ATTR10]]			; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92			; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
	; AMDGPU-SAME: () #[[ATTR0]] {			; AMDGPU-SAME: () #[[ATTR0]] {
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	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__18			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__18
	; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-NEXT: call void @p0() #[[ATTR10]]			; AMDGPU-NEXT: call void @p0() #[[ATTR10]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; AMDGPU: Function Attrs: convergent noinline nounwind			; AMDGPU: Function Attrs: convergent noinline nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized			; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
	; AMDGPU-SAME: () #[[ATTR1]] {			; AMDGPU-SAME: () #[[ATTR1]] {
	Show All 29 Lines
	; AMDGPU: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
	; NVPTX-SAME: () #[[ATTR0:[0-9]+]] {			; NVPTX-SAME: () #[[ATTR0:[0-9]+]] {
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__3			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__3
	; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: call void @p1() #[[ATTR10]]			; NVPTX-NEXT: call void @p1() #[[ATTR10]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
	▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline nounwind			; NVPTX: Function Attrs: convergent noinline nounwind
	; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized			; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
	; NVPTX-SAME: () #[[ATTR1]] {			; NVPTX-SAME: () #[[ATTR1]] {
	▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__8			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__8
	; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: call void @p1() #[[ATTR10]]			; NVPTX-NEXT: call void @p1() #[[ATTR10]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__11			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__11
	; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: call void @p1() #[[ATTR10]]			; NVPTX-NEXT: call void @p1() #[[ATTR10]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__14			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__14
	; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: call void @p1() #[[ATTR10]]			; NVPTX-NEXT: call void @p1() #[[ATTR10]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92			; NVPTX-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
	; NVPTX-SAME: () #[[ATTR0]] {			; NVPTX-SAME: () #[[ATTR0]] {
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	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__18			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__18
	; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-NEXT: call void @p0() #[[ATTR10]]			; NVPTX-NEXT: call void @p0() #[[ATTR10]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; NVPTX: Function Attrs: convergent noinline nounwind			; NVPTX: Function Attrs: convergent noinline nounwind
	; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized			; NVPTX-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
	; NVPTX-SAME: () #[[ATTR1]] {			; NVPTX-SAME: () #[[ATTR1]] {
	Show All 29 Lines
	; NVPTX: Function Attrs: convergent noinline norecurse nounwind			; NVPTX: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
	; AMDGPU-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {
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	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3
	; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]			; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
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	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
	; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
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	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8
	; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]			; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
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	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11
	; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]			; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
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	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14
	; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]			; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
	; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
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	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18
	; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]			; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
	; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {			; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
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	; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
	; NVPTX-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {
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	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3
	; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]			; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
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	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
	; NVPTX-DISABLED-SAME: () #[[ATTR1]] {			; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
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	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8
	; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]			; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
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	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11
	; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]			; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
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	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14
	; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]			; NVPTX-DISABLED-NEXT: call void @p1() #[[ATTR10]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
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	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18
	; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.]], i32 noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8			; NVPTX-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.]] = alloca i32, align 8
	; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10]]			; NVPTX-DISABLED-NEXT: call void @p0() #[[ATTR10]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	;			;
	; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
	; NVPTX-DISABLED-SAME: () #[[ATTR1]] {			; NVPTX-DISABLED-SAME: () #[[ATTR1]] {
	Show All 29 Lines
	; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind			; NVPTX-DISABLED: Function Attrs: convergent noinline norecurse nounwind
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; NVPTX-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;

llvm/test/Transforms/OpenMP/spmdization.ll

	Show First 20 Lines • Show All 244 Lines • ▼ Show 20 Lines
	; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; AMDGPU-DISABLED: thread.user_code.check:			; AMDGPU-DISABLED: thread.user_code.check:
	; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; AMDGPU-DISABLED: common.ret:			; AMDGPU-DISABLED: common.ret:
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	; AMDGPU-DISABLED: user_code.entry:			; AMDGPU-DISABLED: user_code.entry:
	; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3:[0-9]+]]			; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3:[0-9]+]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18:![0-9]+]]			; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18:![0-9]+]]
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]			; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_l5			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_l5
	; NVPTX-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	Show All 37 Lines
	; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; NVPTX-DISABLED: thread.user_code.check:			; NVPTX-DISABLED: thread.user_code.check:
	; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; NVPTX-DISABLED: common.ret:			; NVPTX-DISABLED: common.ret:
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	; NVPTX-DISABLED: user_code.entry:			; NVPTX-DISABLED: user_code.entry:
	; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3:[0-9]+]]			; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3:[0-9]+]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18:![0-9]+]]			; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18:![0-9]+]]
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]			; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	entry:			entry:
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	%.threadid_temp. = alloca i32, align 4			%.threadid_temp. = alloca i32, align 4
	▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines
	; Function Attrs: convergent norecurse nounwind			; Function Attrs: convergent norecurse nounwind
	define internal void @__omp_outlined__1_wrapper(i16 zeroext %0, i32 %1) #3 {			define internal void @__omp_outlined__1_wrapper(i16 zeroext %0, i32 %1) #3 {
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1:[0-9]+]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1:[0-9]+]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1:[0-9]+]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1:[0-9]+]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1:[0-9]+]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1:[0-9]+]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1:[0-9]+]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1:[0-9]+]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	entry:			entry:
	%.addr1 = alloca i32, align 4			%.addr1 = alloca i32, align 4
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	%global_args = alloca i8**, align 8			%global_args = alloca i8**, align 8
	▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
	; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; AMDGPU-DISABLED: thread.user_code.check:			; AMDGPU-DISABLED: thread.user_code.check:
	; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; AMDGPU-DISABLED: common.ret:			; AMDGPU-DISABLED: common.ret:
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	; AMDGPU-DISABLED: user_code.entry:			; AMDGPU-DISABLED: user_code.entry:
	; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]			; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__2(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__2(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]			; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_stack_var_l20
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	Show All 37 Lines
	; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; NVPTX-DISABLED: thread.user_code.check:			; NVPTX-DISABLED: thread.user_code.check:
	; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; NVPTX-DISABLED: common.ret:			; NVPTX-DISABLED: common.ret:
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	; NVPTX-DISABLED: user_code.entry:			; NVPTX-DISABLED: user_code.entry:
	; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]			; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__2(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__2(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]			; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	entry:			entry:
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	%.threadid_temp. = alloca i32, align 4			%.threadid_temp. = alloca i32, align 4
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	; Function Attrs: convergent norecurse nounwind			; Function Attrs: convergent norecurse nounwind
	define internal void @__omp_outlined__3_wrapper(i16 zeroext %0, i32 %1) #3 {			define internal void @__omp_outlined__3_wrapper(i16 zeroext %0, i32 %1) #3 {
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	entry:			entry:
	%.addr1 = alloca i32, align 4			%.addr1 = alloca i32, align 4
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	%global_args = alloca i8**, align 8			%global_args = alloca i8**, align 8
	▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
	; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; AMDGPU-DISABLED: thread.user_code.check:			; AMDGPU-DISABLED: thread.user_code.check:
	; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; AMDGPU-DISABLED: common.ret:			; AMDGPU-DISABLED: common.ret:
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	; AMDGPU-DISABLED: user_code.entry:			; AMDGPU-DISABLED: user_code.entry:
	; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]			; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__4(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__4(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]			; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_l35
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	Show All 37 Lines
	; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; NVPTX-DISABLED: thread.user_code.check:			; NVPTX-DISABLED: thread.user_code.check:
	; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; NVPTX-DISABLED: common.ret:			; NVPTX-DISABLED: common.ret:
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	; NVPTX-DISABLED: user_code.entry:			; NVPTX-DISABLED: user_code.entry:
	; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]			; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__4(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__4(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]			; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	entry:			entry:
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	%.threadid_temp. = alloca i32, align 4			%.threadid_temp. = alloca i32, align 4
	▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
	; Function Attrs: convergent norecurse nounwind			; Function Attrs: convergent norecurse nounwind
	define internal void @__omp_outlined__5_wrapper(i16 zeroext %0, i32 %1) #3 {			define internal void @__omp_outlined__5_wrapper(i16 zeroext %0, i32 %1) #3 {
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			; AMDGPU-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	; AMDGPU-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**			; AMDGPU-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**
	; AMDGPU-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]			; AMDGPU-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]
	; AMDGPU-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			; NVPTX-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	; NVPTX-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**			; NVPTX-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**
	; NVPTX-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]			; NVPTX-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]
	; NVPTX-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			; AMDGPU-DISABLED-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	; AMDGPU-DISABLED-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**			; AMDGPU-DISABLED-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**
	; AMDGPU-DISABLED-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]			; AMDGPU-DISABLED-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			; NVPTX-DISABLED-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	; NVPTX-DISABLED-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**			; NVPTX-DISABLED-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**
	; NVPTX-DISABLED-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]			; NVPTX-DISABLED-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	entry:			entry:
	▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
	; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; AMDGPU-DISABLED: thread.user_code.check:			; AMDGPU-DISABLED: thread.user_code.check:
	; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; AMDGPU-DISABLED: common.ret:			; AMDGPU-DISABLED: common.ret:
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	; AMDGPU-DISABLED: user_code.entry:			; AMDGPU-DISABLED: user_code.entry:
	; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]			; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__6(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__6(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]			; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_sequential_loop_to_shared_var_guarded_l50
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	Show All 37 Lines
	; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; NVPTX-DISABLED: thread.user_code.check:			; NVPTX-DISABLED: thread.user_code.check:
	; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; NVPTX-DISABLED: common.ret:			; NVPTX-DISABLED: common.ret:
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	; NVPTX-DISABLED: user_code.entry:			; NVPTX-DISABLED: user_code.entry:
	; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]			; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4, !tbaa [[TBAA18]]
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__6(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__6(i32* noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]			; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	entry:			entry:
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	%.threadid_temp. = alloca i32, align 4			%.threadid_temp. = alloca i32, align 4
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	; Function Attrs: convergent norecurse nounwind			; Function Attrs: convergent norecurse nounwind
	define internal void @__omp_outlined__7_wrapper(i16 zeroext %0, i32 %1) #3 {			define internal void @__omp_outlined__7_wrapper(i16 zeroext %0, i32 %1) #3 {
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			; AMDGPU-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	; AMDGPU-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**			; AMDGPU-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**
	; AMDGPU-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]			; AMDGPU-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]
	; AMDGPU-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			; NVPTX-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	; NVPTX-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**			; NVPTX-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**
	; NVPTX-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]			; NVPTX-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]
	; NVPTX-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			; AMDGPU-DISABLED-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	; AMDGPU-DISABLED-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**			; AMDGPU-DISABLED-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**
	; AMDGPU-DISABLED-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]			; AMDGPU-DISABLED-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8			; NVPTX-DISABLED-NEXT: [[TMP2:%.]] = load i8, i8** [[GLOBAL_ARGS]], align 8
	; NVPTX-DISABLED-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**			; NVPTX-DISABLED-NEXT: [[TMP3:%.]] = bitcast i8* [[TMP2]] to i32**
	; NVPTX-DISABLED-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]			; NVPTX-DISABLED-NEXT: [[TMP4:%.]] = load i32, i32** [[TMP3]], align 8, !tbaa [[TBAA26]]
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP4]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	entry:			entry:
	▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
	; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; AMDGPU-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; AMDGPU-DISABLED: thread.user_code.check:			; AMDGPU-DISABLED: thread.user_code.check:
	; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; AMDGPU-DISABLED: common.ret:			; AMDGPU-DISABLED: common.ret:
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	; AMDGPU-DISABLED: user_code.entry:			; AMDGPU-DISABLED: user_code.entry:
	; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__8(i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__8(i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]			; AMDGPU-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_fd02_2044372e_do_not_spmdize_target_l65
	; NVPTX-DISABLED-SAME: () #[[ATTR0]] {			; NVPTX-DISABLED-SAME: () #[[ATTR0]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8			; NVPTX-DISABLED-NEXT: [[WORKER_WORK_FN_ADDR:%.]] = alloca i8, align 8
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)			; NVPTX-DISABLED-NEXT: [[TMP0:%.]] = call i32 @__kmpc_target_init(%struct.ident_t @[[GLOB1]], i8 1, i1 false, i1 true)
	tianshilei1992Unsubmitted Not Done Reply Inline Actions Can we do further? Since the store to this variable is removed, its value now is meaningless. We don't have to pass it to the function call below, and we can remove the argument for the callee, and we don't need to allocate this variable. tianshilei1992: Can we do further? Since the store to this variable is removed, its value now is meaningless.
	jdoerfertAuthorUnsubmitted Done Reply Inline Actions Will happen eventually. jdoerfert: Will happen eventually.
	; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()			; NVPTX-DISABLED-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
	; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()			; NVPTX-DISABLED-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
	; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]			; NVPTX-DISABLED-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]			; NVPTX-DISABLED-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[IS_WORKER_CHECK:%.]], label [[WORKER_STATE_MACHINE_FINISHED:%.]]
	; NVPTX-DISABLED: is_worker_check:			; NVPTX-DISABLED: is_worker_check:
	; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1			; NVPTX-DISABLED-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[THREAD_IS_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.]], label [[THREAD_USER_CODE_CHECK:%.]]
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	; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]			; NVPTX-DISABLED-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
	; NVPTX-DISABLED: thread.user_code.check:			; NVPTX-DISABLED: thread.user_code.check:
	; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1			; NVPTX-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
	; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]			; NVPTX-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.]], label [[COMMON_RET:%.]]
	; NVPTX-DISABLED: common.ret:			; NVPTX-DISABLED: common.ret:
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	; NVPTX-DISABLED: user_code.entry:			; NVPTX-DISABLED: user_code.entry:
	; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: [[TMP1:%.]] = call i32 @__kmpc_global_thread_num(%struct.ident_t @[[GLOB1]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__8(i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__8(i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTTHREADID_TEMP_]], i32* noalias nocapture noundef nonnull readnone align 4 dereferenceable(4) [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)			; NVPTX-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
	; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]			; NVPTX-DISABLED-NEXT: br label [[COMMON_RET]]
	;			;
	entry:			entry:
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	%.threadid_temp. = alloca i32, align 4			%.threadid_temp. = alloca i32, align 4
	%0 = call i32 @__kmpc_target_init(%struct.ident_t* @1, i8 1, i1 true, i1 true)			%0 = call i32 @__kmpc_target_init(%struct.ident_t* @1, i8 1, i1 true, i1 true)
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	; Function Attrs: convergent norecurse nounwind			; Function Attrs: convergent norecurse nounwind
	define internal void @__omp_outlined__9_wrapper(i16 zeroext %0, i32 %1) #3 {			define internal void @__omp_outlined__9_wrapper(i16 zeroext %0, i32 %1) #3 {
	; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__9_wrapper			; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__9_wrapper
	; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; AMDGPU-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; AMDGPU-NEXT: entry:			; AMDGPU-NEXT: entry:
	; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-NEXT: call void @__omp_outlined__9(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-NEXT: call void @__omp_outlined__9(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-NEXT: ret void			; AMDGPU-NEXT: ret void
	;			;
	; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__9_wrapper			; NVPTX-LABEL: define {{[^@]+}}@__omp_outlined__9_wrapper
	; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; NVPTX-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; NVPTX-NEXT: entry:			; NVPTX-NEXT: entry:
	; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-NEXT: call void @__omp_outlined__9(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-NEXT: call void @__omp_outlined__9(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-NEXT: ret void			; NVPTX-NEXT: ret void
	;			;
	; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9_wrapper			; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9_wrapper
	; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; AMDGPU-DISABLED-NEXT: entry:			; AMDGPU-DISABLED-NEXT: entry:
	; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; AMDGPU-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__9(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__9(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; AMDGPU-DISABLED-NEXT: ret void			; AMDGPU-DISABLED-NEXT: ret void
	;			;
	; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9_wrapper			; NVPTX-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9_wrapper
	; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {			; NVPTX-DISABLED-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR1]] {
	; NVPTX-DISABLED-NEXT: entry:			; NVPTX-DISABLED-NEXT: entry:
	; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; NVPTX-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; NVPTX-DISABLED-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; NVPTX-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4, !tbaa [[TBAA18]]
	; NVPTX-DISABLED-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; NVPTX-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; NVPTX-DISABLED-NEXT: call void @__omp_outlined__9(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]			; NVPTX-DISABLED-NEXT: call void @__omp_outlined__9(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
	; NVPTX-DISABLED-NEXT: ret void			; NVPTX-DISABLED-NEXT: ret void
	;			;
	entry:			entry:
	%.addr1 = alloca i32, align 4			%.addr1 = alloca i32, align 4
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	%global_args = alloca i8**, align 8			%global_args = alloca i8**, align 8
	▲ Show 20 Lines • Show All 243 Lines • Show Last 20 Lines

llvm/test/Transforms/OpenMP/spmdization_guarding_two_reaching_kernels.ll

	Show First 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
	define internal void @__omp_outlined___wrapper(i16 zeroext %0, i32 %1) #2 {			define internal void @__omp_outlined___wrapper(i16 zeroext %0, i32 %1) #2 {
	; CHECK-LABEL: define {{[^@]+}}@__omp_outlined___wrapper			; CHECK-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
	; CHECK-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {			; CHECK-SAME: (i16 zeroext [[TMP0:%.]], i32 [[TMP1:%.]]) #[[ATTR0]] {
	; CHECK-NEXT: entry:			; CHECK-NEXT: entry:
	; CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2			; CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
	; CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4			; CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
	; CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4			; CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
	; CHECK-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8			; CHECK-NEXT: [[GLOBAL_ARGS:%.]] = alloca i8*, align 8
	; CHECK-NEXT: store i16 [[TMP0]], i16* [[DOTADDR]], align 2
	; CHECK-NEXT: store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
	; CHECK-NEXT: store i32 0, i32* [[DOTZERO_ADDR]], align 4
	; CHECK-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])			; CHECK-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
	; CHECK-NEXT: call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR2]]			; CHECK-NEXT: call void @__omp_outlined__(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR2]]
	; CHECK-NEXT: ret void			; CHECK-NEXT: ret void
	;			;
	entry:			entry:
	%.addr = alloca i16, align 2			%.addr = alloca i16, align 2
	%.addr1 = alloca i32, align 4			%.addr1 = alloca i32, align 4
	%.zero.addr = alloca i32, align 4			%.zero.addr = alloca i32, align 4
	▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines