[AMDGPU] NFC to correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor.

[lamb-j]

Summary

Nonfunctional commit to correct minor typos in llvm/lib/Target/AMDGPU/AMDGPU*.cpp files. Testing workflow as a new contributor.

[kerbowa]

LGTM with nits.

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

62

NIT: this is meant to be a doxygen comment I think. So \returns?

llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp

144–145

NIT: This line looks a bit short.

[lamb-j]

Addressing comments from kerbowa and lint tool.

[foad]

lamb-j closed this revision.

FYI if you add a line like Differential Revision: https://reviews.llvm.org/D109991 to the commit message then the revision will get closed automatically when you push. If you use arc diff to create the revision it will automatically add this line to your local commit message.

llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp

if (asA != AMDGPUAS::FLAT_ADDRESS) {
     std::swap(A, B);
   }
   if (asA == AMDGPUAS::FLAT_ADDRESS &&
       (asB == AMDGPUAS::LOCAL_ADDRESS || asB == AMDGPUAS::PRIVATE_ADDRESS)) {
     const auto *ObjA =
         getUnderlyingObject(A.Ptr->stripPointerCastsForAliasAnalysis());
     if (const LoadInst *LI = dyn_cast<LoadInst>(ObjA)) {
       // If a generic pointer is loaded from the constant address space, it
-      // could only be a GLOBAL or CONSTANT one as that address space is soley
+      // could only be a GLOBAL or CONSTANT one as that address space is solely
       // prepared on the host side, where only GLOBAL or CONSTANT variables are
       // visible. Note that this even holds for regular functions.
       if (LI->getPointerAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS)
         return AliasResult::NoAlias;
     } else if (const Argument *Arg = dyn_cast<Argument>(ObjA)) {
       const Function *F = Arg->getParent();
       switch (F->getCallingConv()) {
       case CallingConv::AMDGPU_KERNEL:

llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp

while (!Stack.empty()) {
 
     if (Instruction *I = dyn_cast<Instruction>(U)) {
       Function *F = I->getParent()->getParent();
       if (!AMDGPU::isEntryFunctionCC(F->getCallingConv())) {
         // FIXME: This is a horrible hack. We should always respect noinline,
         // and just let us hit the error when we can't handle this.
         //
         // Unfortunately, clang adds noinline to all functions at -O0. We have
-        // to override this here. until that's fixed.
+        // to override this here until that's fixed.
         F->removeFnAttr(Attribute::NoInline);
 
         FuncsToAlwaysInline.insert(F);
         Stack.push_back(F);
       }
 
       // No need to look at further users, but we do need to inline any callers.
       continue;

llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp

for (Instruction &I : BB) {
         HaveStackObjects = true;
         continue;
       }
 
       if (auto *CB = dyn_cast<CallBase>(&I)) {
         const Function *Callee =
             dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
 
-        // Note the occurence of indirect call.
+        // Note the occurrence of indirect call.
         if (!Callee) {
           if (!CB->isInlineAsm())
             HaveCall = true;
 
           continue;
         }
 
         Intrinsic::ID IID = Callee->getIntrinsicID();

llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp

if (!NeedResult && ST->hasPermLaneX16()) {
       // too many readlanes and writelanes, which are generally bad for
       // performance.
       NewV = buildReduction(B, ScanOp, NewV, Identity);
     } else {
       NewV = buildScan(B, ScanOp, NewV, Identity);
       if (NeedResult)
         ExclScan = buildShiftRight(B, NewV, Identity);
 
-      // Read the value from the last lane, which has accumlated the values of
+      // Read the value from the last lane, which has accumulated the values of
       // each active lane in the wavefront. This will be our new value which we
       // will provide to the atomic operation.
       Value *const LastLaneIdx = B.getInt32(ST->getWavefrontSize() - 1);
       assert(TyBitWidth == 32);
       NewV = B.CreateIntrinsic(Intrinsic::amdgcn_readlane, {},
                                {NewV, LastLaneIdx});
     }
 

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
   }
 };
 }
 
 AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
   : CallLowering(&TLI) {
 }
 
-// FIXME: Compatability shim
+// FIXME: Compatibility shim
 static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc) {
   switch (MIOpc) {
   case TargetOpcode::G_SEXT:
     return ISD::SIGN_EXTEND;
   case TargetOpcode::G_ZEXT:
     return ISD::ZERO_EXTEND;
   case TargetOpcode::G_ANYEXT:
     return ISD::ANY_EXTEND;

llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

 
 bool AMDGPUCodeGenPrepare::visitXor(BinaryOperator &I) {
   // Match the Xor instruction, its type and its operands
   IntrinsicInst *IntrinsicCall = dyn_cast<IntrinsicInst>(I.getOperand(0));
   ConstantInt *RHS = dyn_cast<ConstantInt>(I.getOperand(1));
   if (!RHS || !IntrinsicCall || RHS->getSExtValue() != -1)
     return visitBinaryOperator(I);
 
-  // Check if the Call is an intrinsic intruction to amdgcn_class intrinsic
+  // Check if the Call is an intrinsic instruction to amdgcn_class intrinsic
   // has only one use
   if (IntrinsicCall->getIntrinsicID() != Intrinsic::amdgcn_class ||
       !IntrinsicCall->hasOneUse())
     return visitBinaryOperator(I);
 
   // "Not" the second argument of the intrinsic call
   ConstantInt *Arg = dyn_cast<ConstantInt>(IntrinsicCall->getOperand(1));
   if (!Arg)

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

static bool isNullConstantOrUndef(SDValue V) {
   if (V.isUndef())
     return true;
 
   ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
   return Const != nullptr && Const->isZero();
 }
 
 static bool getConstantValue(SDValue N, uint32_t &Out) {
-  // This is only used for packed vectors, where ussing 0 for undef should
+  // This is only used for packed vectors, where using 0 for undef should
   // always be good.
   if (N.isUndef()) {
     Out = 0;
     return true;
   }
 
   if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
     Out = C->getAPIntValue().getSExtValue();

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 /// input values across multiple registers.  Each item in the Ins array
 /// represents a single value that will be stored in registers.  Ins[x].VT is
 /// the value type of the value that will be stored in the register, so
 /// whatever SDNode we lower the argument to needs to be this type.
 ///
 /// In order to correctly lower the arguments we need to know the size of each
 /// argument.  Since Ins[x].VT gives us the size of the register that will
 /// hold the value, we need to look at Ins[x].ArgVT to see the 'real' type
-/// for the orignal function argument so that we can deduce the correct memory
+/// for the original function argument so that we can deduce the correct memory
 /// type to use for Ins[x].  In most cases the correct memory type will be
 /// Ins[x].ArgVT.  However, this will not always be the case.  If, for example,
 /// we have a kernel argument of type v8i8, this argument will be split into
 /// 8 parts and each part will be represented by its own item in the Ins array.
 /// For each part the Ins[x].ArgVT will be the v8i8, which is the full type of
 /// the argument before it was split.  From this, we deduce that the memory type
 /// for each individual part is i8.  We pass the memory type as LocVT to the
 /// calling convention analysis function and the register type (Ins[x].VT) as
if (!ZeroUndef) {
     NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64);
   }
 
   return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
 }
 
 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
                                                bool Signed) const {
-  // The regular method coverting a 64-bit integer to float roughly consists of
+  // The regular method converting a 64-bit integer to float roughly consists of
   // 2 steps: normalization and rounding. In fact, after normalization, the
   // conversion from a 64-bit integer to a float is essentially the same as the
   // one from a 32-bit integer. The only difference is that it has more
   // trailing bits to be rounded. To leverage the native 32-bit conversion, a
   // 64-bit integer could be preprocessed and fit into a 32-bit integer then
   // converted into the correct float number. The basic steps for the unsigned
   // conversion are illustrated in the following pseudo code:
   //

llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp

if (COffset) {
       }
     }
 
     bool Signed = IID == Intrinsic::amdgcn_sbfe;
 
     if (!CWidth || !COffset)
       break;
 
-    // The case of Width == 0 is handled above, which makes this tranformation
+    // The case of Width == 0 is handled above, which makes this transformation
     // safe.  If Width == 0, then the ashr and lshr instructions become poison
     // value since the shift amount would be equal to the bit size.
     assert(Width != 0);
 
     // TODO: This allows folding to undef when the hardware has specific
     // behavior?
     if (Offset + Width < IntSize) {
       Value *Shl = IC.Builder.CreateShl(Src, IntSize - Offset - Width);

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 }
 
 bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
   unsigned IntrinsicID = I.getIntrinsicID();
   switch (IntrinsicID) {
   case Intrinsic::amdgcn_if_break: {
     MachineBasicBlock *BB = I.getParent();
 
-    // FIXME: Manually selecting to avoid dealiing with the SReg_1 trick
+    // FIXME: Manually selecting to avoid dealing with the SReg_1 trick
     // SelectionDAG uses for wave32 vs wave64.
     BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::SI_IF_BREAK))
       .add(I.getOperand(0))
       .add(I.getOperand(2))
       .add(I.getOperand(3));
 
     Register DstReg = I.getOperand(0).getReg();
     Register Src0Reg = I.getOperand(2).getReg();
Register LiveIn = getFunctionLiveInPhysReg(MF, TII, ReturnAddrReg,
                                              AMDGPU::SReg_64RegClass);
   BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), DstReg)
     .addReg(LiveIn);
   I.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectEndCfIntrinsic(MachineInstr &MI) const {
-  // FIXME: Manually selecting to avoid dealiing with the SReg_1 trick
+  // FIXME: Manually selecting to avoid dealing with the SReg_1 trick
   // SelectionDAG uses for wave32 vs wave64.
   MachineBasicBlock *BB = MI.getParent();
   BuildMI(*BB, &MI, MI.getDebugLoc(), TII.get(AMDGPU::SI_END_CF))
       .add(MI.getOperand(1));
 
   Register Reg = MI.getOperand(1).getReg();
   MI.eraseFromParent();
 

 
 void AMDGPUInstructionSelector::initM0(MachineInstr &I) const {
   const LLT PtrTy = MRI->getType(I.getOperand(1).getReg());
   unsigned AS = PtrTy.getAddressSpace();
   if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) &&
       STI.ldsRequiresM0Init()) {
     MachineBasicBlock *BB = I.getParent();
 
-    // If DS instructions require M0 initializtion, insert it before selecting.
+    // If DS instructions require M0 initialization, insert it before selecting.
     BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
       .addImm(-1);
   }
 }
 
 bool AMDGPUInstructionSelector::selectG_LOAD_STORE_ATOMICRMW(
   MachineInstr &I) const {
   if (I.getOpcode() == TargetOpcode::G_ATOMICRMW_FADD) {

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 
 // Round the number of bits to the next power of two bits
 static LLT getPow2ScalarType(LLT Ty) {
   unsigned Bits = Ty.getSizeInBits();
   unsigned Pow2Bits = 1 <<  Log2_32_Ceil(Bits);
   return LLT::scalar(Pow2Bits);
 }
 
-/// \returs true if this is an odd sized vector which should widen by adding an
+/// \returns true if this is an odd sized vector which should widen by adding an
 /// additional element. This is mostly to handle <3 x s16> -> <4 x s16>. This
 /// excludes s1 vectors, which should always be scalarized.
 static LegalityPredicate isSmallOddVector(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     const LLT Ty = Query.Types[TypeIdx];
     if (!Ty.isVector())
       return false;
 
MachineMemOperand *GOTMMO = MF.getMachineMemOperand(
       MachinePointerInfo::getGOT(MF),
       MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
           MachineMemOperand::MOInvariant,
       LoadTy, Align(8));
 
   buildPCRelGlobalAddress(GOTAddr, PtrTy, B, GV, 0, SIInstrInfo::MO_GOTPCREL32);
 
   if (Ty.getSizeInBits() == 32) {
-    // Truncate if this is a 32-bit constant adrdess.
+    // Truncate if this is a 32-bit constant address.
     auto Load = B.buildLoad(PtrTy, GOTAddr, *GOTMMO);
     B.buildExtract(DstReg, Load, 0);
   } else
     B.buildLoad(DstReg, GOTAddr, *GOTMMO);
 
   MI.eraseFromParent();
   return true;
 }
void AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B,
   Cond = B.buildICmp(CmpInst::ICMP_UGE, S1, R, Y);
   if (DstDivReg)
     B.buildSelect(DstDivReg, Cond, B.buildAdd(S32, Q, One), Q);
 
   if (DstRemReg)
     B.buildSelect(DstRemReg, Cond, B.buildSub(S32, R, Y), R);
 }
 
-// Build integer reciprocal sequence arounud V_RCP_IFLAG_F32
+// Build integer reciprocal sequence around V_RCP_IFLAG_F32
 //
 // Return lo, hi of result
 //
 // %cvt.lo = G_UITOFP Val.lo
 // %cvt.hi = G_UITOFP Val.hi
 // %mad = G_FMAD %cvt.hi, 2**32, %cvt.lo
 // %rcp = G_AMDGPU_RCP_IFLAG %mad
 // %mul1 = G_FMUL %rcp, 0x5f7ffffc

 /// rewritten to use the low half of 32-bit registers, or directly use a packed
 /// layout. 16-bit addresses should also sometimes be packed into 32-bit
 /// registers.
 ///
 /// We don't want to directly select image instructions just yet, but also want
 /// to exposes all register repacking to the legalizer/combiners. We also don't
 /// want a selected instrution entering RegBankSelect. In order to avoid
 /// defining a multitude of intermediate image instructions, directly hack on
-/// the intrinsic's arguments. In cases like a16 addreses, this requires padding
-/// now unnecessary arguments with $noreg.
+/// the intrinsic's arguments. In cases like a16 addresses, this requires
+/// padding now unnecessary arguments with $noreg.
 bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
     MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer,
     const AMDGPU::ImageDimIntrinsicInfo *Intr) const {
 
   const unsigned NumDefs = MI.getNumExplicitDefs();
   const unsigned ArgOffset = NumDefs + 1;
   bool IsTFE = NumDefs == 2;
   // We are only processing the operands of d16 image operations on subtargets
bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
   const LLT LoadResultTy = IsTFE ? TFETy : RoundedTy;
   const int ResultNumRegs = LoadResultTy.getSizeInBits() / 32;
 
   Register NewResultReg = MRI->createGenericVirtualRegister(LoadResultTy);
 
   MI.getOperand(0).setReg(NewResultReg);
 
   // In the IR, TFE is supposed to be used with a 2 element struct return
-  // type. The intruction really returns these two values in one contiguous
+  // type. The instruction really returns these two values in one contiguous
   // register, with one additional dword beyond the loaded data. Rewrite the
   // return type to use a single register result.
 
   if (IsTFE) {
     Dst1Reg = MI.getOperand(1).getReg();
     if (MRI->getType(Dst1Reg) != S32)
       return false;
 
bool AMDGPULegalizerInfo::legalizeTrapHsa(
   B.buildInstr(AMDGPU::S_TRAP)
       .addImm(static_cast<unsigned>(GCNSubtarget::TrapID::LLVMAMDHSATrap));
   MI.eraseFromParent();
   return true;
 }
 
 bool AMDGPULegalizerInfo::legalizeDebugTrapIntrinsic(
     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
-  // Is non-HSA path or trap-handler disabled? then, report a warning
+  // Is non-HSA path or trap-handler disabled? Then, report a warning
   // accordingly
   if (!ST.isTrapHandlerEnabled() ||
       ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
     DiagnosticInfoUnsupported NoTrap(B.getMF().getFunction(),
                                      "debugtrap handler not supported",
                                      MI.getDebugLoc(), DS_Warning);
     LLVMContext &Ctx = B.getMF().getFunction().getContext();
     Ctx.diagnose(NoTrap);

llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp

private:
 
   const TargetMachine *TM;
 
   // -fuse-native.
   bool AllNative = false;
 
   bool useNativeFunc(const StringRef F) const;
 
-  // Return a pointer (pointer expr) to the function if function defintion with
+  // Return a pointer (pointer expr) to the function if function definition with
   // "FuncName" exists. It may create a new function prototype in pre-link mode.
   FunctionCallee getFunction(Module *M, const FuncInfo &fInfo);
 
   // Replace a normal function with its native version.
   bool replaceWithNative(CallInst *CI, const FuncInfo &FInfo);
 
   bool parseFunctionName(const StringRef& FMangledName,
                          FuncInfo *FInfo=nullptr /*out*/);
if (TDOFold(CI, FInfo))
     return true;
 
   // Under unsafe-math, evaluate calls if possible.
   // According to Brian Sumner, we can do this for all f32 function calls
   // using host's double function calls.
   if (isUnsafeMath(CI) && evaluateCall(CI, FInfo))
     return true;
 
-  // Specilized optimizations for each function call
+  // Specialized optimizations for each function call
   switch (FInfo.getId()) {
   case AMDGPULibFunc::EI_RECIP:
     // skip vector function
     assert ((FInfo.getPrefix() == AMDGPULibFunc::NATIVE ||
              FInfo.getPrefix() == AMDGPULibFunc::HALF) &&
             "recip must be an either native or half function");
     return (getVecSize(FInfo) != 1) ? false : fold_recip(CI, B, FInfo);
 
if (CF->isZero()) {
       replaceCall(nval);
       return true;
     }
   }
 
   return false;
 }
 
-// Get a scalar native builtin signle argument FP function
+// Get a scalar native builtin single argument FP function
 FunctionCallee AMDGPULibCalls::getNativeFunction(Module *M,
                                                  const FuncInfo &FInfo) {
   if (getArgType(FInfo) == AMDGPULibFunc::F64 || !HasNative(FInfo.getId()))
     return nullptr;
   FuncInfo nf = FInfo;
   nf.setPrefix(AMDGPULibFunc::NATIVE);
   return getFunction(M, nf);
 }

llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp

 };
 
 const unsigned UnmangledFuncInfo::TableSize =
     array_lengthof(UnmangledFuncInfo::Table);
 
 static AMDGPULibFunc::Param getRetType(AMDGPULibFunc::EFuncId id,
                                        const AMDGPULibFunc::Param (&Leads)[2]) {
   AMDGPULibFunc::Param Res = Leads[0];
-  // TBD - This switch may require to be extended for other intriniscs
+  // TBD - This switch may require to be extended for other intrinsics
   switch (id) {
   case AMDGPULibFunc::EI_SINCOS:
     Res.PtrKind = AMDGPULibFunc::BYVALUE;
     break;
   default:
     break;
   }
   return Res;

 // Note that while types like images, samplers and events are by the ABI encoded
 // using <class-enum-type> production rule they're not used for substitution
 // because clang consider them as builtin types.
 //
 // DvNN_ type is GCC extension for vectors and is a subject for the substitution.
 
 
 class ItaniumMangler {
-  SmallVector<AMDGPULibFunc::Param, 10> Str; // list of accumulated substituions
+  SmallVector<AMDGPULibFunc::Param, 10> Str; // list of accumulated substitutions
   bool  UseAddrSpace;
 
   int findSubst(const AMDGPULibFunc::Param& P) const {
     for(unsigned I = 0; I < Str.size(); ++I) {
       const AMDGPULibFunc::Param& T = Str[I];
       if (P.PtrKind    == T.PtrKind &&
           P.VectorSize == T.VectorSize &&
           P.ArgType    == T.ArgType) {

llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp

removeFromUsedLists(Module &M,
     removeFromUsedList(M, "llvm.compiler.used", LocalVarsSet);
   }
 
   static void markUsedByKernel(IRBuilder<> &Builder, Function *Func,
                                GlobalVariable *SGV) {
     // The llvm.amdgcn.module.lds instance is implicitly used by all kernels
     // that might call a function which accesses a field within it. This is
     // presently approximated to 'all kernels' if there are any such functions
-    // in the module. This implicit use is reified as an explicit use here so
+    // in the module. This implicit use is redefined as an explicit use here so
     // that later passes, specifically PromoteAlloca, account for the required
     // memory without any knowledge of this transform.
 
     // An operand bundle on llvm.donothing works because the call instruction
     // survives until after the last pass that needs to account for LDS. It is
     // better than inline asm as the latter survives until the end of codegen. A
     // totally robust solution would be a function with the same semantics as
     // llvm.donothing that takes a pointer to the instance and is lowered to a

llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

for (auto SI : phiInfoElementGetSources(I)) {
         Sources.push_back(SI.first);
       }
     }
   }
   return FoundSource;
 }
 
 void PHILinearize::addDest(unsigned DestReg, const DebugLoc &DL) {
-  assert(findPHIInfoElement(DestReg) == nullptr && "Dest already exsists");
+  assert(findPHIInfoElement(DestReg) == nullptr && "Dest already exists");
   PHISourcesT EmptySet;
   PHIInfoElementT *NewElement = new PHIInfoElementT();
   NewElement->DestReg = DestReg;
   NewElement->DL = DL;
   NewElement->Sources = EmptySet;
   PHIInfo.insert(NewElement);
 }
 
void LinearizedRegion::storeLiveOuts(RegionMRT *Region,
   auto Children = Region->getChildren();
   for (auto CI : *Children) {
     if (CI->isMBB()) {
       auto MBB = CI->getMBBMRT()->getMBB();
       storeMBBLiveOuts(MBB, MRI, TRI, PHIInfo, TopRegion);
     } else {
       LinearizedRegion *SubRegion = CI->getRegionMRT()->getLinearizedRegion();
       // We should be limited to only store registers that are live out from the
-      // lineaized region
+      // linearized region
       for (auto MBBI : SubRegion->MBBs) {
         storeMBBLiveOuts(MBBI, MRI, TRI, PHIInfo, TopRegion);
       }
     }
   }
 
   if (CurrentTopRegion == nullptr) {
     auto Succ = Region->getSucc();

 void LinearizedRegion::replaceRegister(unsigned Register,
                                        class Register NewRegister,
                                        MachineRegisterInfo *MRI,
                                        bool ReplaceInside, bool ReplaceOutside,
                                        bool IncludeLoopPHI) {
   assert(Register != NewRegister && "Cannot replace a reg with itself");
 
   LLVM_DEBUG(
-      dbgs() << "Pepareing to replace register (region): "
+      dbgs() << "Preparing to replace register (region): "
              << printReg(Register, MRI->getTargetRegisterInfo()) << " with "
              << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n");
 
   // If we are replacing outside, we also need to update the LiveOuts
   if (ReplaceOutside &&
       (isLiveOut(Register) || this->getParent()->isLiveOut(Register))) {
     LinearizedRegion *Current = this;
     while (Current != nullptr && Current->getEntry() != nullptr) {
void AMDGPUMachineCFGStructurizer::extractKilledPHIs(MachineBasicBlock *MBB) {
   // need to do the renaming outside or inside the block.
   SmallPtrSet<MachineInstr *, 2> PHIs;
   for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
                                          E = MBB->instr_end();
        I != E; ++I) {
     MachineInstr &Instr = *I;
     if (Instr.isPHI()) {
       unsigned PHIDestReg = getPHIDestReg(Instr);
-      LLVM_DEBUG(dbgs() << "Extractking killed phi:\n");
+      LLVM_DEBUG(dbgs() << "Extracting killed phi:\n");
       LLVM_DEBUG(Instr.dump());
       PHIs.insert(&Instr);
       PHIInfo.addDest(PHIDestReg, Instr.getDebugLoc());
       storePHILinearizationInfoDest(PHIDestReg, Instr);
     }
   }
 
   for (auto PI : PHIs) {
if ((*PI) != MBB) {
       (MBB)->removeSuccessor(*PI);
     }
   }
 }
 
 static void removeExternalCFGEdges(MachineBasicBlock *StartMBB,
                                    MachineBasicBlock *EndMBB) {
 
-  // We have to check against the StartMBB successor becasuse a
+  // We have to check against the StartMBB successor because a
   // structurized region with a loop will have the entry block split,
   // and the backedge will go to the entry successor.
   DenseSet<std::pair<MachineBasicBlock *, MachineBasicBlock *>> Succs;
   unsigned SuccSize = StartMBB->succ_size();
   if (SuccSize > 0) {
     MachineBasicBlock *StartMBBSucc = *(StartMBB->succ_begin());
     for (MachineBasicBlock::succ_iterator PI = EndMBB->succ_begin(),
                                           E = EndMBB->succ_end();
void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB,
   for (auto OLI : *LiveOuts) {
     OldLiveOuts.push_back(OLI);
   }
 
   for (auto LI : OldLiveOuts) {
     LLVM_DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI));
     if (!containsDef(CodeBB, InnerRegion, LI) ||
         (!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) {
-      // If the register simly lives through the CodeBB, we don't have
+      // If the register simply lives through the CodeBB, we don't have
       // to rewrite anything since the register is not defined in this
       // part of the code.
       LLVM_DEBUG(dbgs() << "- through");
       continue;
     }
     LLVM_DEBUG(dbgs() << "\n");
     unsigned Reg = LI;
     if (/*!PHIInfo.isSource(Reg) &&*/ Reg != InnerRegion->getBBSelectRegOut()) {
       // If the register is live out, we do want to create a phi,
-      // unless it is from the Exit block, becasuse in that case there
+      // unless it is from the Exit block, because in that case there
       // is already a PHI, and no need to create a new one.
 
       // If the register is just a live out def and not part of a phi
       // chain, we need to create a PHI node to handle the if region,
       // and replace all uses outside of the region with the new dest
       // register, unless it is the outgoing BB select register. We have
-      // already creaed phi nodes for these.
+      // already created phi nodes for these.
       const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
       Register PHIDestReg = MRI->createVirtualRegister(RegClass);
       Register IfSourceReg = MRI->createVirtualRegister(RegClass);
       // Create initializer, this value is never used, but is needed
       // to satisfy SSA.
       LLVM_DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n");
       TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(),
                         IfSourceReg, 0);

llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp

bool AMDGPUPrintfRuntimeBindingImpl::shouldPrintAsStr(char Specifier,
   return ElemIType->getBitWidth() == 8;
 }
 
 bool AMDGPUPrintfRuntimeBindingImpl::lowerPrintfForGpu(Module &M) {
   LLVMContext &Ctx = M.getContext();
   IRBuilder<> Builder(Ctx);
   Type *I32Ty = Type::getInt32Ty(Ctx);
   unsigned UniqID = 0;
-  // NB: This is important for this string size to be divizable by 4
+  // NB: This is important for this string size to be divisible by 4
   const char NonLiteralStr[4] = "???";
 
   for (auto CI : Printfs) {
     unsigned NumOps = CI->getNumArgOperands();
 
     SmallString<16> OpConvSpecifiers;
     Value *Op = CI->getArgOperand(0);
 

llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp

 //===--- AMDGPUPropagateAttributes.cpp --------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// \brief This pass propagates attributes from kernels to the non-entry
 /// functions. Most of the library functions were not compiled for specific ABI,
-/// yet will be correctly compiled if proper attrbutes are propagated from the
+/// yet will be correctly compiled if proper attributes are propagated from the
 /// caller.
 ///
 /// The pass analyzes call graph and propagates ABI target features through the
 /// call graph.
 ///
 /// It can run in two modes: as a function or module pass. A function pass
 /// simply propagates attributes. A module pass clones functions if there are
-/// callers with different ABI. If a function is clonned all call sites will
+/// callers with different ABI. If a function is cloned all call sites will
 /// be updated to use a correct clone.
 ///
 /// A function pass is limited in functionality but can run early in the
 /// pipeline. A module pass is more powerful but has to run late, so misses
 /// library folding opportunities.
 //
 //===----------------------------------------------------------------------===//
 
public:
 
   // Use F as a root and propagate its attributes.
   bool process(Function &F);
 
   // Propagate attributes starting from kernel functions.
   bool process(Module &M);
 };
 
-// Allows to propagate attributes early, but no clonning is allowed as it must
+// Allows to propagate attributes early, but no cloning is allowed as it must
 // be a function pass to run before any optimizations.
 // TODO: We shall only need a one instance of module pass, but that needs to be
 // in the linker pipeline which is currently not possible.
 class AMDGPUPropagateAttributesEarly : public FunctionPass {
   const TargetMachine *TM;
 
 public:
   static char ID; // Pass identification
 
   AMDGPUPropagateAttributesEarly(const TargetMachine *TM = nullptr) :
     FunctionPass(ID), TM(TM) {
     initializeAMDGPUPropagateAttributesEarlyPass(
       *PassRegistry::getPassRegistry());
   }
 
   bool runOnFunction(Function &F) override;
 };
 
-// Allows to propagate attributes with clonning but does that late in the
+// Allows to propagate attributes with cloning but does that late in the
 // pipeline.
 class AMDGPUPropagateAttributesLate : public ModulePass {
   const TargetMachine *TM;
 
 public:
   static char ID; // Pass identification
 
   AMDGPUPropagateAttributesLate(const TargetMachine *TM = nullptr) :
for (auto &F : M.functions()) {
             NewRoots.insert(&F);
           continue;
         }
 
         Function *NewF = findFunction(CallerProps, &F);
         if (!NewF) {
           const FnProperties NewProps = CalleeProps.adjustToCaller(CallerProps);
           if (!AllowClone) {
-            // This may set different features on different iteartions if
+            // This may set different features on different iterations if
             // there is a contradiction in callers' attributes. In this case
             // we rely on a second pass running on Module, which is allowed
             // to clone.
             setFeatures(F, NewProps.Features);
             setAttributes(F, NewProps.Attributes);
             NewRoots.insert(&F);
             Changed = true;
             break;

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

 /// instructions). This is one unique SGPR, so the same SGPR may be used for
 /// multiple operands. From a register bank perspective, any combination of
 /// operands should be legal as an SGPR, but this is contextually dependent on
 /// the SGPR operands all being the same register. There is therefore optimal to
 /// choose the SGPR with the most uses to minimize the number of copies.
 ///
 /// We avoid trying to solve this problem in RegBankSelect. Any VALU G_*
 /// operation should have its source operands all mapped to VGPRs (except for
-/// VCC), inserting copies from any SGPR operands. This the most trival legal
+/// VCC), inserting copies from any SGPR operands. This the most trivial legal
 /// mapping. Anything beyond the simplest 1:1 instruction selection would be too
 /// complicated to solve here. Every optimization pattern or instruction
 /// selected to multiple outputs would have to enforce this rule, and there
 /// would be additional complexity in tracking this rule for every G_*
 /// operation. By forcing all inputs to VGPRs, it also simplifies the task of
 /// picking the optimal operand combination from a post-isel optimization pass.
 ///
 //===----------------------------------------------------------------------===//
public:
 
   /// Set any registers that don't have a set register class or bank to SALU.
   void applyBank(MachineInstr &MI) {
     const unsigned Opc = MI.getOpcode();
     if (Opc == AMDGPU::G_ANYEXT || Opc == AMDGPU::G_ZEXT ||
         Opc == AMDGPU::G_SEXT) {
       // LegalizerHelper wants to use the basic legalization artifacts when
       // widening etc. We don't handle selection with vcc in artifact sources,
-      // so we need to use a sslect instead to handle these properly.
+      // so we need to use a select instead to handle these properly.
       Register DstReg = MI.getOperand(0).getReg();
       Register SrcReg = MI.getOperand(1).getReg();
       const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI);
       if (SrcBank == &AMDGPU::VCCRegBank) {
         const LLT S32 = LLT::scalar(32);
         assert(MRI.getType(SrcReg) == LLT::scalar(1));
         assert(MRI.getType(DstReg) == S32);
         assert(NewBank == &AMDGPU::VGPRRegBank);
AMDGPURegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
                                                LLT Ty) const {
   if (&RC == &AMDGPU::SReg_1RegClass)
     return AMDGPU::VCCRegBank;
 
   // We promote real scalar booleans to SReg_32. Any SGPR using s1 is really a
   // VCC-like use.
   if (TRI->isSGPRClass(&RC)) {
     // FIXME: This probably came from a copy from a physical register, which
-    // should be inferrrable from the copied to-type. We don't have many boolean
+    // should be inferable from the copied to-type. We don't have many boolean
     // physical register constraints so just assume a normal SGPR for now.
     if (!Ty.isValid())
       return AMDGPU::SGPRRegBank;
 
     return Ty == LLT::scalar(1) ? AMDGPU::VCCRegBank : AMDGPU::SGPRRegBank;
   }
 
   return TRI->isAGPRClass(&RC) ? AMDGPU::AGPRRegBank : AMDGPU::VGPRRegBank;
bool AMDGPURegisterBankInfo::applyMappingSBufferLoad(
   const RegisterBank *RSrcBank =
     OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
   const RegisterBank *OffsetBank =
     OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
   if (RSrcBank == &AMDGPU::SGPRRegBank &&
       OffsetBank == &AMDGPU::SGPRRegBank)
     return true; // Legal mapping
 
-  // FIXME: 96-bit case was widened during legalize. We neeed to narrow it back
+  // FIXME: 96-bit case was widened during legalize. We need to narrow it back
   // here but don't have an MMO.
 
   unsigned LoadSize = Ty.getSizeInBits();
   int NumLoads = 1;
   if (LoadSize == 256 || LoadSize == 512) {
     NumLoads = LoadSize / 128;
     Ty = Ty.divide(NumLoads);
   }
 
   // Use the alignment to ensure that the required offsets will fit into the
   // immediate offsets.
   const Align Alignment = NumLoads > 1 ? Align(16 * NumLoads) : Align(1);
 
   MachineIRBuilder B(MI);
   MachineFunction &MF = B.getMF();
 
   Register SOffset;
   Register VOffset;
   int64_t ImmOffset = 0;
 
   unsigned MMOOffset = setBufferOffsets(B, *this, MI.getOperand(2).getReg(),
                                         VOffset, SOffset, ImmOffset, Alignment);
 
   // TODO: 96-bit loads were widened to 128-bit results. Shrink the result if we
-  // can, but we neeed to track an MMO for that.
+  // can, but we need to track an MMO for that.
   const unsigned MemSize = (Ty.getSizeInBits() + 7) / 8;
   const Align MemAlign(4); // FIXME: ABI type alignment?
   MachineMemOperand *BaseMMO = MF.getMachineMemOperand(
     MachinePointerInfo(),
     MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
     MachineMemOperand::MOInvariant,
     MemSize, MemAlign);
   if (MMOOffset != 0)
case AMDGPU::G_PHI: {
     const LLT S32 = LLT::scalar(32);
     const RegisterBank *DstBank =
       OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
     if (DstBank == &AMDGPU::VCCRegBank) {
       applyDefaultMapping(OpdMapper);
       // The standard handling only considers the result register bank for
       // phis. For VCC, blindly inserting a copy when the phi is lowered will
       // produce an invalid copy. We can only copy with some kind of compare to
-      // get a vector boolean result. Insert a regitser bank copy that will be
+      // get a vector boolean result. Insert a register bank copy that will be
       // correctly lowered to a compare.
       MachineIRBuilder B(*MI.getParent()->getParent());
 
       for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
         Register SrcReg = MI.getOperand(I).getReg();
         const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
 
         if (SrcBank != &AMDGPU::VCCRegBank) {
if (MustBeSGPR) {
       // Some operands must be VGPR, and these are easy to copy to.
       OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
     }
   }
 
   return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping), NumOps);
 }
 
-/// Return the mapping for a pointer arugment.
+/// Return the mapping for a pointer argument.
 const RegisterBankInfo::ValueMapping *
 AMDGPURegisterBankInfo::getValueMappingForPtr(const MachineRegisterInfo &MRI,
                                               Register PtrReg) const {
   LLT PtrTy = MRI.getType(PtrReg);
   unsigned Size = PtrTy.getSizeInBits();
   if (Subtarget.useFlatForGlobal() ||
       !AMDGPU::isFlatGlobalAddrSpace(PtrTy.getAddressSpace()))
     return AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);

llvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp

LDSGlobals.erase(std::remove_if(LDSGlobals.begin(), LDSGlobals.end(),
                      LDSGlobals.end());
 
     return LDSGlobals;
   }
 
   // Returns true if uses of given LDS global within non-kernel functions should
   // be keep as it is without pointer replacement.
   bool shouldIgnorePointerReplacement(GlobalVariable *GV) {
-    // LDS whose size is very small and doesn`t exceed pointer size is not worth
+    // LDS whose size is very small and doesn't exceed pointer size is not worth
     // replacing.
     if (DL.getTypeAllocSize(GV->getValueType()) <= 2)
       return true;
 
     // LDS which is not used from non-kernel function scope or it is used from
     // global scope does not qualify for replacement.
     LDSToNonKernels[GV] = AMDGPU::collectNonKernelAccessorsOfLDS(GV);
     return LDSToNonKernels[GV].empty();
 
     // FIXME: When GV is used within all (or within most of the kernels), then
     // it does not make sense to create a pointer for it.
   }
 
   // Insert new global LDS pointer which points to LDS.
   GlobalVariable *createLDSPointer(GlobalVariable *GV) {
-    // LDS pointer which points to LDS is already created? return it.
+    // LDS pointer which points to LDS is already created? Return it.
     auto PointerEntry = LDSToPointer.insert(std::make_pair(GV, nullptr));
     if (!PointerEntry.second)
       return PointerEntry.first->second;
 
     // We need to create new LDS pointer which points to LDS.
     //
     // Each CU owns at max 64K of LDS memory, so LDS address ranges from 0 to
     // 2^16 - 1. Hence 16 bit pointer is enough to hold the LDS address.
GlobalVariable *createLDSPointer(GlobalVariable *GV) {
     LDSToPointer[GV] = LDSPointer;
 
     return LDSPointer;
   }
 
   // Split entry basic block in such a way that only lane 0 of each wave does
   // the LDS pointer initialization, and return newly created basic block.
   BasicBlock *activateLaneZero(Function *K) {
-    // If the entry basic block of kernel K is already splitted, then return
+    // If the entry basic block of kernel K is already split, then return
     // newly created basic block.
     auto BasicBlockEntry = KernelToInitBB.insert(std::make_pair(K, nullptr));
     if (!BasicBlockEntry.second)
       return BasicBlockEntry.first->second;
 
     // Split entry basic block of kernel K.
     auto *EI = &(*(K->getEntryBlock().getFirstInsertionPt()));
     IRBuilder<> Builder(EI);
 
     Value *Mbcnt =
         Builder.CreateIntrinsic(Intrinsic::amdgcn_mbcnt_lo, {},
                                 {Builder.getInt32(-1), Builder.getInt32(0)});
     Value *Cond = Builder.CreateICmpEQ(Mbcnt, Builder.getInt32(0));
     Instruction *WB = cast<Instruction>(
         Builder.CreateIntrinsic(Intrinsic::amdgcn_wave_barrier, {}, {}));
 
     BasicBlock *NBB = SplitBlockAndInsertIfThen(Cond, WB, false)->getParent();
 
-    // Mark that the entry basic block of kernel K is splitted.
+    // Mark that the entry basic block of kernel K is split.
     KernelToInitBB[K] = NBB;
 
     return NBB;
   }
 
   // Within given kernel, initialize given LDS pointer to point to given LDS.
   void initializeLDSPointer(Function *K, GlobalVariable *GV,
                             GlobalVariable *LDSPointer) {
void initializeLDSPointer(Function *K, GlobalVariable *GV,
     Builder.CreateStore(Builder.CreatePtrToInt(GV, Type::getInt16Ty(Ctx)),
                         LDSPointer);
 
     // Mark that LDS pointer is initialized within kernel K.
     KernelToLDSPointers[K].insert(LDSPointer);
   }
 
   // We have created an LDS pointer for LDS, and initialized it to point-to LDS
-  // within all relevent kernels. Now replace all the uses of LDS within
+  // within all relevant kernels. Now replace all the uses of LDS within
   // non-kernel functions by LDS pointer.
   void replaceLDSUseByPointer(GlobalVariable *GV, GlobalVariable *LDSPointer) {
     SmallVector<User *, 8> LDSUsers(GV->users());
     for (auto *U : LDSUsers) {
       // When `U` is a constant expression, it is possible that same constant
       // expression exists within multiple instructions, and within multiple
       // non-kernel functions. Collect all those non-kernel functions and all
       // those instructions within which `U` exist.
for (auto *U : LDSUsers) {
             UserInsts.insert(I);
           } else {
             // `U` is a constant expression, convert it into corresponding set
             // of instructions.
             auto *CE = cast<ConstantExpr>(U);
             convertConstantExprsToInstructions(I, CE, &UserInsts);
           }
 
-          // Go through all the user instrutions, if LDS exist within them as an
-          // operand, then replace it by replace instruction.
+          // Go through all the user instructions, if LDS exist within them as
+          // an operand, then replace it by replace instruction.
           for (auto *II : UserInsts) {
             auto *ReplaceInst = getReplacementInst(F, GV, LDSPointer);
             II->replaceUsesOfWith(GV, ReplaceInst);
           }
         }
       }
     }
   }
bool ReplaceLDSUseImpl::replaceLDSUse(GlobalVariable *GV) {
   }
 
   // We have not found reachable and LDS used callees for any of the kernels,
   // and hence we have not created LDS pointer.
   if (!LDSPointer)
     return false;
 
   // We have created an LDS pointer for LDS, and initialized it to point-to LDS
-  // within all relevent kernels. Now replace all the uses of LDS within
+  // within all relevant kernels. Now replace all the uses of LDS within
   // non-kernel functions by LDS pointer.
   replaceLDSUseByPointer(GV, LDSPointer);
 
   return true;
 }
 
 // Entry-point function which interface ReplaceLDSUseImpl with outside of the
 // class.

llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp

if (!SI) {
 
       // We could handle these if we had a convenient way to bitcast between
       // them.
       Type *SrcEltTy = Arg.getType()->getPointerElementType();
       if (SrcEltTy->isArrayTy())
         return false;
 
       // Special case handle structs with single members. It is useful to handle
       // some casts between structs and non-structs, but we can't bitcast
-      // directly between them.  directly bitcast between them.  Blender uses
-      // some casts that look like { <3 x float> }* to <4 x float>*
+      // directly between them. Blender uses some casts that look like
+      // { <3 x float> }* to <4 x float>*
       if ((SrcEltTy->isStructTy() && (SrcEltTy->getStructNumElements() != 1)))
         return false;
 
       // Clang emits OpenCL 3-vector type accesses with a bitcast to the
       // equivalent 4-element vector and accesses that, and we're looking for
       // this pointer cast.
       if (DL->getTypeAllocSize(SrcEltTy) != DL->getTypeAllocSize(DestEltTy))
         return false;
bool AMDGPURewriteOutArguments::runOnFunction(Function &F) {
 
   bool Changing;
 
   do {
     Changing = false;
 
     // Keep retrying if we are able to successfully eliminate an argument. This
     // helps with cases with multiple arguments which may alias, such as in a
-    // sincos implemntation. If we have 2 stores to arguments, on the first
+    // sincos implementation. If we have 2 stores to arguments, on the first
     // attempt the MDA query will succeed for the second store but not the
     // first. On the second iteration we've removed that out clobbering argument
     // (by effectively moving it into another function) and will find the second
     // argument is OK to move.
     for (Argument *OutArg : OutArgs) {
       bool ThisReplaceable = true;
       SmallVector<std::pair<ReturnInst *, StoreInst *>, 4> ReplaceableStores;
 

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

while (!Preds.empty()) {
       for (const SDep &SI : SU->Preds)
         if (SI.getSUnit() != SU && !Visited.count(SI.getSUnit()))
           Preds.push_back(SI.getSUnit());
     }
 
     return true;
   }
 
-  // Link as much SALU intructions in chain as possible. Return the size
+  // Link as many SALU instructions in chain as possible. Return the size
   // of the chain. Links up to MaxChain instructions.
   unsigned linkSALUChain(SUnit *From, SUnit *To, unsigned MaxChain,
                          SmallPtrSetImpl<SUnit *> &Visited) const {
     SmallVector<SUnit *, 8> Worklist({To});
     unsigned Linked = 0;
 
     while (!Worklist.empty() && MaxChain-- > 0) {
       SUnit *SU = Worklist.pop_back_val();

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
   else
     addPass(createEarlyCSEPass());
 }
 
 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
   addPass(createLICMPass());
   addPass(createSeparateConstOffsetFromGEPPass());
   addPass(createSpeculativeExecutionPass());
-  // ReassociateGEPs exposes more opportunites for SLSR. See
+  // ReassociateGEPs exposes more opportunities for SLSR. See
   // the example in reassociate-geps-and-slsr.ll.
   addPass(createStraightLineStrengthReducePass());
   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
   // EarlyCSE can reuse.
   addEarlyCSEOrGVNPass();
   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
   addPass(createNaryReassociatePass());
   // NaryReassociate on GEPs creates redundant common expressions, so run
bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
   if (!usingDefaultRegAlloc())
     report_fatal_error(RegAllocOptNotSupportedMessage);
 
   addPass(createSGPRAllocPass(true));
 
   // Commit allocated register changes. This is mostly necessary because too
   // many things rely on the use lists of the physical registers, such as the
   // verifier. This is only necessary with allocators which use LiveIntervals,
-  // since FastRegAlloc does the replacments itself.
+  // since FastRegAlloc does the replacements itself.
   addPass(createVirtRegRewriter(false));
 
   // Equivalent of PEI for SGPRs.
   addPass(&SILowerSGPRSpillsID);
 
   addPass(createVGPRAllocPass(true));
 
   addPreRewrite();