AMDGPU/GlobalISel: Add isel patterns for min3 and max3

[foad]

AMDGPU/GlobalISel: Add min3 and max3 combines

These are not combines, and it looks like they work for SelectionDAG as well as GlobalISel?

[foad]

If they do work for SelectionDAG as well, maybe move your new test out of the GlobalISel/ directory and run it for both instruction selectors?

[Petar.Avramovic]

Dag does this in dag-combiner. For GlobalISel combine would be in regbankcombiner (we need banks to not combine for uniform min and max) which runs just before isel. And since it is simple to match I did this in tablegen.
I will check if this works for sdag without regressions.

[Petar.Avramovic]

Remove min3 and max3 combine from sdag path, use isel patterns. I am not sure about this for sdag, generated code looks worse. I could move this to the post-regbankcombiner for global-isel.
Notable test changes:

• ieee = true : quieting(fcanonicalize) of operands that go in min3/max3. This is because min/max legalization happens, originally combine would make min3/max3 before legalizing.
• uniform ctlz/cttz lowering : isel selects uniform min/max thus no min3/max3. SI Fix SGPR copies turns this into v_min/v_max and it looks like a regression.

[Petar.Avramovic]

Rebase and ping.

[arsenm]

My main worry here would be the constant bus restriction handling. Can you add tests for every permutation of SGPR and VGPR operands?

[arsenm]

In D109969#3196114, @arsenm wrote:

My main worry here would be the constant bus restriction handling. Can you add tests for every permutation of SGPR and VGPR operands?

I'm pretty sure these already exist for the DAG path, should be able to just copy them

[foad]

As discussed offline, can min3/max3 use the existing ThreeOpFrag that is already used for other cases like add3 and or3?

As a separate improvement, SITargetLowering::reassociateScalarOps is currently only used for add but could also be used for and/or/xor/min/max/...

[foad]

llvm/test/CodeGen/AMDGPU/ctlz.ll

579–580

Regression here.

llvm/test/CodeGen/AMDGPU/max3.ll

264

Please precommit new tests like this.

[Petar.Avramovic]

Use ThreeOpFrag for integer min3 and max3.
Floating point min3 and max3 use regular pattern since Tablegen does not support complex pattern (VOP3Mods) inside PatFrag which would count sgpr operands. There should not be many cases where this would make a big difference since sgpr float operands come as function arguments or uniform loads, there are no uniform versions of floating point instructions.
There should be no constant bus restriction errors (sdag also takes care of cst_bus_restrictions when it prints mir from selected DAG)

• integer min/max3 ThreeOpFrag handles cst_bus_restrictions
• float min/max3
  • sdag deals with cst_bus_restrictions when it prints mir from selected DAG
  • globalisel all float min/max3 operands are set to vgpr by regbankselect

Improve test coverage and add precommit for new tests.

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

bool AMDGPUDAGToDAGISel::fp16SrcZerosHighBits(unsigned Opc) const {
   case ISD::FROUND:
   case ISD::FFLOOR:
   case ISD::FMINNUM:
   case ISD::FMAXNUM:
   case AMDGPUISD::FRACT:
   case AMDGPUISD::CLAMP:
   case AMDGPUISD::COS_HW:
   case AMDGPUISD::SIN_HW:
-  case AMDGPUISD::FMIN3:
-  case AMDGPUISD::FMAX3:
   case AMDGPUISD::FMED3:
   case AMDGPUISD::FMAD_FTZ:
   case AMDGPUISD::RCP:
   case AMDGPUISD::RSQ:
   case AMDGPUISD::RCP_IFLAG:
   case AMDGPUISD::LDEXP:
     // On gfx10, all 16-bit instructions preserve the high bits.
     return Subtarget->getGeneration() <= AMDGPUSubtarget::GFX9;

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

enum NodeType : unsigned {
 
   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
   // Denormals handled on some parts.
   COS_HW,
   SIN_HW,
   FMAX_LEGACY,
   FMIN_LEGACY,
 
-  FMAX3,
-  SMAX3,
-  UMAX3,
-  FMIN3,
-  SMIN3,
-  UMIN3,
   FMED3,
   SMED3,
   UMED3,
   FDOT2,
   URECIP,
   DIV_SCALE,
   DIV_FMAS,
   DIV_FIXUP,

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
   NODE_NAME_CASE(DENORM_MODE)
   NODE_NAME_CASE(FMA_W_CHAIN)
   NODE_NAME_CASE(FMUL_W_CHAIN)
   NODE_NAME_CASE(CLAMP)
   NODE_NAME_CASE(COS_HW)
   NODE_NAME_CASE(SIN_HW)
   NODE_NAME_CASE(FMAX_LEGACY)
   NODE_NAME_CASE(FMIN_LEGACY)
-  NODE_NAME_CASE(FMAX3)
-  NODE_NAME_CASE(SMAX3)
-  NODE_NAME_CASE(UMAX3)
-  NODE_NAME_CASE(FMIN3)
-  NODE_NAME_CASE(SMIN3)
-  NODE_NAME_CASE(UMIN3)
   NODE_NAME_CASE(FMED3)
   NODE_NAME_CASE(SMED3)
   NODE_NAME_CASE(UMED3)
   NODE_NAME_CASE(FDOT2)
   NODE_NAME_CASE(URECIP)
   NODE_NAME_CASE(DIV_SCALE)
   NODE_NAME_CASE(DIV_FMAS)
   NODE_NAME_CASE(DIV_FIXUP)
bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
   case AMDGPUISD::FMUL_LEGACY:
   case AMDGPUISD::CVT_PKRTZ_F16_F32: {
     if (SNaN)
       return true;
     return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
            DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
   }
   case AMDGPUISD::FMED3:
-  case AMDGPUISD::FMIN3:
-  case AMDGPUISD::FMAX3:
   case AMDGPUISD::FMAD_FTZ: {
     if (SNaN)
       return true;
     return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
            DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
            DAG.isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
   }
   case AMDGPUISD::CVT_F32_UBYTE0:

llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td

def AMDGPUfmul_legacy_impl : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
   [SDNPCommutative, SDNPAssociative]
 >;
 
 // out = min(a, b) a and b are floats, where a nan comparison fails.
 def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
   []
 >;
 
-// FIXME: TableGen doesn't like commutative instructions with more
-// than 2 operands.
-// out = max(a, b, c) a, b and c are floats
-def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
-  [/*SDNPCommutative, SDNPAssociative*/]
->;
-
-// out = max(a, b, c) a, b, and c are signed ints
-def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
-  [/*SDNPCommutative, SDNPAssociative*/]
->;
-
-// out = max(a, b, c) a, b and c are unsigned ints
-def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
-  [/*SDNPCommutative, SDNPAssociative*/]
->;
-
-// out = min(a, b, c) a, b and c are floats
-def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
-  [/*SDNPCommutative, SDNPAssociative*/]
->;
-
-// out = min(a, b, c) a, b and c are signed ints
-def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
-  [/*SDNPCommutative, SDNPAssociative*/]
->;
-
-// out = min(a, b) a and b are unsigned ints
-def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
-  [/*SDNPCommutative, SDNPAssociative*/]
->;
-
 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
 def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
 
 // out = (src1 > src0) ? 1 : 0
 def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
 
 def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
   SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>

llvm/lib/Target/AMDGPU/GCNSubtarget.h

public:
   bool hasFFBH() const {
     return true;
   }
 
   bool hasMed3_16() const {
     return getGeneration() >= AMDGPUSubtarget::GFX9;
   }
 
-  bool hasMin3Max3_16() const {
-    return getGeneration() >= AMDGPUSubtarget::GFX9;
-  }
-
   bool hasFmaMixInsts() const {
     return HasFmaMixInsts;
   }
 
   bool hasCARRY() const {
     return true;
   }
 

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,
   case ISD::FSINCOS:
     return Op.getValueType().getScalarType() != MVT::f16;
 
   case ISD::FMINNUM:
   case ISD::FMAXNUM:
   case ISD::FMINNUM_IEEE:
   case ISD::FMAXNUM_IEEE:
   case AMDGPUISD::CLAMP:
-  case AMDGPUISD::FMED3:
-  case AMDGPUISD::FMAX3:
-  case AMDGPUISD::FMIN3: {
+  case AMDGPUISD::FMED3: {
     // FIXME: Shouldn't treat the generic operations different based these.
     // However, we aren't really required to flush the result from
     // minnum/maxnum..
 
     // snans will be quieted, so we only need to worry about denormals.
     if (Subtarget->supportsMinMaxDenormModes() ||
         denormalsEnabledForType(DAG, Op.getValueType()))
       return true;
if (CRHS && N0.hasOneUse()) {
 
       return DAG.getNode(N0.getOpcode(), SL, VT, Canon0, Canon1);
     }
   }
 
   return isCanonicalized(DAG, N0) ? N0 : SDValue();
 }
 
-static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
-  switch (Opc) {
-  case ISD::FMAXNUM:
-  case ISD::FMAXNUM_IEEE:
-    return AMDGPUISD::FMAX3;
-  case ISD::SMAX:
-    return AMDGPUISD::SMAX3;
-  case ISD::UMAX:
-    return AMDGPUISD::UMAX3;
-  case ISD::FMINNUM:
-  case ISD::FMINNUM_IEEE:
-    return AMDGPUISD::FMIN3;
-  case ISD::SMIN:
-    return AMDGPUISD::SMIN3;
-  case ISD::UMIN:
-    return AMDGPUISD::UMIN3;
-  default:
-    llvm_unreachable("Not a min/max opcode");
-  }
-}
-
 SDValue SITargetLowering::performIntMed3ImmCombine(
   SelectionDAG &DAG, const SDLoc &SL,
   SDValue Op0, SDValue Op1, bool Signed) const {
   ConstantSDNode *K1 = dyn_cast<ConstantSDNode>(Op1);
   if (!K1)
     return SDValue();
 
   ConstantSDNode *K0 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
   EVT VT = N->getValueType(0);
   unsigned Opc = N->getOpcode();
   SDValue Op0 = N->getOperand(0);
   SDValue Op1 = N->getOperand(1);
 
   // Only do this if the inner op has one use since this will just increases
   // register pressure for no benefit.
 
-  if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY &&
-      !VT.isVector() &&
-      (VT == MVT::i32 || VT == MVT::f32 ||
-       ((VT == MVT::f16 || VT == MVT::i16) && Subtarget->hasMin3Max3_16()))) {
-    // max(max(a, b), c) -> max3(a, b, c)
-    // min(min(a, b), c) -> min3(a, b, c)
-    if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
-      SDLoc DL(N);
-      return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
-                         DL,
-                         N->getValueType(0),
-                         Op0.getOperand(0),
-                         Op0.getOperand(1),
-                         Op1);
-    }
-
-    // Try commuted.
-    // max(a, max(b, c)) -> max3(a, b, c)
-    // min(a, min(b, c)) -> min3(a, b, c)
-    if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
-      SDLoc DL(N);
-      return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
-                         DL,
-                         N->getValueType(0),
-                         Op0,
-                         Op1.getOperand(0),
-                         Op1.getOperand(1));
-    }
-  }
-
   // min(max(x, K0), K1), K0 < K1 -> med3(x, K0, K1)
   if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
     if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, true))
       return Med3;
   }
 
   if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
     if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, false))

llvm/lib/Target/AMDGPU/VOP3Instructions.td

 defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
 defm V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
 defm V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>;
 defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
 
 // XXX - No FPException seems suspect but manual doesn't say it does
 let mayRaiseFPException = 0 in {
   let isCommutable = 1 in {
-    defm V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
-    defm V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
-    defm V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
-    defm V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
+    defm V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
+    defm V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
+    defm V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
+    defm V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
     defm V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
     defm V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
   } // End isCommutable = 1
-  defm V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
-  defm V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
+  defm V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
+  defm V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
   defm V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
 } // End mayRaiseFPException = 0
 
 let isCommutable = 1 in {
   defm V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
   defm V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
   defm V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
   defm V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
for (unsigned i = 0; i < 3; ++i) {
         if (++ConstantBusUses > ConstantBusLimit)
           return false;
       }
     }
     return true;
   }];
 }
 
+class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat <
+  // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions.
+  (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2),
+  (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
+>;
+
 let SubtargetPredicate = isGFX9Plus in {
 let isCommutable = 1, isReMaterializable = 1 in {
   defm V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
   defm V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
   defm V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
   defm V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
   defm V_ADD_I32 : VOP3Inst <"v_add_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>;
   defm V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
 } // End isCommutable = 1, isReMaterializable = 1
 // TODO src0 contains the opsel bit for dst, so if we commute, need to mask and swap this
 // to the new src0.
 defm V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>;
 defm V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>;
 defm V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>;
 
-defm V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>;
-defm V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>;
-defm V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>;
-
-defm V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>;
-defm V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>;
-defm V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>;
+defm V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
+defm V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
+defm V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
+
+defm V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
+defm V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
+defm V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
 
 defm V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
 defm V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
 
 defm V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
 defm V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
 
 defm V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
 defm V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
 
 defm V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
 
 let isReMaterializable = 1 in {
 defm V_SUB_I32 : VOP3Inst <"v_sub_i32", VOP3_Profile<VOP_I32_I32_I32_ARITH>>;
 defm V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
 defm V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
 } // End isReMaterializable = 1
 
-
-class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat <
-  // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions.
-  (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2),
-  (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
->;
-
 def : ThreeOp_i32_Pats<cshl_32, add, V_LSHL_ADD_U32_e64>;
 def : ThreeOp_i32_Pats<add, cshl_32, V_ADD_LSHL_U32_e64>;
 def : ThreeOp_i32_Pats<add, add, V_ADD3_U32_e64>;
 def : ThreeOp_i32_Pats<cshl_32, or, V_LSHL_OR_B32_e64>;
 def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32_e64>;
 def : ThreeOp_i32_Pats<or, or, V_OR3_B32_e64>;
 def : ThreeOp_i32_Pats<xor, add, V_XAD_U32_e64>;
 
(node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)),
        (i16 (VOP3OpSel i16:$src1, i32:$src1_modifiers))),
   (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0)
 >;
 
 def : OpSelBinOpClampPat<saddsat, V_ADD_I16_e64>;
 def : OpSelBinOpClampPat<ssubsat, V_SUB_I16_e64>;
 } // End SubtargetPredicate = isGFX9Plus
 
+class ThreeOp_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
+                        Instruction inst> : GCNPat <
+  (ThreeOpFrag<op1, op2> i16:$src0, i16:$src1, i16:$src2),
+  (inst SRCMODS.NONE, i16:$src0, SRCMODS.NONE, i16:$src1,
+        SRCMODS.NONE, i16:$src2, DSTCLAMP.NONE, DSTOMOD.NONE)
+>;
+
+class ThreeOpFP_Pats<ValueType vt, SDPatternOperator op1, SDPatternOperator op2,
+                     Instruction inst> : GCNPat <
+  (DivergentBinFrag<op1> (HasOneUseBinOp<op2>
+                          (VOP3Mods vt:$src0, i32:$src0_mods),
+                          (VOP3Mods vt:$src1, i32:$src1_mods)),
+                         (vt (VOP3Mods vt:$src2, i32:$src2_mods))),
+  (inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
+        DSTCLAMP.NONE, DSTOMOD.NONE)
+>;
+
+def : ThreeOp_i32_Pats<smin, smin, V_MIN3_I32_e64>;
+def : ThreeOp_i32_Pats<umin, umin, V_MIN3_U32_e64>;
+def : ThreeOp_i32_Pats<smax, smax, V_MAX3_I32_e64>;
+def : ThreeOp_i32_Pats<umax, umax, V_MAX3_U32_e64>;
+def : ThreeOpFP_Pats<f32, fminnum_like, fminnum_like, V_MIN3_F32_e64>;
+def : ThreeOpFP_Pats<f32, fmaxnum_like, fmaxnum_like, V_MAX3_F32_e64>;
+
+let SubtargetPredicate = isGFX9Plus in {
+def : ThreeOp_i16_Pats<smin, smin, V_MIN3_I16_e64>;
+def : ThreeOp_i16_Pats<umin, umin, V_MIN3_U16_e64>;
+def : ThreeOp_i16_Pats<smax, smax, V_MAX3_I16_e64>;
+def : ThreeOp_i16_Pats<umax, umax, V_MAX3_U16_e64>;
+def : ThreeOpFP_Pats<f16, fminnum_like, fminnum_like, V_MIN3_F16_e64>;
+def : ThreeOpFP_Pats<f16, fmaxnum_like, fmaxnum_like, V_MAX3_F16_e64>;
+}
+
 def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> {
   let Src0RC64 = VRegSrc_32;
   let Src1RC64 = SCSrc_b32;
   let Src2RC64 = SCSrc_b32;
   let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
                           IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1,
                           IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2,
                           VGPR_32:$vdst_in, op_sel0:$op_sel);

llvm/test/CodeGen/AMDGPU/GlobalISel/fmax3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI_VI,SI %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI_VI,VI %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX10 %s
 
 define float @test_max3_f32_ieee_true(float %a, float %b, float %c) {
 ; SI_VI-LABEL: test_max3_f32_ieee_true:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI_VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0
 ; SI_VI-NEXT:    v_mul_f32_e32 v1, 1.0, v1
-; SI_VI-NEXT:    v_max_f32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_mul_f32_e32 v1, 1.0, v2
-; SI_VI-NEXT:    v_max_f32_e32 v0, v0, v1
+; SI_VI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
+; SI_VI-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_f32_ieee_true:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_max_f32_e32 v0, v0, v0
 ; GFX9-NEXT:    v_max_f32_e32 v1, v1, v1
-; GFX9-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_f32_e32 v1, v2, v2
-; GFX9-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX9-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX9-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_f32_ieee_true:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
 ; GFX10-NEXT:    v_max_f32_e32 v1, v1, v1
-; GFX10-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_f32_e32 v1, v2, v2
-; GFX10-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX10-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %max = call float @llvm.maxnum.f32(float %a, float %b)
   %max3 = call float @llvm.maxnum.f32(float %max, float %c)
   ret float %max3
 }
 
 define float @test_max3_f32_commute_ieee_true(float %a, float %b, float %c) {
 ; SI_VI-LABEL: test_max3_f32_commute_ieee_true:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI_VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0
 ; SI_VI-NEXT:    v_mul_f32_e32 v1, 1.0, v1
-; SI_VI-NEXT:    v_max_f32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_mul_f32_e32 v1, 1.0, v2
-; SI_VI-NEXT:    v_max_f32_e32 v0, v1, v0
+; SI_VI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
+; SI_VI-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_f32_commute_ieee_true:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_max_f32_e32 v0, v0, v0
 ; GFX9-NEXT:    v_max_f32_e32 v1, v1, v1
-; GFX9-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_f32_e32 v1, v2, v2
-; GFX9-NEXT:    v_max_f32_e32 v0, v1, v0
+; GFX9-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX9-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_f32_commute_ieee_true:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
 ; GFX10-NEXT:    v_max_f32_e32 v1, v1, v1
-; GFX10-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_f32_e32 v1, v2, v2
-; GFX10-NEXT:    v_max_f32_e32 v0, v1, v0
+; GFX10-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %max = call float @llvm.maxnum.f32(float %a, float %b)
   %max3 = call float @llvm.maxnum.f32(float %c, float %max)
   ret float %max3
 }
 
 define half @test_max3_f16_ieee_true(half %a, half %b, half %c) {
 ; SI-LABEL: test_max3_f16_ieee_true:

 ; VI-NEXT:    v_max_f16_e32 v0, v0, v1
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_f16_ieee_true:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_max_f16_e32 v0, v0, v0
 ; GFX9-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX9-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_f16_e32 v1, v2, v2
-; GFX9-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX9-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX9-NEXT:    v_max3_f16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_f16_ieee_true:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v0
 ; GFX10-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_f16_e32 v1, v2, v2
-; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX10-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX10-NEXT:    v_max3_f16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %max = call half @llvm.maxnum.f16(half %a, half %b)
   %max3 = call half @llvm.maxnum.f16(half %max, half %c)
   ret half %max3
 }
 
 define half @test_max3_f16_commute_ieee_true(half %a, half %b, half %c) {
 ; SI-LABEL: test_max3_f16_commute_ieee_true:

 ; VI-NEXT:    v_max_f16_e32 v0, v1, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_f16_commute_ieee_true:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_max_f16_e32 v0, v0, v0
 ; GFX9-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX9-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_f16_e32 v1, v2, v2
-; GFX9-NEXT:    v_max_f16_e32 v0, v1, v0
+; GFX9-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX9-NEXT:    v_max3_f16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_f16_commute_ieee_true:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v0
 ; GFX10-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX10-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_f16_e32 v1, v2, v2
-; GFX10-NEXT:    v_max_f16_e32 v0, v1, v0
+; GFX10-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX10-NEXT:    v_max3_f16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %max = call half @llvm.maxnum.f16(half %a, half %b)
   %max3 = call half @llvm.maxnum.f16(half %c, half %max)
   ret half %max3
 }
 
 define amdgpu_ps float @test_max3_f32_ieee_false(float %a, float %b, float %c) {
 ; GCN-LABEL: test_max3_f32_ieee_false:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-NEXT:    v_max_f32_e32 v0, v0, v2
+; GCN-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; GCN-NEXT:    ; return to shader part epilog
   %max = call float @llvm.maxnum.f32(float %a, float %b)
   %max3 = call float @llvm.maxnum.f32(float %max, float %c)
   ret float %max3
 }
 
 define amdgpu_ps float @test_max3_f32_commute_ieee_false(float %a, float %b, float %c) {
 ; GCN-LABEL: test_max3_f32_commute_ieee_false:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    v_max_f32_e32 v0, v0, v1
-; GCN-NEXT:    v_max_f32_e32 v0, v2, v0
+; GCN-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; GCN-NEXT:    ; return to shader part epilog
   %max = call float @llvm.maxnum.f32(float %a, float %b)
   %max3 = call float @llvm.maxnum.f32(float %c, float %max)
   ret float %max3
 }
 
 define amdgpu_ps half @test_max3_f16_ieee_false(half %a, half %b, half %c) {
 ; SI-LABEL: test_max3_f16_ieee_false:

 ; VI-LABEL: test_max3_f16_ieee_false:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_f16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_f16_e32 v0, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9_10-LABEL: test_max3_f16_ieee_false:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_max_f16_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_max3_f16 v0, v0, v1, v2
 ; GFX9_10-NEXT:    ; return to shader part epilog
   %max = call half @llvm.maxnum.f16(half %a, half %b)
   %max3 = call half @llvm.maxnum.f16(half %max, half %c)
   ret half %max3
 }
 
 define amdgpu_ps half @test_max3_f16_commute_ieee_false(half %a, half %b, half %c) {
 ; SI-LABEL: test_max3_f16_commute_ieee_false:

 ; VI-LABEL: test_max3_f16_commute_ieee_false:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_f16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_f16_e32 v0, v2, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9_10-LABEL: test_max3_f16_commute_ieee_false:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_max_f16_e32 v0, v2, v0
+; GFX9_10-NEXT:    v_max3_f16 v0, v0, v1, v2
 ; GFX9_10-NEXT:    ; return to shader part epilog
   %max = call half @llvm.maxnum.f16(half %a, half %b)
   %max3 = call half @llvm.maxnum.f16(half %c, half %max)
   ret half %max3
 }
 
 define amdgpu_ps void @test_fmax3_f32_2_uses(float %a, float %b, float %c, float %d, float addrspace(1)* %out1, float addrspace(1)* %out2) {
 ; SI-LABEL: test_fmax3_f32_2_uses:

 }
 
 define amdgpu_ps void @test_max3_f32_fabs_fneg(float %a, float %b, float %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_max3_f32_fabs_fneg:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    v_sub_f32_e32 v1, 0x80000000, v1
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_max_f32_e64 v0, |v0|, v1
-; SI-NEXT:    v_max_f32_e32 v0, v0, v2
+; SI-NEXT:    v_max3_f32 v0, |v0|, v1, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[3:4], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_max3_f32_fabs_fneg:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_sub_f32_e32 v1, 0x80000000, v1
-; VI-NEXT:    v_max_f32_e64 v0, |v0|, v1
-; VI-NEXT:    v_max_f32_e32 v0, v0, v2
+; VI-NEXT:    v_max3_f32 v0, |v0|, v1, v2
 ; VI-NEXT:    flat_store_dword v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_max3_f32_fabs_fneg:
 ; GFX9_10:       ; %bb.0:
 ; GFX9_10-NEXT:    v_sub_f32_e32 v1, 0x80000000, v1
-; GFX9_10-NEXT:    v_max_f32_e64 v0, |v0|, v1
-; GFX9_10-NEXT:    v_max_f32_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_max3_f32 v0, |v0|, v1, v2
 ; GFX9_10-NEXT:    global_store_dword v[3:4], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fabs = call float @llvm.fabs.f32(float %a)
   %fneg = fsub float -0.0, %b
   %fmax = call float @llvm.maxnum.f32(float %fabs, float %fneg)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; Tests for constant bus limitations on fmax3 with mixed vgpr and sgpr operands.
 
 define amdgpu_ps void @test_fmax3_f32_vvv(float %a, float %b, float %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmax3_f32_vvv:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_max_f32_e32 v0, v0, v1
+; SI-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_max_f32_e32 v0, v0, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[3:4], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmax3_f32_vvv:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_max_f32_e32 v0, v0, v1
-; VI-NEXT:    v_max_f32_e32 v0, v0, v2
+; VI-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; VI-NEXT:    flat_store_dword v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_fmax3_f32_vvv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_max_f32_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_max3_f32 v0, v0, v1, v2
 ; GFX9_10-NEXT:    global_store_dword v[3:4], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmax = call float @llvm.maxnum.f32(float %a, float %b)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmax3_f32_svv(float inreg %a, float %b, float %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmax3_f32_svv:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_max_f32_e32 v0, s2, v0
+; SI-NEXT:    v_max3_f32 v0, s2, v0, v1
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_max_f32_e32 v0, v0, v1
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmax3_f32_svv:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_max_f32_e32 v0, s2, v0
-; VI-NEXT:    v_max_f32_e32 v0, v0, v1
+; VI-NEXT:    v_max3_f32 v0, s2, v0, v1
 ; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_fmax3_f32_svv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f32_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_max_f32_e32 v0, v0, v1
+; GFX9_10-NEXT:    v_max3_f32 v0, s2, v0, v1
 ; GFX9_10-NEXT:    global_store_dword v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmax = call float @llvm.maxnum.f32(float %a, float %b)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmax3_f32_vvs(float %a, float %b, float inreg %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmax3_f32_vvs:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_max_f32_e32 v0, v0, v1
-; SI-NEXT:    s_mov_b32 s6, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_max_f32_e32 v0, s2, v0
-; SI-NEXT:    s_mov_b64 s[4:5], 0
-; SI-NEXT:    buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
+; SI-NEXT:    v_max3_f32 v0, v0, v1, s2
+; SI-NEXT:    s_mov_b32 s2, 0
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b64 s[0:1], 0
+; SI-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmax3_f32_vvs:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_max_f32_e32 v0, v0, v1
-; VI-NEXT:    v_max_f32_e32 v0, s2, v0
+; VI-NEXT:    v_max3_f32 v0, v0, v1, s2
 ; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_fmax3_f32_vvs:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f32_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_max_f32_e32 v0, s2, v0
+; GFX9_10-NEXT:    v_max3_f32 v0, v0, v1, s2
 ; GFX9_10-NEXT:    global_store_dword v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmax = call float @llvm.maxnum.f32(float %a, float %b)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmax3_f32_ssv(float inreg %a, float inreg %b, float %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmax3_f32_ssv:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    v_mov_b32_e32 v3, s3
-; SI-NEXT:    v_max_f32_e32 v3, s2, v3
+; SI-NEXT:    v_max3_f32 v0, s2, v3, v0
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_max_f32_e32 v0, v3, v0
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmax3_f32_ssv:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    v_max_f32_e32 v3, s2, v3
-; VI-NEXT:    v_max_f32_e32 v0, v3, v0
+; VI-NEXT:    v_max3_f32 v0, s2, v3, v0
 ; VI-NEXT:    flat_store_dword v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_fmax3_f32_ssv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s3
-; GFX9-NEXT:    v_max_f32_e32 v3, s2, v3
-; GFX9-NEXT:    v_max_f32_e32 v0, v3, v0
+; GFX9-NEXT:    v_max3_f32 v0, s2, v3, v0
 ; GFX9-NEXT:    global_store_dword v[1:2], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_fmax3_f32_ssv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_max_f32_e64 v3, s2, s3
-; GFX10-NEXT:    v_max_f32_e32 v0, v3, v0
+; GFX10-NEXT:    v_max3_f32 v0, s2, s3, v0
 ; GFX10-NEXT:    global_store_dword v[1:2], v0, off
 ; GFX10-NEXT:    s_endpgm
   %fmax = call float @llvm.maxnum.f32(float %a, float %b)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmax3_f32_vss(float %a, float inreg %b, float inreg %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmax3_f32_vss:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_max_f32_e32 v0, s2, v0
-; SI-NEXT:    s_mov_b32 s6, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_max_f32_e32 v0, s3, v0
-; SI-NEXT:    s_mov_b64 s[4:5], 0
-; SI-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
+; SI-NEXT:    v_mov_b32_e32 v3, s3
+; SI-NEXT:    v_max3_f32 v0, v0, s2, v3
+; SI-NEXT:    s_mov_b32 s2, 0
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b64 s[0:1], 0
+; SI-NEXT:    buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmax3_f32_vss:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_max_f32_e32 v0, s2, v0
-; VI-NEXT:    v_max_f32_e32 v0, s3, v0
+; VI-NEXT:    v_mov_b32_e32 v3, s3
+; VI-NEXT:    v_max3_f32 v0, v0, s2, v3
 ; VI-NEXT:    flat_store_dword v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9_10-LABEL: test_fmax3_f32_vss:
-; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f32_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_max_f32_e32 v0, s3, v0
-; GFX9_10-NEXT:    global_store_dword v[1:2], v0, off
-; GFX9_10-NEXT:    s_endpgm
+; GFX9-LABEL: test_fmax3_f32_vss:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    v_max3_f32 v0, v0, s2, v3
+; GFX9-NEXT:    global_store_dword v[1:2], v0, off
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: test_fmax3_f32_vss:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_max3_f32 v0, v0, s2, s3
+; GFX10-NEXT:    global_store_dword v[1:2], v0, off
+; GFX10-NEXT:    s_endpgm
   %fmax = call float @llvm.maxnum.f32(float %a, float %b)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmax3_f32_sss(float inreg %a, float inreg %b, float inreg %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmax3_f32_sss:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    v_mov_b32_e32 v2, s3
-; SI-NEXT:    v_max_f32_e32 v2, s2, v2
+; SI-NEXT:    v_mov_b32_e32 v3, s4
+; SI-NEXT:    v_max3_f32 v2, s2, v2, v3
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_max_f32_e32 v2, s4, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmax3_f32_sss:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_mov_b32_e32 v2, s3
-; VI-NEXT:    v_max_f32_e32 v2, s2, v2
-; VI-NEXT:    v_max_f32_e32 v2, s4, v2
+; VI-NEXT:    v_mov_b32_e32 v3, s4
+; VI-NEXT:    v_max3_f32 v2, s2, v2, v3
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_fmax3_f32_sss:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s3
-; GFX9-NEXT:    v_max_f32_e32 v2, s2, v2
-; GFX9-NEXT:    v_max_f32_e32 v2, s4, v2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s4
+; GFX9-NEXT:    v_max3_f32 v2, s2, v2, v3
 ; GFX9-NEXT:    global_store_dword v[0:1], v2, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_fmax3_f32_sss:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_max_f32_e64 v2, s2, s3
-; GFX10-NEXT:    v_max_f32_e32 v2, s4, v2
+; GFX10-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10-NEXT:    v_max3_f32 v2, s2, s3, v2
 ; GFX10-NEXT:    global_store_dword v[0:1], v2, off
 ; GFX10-NEXT:    s_endpgm
   %fmax = call float @llvm.maxnum.f32(float %a, float %b)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 

 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_f16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_f16_e32 v0, v0, v2
 ; VI-NEXT:    flat_store_short v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_max3_f16_vvv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_max_f16_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_max3_f16 v0, v0, v1, v2
 ; GFX9_10-NEXT:    global_store_short v[3:4], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmax = call half @llvm.maxnum.f16(half %a, half %b)
   %fmax3 = call half @llvm.maxnum.f16(half %fmax, half %c)
   store half %fmax3, half addrspace(1)* %out, align 4
   ret void
 }
 

 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_f16_e32 v0, s2, v0
 ; VI-NEXT:    v_max_f16_e32 v0, v0, v1
 ; VI-NEXT:    flat_store_short v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_max3_f16_svv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f16_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_max_f16_e32 v0, v0, v1
+; GFX9_10-NEXT:    v_max3_f16 v0, s2, v0, v1
 ; GFX9_10-NEXT:    global_store_short v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmax = call half @llvm.maxnum.f16(half %a, half %b)
   %fmax3 = call half @llvm.maxnum.f16(half %fmax, half %c)
   store half %fmax3, half addrspace(1)* %out, align 4
   ret void
 }
 

 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_f16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_f16_e32 v0, s2, v0
 ; VI-NEXT:    flat_store_short v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_max3_f16_vvs:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f16_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_max_f16_e32 v0, s2, v0
+; GFX9_10-NEXT:    v_max3_f16 v0, v0, v1, s2
 ; GFX9_10-NEXT:    global_store_short v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmax = call half @llvm.maxnum.f16(half %a, half %b)
   %fmax3 = call half @llvm.maxnum.f16(half %fmax, half %c)
   store half %fmax3, half addrspace(1)* %out, align 4
   ret void
 }
 

 ; VI-NEXT:    v_max_f16_e32 v3, s2, v3
 ; VI-NEXT:    v_max_f16_e32 v0, v3, v0
 ; VI-NEXT:    flat_store_short v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_max3_f16_ssv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s3
-; GFX9-NEXT:    v_max_f16_e32 v3, s2, v3
-; GFX9-NEXT:    v_max_f16_e32 v0, v3, v0
+; GFX9-NEXT:    v_max3_f16 v0, s2, v3, v0
 ; GFX9-NEXT:    global_store_short v[1:2], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_max3_f16_ssv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_max_f16_e64 v3, s2, s3
-; GFX10-NEXT:    v_max_f16_e32 v0, v3, v0
+; GFX10-NEXT:    v_max3_f16 v0, s2, s3, v0
 ; GFX10-NEXT:    global_store_short v[1:2], v0, off
 ; GFX10-NEXT:    s_endpgm
   %fmax = call half @llvm.maxnum.f16(half %a, half %b)
   %fmax3 = call half @llvm.maxnum.f16(half %fmax, half %c)
   store half %fmax3, half addrspace(1)* %out, align 4
   ret void
 }
 

 ;
 ; VI-LABEL: test_max3_f16_vss:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_f16_e32 v0, s2, v0
 ; VI-NEXT:    v_max_f16_e32 v0, s3, v0
 ; VI-NEXT:    flat_store_short v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9_10-LABEL: test_max3_f16_vss:
-; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_f16_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_max_f16_e32 v0, s3, v0
-; GFX9_10-NEXT:    global_store_short v[1:2], v0, off
-; GFX9_10-NEXT:    s_endpgm
+; GFX9-LABEL: test_max3_f16_vss:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    v_max3_f16 v0, v0, s2, v3
+; GFX9-NEXT:    global_store_short v[1:2], v0, off
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: test_max3_f16_vss:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_max3_f16 v0, v0, s2, s3
+; GFX10-NEXT:    global_store_short v[1:2], v0, off
+; GFX10-NEXT:    s_endpgm
   %fmax = call half @llvm.maxnum.f16(half %a, half %b)
   %fmax3 = call half @llvm.maxnum.f16(half %fmax, half %c)
   store half %fmax3, half addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_max3_f16_sss(half inreg %a, half inreg %b, half inreg %c, half addrspace(1)* %out) {
 ; SI-LABEL: test_max3_f16_sss:

 ; VI-NEXT:    v_max_f16_e32 v2, s2, v2
 ; VI-NEXT:    v_max_f16_e32 v2, s4, v2
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_max3_f16_sss:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s3
-; GFX9-NEXT:    v_max_f16_e32 v2, s2, v2
-; GFX9-NEXT:    v_max_f16_e32 v2, s4, v2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s4
+; GFX9-NEXT:    v_max3_f16 v2, s2, v2, v3
 ; GFX9-NEXT:    global_store_short v[0:1], v2, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_max3_f16_sss:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_max_f16_e64 v2, s2, s3
-; GFX10-NEXT:    v_max_f16_e32 v2, s4, v2
+; GFX10-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10-NEXT:    v_max3_f16 v2, s2, s3, v2
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off
 ; GFX10-NEXT:    s_endpgm
   %fmax = call half @llvm.maxnum.f16(half %a, half %b)
   %fmax3 = call half @llvm.maxnum.f16(half %fmax, half %c)
   store half %fmax3, half addrspace(1)* %out, align 4
   ret void
 }
 
 declare half @llvm.maxnum.f16(half, half)
 declare float @llvm.maxnum.f32(float, float)
 declare float @llvm.fabs.f32(float)

llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI_VI,SI %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI_VI,VI %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX10 %s
 
 define float @test_min3_f32_ieee_true(float %a, float %b, float %c) {
 ; SI_VI-LABEL: test_min3_f32_ieee_true:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI_VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0
 ; SI_VI-NEXT:    v_mul_f32_e32 v1, 1.0, v1
-; SI_VI-NEXT:    v_min_f32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_mul_f32_e32 v1, 1.0, v2
-; SI_VI-NEXT:    v_min_f32_e32 v0, v0, v1
+; SI_VI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
+; SI_VI-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_f32_ieee_true:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_max_f32_e32 v0, v0, v0
 ; GFX9-NEXT:    v_max_f32_e32 v1, v1, v1
-; GFX9-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_f32_e32 v1, v2, v2
-; GFX9-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX9-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX9-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_f32_ieee_true:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
 ; GFX10-NEXT:    v_max_f32_e32 v1, v1, v1
-; GFX10-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_f32_e32 v1, v2, v2
-; GFX10-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX10-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %min = call float @llvm.minnum.f32(float %a, float %b)
   %min3 = call float @llvm.minnum.f32(float %min, float %c)
   ret float %min3
 }
 
 define float @test_min3_f32_commute_ieee_true(float %a, float %b, float %c) {
 ; SI_VI-LABEL: test_min3_f32_commute_ieee_true:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI_VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0
 ; SI_VI-NEXT:    v_mul_f32_e32 v1, 1.0, v1
-; SI_VI-NEXT:    v_min_f32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_mul_f32_e32 v1, 1.0, v2
-; SI_VI-NEXT:    v_min_f32_e32 v0, v1, v0
+; SI_VI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
+; SI_VI-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_f32_commute_ieee_true:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_max_f32_e32 v0, v0, v0
 ; GFX9-NEXT:    v_max_f32_e32 v1, v1, v1
-; GFX9-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_f32_e32 v1, v2, v2
-; GFX9-NEXT:    v_min_f32_e32 v0, v1, v0
+; GFX9-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX9-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_f32_commute_ieee_true:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
 ; GFX10-NEXT:    v_max_f32_e32 v1, v1, v1
-; GFX10-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_f32_e32 v1, v2, v2
-; GFX10-NEXT:    v_min_f32_e32 v0, v1, v0
+; GFX10-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %min = call float @llvm.minnum.f32(float %a, float %b)
   %min3 = call float @llvm.minnum.f32(float %c, float %min)
   ret float %min3
 }
 
 define half @test_min3_f16_ieee_true(half %a, half %b, half %c) {
 ; SI-LABEL: test_min3_f16_ieee_true:

 ; VI-NEXT:    v_min_f16_e32 v0, v0, v1
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_f16_ieee_true:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_max_f16_e32 v0, v0, v0
 ; GFX9-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX9-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_f16_e32 v1, v2, v2
-; GFX9-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX9-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX9-NEXT:    v_min3_f16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_f16_ieee_true:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v0
 ; GFX10-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_f16_e32 v1, v2, v2
-; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX10-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX10-NEXT:    v_min3_f16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %min = call half @llvm.minnum.f16(half %a, half %b)
   %min3 = call half @llvm.minnum.f16(half %min, half %c)
   ret half %min3
 }
 
 define half @test_min3_f16_commute_ieee_true(half %a, half %b, half %c) {
 ; SI-LABEL: test_min3_f16_commute_ieee_true:

 ; VI-NEXT:    v_min_f16_e32 v0, v1, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_f16_commute_ieee_true:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_max_f16_e32 v0, v0, v0
 ; GFX9-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX9-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_f16_e32 v1, v2, v2
-; GFX9-NEXT:    v_min_f16_e32 v0, v1, v0
+; GFX9-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX9-NEXT:    v_min3_f16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_f16_commute_ieee_true:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_max_f16_e32 v0, v0, v0
 ; GFX10-NEXT:    v_max_f16_e32 v1, v1, v1
-; GFX10-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_f16_e32 v1, v2, v2
-; GFX10-NEXT:    v_min_f16_e32 v0, v1, v0
+; GFX10-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX10-NEXT:    v_min3_f16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %min = call half @llvm.minnum.f16(half %a, half %b)
   %min3 = call half @llvm.minnum.f16(half %c, half %min)
   ret half %min3
 }
 
 define amdgpu_ps float @test_min3_f32_ieee_false(float %a, float %b, float %c) {
 ; GCN-LABEL: test_min3_f32_ieee_false:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    v_min_f32_e32 v0, v0, v1
-; GCN-NEXT:    v_min_f32_e32 v0, v0, v2
+; GCN-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; GCN-NEXT:    ; return to shader part epilog
   %min = call float @llvm.minnum.f32(float %a, float %b)
   %min3 = call float @llvm.minnum.f32(float %min, float %c)
   ret float %min3
 }
 
 define amdgpu_ps float @test_min3_f32_commute_ieee_false(float %a, float %b, float %c) {
 ; GCN-LABEL: test_min3_f32_commute_ieee_false:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    v_min_f32_e32 v0, v0, v1
-; GCN-NEXT:    v_min_f32_e32 v0, v2, v0
+; GCN-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; GCN-NEXT:    ; return to shader part epilog
   %min = call float @llvm.minnum.f32(float %a, float %b)
   %min3 = call float @llvm.minnum.f32(float %c, float %min)
   ret float %min3
 }
 
 define amdgpu_ps half @test_min3_f16_ieee_false(half %a, half %b, half %c) {
 ; SI-LABEL: test_min3_f16_ieee_false:

 ; VI-LABEL: test_min3_f16_ieee_false:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_f16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_f16_e32 v0, v0, v2
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9_10-LABEL: test_min3_f16_ieee_false:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_min_f16_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_min3_f16 v0, v0, v1, v2
 ; GFX9_10-NEXT:    ; return to shader part epilog
   %min = call half @llvm.minnum.f16(half %a, half %b)
   %min3 = call half @llvm.minnum.f16(half %min, half %c)
   ret half %min3
 }
 
 define amdgpu_ps half @test_min3_f16_commute_ieee_false(half %a, half %b, half %c) {
 ; SI-LABEL: test_min3_f16_commute_ieee_false:

 ; VI-LABEL: test_min3_f16_commute_ieee_false:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_f16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_f16_e32 v0, v2, v0
 ; VI-NEXT:    ; return to shader part epilog
 ;
 ; GFX9_10-LABEL: test_min3_f16_commute_ieee_false:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_min_f16_e32 v0, v2, v0
+; GFX9_10-NEXT:    v_min3_f16 v0, v0, v1, v2
 ; GFX9_10-NEXT:    ; return to shader part epilog
   %min = call half @llvm.minnum.f16(half %a, half %b)
   %min3 = call half @llvm.minnum.f16(half %c, half %min)
   ret half %min3
 }
 
 define amdgpu_ps void @test_fmin3_f32_2_uses(float %a, float %b, float %c, float %d, float addrspace(1)* %out1, float addrspace(1)* %out2) {
 ; SI-LABEL: test_fmin3_f32_2_uses:

 }
 
 define amdgpu_ps void @test_min3_f32_fabs_fneg(float %a, float %b, float %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_min3_f32_fabs_fneg:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    v_sub_f32_e32 v1, 0x80000000, v1
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_min_f32_e64 v0, |v0|, v1
-; SI-NEXT:    v_min_f32_e32 v0, v0, v2
+; SI-NEXT:    v_min3_f32 v0, |v0|, v1, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[3:4], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_min3_f32_fabs_fneg:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_sub_f32_e32 v1, 0x80000000, v1
-; VI-NEXT:    v_min_f32_e64 v0, |v0|, v1
-; VI-NEXT:    v_min_f32_e32 v0, v0, v2
+; VI-NEXT:    v_min3_f32 v0, |v0|, v1, v2
 ; VI-NEXT:    flat_store_dword v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_min3_f32_fabs_fneg:
 ; GFX9_10:       ; %bb.0:
 ; GFX9_10-NEXT:    v_sub_f32_e32 v1, 0x80000000, v1
-; GFX9_10-NEXT:    v_min_f32_e64 v0, |v0|, v1
-; GFX9_10-NEXT:    v_min_f32_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_min3_f32 v0, |v0|, v1, v2
 ; GFX9_10-NEXT:    global_store_dword v[3:4], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fabs = call float @llvm.fabs.f32(float %a)
   %fneg = fsub float -0.0, %b
   %fmin = call float @llvm.minnum.f32(float %fabs, float %fneg)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; Tests for constant bus limitations on fmin3 with mixed vgpr and sgpr operands.
 
 define amdgpu_ps void @test_fmin3_f32_vvv(float %a, float %b, float %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmin3_f32_vvv:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_min_f32_e32 v0, v0, v1
+; SI-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_min_f32_e32 v0, v0, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[3:4], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmin3_f32_vvv:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_min_f32_e32 v0, v0, v1
-; VI-NEXT:    v_min_f32_e32 v0, v0, v2
+; VI-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; VI-NEXT:    flat_store_dword v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_fmin3_f32_vvv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_min_f32_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; GFX9_10-NEXT:    global_store_dword v[3:4], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmin = call float @llvm.minnum.f32(float %a, float %b)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmin3_f32_svv(float inreg %a, float %b, float %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmin3_f32_svv:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_min_f32_e32 v0, s2, v0
+; SI-NEXT:    v_min3_f32 v0, s2, v0, v1
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_min_f32_e32 v0, v0, v1
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmin3_f32_svv:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_min_f32_e32 v0, s2, v0
-; VI-NEXT:    v_min_f32_e32 v0, v0, v1
+; VI-NEXT:    v_min3_f32 v0, s2, v0, v1
 ; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_fmin3_f32_svv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f32_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_min_f32_e32 v0, v0, v1
+; GFX9_10-NEXT:    v_min3_f32 v0, s2, v0, v1
 ; GFX9_10-NEXT:    global_store_dword v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmin = call float @llvm.minnum.f32(float %a, float %b)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmin3_f32_vvs(float %a, float %b, float inreg %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmin3_f32_vvs:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_min_f32_e32 v0, v0, v1
-; SI-NEXT:    s_mov_b32 s6, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_min_f32_e32 v0, s2, v0
-; SI-NEXT:    s_mov_b64 s[4:5], 0
-; SI-NEXT:    buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
+; SI-NEXT:    v_min3_f32 v0, v0, v1, s2
+; SI-NEXT:    s_mov_b32 s2, 0
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b64 s[0:1], 0
+; SI-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmin3_f32_vvs:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_min_f32_e32 v0, v0, v1
-; VI-NEXT:    v_min_f32_e32 v0, s2, v0
+; VI-NEXT:    v_min3_f32 v0, v0, v1, s2
 ; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_fmin3_f32_vvs:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f32_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_min_f32_e32 v0, s2, v0
+; GFX9_10-NEXT:    v_min3_f32 v0, v0, v1, s2
 ; GFX9_10-NEXT:    global_store_dword v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmin = call float @llvm.minnum.f32(float %a, float %b)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmin3_f32_ssv(float inreg %a, float inreg %b, float %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmin3_f32_ssv:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    v_mov_b32_e32 v3, s3
-; SI-NEXT:    v_min_f32_e32 v3, s2, v3
+; SI-NEXT:    v_min3_f32 v0, s2, v3, v0
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_min_f32_e32 v0, v3, v0
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmin3_f32_ssv:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    v_min_f32_e32 v3, s2, v3
-; VI-NEXT:    v_min_f32_e32 v0, v3, v0
+; VI-NEXT:    v_min3_f32 v0, s2, v3, v0
 ; VI-NEXT:    flat_store_dword v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_fmin3_f32_ssv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s3
-; GFX9-NEXT:    v_min_f32_e32 v3, s2, v3
-; GFX9-NEXT:    v_min_f32_e32 v0, v3, v0
+; GFX9-NEXT:    v_min3_f32 v0, s2, v3, v0
 ; GFX9-NEXT:    global_store_dword v[1:2], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_fmin3_f32_ssv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_min_f32_e64 v3, s2, s3
-; GFX10-NEXT:    v_min_f32_e32 v0, v3, v0
+; GFX10-NEXT:    v_min3_f32 v0, s2, s3, v0
 ; GFX10-NEXT:    global_store_dword v[1:2], v0, off
 ; GFX10-NEXT:    s_endpgm
   %fmin = call float @llvm.minnum.f32(float %a, float %b)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmin3_f32_vss(float %a, float inreg %b, float inreg %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmin3_f32_vss:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_min_f32_e32 v0, s2, v0
-; SI-NEXT:    s_mov_b32 s6, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_min_f32_e32 v0, s3, v0
-; SI-NEXT:    s_mov_b64 s[4:5], 0
-; SI-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
+; SI-NEXT:    v_mov_b32_e32 v3, s3
+; SI-NEXT:    v_min3_f32 v0, v0, s2, v3
+; SI-NEXT:    s_mov_b32 s2, 0
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b64 s[0:1], 0
+; SI-NEXT:    buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmin3_f32_vss:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_min_f32_e32 v0, s2, v0
-; VI-NEXT:    v_min_f32_e32 v0, s3, v0
+; VI-NEXT:    v_mov_b32_e32 v3, s3
+; VI-NEXT:    v_min3_f32 v0, v0, s2, v3
 ; VI-NEXT:    flat_store_dword v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9_10-LABEL: test_fmin3_f32_vss:
-; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f32_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_min_f32_e32 v0, s3, v0
-; GFX9_10-NEXT:    global_store_dword v[1:2], v0, off
-; GFX9_10-NEXT:    s_endpgm
+; GFX9-LABEL: test_fmin3_f32_vss:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    v_min3_f32 v0, v0, s2, v3
+; GFX9-NEXT:    global_store_dword v[1:2], v0, off
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: test_fmin3_f32_vss:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_min3_f32 v0, v0, s2, s3
+; GFX10-NEXT:    global_store_dword v[1:2], v0, off
+; GFX10-NEXT:    s_endpgm
   %fmin = call float @llvm.minnum.f32(float %a, float %b)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_fmin3_f32_sss(float inreg %a, float inreg %b, float inreg %c, float addrspace(1)* %out) {
 ; SI-LABEL: test_fmin3_f32_sss:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    v_mov_b32_e32 v2, s3
-; SI-NEXT:    v_min_f32_e32 v2, s2, v2
+; SI-NEXT:    v_mov_b32_e32 v3, s4
+; SI-NEXT:    v_min3_f32 v2, s2, v2, v3
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_min_f32_e32 v2, s4, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_fmin3_f32_sss:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_mov_b32_e32 v2, s3
-; VI-NEXT:    v_min_f32_e32 v2, s2, v2
-; VI-NEXT:    v_min_f32_e32 v2, s4, v2
+; VI-NEXT:    v_mov_b32_e32 v3, s4
+; VI-NEXT:    v_min3_f32 v2, s2, v2, v3
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_fmin3_f32_sss:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s3
-; GFX9-NEXT:    v_min_f32_e32 v2, s2, v2
-; GFX9-NEXT:    v_min_f32_e32 v2, s4, v2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s4
+; GFX9-NEXT:    v_min3_f32 v2, s2, v2, v3
 ; GFX9-NEXT:    global_store_dword v[0:1], v2, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_fmin3_f32_sss:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_min_f32_e64 v2, s2, s3
-; GFX10-NEXT:    v_min_f32_e32 v2, s4, v2
+; GFX10-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10-NEXT:    v_min3_f32 v2, s2, s3, v2
 ; GFX10-NEXT:    global_store_dword v[0:1], v2, off
 ; GFX10-NEXT:    s_endpgm
   %fmin = call float @llvm.minnum.f32(float %a, float %b)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 

 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_f16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_f16_e32 v0, v0, v2
 ; VI-NEXT:    flat_store_short v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_min3_f16_vvv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_min_f16_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_min3_f16 v0, v0, v1, v2
 ; GFX9_10-NEXT:    global_store_short v[3:4], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmin = call half @llvm.minnum.f16(half %a, half %b)
   %fmin3 = call half @llvm.minnum.f16(half %fmin, half %c)
   store half %fmin3, half addrspace(1)* %out, align 4
   ret void
 }
 

 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_f16_e32 v0, s2, v0
 ; VI-NEXT:    v_min_f16_e32 v0, v0, v1
 ; VI-NEXT:    flat_store_short v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_min3_f16_svv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f16_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_min_f16_e32 v0, v0, v1
+; GFX9_10-NEXT:    v_min3_f16 v0, s2, v0, v1
 ; GFX9_10-NEXT:    global_store_short v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmin = call half @llvm.minnum.f16(half %a, half %b)
   %fmin3 = call half @llvm.minnum.f16(half %fmin, half %c)
   store half %fmin3, half addrspace(1)* %out, align 4
   ret void
 }
 

 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_f16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_f16_e32 v0, s2, v0
 ; VI-NEXT:    flat_store_short v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_min3_f16_vvs:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f16_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_min_f16_e32 v0, s2, v0
+; GFX9_10-NEXT:    v_min3_f16 v0, v0, v1, s2
 ; GFX9_10-NEXT:    global_store_short v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %fmin = call half @llvm.minnum.f16(half %a, half %b)
   %fmin3 = call half @llvm.minnum.f16(half %fmin, half %c)
   store half %fmin3, half addrspace(1)* %out, align 4
   ret void
 }
 

 ; VI-NEXT:    v_min_f16_e32 v3, s2, v3
 ; VI-NEXT:    v_min_f16_e32 v0, v3, v0
 ; VI-NEXT:    flat_store_short v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_min3_f16_ssv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s3
-; GFX9-NEXT:    v_min_f16_e32 v3, s2, v3
-; GFX9-NEXT:    v_min_f16_e32 v0, v3, v0
+; GFX9-NEXT:    v_min3_f16 v0, s2, v3, v0
 ; GFX9-NEXT:    global_store_short v[1:2], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_min3_f16_ssv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_min_f16_e64 v3, s2, s3
-; GFX10-NEXT:    v_min_f16_e32 v0, v3, v0
+; GFX10-NEXT:    v_min3_f16 v0, s2, s3, v0
 ; GFX10-NEXT:    global_store_short v[1:2], v0, off
 ; GFX10-NEXT:    s_endpgm
   %fmin = call half @llvm.minnum.f16(half %a, half %b)
   %fmin3 = call half @llvm.minnum.f16(half %fmin, half %c)
   store half %fmin3, half addrspace(1)* %out, align 4
   ret void
 }
 

 ;
 ; VI-LABEL: test_min3_f16_vss:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_f16_e32 v0, s2, v0
 ; VI-NEXT:    v_min_f16_e32 v0, s3, v0
 ; VI-NEXT:    flat_store_short v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9_10-LABEL: test_min3_f16_vss:
-; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_f16_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_min_f16_e32 v0, s3, v0
-; GFX9_10-NEXT:    global_store_short v[1:2], v0, off
-; GFX9_10-NEXT:    s_endpgm
+; GFX9-LABEL: test_min3_f16_vss:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    v_min3_f16 v0, v0, s2, v3
+; GFX9-NEXT:    global_store_short v[1:2], v0, off
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: test_min3_f16_vss:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_min3_f16 v0, v0, s2, s3
+; GFX10-NEXT:    global_store_short v[1:2], v0, off
+; GFX10-NEXT:    s_endpgm
   %fmin = call half @llvm.minnum.f16(half %a, half %b)
   %fmin3 = call half @llvm.minnum.f16(half %fmin, half %c)
   store half %fmin3, half addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_min3_f16_sss(half inreg %a, half inreg %b, half inreg %c, half addrspace(1)* %out) {
 ; SI-LABEL: test_min3_f16_sss:

 ; VI-NEXT:    v_min_f16_e32 v2, s2, v2
 ; VI-NEXT:    v_min_f16_e32 v2, s4, v2
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_min3_f16_sss:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s3
-; GFX9-NEXT:    v_min_f16_e32 v2, s2, v2
-; GFX9-NEXT:    v_min_f16_e32 v2, s4, v2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s4
+; GFX9-NEXT:    v_min3_f16 v2, s2, v2, v3
 ; GFX9-NEXT:    global_store_short v[0:1], v2, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_min3_f16_sss:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_min_f16_e64 v2, s2, s3
-; GFX10-NEXT:    v_min_f16_e32 v2, s4, v2
+; GFX10-NEXT:    v_mov_b32_e32 v2, s4
+; GFX10-NEXT:    v_min3_f16 v2, s2, s3, v2
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off
 ; GFX10-NEXT:    s_endpgm
   %fmin = call half @llvm.minnum.f16(half %a, half %b)
   %fmin3 = call half @llvm.minnum.f16(half %fmin, half %c)
   store half %fmin3, half addrspace(1)* %out, align 4
   ret void
 }
 
 declare half @llvm.minnum.f16(half, half)
 declare float @llvm.minnum.f32(float, float)
 declare float @llvm.fabs.f32(float)

llvm/test/CodeGen/AMDGPU/GlobalISel/max3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI_VI,SI %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI_VI,VI %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX10 %s
 
 define i32 @test_max3_u32(i32 %a, i32 %b, i32 %c) {
 ; SI_VI-LABEL: test_max3_u32:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI_VI-NEXT:    v_max_u32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_max_u32_e32 v0, v0, v2
+; SI_VI-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_u32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_max_u32_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_u32_e32 v0, v0, v2
+; GFX9-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_u32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_max_u32_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_u32_e32 v0, v0, v2
+; GFX10-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
   %umax3 = call i32 @llvm.umax.i32(i32 %umax, i32 %c)
   ret i32 %umax3
 }
 
 define amdgpu_ps i32 @test_max3_u32_uniform(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
 ; GCN-LABEL: test_max3_u32_uniform:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_max_u32 s0, s2, s3
 ; GCN-NEXT:    s_max_u32 s0, s0, s4
 ; GCN-NEXT:    ; return to shader part epilog
   %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
   %umax3 = call i32 @llvm.umax.i32(i32 %umax, i32 %c)
   ret i32 %umax3
 }
 
 define i32 @test_max3_u32_commute(i32 %a, i32 %b, i32 %c) {
 ; SI_VI-LABEL: test_max3_u32_commute:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI_VI-NEXT:    v_max_u32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_max_u32_e32 v0, v2, v0
+; SI_VI-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_u32_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_max_u32_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_u32_e32 v0, v2, v0
+; GFX9-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_u32_commute:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_max_u32_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_u32_e32 v0, v2, v0
+; GFX10-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
   %umax3 = call i32 @llvm.umax.i32(i32 %c, i32 %umax)
   ret i32 %umax3
 }
 
 define i16 @test_max3_u16(i16 %a, i16 %b, i16 %c) {
 ; SI-LABEL: test_max3_u16:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-NEXT:    s_mov_b32 s4, 0xffff
 ; SI-NEXT:    v_and_b32_e32 v0, s4, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s4, v1
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
-; SI-NEXT:    v_and_b32_e32 v1, s4, v2
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
+; SI-NEXT:    v_and_b32_e32 v2, s4, v2
+; SI-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: test_max3_u16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_max_u16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_u16_e32 v0, v0, v2
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_u16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_max_u16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_u16_e32 v0, v0, v2
+; GFX9-NEXT:    v_max3_u16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_u16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_max_u16 v0, v0, v1
-; GFX10-NEXT:    v_max_u16 v0, v0, v2
+; GFX10-NEXT:    v_max3_u16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %umax = call i16 @llvm.umax.i16(i16 %a, i16 %b)
   %umax3 = call i16 @llvm.umax.i16(i16 %umax, i16 %c)
   ret i16 %umax3
 }
 
 define i16 @test_max3_u16_commute(i16 %a, i16 %b, i16 %c) {
 ; SI-LABEL: test_max3_u16_commute:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-NEXT:    s_mov_b32 s4, 0xffff
 ; SI-NEXT:    v_and_b32_e32 v0, s4, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s4, v1
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
-; SI-NEXT:    v_and_b32_e32 v1, s4, v2
-; SI-NEXT:    v_max_u32_e32 v0, v1, v0
+; SI-NEXT:    v_and_b32_e32 v2, s4, v2
+; SI-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: test_max3_u16_commute:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_max_u16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_u16_e32 v0, v2, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_u16_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_max_u16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_u16_e32 v0, v2, v0
+; GFX9-NEXT:    v_max3_u16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_u16_commute:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_max_u16 v0, v0, v1
-; GFX10-NEXT:    v_max_u16 v0, v2, v0
+; GFX10-NEXT:    v_max3_u16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %umax = call i16 @llvm.umax.i16(i16 %a, i16 %b)
   %umax3 = call i16 @llvm.umax.i16(i16 %c, i16 %umax)
   ret i16 %umax3
 }
 
 define i32 @test_max3_i32(i32 %a, i32 %b, i32 %c) {
 ; SI_VI-LABEL: test_max3_i32:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI_VI-NEXT:    v_max_i32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_max_i32_e32 v0, v0, v2
+; SI_VI-NEXT:    v_max3_i32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_i32_e32 v0, v0, v2
+; GFX9-NEXT:    v_max3_i32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_i32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_i32_e32 v0, v0, v2
+; GFX10-NEXT:    v_max3_i32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
   %smax3 = call i32 @llvm.smax.i32(i32 %smax, i32 %c)
   ret i32 %smax3
 }
 
 define amdgpu_ps i32 @test_max3_i32_uniform(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
 ; GCN-LABEL: test_max3_i32_uniform:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_max_i32 s0, s2, s3
 ; GCN-NEXT:    s_max_i32 s0, s0, s4
 ; GCN-NEXT:    ; return to shader part epilog
   %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
   %smax3 = call i32 @llvm.smax.i32(i32 %smax, i32 %c)
   ret i32 %smax3
 }
 
 define i32 @test_max3_i32_commute(i32 %a, i32 %b, i32 %c) {
 ; SI_VI-LABEL: test_max3_i32_commute:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI_VI-NEXT:    v_max_i32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_max_i32_e32 v0, v2, v0
+; SI_VI-NEXT:    v_max3_i32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_i32_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_i32_e32 v0, v2, v0
+; GFX9-NEXT:    v_max3_i32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_i32_commute:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX10-NEXT:    v_max_i32_e32 v0, v2, v0
+; GFX10-NEXT:    v_max3_i32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
   %smax3 = call i32 @llvm.smax.i32(i32 %c, i32 %smax)
   ret i32 %smax3
 }
 
 define i16 @test_max3_i16(i16 %a, i16 %b, i16 %c) {
 ; SI-LABEL: test_max3_i16:

 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_max_i16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_i16_e32 v0, v0, v2
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_max_i16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_i16_e32 v0, v0, v2
+; GFX9-NEXT:    v_max3_i16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_max_i16 v0, v0, v1
-; GFX10-NEXT:    v_max_i16 v0, v0, v2
+; GFX10-NEXT:    v_max3_i16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %smax = call i16 @llvm.smax.i16(i16 %a, i16 %b)
   %smax3 = call i16 @llvm.smax.i16(i16 %smax, i16 %c)
   ret i16 %smax3
 }
 
 define i16 @test_max3_i16_commute(i16 %a, i16 %b, i16 %c) {
 ; SI-LABEL: test_max3_i16_commute:

 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_max_i16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_i16_e32 v0, v2, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_max3_i16_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_max_i16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_i16_e32 v0, v2, v0
+; GFX9-NEXT:    v_max3_i16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_max3_i16_commute:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_max_i16 v0, v0, v1
-; GFX10-NEXT:    v_max_i16 v0, v2, v0
+; GFX10-NEXT:    v_max3_i16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %smax = call i16 @llvm.smax.i16(i16 %a, i16 %b)
   %smax3 = call i16 @llvm.smax.i16(i16 %c, i16 %smax)
   ret i16 %smax3
 }
 
 define amdgpu_ps void @test_max3_u32_2_uses(i32 %a, i32 %b, i32 %c, i32 %d, i32 addrspace(1)* %out1, i32 addrspace(1)* %out2) {
 ; SI-LABEL: test_max3_u32_2_uses:
; GFX9_10-NEXT:    s_endpgm
   ret void
 }
 
 ; Tests for constant bus limitations on max3 with mixed vgpr and sgpr operands.
 
 define amdgpu_ps void @test_max3_u32_vvv(i32 %a, i32 %b, i32 %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_max3_u32_vvv:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
+; SI-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_max_u32_e32 v0, v0, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[3:4], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_max3_u32_vvv:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_max_u32_e32 v0, v0, v1
-; VI-NEXT:    v_max_u32_e32 v0, v0, v2
+; VI-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; VI-NEXT:    flat_store_dword v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_max3_u32_vvv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_u32_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_max_u32_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; GFX9_10-NEXT:    global_store_dword v[3:4], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
   %max3 = call i32 @llvm.umax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_max3_u32_svv(i32 inreg %a, i32 %b, i32 %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_max3_u32_svv:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_max_u32_e32 v0, s2, v0
+; SI-NEXT:    v_max3_u32 v0, s2, v0, v1
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_max3_u32_svv:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_max_u32_e32 v0, s2, v0
-; VI-NEXT:    v_max_u32_e32 v0, v0, v1
+; VI-NEXT:    v_max3_u32 v0, s2, v0, v1
 ; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_max3_u32_svv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_u32_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_max_u32_e32 v0, v0, v1
+; GFX9_10-NEXT:    v_max3_u32 v0, s2, v0, v1
 ; GFX9_10-NEXT:    global_store_dword v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
   %max3 = call i32 @llvm.umax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_max3_u32_vvs(i32 %a, i32 %b, i32 inreg %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_max3_u32_vvs:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
-; SI-NEXT:    s_mov_b32 s6, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_max_u32_e32 v0, s2, v0
-; SI-NEXT:    s_mov_b64 s[4:5], 0
-; SI-NEXT:    buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
+; SI-NEXT:    v_max3_u32 v0, v0, v1, s2
+; SI-NEXT:    s_mov_b32 s2, 0
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b64 s[0:1], 0
+; SI-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_max3_u32_vvs:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_max_u32_e32 v0, v0, v1
-; VI-NEXT:    v_max_u32_e32 v0, s2, v0
+; VI-NEXT:    v_max3_u32 v0, v0, v1, s2
 ; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_max3_u32_vvs:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_u32_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_max_u32_e32 v0, s2, v0
+; GFX9_10-NEXT:    v_max3_u32 v0, v0, v1, s2
 ; GFX9_10-NEXT:    global_store_dword v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
   %max3 = call i32 @llvm.umax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
; GFX9_10-NEXT:    s_endpgm
   %max3 = call i32 @llvm.smax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_max3_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_max3_i32_vss:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_max_i32_e32 v0, s2, v0
-; SI-NEXT:    s_mov_b32 s6, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_max_i32_e32 v0, s3, v0
-; SI-NEXT:    s_mov_b64 s[4:5], 0
-; SI-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
+; SI-NEXT:    v_mov_b32_e32 v3, s3
+; SI-NEXT:    v_max3_i32 v0, v0, s2, v3
+; SI-NEXT:    s_mov_b32 s2, 0
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b64 s[0:1], 0
+; SI-NEXT:    buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_max3_i32_vss:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_max_i32_e32 v0, s2, v0
-; VI-NEXT:    v_max_i32_e32 v0, s3, v0
+; VI-NEXT:    v_mov_b32_e32 v3, s3
+; VI-NEXT:    v_max3_i32 v0, v0, s2, v3
 ; VI-NEXT:    flat_store_dword v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9_10-LABEL: test_max3_i32_vss:
-; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_max_i32_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_max_i32_e32 v0, s3, v0
-; GFX9_10-NEXT:    global_store_dword v[1:2], v0, off
-; GFX9_10-NEXT:    s_endpgm
+; GFX9-LABEL: test_max3_i32_vss:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    v_max3_i32 v0, v0, s2, v3
+; GFX9-NEXT:    global_store_dword v[1:2], v0, off
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: test_max3_i32_vss:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_max3_i32 v0, v0, s2, s3
+; GFX10-NEXT:    global_store_dword v[1:2], v0, off
+; GFX10-NEXT:    s_endpgm
   %max = call i32 @llvm.smax.i32(i32 %a, i32 %b)
   %max3 = call i32 @llvm.smax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_max3_i32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_max3_i32_sss:

 ; SI-LABEL: test_max3_u16_vvv:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_mov_b32 s0, 0xffff
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    v_and_b32_e32 v0, s0, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s0, v1
 ; SI-NEXT:    v_and_b32_e32 v2, s0, v2
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
-; SI-NEXT:    v_max_u32_e32 v0, v0, v2
+; SI-NEXT:    v_max3_u32 v0, v0, v1, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_short v0, v[3:4], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_max3_u16_vvv:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_u16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_u16_e32 v0, v0, v2
 ; VI-NEXT:    flat_store_short v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: test_max3_u16_vvv:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_max_u16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_u16_e32 v0, v0, v2
-; GFX9-NEXT:    global_store_short v[3:4], v0, off
-; GFX9-NEXT:    s_endpgm
-;
-; GFX10-LABEL: test_max3_u16_vvv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_max_u16 v0, v0, v1
-; GFX10-NEXT:    v_max_u16 v0, v0, v2
-; GFX10-NEXT:    global_store_short v[3:4], v0, off
-; GFX10-NEXT:    s_endpgm
+; GFX9_10-LABEL: test_max3_u16_vvv:
+; GFX9_10:       ; %bb.0:
+; GFX9_10-NEXT:    v_max3_u16 v0, v0, v1, v2
+; GFX9_10-NEXT:    global_store_short v[3:4], v0, off
+; GFX9_10-NEXT:    s_endpgm
   %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
   %max3 = call i16 @llvm.umax.i16(i16 %max, i16 %c)
   store i16 %max3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_max3_u16_svv(i16 inreg %a, i16 %b, i16 %c, i16 addrspace(1)* %out) {
 ; SI-LABEL: test_max3_u16_svv:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_mov_b32 s0, 0xffff
 ; SI-NEXT:    s_mov_b32 s6, 0
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_and_b32 s1, s2, s0
 ; SI-NEXT:    v_and_b32_e32 v0, s0, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s0, v1
-; SI-NEXT:    v_max_u32_e32 v0, s1, v0
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
+; SI-NEXT:    v_max3_u32 v0, s1, v0, v1
 ; SI-NEXT:    s_mov_b64 s[4:5], 0
 ; SI-NEXT:    buffer_store_short v0, v[2:3], s[4:7], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_max3_u16_svv:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_u16_e32 v0, s2, v0
 ; VI-NEXT:    v_max_u16_e32 v0, v0, v1
 ; VI-NEXT:    flat_store_short v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: test_max3_u16_svv:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_max_u16_e32 v0, s2, v0
-; GFX9-NEXT:    v_max_u16_e32 v0, v0, v1
-; GFX9-NEXT:    global_store_short v[2:3], v0, off
-; GFX9-NEXT:    s_endpgm
-;
-; GFX10-LABEL: test_max3_u16_svv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_max_u16 v0, s2, v0
-; GFX10-NEXT:    v_max_u16 v0, v0, v1
-; GFX10-NEXT:    global_store_short v[2:3], v0, off
-; GFX10-NEXT:    s_endpgm
+; GFX9_10-LABEL: test_max3_u16_svv:
+; GFX9_10:       ; %bb.0:
+; GFX9_10-NEXT:    v_max3_u16 v0, s2, v0, v1
+; GFX9_10-NEXT:    global_store_short v[2:3], v0, off
+; GFX9_10-NEXT:    s_endpgm
   %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
   %max3 = call i16 @llvm.umax.i16(i16 %max, i16 %c)
   store i16 %max3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_max3_u16_vvs(i16 %a, i16 %b, i16 inreg %c, i16 addrspace(1)* %out) {
 ; SI-LABEL: test_max3_u16_vvs:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_mov_b32 s0, 0xffff
 ; SI-NEXT:    s_mov_b32 s6, 0
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    v_and_b32_e32 v0, s0, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s0, v1
 ; SI-NEXT:    s_and_b32 s0, s2, s0
-; SI-NEXT:    v_max_u32_e32 v0, v0, v1
-; SI-NEXT:    v_max_u32_e32 v0, s0, v0
+; SI-NEXT:    v_max3_u32 v0, v0, v1, s0
 ; SI-NEXT:    s_mov_b64 s[4:5], 0
 ; SI-NEXT:    buffer_store_short v0, v[2:3], s[4:7], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_max3_u16_vvs:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_u16_e32 v0, v0, v1
 ; VI-NEXT:    v_max_u16_e32 v0, s2, v0
 ; VI-NEXT:    flat_store_short v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: test_max3_u16_vvs:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_max_u16_e32 v0, v0, v1
-; GFX9-NEXT:    v_max_u16_e32 v0, s2, v0
-; GFX9-NEXT:    global_store_short v[2:3], v0, off
-; GFX9-NEXT:    s_endpgm
-;
-; GFX10-LABEL: test_max3_u16_vvs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_max_u16 v0, v0, v1
-; GFX10-NEXT:    v_max_u16 v0, v0, s2
-; GFX10-NEXT:    global_store_short v[2:3], v0, off
-; GFX10-NEXT:    s_endpgm
+; GFX9_10-LABEL: test_max3_u16_vvs:
+; GFX9_10:       ; %bb.0:
+; GFX9_10-NEXT:    v_max3_u16 v0, v0, v1, s2
+; GFX9_10-NEXT:    global_store_short v[2:3], v0, off
+; GFX9_10-NEXT:    s_endpgm
   %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
   %max3 = call i16 @llvm.umax.i16(i16 %max, i16 %c)
   store i16 %max3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_max3_i16_ssv(i16 inreg %a, i16 inreg %b, i16 %c, i16 addrspace(1)* %out) {
 ; SI-LABEL: test_max3_i16_ssv:

 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_max_i16_e32 v0, s2, v0
 ; VI-NEXT:    v_max_i16_e32 v0, s3, v0
 ; VI-NEXT:    flat_store_short v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_max3_i16_vss:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_max_i16_e32 v0, s2, v0
-; GFX9-NEXT:    v_max_i16_e32 v0, s3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    v_max3_i16 v0, v0, s2, v3
 ; GFX9-NEXT:    global_store_short v[1:2], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_max3_i16_vss:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_max_i16 v0, v0, s2
-; GFX10-NEXT:    v_max_i16 v0, v0, s3
+; GFX10-NEXT:    v_max3_i16 v0, v0, s2, s3
 ; GFX10-NEXT:    global_store_short v[1:2], v0, off
 ; GFX10-NEXT:    s_endpgm
   %max = call i16 @llvm.smax.i16(i16 %a, i16 %b)
   %max3 = call i16 @llvm.smax.i16(i16 %max, i16 %c)
   store i16 %max3, i16 addrspace(1)* %out, align 4
   ret void
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/min3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI_VI,SI %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI_VI,VI %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX9 %s
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX10 %s
 
 define i32 @test_min3_u32(i32 %a, i32 %b, i32 %c) {
 ; SI_VI-LABEL: test_min3_u32:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI_VI-NEXT:    v_min_u32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_min_u32_e32 v0, v0, v2
+; SI_VI-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_u32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_min_u32_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_u32_e32 v0, v0, v2
+; GFX9-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_u32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_min_u32_e32 v0, v0, v1
-; GFX10-NEXT:    v_min_u32_e32 v0, v0, v2
+; GFX10-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b)
   %umin3 = call i32 @llvm.umin.i32(i32 %umin, i32 %c)
   ret i32 %umin3
 }
 
 define amdgpu_ps i32 @test_min3_u32_uniform(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
 ; GCN-LABEL: test_min3_u32_uniform:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_min_u32 s0, s2, s3
 ; GCN-NEXT:    s_min_u32 s0, s0, s4
 ; GCN-NEXT:    ; return to shader part epilog
   %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b)
   %umin3 = call i32 @llvm.umin.i32(i32 %umin, i32 %c)
   ret i32 %umin3
 }
 
 define i32 @test_min3_u32_commute(i32 %a, i32 %b, i32 %c) {
 ; SI_VI-LABEL: test_min3_u32_commute:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI_VI-NEXT:    v_min_u32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_min_u32_e32 v0, v2, v0
+; SI_VI-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_u32_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_min_u32_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_u32_e32 v0, v2, v0
+; GFX9-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_u32_commute:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_min_u32_e32 v0, v0, v1
-; GFX10-NEXT:    v_min_u32_e32 v0, v2, v0
+; GFX10-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b)
   %umin3 = call i32 @llvm.umin.i32(i32 %c, i32 %umin)
   ret i32 %umin3
 }
 
 define i16 @test_min3_u16(i16 %a, i16 %b, i16 %c) {
 ; SI-LABEL: test_min3_u16:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-NEXT:    s_mov_b32 s4, 0xffff
 ; SI-NEXT:    v_and_b32_e32 v0, s4, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s4, v1
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
-; SI-NEXT:    v_and_b32_e32 v1, s4, v2
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
+; SI-NEXT:    v_and_b32_e32 v2, s4, v2
+; SI-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: test_min3_u16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_min_u16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_u16_e32 v0, v0, v2
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_u16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_min_u16_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_u16_e32 v0, v0, v2
+; GFX9-NEXT:    v_min3_u16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_u16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_min_u16 v0, v0, v1
-; GFX10-NEXT:    v_min_u16 v0, v0, v2
+; GFX10-NEXT:    v_min3_u16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %umin = call i16 @llvm.umin.i16(i16 %a, i16 %b)
   %umin3 = call i16 @llvm.umin.i16(i16 %umin, i16 %c)
   ret i16 %umin3
 }
 
 define i16 @test_min3_u16_commute(i16 %a, i16 %b, i16 %c) {
 ; SI-LABEL: test_min3_u16_commute:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-NEXT:    s_mov_b32 s4, 0xffff
 ; SI-NEXT:    v_and_b32_e32 v0, s4, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s4, v1
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
-; SI-NEXT:    v_and_b32_e32 v1, s4, v2
-; SI-NEXT:    v_min_u32_e32 v0, v1, v0
+; SI-NEXT:    v_and_b32_e32 v2, s4, v2
+; SI-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: test_min3_u16_commute:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_min_u16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_u16_e32 v0, v2, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_u16_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_min_u16_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_u16_e32 v0, v2, v0
+; GFX9-NEXT:    v_min3_u16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_u16_commute:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_min_u16 v0, v0, v1
-; GFX10-NEXT:    v_min_u16 v0, v2, v0
+; GFX10-NEXT:    v_min3_u16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %umin = call i16 @llvm.umin.i16(i16 %a, i16 %b)
   %umin3 = call i16 @llvm.umin.i16(i16 %c, i16 %umin)
   ret i16 %umin3
 }
 
 define i32 @test_min3_i32(i32 %a, i32 %b, i32 %c) {
 ; SI_VI-LABEL: test_min3_i32:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI_VI-NEXT:    v_min_i32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_min_i32_e32 v0, v0, v2
+; SI_VI-NEXT:    v_min3_i32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_min_i32_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_i32_e32 v0, v0, v2
+; GFX9-NEXT:    v_min3_i32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_i32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_min_i32_e32 v0, v0, v1
-; GFX10-NEXT:    v_min_i32_e32 v0, v0, v2
+; GFX10-NEXT:    v_min3_i32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b)
   %smin3 = call i32 @llvm.smin.i32(i32 %smin, i32 %c)
   ret i32 %smin3
 }
 
 define amdgpu_ps i32 @test_min3_i32_uniform(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
 ; GCN-LABEL: test_min3_i32_uniform:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_min_i32 s0, s2, s3
 ; GCN-NEXT:    s_min_i32 s0, s0, s4
 ; GCN-NEXT:    ; return to shader part epilog
   %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b)
   %smin3 = call i32 @llvm.smin.i32(i32 %smin, i32 %c)
   ret i32 %smin3
 }
 
 define i32 @test_min3_i32_commute(i32 %a, i32 %b, i32 %c) {
 ; SI_VI-LABEL: test_min3_i32_commute:
 ; SI_VI:       ; %bb.0:
 ; SI_VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI_VI-NEXT:    v_min_i32_e32 v0, v0, v1
-; SI_VI-NEXT:    v_min_i32_e32 v0, v2, v0
+; SI_VI-NEXT:    v_min3_i32 v0, v0, v1, v2
 ; SI_VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_i32_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_min_i32_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_i32_e32 v0, v2, v0
+; GFX9-NEXT:    v_min3_i32 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_i32_commute:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_min_i32_e32 v0, v0, v1
-; GFX10-NEXT:    v_min_i32_e32 v0, v2, v0
+; GFX10-NEXT:    v_min3_i32 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b)
   %smin3 = call i32 @llvm.smin.i32(i32 %c, i32 %smin)
   ret i32 %smin3
 }
 
 define i16 @test_min3_i16(i16 %a, i16 %b, i16 %c) {
 ; SI-LABEL: test_min3_i16:

 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_min_i16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_i16_e32 v0, v0, v2
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_min_i16_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_i16_e32 v0, v0, v2
+; GFX9-NEXT:    v_min3_i16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_min_i16 v0, v0, v1
-; GFX10-NEXT:    v_min_i16 v0, v0, v2
+; GFX10-NEXT:    v_min3_i16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %smin = call i16 @llvm.smin.i16(i16 %a, i16 %b)
   %smin3 = call i16 @llvm.smin.i16(i16 %smin, i16 %c)
   ret i16 %smin3
 }
 
 define i16 @test_min3_i16_commute(i16 %a, i16 %b, i16 %c) {
 ; SI-LABEL: test_min3_i16_commute:

 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_min_i16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_i16_e32 v0, v2, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: test_min3_i16_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_min_i16_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_i16_e32 v0, v2, v0
+; GFX9-NEXT:    v_min3_i16 v0, v0, v1, v2
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: test_min3_i16_commute:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_min_i16 v0, v0, v1
-; GFX10-NEXT:    v_min_i16 v0, v2, v0
+; GFX10-NEXT:    v_min3_i16 v0, v0, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %smin = call i16 @llvm.smin.i16(i16 %a, i16 %b)
   %smin3 = call i16 @llvm.smin.i16(i16 %c, i16 %smin)
   ret i16 %smin3
 }
 
 define amdgpu_ps void @test_min3_u32_2_uses(i32 %a, i32 %b, i32 %c, i32 %d, i32 addrspace(1)* %out1, i32 addrspace(1)* %out2) {
 ; SI-LABEL: test_min3_u32_2_uses:
; GFX9_10-NEXT:    s_endpgm
   ret void
 }
 
 ; Tests for constant bus limitations on min3 with mixed vgpr and sgpr operands.
 
 define amdgpu_ps void @test_min3_u32_vvv(i32 %a, i32 %b, i32 %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_min3_u32_vvv:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
+; SI-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_min_u32_e32 v0, v0, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[3:4], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_min3_u32_vvv:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_min_u32_e32 v0, v0, v1
-; VI-NEXT:    v_min_u32_e32 v0, v0, v2
+; VI-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; VI-NEXT:    flat_store_dword v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_min3_u32_vvv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_u32_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_min_u32_e32 v0, v0, v2
+; GFX9_10-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; GFX9_10-NEXT:    global_store_dword v[3:4], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
   %min3 = call i32 @llvm.umin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_min3_u32_svv(i32 inreg %a, i32 %b, i32 %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_min3_u32_svv:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_min_u32_e32 v0, s2, v0
+; SI-NEXT:    v_min3_u32 v0, s2, v0, v1
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_min3_u32_svv:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_min_u32_e32 v0, s2, v0
-; VI-NEXT:    v_min_u32_e32 v0, v0, v1
+; VI-NEXT:    v_min3_u32 v0, s2, v0, v1
 ; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_min3_u32_svv:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_u32_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_min_u32_e32 v0, v0, v1
+; GFX9_10-NEXT:    v_min3_u32 v0, s2, v0, v1
 ; GFX9_10-NEXT:    global_store_dword v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
   %min3 = call i32 @llvm.umin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_min3_u32_vvs(i32 %a, i32 %b, i32 inreg %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_min3_u32_vvs:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
-; SI-NEXT:    s_mov_b32 s6, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_min_u32_e32 v0, s2, v0
-; SI-NEXT:    s_mov_b64 s[4:5], 0
-; SI-NEXT:    buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
+; SI-NEXT:    v_min3_u32 v0, v0, v1, s2
+; SI-NEXT:    s_mov_b32 s2, 0
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b64 s[0:1], 0
+; SI-NEXT:    buffer_store_dword v0, v[2:3], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_min3_u32_vvs:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_min_u32_e32 v0, v0, v1
-; VI-NEXT:    v_min_u32_e32 v0, s2, v0
+; VI-NEXT:    v_min3_u32 v0, v0, v1, s2
 ; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9_10-LABEL: test_min3_u32_vvs:
 ; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_u32_e32 v0, v0, v1
-; GFX9_10-NEXT:    v_min_u32_e32 v0, s2, v0
+; GFX9_10-NEXT:    v_min3_u32 v0, v0, v1, s2
 ; GFX9_10-NEXT:    global_store_dword v[2:3], v0, off
 ; GFX9_10-NEXT:    s_endpgm
   %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
   %min3 = call i32 @llvm.umin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
; GFX9_10-NEXT:    s_endpgm
   %min3 = call i32 @llvm.smin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_min3_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_min3_i32_vss:
 ; SI:       ; %bb.0:
-; SI-NEXT:    v_min_i32_e32 v0, s2, v0
-; SI-NEXT:    s_mov_b32 s6, 0
-; SI-NEXT:    s_mov_b32 s7, 0xf000
-; SI-NEXT:    v_min_i32_e32 v0, s3, v0
-; SI-NEXT:    s_mov_b64 s[4:5], 0
-; SI-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
+; SI-NEXT:    v_mov_b32_e32 v3, s3
+; SI-NEXT:    v_min3_i32 v0, v0, s2, v3
+; SI-NEXT:    s_mov_b32 s2, 0
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b64 s[0:1], 0
+; SI-NEXT:    buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_min3_i32_vss:
 ; VI:       ; %bb.0:
-; VI-NEXT:    v_min_i32_e32 v0, s2, v0
-; VI-NEXT:    v_min_i32_e32 v0, s3, v0
+; VI-NEXT:    v_mov_b32_e32 v3, s3
+; VI-NEXT:    v_min3_i32 v0, v0, s2, v3
 ; VI-NEXT:    flat_store_dword v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9_10-LABEL: test_min3_i32_vss:
-; GFX9_10:       ; %bb.0:
-; GFX9_10-NEXT:    v_min_i32_e32 v0, s2, v0
-; GFX9_10-NEXT:    v_min_i32_e32 v0, s3, v0
-; GFX9_10-NEXT:    global_store_dword v[1:2], v0, off
-; GFX9_10-NEXT:    s_endpgm
+; GFX9-LABEL: test_min3_i32_vss:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    v_min3_i32 v0, v0, s2, v3
+; GFX9-NEXT:    global_store_dword v[1:2], v0, off
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: test_min3_i32_vss:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_min3_i32 v0, v0, s2, s3
+; GFX10-NEXT:    global_store_dword v[1:2], v0, off
+; GFX10-NEXT:    s_endpgm
   %min = call i32 @llvm.smin.i32(i32 %a, i32 %b)
   %min3 = call i32 @llvm.smin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_min3_i32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 addrspace(1)* %out) {
 ; SI-LABEL: test_min3_i32_sss:

 ; SI-LABEL: test_min3_u16_vvv:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_mov_b32 s0, 0xffff
 ; SI-NEXT:    s_mov_b32 s2, 0
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    v_and_b32_e32 v0, s0, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s0, v1
 ; SI-NEXT:    v_and_b32_e32 v2, s0, v2
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
-; SI-NEXT:    v_min_u32_e32 v0, v0, v2
+; SI-NEXT:    v_min3_u32 v0, v0, v1, v2
 ; SI-NEXT:    s_mov_b64 s[0:1], 0
 ; SI-NEXT:    buffer_store_short v0, v[3:4], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_min3_u16_vvv:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_u16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_u16_e32 v0, v0, v2
 ; VI-NEXT:    flat_store_short v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: test_min3_u16_vvv:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_min_u16_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_u16_e32 v0, v0, v2
-; GFX9-NEXT:    global_store_short v[3:4], v0, off
-; GFX9-NEXT:    s_endpgm
-;
-; GFX10-LABEL: test_min3_u16_vvv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_min_u16 v0, v0, v1
-; GFX10-NEXT:    v_min_u16 v0, v0, v2
-; GFX10-NEXT:    global_store_short v[3:4], v0, off
-; GFX10-NEXT:    s_endpgm
+; GFX9_10-LABEL: test_min3_u16_vvv:
+; GFX9_10:       ; %bb.0:
+; GFX9_10-NEXT:    v_min3_u16 v0, v0, v1, v2
+; GFX9_10-NEXT:    global_store_short v[3:4], v0, off
+; GFX9_10-NEXT:    s_endpgm
   %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
   %min3 = call i16 @llvm.umin.i16(i16 %min, i16 %c)
   store i16 %min3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_min3_u16_svv(i16 inreg %a, i16 %b, i16 %c, i16 addrspace(1)* %out) {
 ; SI-LABEL: test_min3_u16_svv:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_mov_b32 s0, 0xffff
 ; SI-NEXT:    s_mov_b32 s6, 0
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_and_b32 s1, s2, s0
 ; SI-NEXT:    v_and_b32_e32 v0, s0, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s0, v1
-; SI-NEXT:    v_min_u32_e32 v0, s1, v0
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
+; SI-NEXT:    v_min3_u32 v0, s1, v0, v1
 ; SI-NEXT:    s_mov_b64 s[4:5], 0
 ; SI-NEXT:    buffer_store_short v0, v[2:3], s[4:7], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_min3_u16_svv:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_u16_e32 v0, s2, v0
 ; VI-NEXT:    v_min_u16_e32 v0, v0, v1
 ; VI-NEXT:    flat_store_short v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: test_min3_u16_svv:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_min_u16_e32 v0, s2, v0
-; GFX9-NEXT:    v_min_u16_e32 v0, v0, v1
-; GFX9-NEXT:    global_store_short v[2:3], v0, off
-; GFX9-NEXT:    s_endpgm
-;
-; GFX10-LABEL: test_min3_u16_svv:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_min_u16 v0, s2, v0
-; GFX10-NEXT:    v_min_u16 v0, v0, v1
-; GFX10-NEXT:    global_store_short v[2:3], v0, off
-; GFX10-NEXT:    s_endpgm
+; GFX9_10-LABEL: test_min3_u16_svv:
+; GFX9_10:       ; %bb.0:
+; GFX9_10-NEXT:    v_min3_u16 v0, s2, v0, v1
+; GFX9_10-NEXT:    global_store_short v[2:3], v0, off
+; GFX9_10-NEXT:    s_endpgm
   %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
   %min3 = call i16 @llvm.umin.i16(i16 %min, i16 %c)
   store i16 %min3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_min3_u16_vvs(i16 %a, i16 %b, i16 inreg %c, i16 addrspace(1)* %out) {
 ; SI-LABEL: test_min3_u16_vvs:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_mov_b32 s0, 0xffff
 ; SI-NEXT:    s_mov_b32 s6, 0
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    v_and_b32_e32 v0, s0, v0
 ; SI-NEXT:    v_and_b32_e32 v1, s0, v1
 ; SI-NEXT:    s_and_b32 s0, s2, s0
-; SI-NEXT:    v_min_u32_e32 v0, v0, v1
-; SI-NEXT:    v_min_u32_e32 v0, s0, v0
+; SI-NEXT:    v_min3_u32 v0, v0, v1, s0
 ; SI-NEXT:    s_mov_b64 s[4:5], 0
 ; SI-NEXT:    buffer_store_short v0, v[2:3], s[4:7], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: test_min3_u16_vvs:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_u16_e32 v0, v0, v1
 ; VI-NEXT:    v_min_u16_e32 v0, s2, v0
 ; VI-NEXT:    flat_store_short v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: test_min3_u16_vvs:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_min_u16_e32 v0, v0, v1
-; GFX9-NEXT:    v_min_u16_e32 v0, s2, v0
-; GFX9-NEXT:    global_store_short v[2:3], v0, off
-; GFX9-NEXT:    s_endpgm
-;
-; GFX10-LABEL: test_min3_u16_vvs:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_min_u16 v0, v0, v1
-; GFX10-NEXT:    v_min_u16 v0, v0, s2
-; GFX10-NEXT:    global_store_short v[2:3], v0, off
-; GFX10-NEXT:    s_endpgm
+; GFX9_10-LABEL: test_min3_u16_vvs:
+; GFX9_10:       ; %bb.0:
+; GFX9_10-NEXT:    v_min3_u16 v0, v0, v1, s2
+; GFX9_10-NEXT:    global_store_short v[2:3], v0, off
+; GFX9_10-NEXT:    s_endpgm
   %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
   %min3 = call i16 @llvm.umin.i16(i16 %min, i16 %c)
   store i16 %min3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 define amdgpu_ps void @test_min3_i16_ssv(i16 inreg %a, i16 inreg %b, i16 %c, i16 addrspace(1)* %out) {
 ; SI-LABEL: test_min3_i16_ssv:

 ; VI:       ; %bb.0:
 ; VI-NEXT:    v_min_i16_e32 v0, s2, v0
 ; VI-NEXT:    v_min_i16_e32 v0, s3, v0
 ; VI-NEXT:    flat_store_short v[1:2], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: test_min3_i16_vss:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    v_min_i16_e32 v0, s2, v0
-; GFX9-NEXT:    v_min_i16_e32 v0, s3, v0
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    v_min3_i16 v0, v0, s2, v3
 ; GFX9-NEXT:    global_store_short v[1:2], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: test_min3_i16_vss:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_min_i16 v0, v0, s2
-; GFX10-NEXT:    v_min_i16 v0, v0, s3
+; GFX10-NEXT:    v_min3_i16 v0, v0, s2, s3
 ; GFX10-NEXT:    global_store_short v[1:2], v0, off
 ; GFX10-NEXT:    s_endpgm
   %min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
   %min3 = call i16 @llvm.smin.i16(i16 %min, i16 %c)
   store i16 %min3, i16 addrspace(1)* %out, align 4
   ret void
 }
 

llvm/test/CodeGen/AMDGPU/ctlz.ll

 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x13
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_flbit_i32_b32 s4, s4
 ; SI-NEXT:    s_flbit_i32_b32 s5, s5
 ; SI-NEXT:    s_min_u32 s4, s4, 0xffffffdf
-; SI-NEXT:    v_mov_b32_e32 v0, s5
 ; SI-NEXT:    s_add_i32 s4, s4, 32
-; SI-NEXT:    v_min3_u32 v0, s4, v0, 64
+; SI-NEXT:    s_min_u32 s4, s4, s5
+; SI-NEXT:    s_min_u32 s4, s4, 64
 ; SI-NEXT:    v_mov_b32_e32 v1, 0
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_ctlz_i64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x4c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    v_mov_b32_e32 v1, 0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_flbit_i32_b32 s4, s4
 ; VI-NEXT:    v_add_u32_e64 v0, s[6:7], s4, 32 clamp
 ; VI-NEXT:    s_flbit_i32_b32 s4, s5
-; VI-NEXT:    v_min3_u32 v0, v0, s4, 64
+; VI-NEXT:    v_min_u32_e32 v0, s4, v0
+; VI-NEXT:    v_min_u32_e32 v0, 64, v0
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_ctlz_i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END

 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x4c
 ; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_flbit_i32_b32 s0, s2
 ; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, 32 clamp
 ; GFX10-NEXT:    s_flbit_i32_b32 s0, s3
-; GFX10-NEXT:    v_min3_u32 v0, v0, s0, 64
+; GFX10-NEXT:    v_min_u32_e32 v0, s0, v0
+; GFX10-NEXT:    v_min_u32_e32 v0, 64, v0
 ; GFX10-NEXT:    global_store_dwordx2 v1, v[0:1], s[4:5]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX10-GISEL-LABEL: s_ctlz_i64:
 ; GFX10-GISEL:       ; %bb.0:
 ; GFX10-GISEL-NEXT:    s_clause 0x1
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x4c
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24

 }
 
 define amdgpu_kernel void @s_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
 ; SI-LABEL: s_ctlz_i64_trunc:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_flbit_i32_b32 s4, s4
-; SI-NEXT:    s_min_u32 s4, s4, 0xffffffdf
-; SI-NEXT:    s_flbit_i32_b32 s5, s5
-; SI-NEXT:    s_add_i32 s4, s4, 32
-; SI-NEXT:    v_mov_b32_e32 v0, s5
-; SI-NEXT:    v_min3_u32 v0, s4, v0, 64
+; SI-NEXT:    s_flbit_i32_b32 s2, s4
+; SI-NEXT:    s_flbit_i32_b32 s4, s5
+; SI-NEXT:    s_min_u32 s2, s2, 0xffffffdf
+; SI-NEXT:    s_add_i32 s2, s2, 32
+; SI-NEXT:    s_min_u32 s2, s2, s4
+; SI-NEXT:    s_min_u32 s4, s2, 64
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_ctlz_i64_trunc:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_flbit_i32_b32 s4, s4
 ; VI-NEXT:    v_add_u32_e64 v0, s[6:7], s4, 32 clamp
 ; VI-NEXT:    s_flbit_i32_b32 s4, s5
-; VI-NEXT:    v_min3_u32 v0, v0, s4, 64
+; VI-NEXT:    v_min_u32_e32 v0, s4, v0
+; VI-NEXT:    v_min_u32_e32 v0, 64, v0
 ; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_ctlz_i64_trunc:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; EG-NEXT:    CF_END

 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
 ; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_flbit_i32_b32 s0, s2
 ; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, 32 clamp
 ; GFX10-NEXT:    s_flbit_i32_b32 s0, s3
-; GFX10-NEXT:    v_min3_u32 v0, v0, s0, 64
+; GFX10-NEXT:    v_min_u32_e32 v0, s0, v0
+; GFX10-NEXT:    v_min_u32_e32 v0, 64, v0
 ; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX10-GISEL-LABEL: s_ctlz_i64_trunc:
 ; GFX10-GISEL:       ; %bb.0:
 ; GFX10-GISEL-NEXT:    s_clause 0x1
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24

 ; GFX10-GISEL-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-GISEL-NEXT:    v_ffbh_u32_e32 v0, v0
 ; GFX10-GISEL-NEXT:    v_ffbh_u32_e32 v1, v1
 ; GFX10-GISEL-NEXT:    v_add_nc_u32_e64 v0, v0, 32 clamp
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT:    v_min3_u32 v0, v1, v0, 64
 ; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v0, 64, v0
 ; GFX10-GISEL-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
   %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
   %val = load i64, i64 addrspace(1)* %in.gep
   %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false)
   store i64 %ctlz, i64 addrspace(1)* %out.gep

 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    global_load_dwordx2 v[1:2], v1, s[2:3]
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-GISEL-NEXT:    v_ffbh_u32_e32 v1, v1
 ; GFX10-GISEL-NEXT:    v_ffbh_u32_e32 v2, v2
 ; GFX10-GISEL-NEXT:    v_add_nc_u32_e64 v1, v1, 32 clamp
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v1, v2, v1
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v1, 64, v1
+; GFX10-GISEL-NEXT:    v_min3_u32 v1, v2, v1, 64
 ; GFX10-GISEL-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
   %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
   %val = load i64, i64 addrspace(1)* %in.gep
   %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false)
   %trunc = trunc i64 %ctlz to i32

llvm/test/CodeGen/AMDGPU/cttz.ll

 ; SI-LABEL: s_cttz_i64:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x13
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_ff1_i32_b32 s5, s5
+; SI-NEXT:    s_ff1_i32_b32 s4, s4
 ; SI-NEXT:    s_min_u32 s5, s5, 0xffffffdf
 ; SI-NEXT:    s_add_i32 s5, s5, 32
-; SI-NEXT:    s_ff1_i32_b32 s4, s4
-; SI-NEXT:    v_mov_b32_e32 v0, s5
-; SI-NEXT:    v_min3_u32 v0, s4, v0, 64
+; SI-NEXT:    s_min_u32 s4, s4, s5
+; SI-NEXT:    s_min_u32 s4, s4, 64
 ; SI-NEXT:    v_mov_b32_e32 v1, 0
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_cttz_i64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x4c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    v_mov_b32_e32 v1, 0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_ff1_i32_b32 s5, s5
 ; VI-NEXT:    v_add_u32_e64 v0, s[6:7], s5, 32 clamp
 ; VI-NEXT:    s_ff1_i32_b32 s4, s4
-; VI-NEXT:    v_min3_u32 v0, s4, v0, 64
+; VI-NEXT:    v_min_u32_e32 v0, s4, v0
+; VI-NEXT:    v_min_u32_e32 v0, 64, v0
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_cttz_i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END

 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x4c
 ; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_ff1_i32_b32 s0, s3
 ; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, 32 clamp
 ; GFX10-NEXT:    s_ff1_i32_b32 s0, s2
-; GFX10-NEXT:    v_min3_u32 v0, s0, v0, 64
+; GFX10-NEXT:    v_min_u32_e32 v0, s0, v0
+; GFX10-NEXT:    v_min_u32_e32 v0, 64, v0
 ; GFX10-NEXT:    global_store_dwordx2 v1, v[0:1], s[4:5]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX10-GISEL-LABEL: s_cttz_i64:
 ; GFX10-GISEL:       ; %bb.0:
 ; GFX10-GISEL-NEXT:    s_clause 0x1
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x4c
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24

 }
 
 define amdgpu_kernel void @s_cttz_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
 ; SI-LABEL: s_cttz_i64_trunc:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_ff1_i32_b32 s5, s5
-; SI-NEXT:    s_min_u32 s5, s5, 0xffffffdf
-; SI-NEXT:    s_add_i32 s5, s5, 32
+; SI-NEXT:    s_ff1_i32_b32 s2, s5
 ; SI-NEXT:    s_ff1_i32_b32 s4, s4
-; SI-NEXT:    v_mov_b32_e32 v0, s5
-; SI-NEXT:    v_min3_u32 v0, s4, v0, 64
+; SI-NEXT:    s_min_u32 s2, s2, 0xffffffdf
+; SI-NEXT:    s_add_i32 s2, s2, 32
+; SI-NEXT:    s_min_u32 s2, s4, s2
+; SI-NEXT:    s_min_u32 s4, s2, 64
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_cttz_i64_trunc:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_ff1_i32_b32 s5, s5
 ; VI-NEXT:    v_add_u32_e64 v0, s[6:7], s5, 32 clamp
 ; VI-NEXT:    s_ff1_i32_b32 s4, s4
-; VI-NEXT:    v_min3_u32 v0, s4, v0, 64
+; VI-NEXT:    v_min_u32_e32 v0, s4, v0
+; VI-NEXT:    v_min_u32_e32 v0, 64, v0
 ; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_cttz_i64_trunc:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; EG-NEXT:    CF_END

 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
 ; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_ff1_i32_b32 s0, s3
 ; GFX10-NEXT:    v_add_nc_u32_e64 v0, s0, 32 clamp
 ; GFX10-NEXT:    s_ff1_i32_b32 s0, s2
-; GFX10-NEXT:    v_min3_u32 v0, s0, v0, 64
+; GFX10-NEXT:    v_min_u32_e32 v0, s0, v0
+; GFX10-NEXT:    v_min_u32_e32 v0, 64, v0
 ; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX10-GISEL-LABEL: s_cttz_i64_trunc:
 ; GFX10-GISEL:       ; %bb.0:
 ; GFX10-GISEL-NEXT:    s_clause 0x1
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24

 ; GFX10-GISEL-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-GISEL-NEXT:    v_ffbl_b32_e32 v1, v1
 ; GFX10-GISEL-NEXT:    v_ffbl_b32_e32 v0, v0
 ; GFX10-GISEL-NEXT:    v_add_nc_u32_e64 v1, v1, 32 clamp
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT:    v_min3_u32 v0, v0, v1, 64
 ; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v0, 64, v0
 ; GFX10-GISEL-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
   %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
   %val = load i64, i64 addrspace(1)* %in.gep
   %cttz = call i64 @llvm.cttz.i64(i64 %val, i1 false)
   store i64 %cttz, i64 addrspace(1)* %out.gep

 ; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-GISEL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    global_load_dwordx2 v[1:2], v1, s[2:3]
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-GISEL-NEXT:    v_ffbl_b32_e32 v2, v2
 ; GFX10-GISEL-NEXT:    v_ffbl_b32_e32 v1, v1
 ; GFX10-GISEL-NEXT:    v_add_nc_u32_e64 v2, v2, 32 clamp
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v1, v1, v2
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v1, 64, v1
+; GFX10-GISEL-NEXT:    v_min3_u32 v1, v1, v2, 64
 ; GFX10-GISEL-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
   %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
   %val = load i64, i64 addrspace(1)* %in.gep
   %cttz = call i64 @llvm.cttz.i64(i64 %val, i1 false)
   %trunc = trunc i64 %cttz to i32

llvm/test/CodeGen/AMDGPU/fmax3.ll

-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,CST_BUS_LIM_1 %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CST_BUS_LIM_1 %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SI_VI,CST_BUS_LIM_1 %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SI_VI,CST_BUS_LIM_1 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9_10,CST_BUS_LIM_1 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,GFX9_10,CST_BUS_LIM_2 %s
 
 ; GCN-LABEL: {{^}}test_fmax3_olt_0_f32:
-; GCN: buffer_load_dword [[REGC:v[0-9]+]]
-; GCN: buffer_load_dword [[REGB:v[0-9]+]]
 ; GCN: buffer_load_dword [[REGA:v[0-9]+]]
-; GCN: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
+; GCN: buffer_load_dword [[REGB:v[0-9]+]]
+; GCN: buffer_load_dword [[REGC:v[0-9]+]]
+; SI_VI: v_mul_f32_e32 [[QUIET_A:v[0-9]+]], 1.0, [[REGA]]
+; SI_VI: v_mul_f32_e32 [[QUIET_B:v[0-9]+]], 1.0, [[REGB]]
+; GFX9_10: v_max_f32_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
+; GFX9_10: v_max_f32_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
+; GCN: v_max_f32_e32 [[FMAX:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; SI_VI: v_mul_f32_e32 [[QUIET_C:v[0-9]+]], 1.0, [[REGC]]
+; GFX9_10: v_max_f32_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
+; GCN: v_max_f32_e32 [[RESULT:v[0-9]+]], [[FMAX]], [[QUIET_C]]
 ; GCN: buffer_store_dword [[RESULT]],
 ; GCN: s_endpgm
 define amdgpu_kernel void @test_fmax3_olt_0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
   %a = load volatile  float, float addrspace(1)* %aptr, align 4
   %b = load volatile float, float addrspace(1)* %bptr, align 4
   %c = load volatile float, float addrspace(1)* %cptr, align 4
   %f0 = call float @llvm.maxnum.f32(float %a, float %b)
   %f1 = call float @llvm.maxnum.f32(float %f0, float %c)
   store float %f1, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; Commute operand of second fmax
 ; GCN-LABEL: {{^}}test_fmax3_olt_1_f32:
-; GCN: buffer_load_dword [[REGB:v[0-9]+]]
 ; GCN: buffer_load_dword [[REGA:v[0-9]+]]
+; GCN: buffer_load_dword [[REGB:v[0-9]+]]
 ; GCN: buffer_load_dword [[REGC:v[0-9]+]]
-; GCN: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
+; SI_VI: v_mul_f32_e32 [[QUIET_A:v[0-9]+]], 1.0, [[REGA]]
+; SI_VI: v_mul_f32_e32 [[QUIET_B:v[0-9]+]], 1.0, [[REGB]]
+; GFX9_10: v_max_f32_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
+; GFX9_10: v_max_f32_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
+; GCN: v_max_f32_e32 [[FMAX:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; SI_VI: v_mul_f32_e32 [[QUIET_C:v[0-9]+]], 1.0, [[REGC]]
+; GFX9_10: v_max_f32_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
+; GCN: v_max_f32_e32 [[RESULT:v[0-9]+]], [[QUIET_C]], [[FMAX]]
 ; GCN: buffer_store_dword [[RESULT]],
 ; GCN: s_endpgm
 define amdgpu_kernel void @test_fmax3_olt_1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
   %a = load volatile float, float addrspace(1)* %aptr, align 4
   %b = load volatile float, float addrspace(1)* %bptr, align 4
   %c = load volatile float, float addrspace(1)* %cptr, align 4
   %f0 = call float @llvm.maxnum.f32(float %a, float %b)
   %f1 = call float @llvm.maxnum.f32(float %c, float %f0)
   store float %f1, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_fmax3_olt_0_f16:
 ; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
 ; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
 ; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
 
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]]
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]]
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]]
-; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_A]], [[CVT_B]], [[CVT_C]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_A:v[0-9]+]], 1.0, [[CVT_A]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_B:v[0-9]+]], 1.0, [[CVT_B]]
+; SI-DAG: v_max_f32_e32 [[FMAX:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_C:v[0-9]+]], 1.0, [[CVT_C]]
+; SI-DAG: v_max_f32_e32 [[RESULT_F32:v[0-9]+]], [[FMAX]], [[QUIET_C]]
 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]]
 
 ; VI-DAG: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
 ; VI-DAG: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
 ; VI: v_max_f16_e32 [[MAX0:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
 ; VI: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], [[MAX0]], [[QUIET_C]]
 
-; GFX9_10: v_max3_f16 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], [[REGC]]
+
+; GFX9_10: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
+; GFX9_10: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
+; GFX9_10: v_max_f16_e32 [[FMAX:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; GFX9_10: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
+; GFX9_10: v_max_f16_e32 [[RESULT:v[0-9]+]], [[FMAX]], [[QUIET_C]]
 ; GCN: buffer_store_short [[RESULT]],
 define amdgpu_kernel void @test_fmax3_olt_0_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
   %a = load volatile half, half addrspace(1)* %aptr, align 2
   %b = load volatile half, half addrspace(1)* %bptr, align 2
   %c = load volatile half, half addrspace(1)* %cptr, align 2
   %f0 = call half @llvm.maxnum.f16(half %a, half %b)
   %f1 = call half @llvm.maxnum.f16(half %f0, half %c)
   store half %f1, half addrspace(1)* %out, align 2
   ret void
 }
 
 ; Commute operand of second fmax
 ; GCN-LABEL: {{^}}test_fmax3_olt_1_f16:
 ; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
 ; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
 ; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
 
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]]
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]]
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]]
-; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_C]], [[CVT_A]], [[CVT_B]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_A:v[0-9]+]], 1.0, [[CVT_A]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_B:v[0-9]+]], 1.0, [[CVT_B]]
+; SI-DAG: v_max_f32_e32 [[FMAX:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_C:v[0-9]+]], 1.0, [[CVT_C]]
+; SI-DAG: v_max_f32_e32 [[RESULT_F32:v[0-9]+]], [[QUIET_C]], [[FMAX]]
 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]]
 
 ; VI-DAG: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
 ; VI-DAG: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
 ; VI: v_max_f16_e32 [[MAX0:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
 ; VI: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
 ; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], [[QUIET_C]], [[MAX0]]
 
-; GFX9_10: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]]
+; GFX9_10: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
+; GFX9_10: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
+; GFX9_10: v_max_f16_e32 [[FMAX:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; GFX9_10: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
+; GFX9_10: v_max_f16_e32 [[RESULT:v[0-9]+]], [[QUIET_C]], [[FMAX]]
 ; GCN: buffer_store_short [[RESULT]],
 define amdgpu_kernel void @test_fmax3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
   %a = load volatile half, half addrspace(1)* %aptr, align 2
   %b = load volatile half, half addrspace(1)* %bptr, align 2
   %c = load volatile half, half addrspace(1)* %cptr, align 2
   %f0 = call half @llvm.maxnum.f16(half %a, half %b)
   %f1 = call half @llvm.maxnum.f16(half %c, half %f0)
   store half %f1, half addrspace(1)* %out, align 2
define amdgpu_ps void @test_max3_f32_vss(float %a, float inreg %b, float inreg %c, float addrspace(1)* %out) {
   %fmax = call float @llvm.maxnum.f32(float %a, float %b)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_f32_sss:
 ; CST_BUS_LIM_1: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; CST_BUS_LIM_1: v_max3_f32 v{{[0-9]+}}, s0, v[[B]], v[[C]]
+; CST_BUS_LIM_1: v_max_f32_e32 v[[FMAX:[0-9]+]], s0, v[[B]]
+; CST_BUS_LIM_1: v_max_f32_e32 v{{[0-9]+}}, s2, v[[FMAX]]
 
-; CST_BUS_LIM_2: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; CST_BUS_LIM_2: v_max3_f32 v{{[0-9]+}}, s0, s1, v[[C]]
+; CST_BUS_LIM_2: v_max_f32_e64 v[[FMAX:[0-9]+]], s0, s1
+; CST_BUS_LIM_2: v_max_f32_e32 v{{[0-9]+}}, s2, v[[FMAX]]
 define amdgpu_ps void @test_max3_f32_sss(float inreg %a, float inreg %b, float inreg %c, float addrspace(1)* %out) {
   %fmax = call float @llvm.maxnum.f32(float %a, float %b)
   %fmax3 = call float @llvm.maxnum.f32(float %fmax, float %c)
   store float %fmax3, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_f16_vvv:

 
 ; GCN-LABEL: {{^}}test_max3_f16_sss:
 ; SI: v_cvt_f16_f32_e32 v[[C_F16:[0-9]+]], s2
 ; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], s1
 ; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], s0
 ; SI: v_cvt_f32_f16_e32 v[[C:[0-9]+]], v[[C_F16]]
 ; SI: v_cvt_f32_f16_e32 v[[B:[0-9]+]], v[[B_F16]]
 ; SI: v_cvt_f32_f16_e32 v[[A:[0-9]+]], v[[A_F16]]
-; SI: v_max3_f32 v{{[0-9]+}}, v[[A]], v[[B]], v[[C]]
+; SI: v_max_f32_e32 v[[FMAX:[0-9]+]], v[[A]], v[[B]]
+; SI: v_max_f32_e32 v{{[0-9]+}}, v[[FMAX]], v[[C]]
 ; VI: v_mov_b32_e32 v[[B:[0-9]+]], s1
 ; VI: v_max_f16_e32 v[[MAX:[0-9]+]], s0, v[[B]]
 ; VI: v_max_f16_e32 v{{[0-9]+}}, s2, v[[MAX]]
 ; GFX9: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; GFX9: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; GFX9: v_max3_f16 v{{[0-9]+}}, s0, v[[B]], v[[C]]
-; GFX10: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; GFX10: v_max3_f16 v{{[0-9]+}}, s0, s1, v[[C]]
+; GFX9: v_max_f16_e32 v[[FMAX:[0-9]+]], s0, v[[B]]
+; GFX9: v_max_f16_e32 v{{[0-9]+}}, s2, v[[FMAX]]
+; GFX10: v_max_f16_e64 v[[FMAX:[0-9]+]], s0, s1
+; GFX10: v_max_f16_e32 v{{[0-9]+}}, s2, v[[FMAX]]
 define amdgpu_ps void @test_max3_f16_sss(half inreg %a, half inreg %b, half inreg %c, half addrspace(1)* %out) {
   %fmax = call half @llvm.maxnum.f16(half %a, half %b)
   %fmax3 = call half @llvm.maxnum.f16(half %fmax, half %c)
   store half %fmax3, half addrspace(1)* %out, align 4
   ret void
 }
 
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 declare float @llvm.maxnum.f32(float, float) #1
 declare half @llvm.maxnum.f16(half, half) #1
 declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
 declare float @llvm.fabs.f32(float)
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone speculatable }
 attributes #2 = { nounwind "no-nans-fp-math"="true" }

llvm/test/CodeGen/AMDGPU/fmin3.ll

-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,CST_BUS_LIM_1 %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CST_BUS_LIM_1 %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SI_VI,CST_BUS_LIM_1 %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SI_VI,CST_BUS_LIM_1 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9_10,CST_BUS_LIM_1 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10,GFX9_10,CST_BUS_LIM_2 %s
 
 ; GCN-LABEL: {{^}}test_fmin3_olt_0_f32:
-; GCN: buffer_load_dword [[REGC:v[0-9]+]]
-; GCN: buffer_load_dword [[REGB:v[0-9]+]]
 ; GCN: buffer_load_dword [[REGA:v[0-9]+]]
-; GCN: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
+; GCN: buffer_load_dword [[REGB:v[0-9]+]]
+; GCN: buffer_load_dword [[REGC:v[0-9]+]]
+; SI_VI: v_mul_f32_e32 [[QUIET_A:v[0-9]+]], 1.0, [[REGA]]
+; SI_VI: v_mul_f32_e32 [[QUIET_B:v[0-9]+]], 1.0, [[REGB]]
+; GFX9_10: v_max_f32_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
+; GFX9_10: v_max_f32_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
+; GCN: v_min_f32_e32 [[FMIN:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; SI_VI: v_mul_f32_e32 [[QUIET_C:v[0-9]+]], 1.0, [[REGC]]
+; GFX9_10: v_max_f32_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
+; GCN: v_min_f32_e32 [[RESULT:v[0-9]+]], [[FMIN]], [[QUIET_C]]
 ; GCN: buffer_store_dword [[RESULT]],
 define amdgpu_kernel void @test_fmin3_olt_0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
   %a = load volatile float, float addrspace(1)* %aptr, align 4
   %b = load volatile float, float addrspace(1)* %bptr, align 4
   %c = load volatile float, float addrspace(1)* %cptr, align 4
   %f0 = call float @llvm.minnum.f32(float %a, float %b)
   %f1 = call float @llvm.minnum.f32(float %f0, float %c)
   store float %f1, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; Commute operand of second fmin
 ; GCN-LABEL: {{^}}test_fmin3_olt_1_f32:
-; GCN: buffer_load_dword [[REGB:v[0-9]+]]
 ; GCN: buffer_load_dword [[REGA:v[0-9]+]]
+; GCN: buffer_load_dword [[REGB:v[0-9]+]]
 ; GCN: buffer_load_dword [[REGC:v[0-9]+]]
-; GCN: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
+; SI_VI: v_mul_f32_e32 [[QUIET_A:v[0-9]+]], 1.0, [[REGA]]
+; SI_VI: v_mul_f32_e32 [[QUIET_B:v[0-9]+]], 1.0, [[REGB]]
+; GFX9_10: v_max_f32_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
+; GFX9_10: v_max_f32_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
+; GCN: v_min_f32_e32 [[FMIN:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; SI_VI: v_mul_f32_e32 [[QUIET_C:v[0-9]+]], 1.0, [[REGC]]
+; GFX9_10: v_max_f32_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
+; GCN: v_min_f32_e32 [[RESULT:v[0-9]+]], [[QUIET_C]], [[FMIN]]
 ; GCN: buffer_store_dword [[RESULT]],
 define amdgpu_kernel void @test_fmin3_olt_1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
   %a = load volatile float, float addrspace(1)* %aptr, align 4
   %b = load volatile float, float addrspace(1)* %bptr, align 4
   %c = load volatile float, float addrspace(1)* %cptr, align 4
   %f0 = call float @llvm.minnum.f32(float %a, float %b)
   %f1 = call float @llvm.minnum.f32(float %c, float %f0)
   store float %f1, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_fmin3_olt_0_f16:
-; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
-; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
 ; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
+; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
+; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
 
-; SI: v_min3_f32 [[RESULT_F32:v[0-9]+]],
+; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]]
+; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]]
+; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_A:v[0-9]+]], 1.0, [[CVT_A]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_B:v[0-9]+]], 1.0, [[CVT_B]]
+; SI-DAG: v_min_f32_e32 [[FMIN:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_C:v[0-9]+]], 1.0, [[CVT_C]]
+; SI-DAG: v_min_f32_e32 [[RESULT_F32:v[0-9]+]], [[FMIN]], [[QUIET_C]]
 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
 
 ; VI: v_min_f16_e32
 ; VI: v_min_f16_e32 [[RESULT:v[0-9]+]],
 
-; GFX9_10: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
+; GFX9_10: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
+; GFX9_10: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
+; GFX9_10: v_min_f16_e32 [[FMIN:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; GFX9_10: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
+; GFX9_10: v_min_f16_e32 [[RESULT:v[0-9]+]], [[FMIN]], [[QUIET_C]]
+
 ; GCN: buffer_store_short [[RESULT]],
 define amdgpu_kernel void @test_fmin3_olt_0_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
   %a = load volatile half, half addrspace(1)* %aptr, align 2
   %b = load volatile half, half addrspace(1)* %bptr, align 2
   %c = load volatile half, half addrspace(1)* %cptr, align 2
   %f0 = call half @llvm.minnum.f16(half %a, half %b)
   %f1 = call half @llvm.minnum.f16(half %f0, half %c)
   store half %f1, half addrspace(1)* %out, align 2
   ret void
 }
 
 ; Commute operand of second fmin
 ; GCN-LABEL: {{^}}test_fmin3_olt_1_f16:
 ; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
 ; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
 ; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
 
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]]
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]]
 ; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]]
-; SI: v_min3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_C]], [[CVT_A]], [[CVT_B]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_A:v[0-9]+]], 1.0, [[CVT_A]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_B:v[0-9]+]], 1.0, [[CVT_B]]
+; SI-DAG: v_min_f32_e32 [[FMIN:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; SI-DAG: v_mul_f32_e32 [[QUIET_C:v[0-9]+]], 1.0, [[CVT_C]]
+; SI-DAG: v_min_f32_e32 [[RESULT_F32:v[0-9]+]], [[QUIET_C]], [[FMIN]]
 ; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]]
 
 ; VI: v_min_f16_e32
 ; VI: v_min_f16_e32 [[RESULT:v[0-9]+]],
 
-; GFX9_10: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]]
+; GFX9_10: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]]
+; GFX9_10: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]]
+; GFX9_10: v_min_f16_e32 [[FMIN:v[0-9]+]], [[QUIET_A]], [[QUIET_B]]
+; GFX9_10: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]]
+; GFX9_10: v_min_f16_e32 [[RESULT:v[0-9]+]], [[QUIET_C]], [[FMIN]]
+
 ; GCN: buffer_store_short [[RESULT]],
 define amdgpu_kernel void @test_fmin3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
   %a = load volatile half, half addrspace(1)* %aptr, align 2
   %b = load volatile half, half addrspace(1)* %bptr, align 2
   %c = load volatile half, half addrspace(1)* %cptr, align 2
   %f0 = call half @llvm.minnum.f16(half %a, half %b)
   %f1 = call half @llvm.minnum.f16(half %c, half %f0)
   store half %f1, half addrspace(1)* %out, align 2
define amdgpu_ps void @test_fmin3_f32_vss(float %a, float inreg %b, float inreg %c, float addrspace(1)* %out) {
   %fmin = call float @llvm.minnum.f32(float %a, float %b)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_fmin3_f32_sss:
 ; CST_BUS_LIM_1: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; CST_BUS_LIM_1: v_min3_f32 v{{[0-9]+}}, s0, v[[B]], v[[C]]
+; CST_BUS_LIM_1: v_min_f32_e32 v[[FMIN:[0-9]+]], s0, v[[B]]
+; CST_BUS_LIM_1: v_min_f32_e32 v{{[0-9]+}}, s2, v[[FMIN]]
 
-; CST_BUS_LIM_2: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; CST_BUS_LIM_2: v_min3_f32 v{{[0-9]+}}, s0, s1, v[[C]]
+; CST_BUS_LIM_2: v_min_f32_e64 v[[FMIN:[0-9]+]], s0, s1
+; CST_BUS_LIM_2: v_min_f32_e32 v{{[0-9]+}}, s2, v[[FMIN]]
 define amdgpu_ps void @test_fmin3_f32_sss(float inreg %a, float inreg %b, float inreg %c, float addrspace(1)* %out) {
   %fmin = call float @llvm.minnum.f32(float %a, float %b)
   %fmin3 = call float @llvm.minnum.f32(float %fmin, float %c)
   store float %fmin3, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_min3_f16_vvv:

 
 ; GCN-LABEL: {{^}}test_min3_f16_sss:
 ; SI: v_cvt_f16_f32_e32 v[[C_F16:[0-9]+]], s2
 ; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], s1
 ; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], s0
 ; SI: v_cvt_f32_f16_e32 v[[C:[0-9]+]], v[[C_F16]]
 ; SI: v_cvt_f32_f16_e32 v[[B:[0-9]+]], v[[B_F16]]
 ; SI: v_cvt_f32_f16_e32 v[[A:[0-9]+]], v[[A_F16]]
-; SI: v_min3_f32 v{{[0-9]+}}, v[[A]], v[[B]], v[[C]]
+; SI: v_min_f32_e32 v[[FMIN:[0-9]+]], v[[A]], v[[B]]
+; SI: v_min_f32_e32 v{{[0-9]+}}, v[[FMIN]], v[[C]]
 ; VI: v_mov_b32_e32 v[[B:[0-9]+]], s1
 ; VI: v_min_f16_e32 v[[MIN:[0-9]+]], s0, v[[B]]
 ; VI: v_min_f16_e32 v{{[0-9]+}}, s2, v[[MIN]]
 ; GFX9: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; GFX9: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; GFX9: v_min3_f16 v{{[0-9]+}}, s0, v[[B]], v[[C]]
-; GFX10: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; GFX10: v_min3_f16 v{{[0-9]+}}, s0, s1, v[[C]]
+; GFX9: v_min_f16_e32 v[[FMIN:[0-9]+]], s0, v[[B]]
+; GFX9: v_min_f16_e32 v{{[0-9]+}}, s2, v[[FMIN]]
+; GFX10: v_min_f16_e64 v[[FMIN:[0-9]+]], s0, s1
+; GFX10: v_min_f16_e32 v{{[0-9]+}}, s2, v[[FMIN]]
 define amdgpu_ps void @test_min3_f16_sss(half inreg %a, half inreg %b, half inreg %c, half addrspace(1)* %out) {
   %fmin = call half @llvm.minnum.f16(half %a, half %b)
   %fmin3 = call half @llvm.minnum.f16(half %fmin, half %c)
   store half %fmin3, half addrspace(1)* %out, align 4
   ret void
 }
 
 declare i32 @llvm.amdgcn.workitem.id.x() #1

llvm/test/CodeGen/AMDGPU/known-never-snan.ll

; GCN-NEXT:    s_setpc_b64 s[30:31]
   %med = call float @llvm.minnum.f32(float %max, float 4.0)
   ret float %med
 }
 
 define float @v_test_known_not_snan_fmin3_input_fmed3_r_i_i_f32(float %a, float %b, float %c) #0 {
 ; GCN-LABEL: v_test_known_not_snan_fmin3_input_fmed3_r_i_i_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; GCN-NEXT:    v_mul_f32_e32 v0, 1.0, v0
+; GCN-NEXT:    v_mul_f32_e32 v2, 1.0, v2
 ; GCN-NEXT:    v_min3_f32 v0, v0, v1, v2
 ; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %min0 = call float @llvm.minnum.f32(float %a, float %b)
   %known.not.snan = call float @llvm.minnum.f32(float %min0, float %c)
   %max = call float @llvm.maxnum.f32(float %known.not.snan, float 2.0)
   %med = call float @llvm.minnum.f32(float %max, float 4.0)
   ret float %med

llvm/test/CodeGen/AMDGPU/max3.ll

define amdgpu_kernel void @v_test_umax3_ugt_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
   %icmp0 = icmp ugt i64 %a, %b
   %i0 = select i1 %icmp0, i64 %a, i64 %b
   %icmp1 = icmp ugt i64 %i0, %c
   %i1 = select i1 %icmp1, i64 %i0, i64 %c
   store i64 %i1, i64 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_u32_2_uses:
 ; GCN-NOT: v_max3
 define amdgpu_ps void @test_max3_u32_2_uses(i32 %a, i32 %b, i32 %c, i32 %d, i32 addrspace(1)* %out1, i32 addrspace(1)* %out2) {
   %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
   %max3_1 = call i32 @llvm.umax.i32(i32 %max, i32 %c)
   %max3_2 = call i32 @llvm.umax.i32(i32 %max, i32 %d)
   store i32 %max3_1, i32 addrspace(1)* %out1, align 4
   store i32 %max3_2, i32 addrspace(1)* %out2, align 4
   ret void

 define amdgpu_ps void @test_max3_u32_vvs(i32 %a, i32 %b, i32 inreg %c, i32 addrspace(1)* %out) {
   %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
   %max3 = call i32 @llvm.umax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_i32_ssv:
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; CST_BUS_LIM_1: v_max3_i32 v{{[0-9]+}}, s0, v[[B]], v0
+; CST_BUS_LIM_1: s_max_i32 s[[S_MIN:[0-9]+]], s0, s1
+; CST_BUS_LIM_1: v_max_i32_e32 v{{[0-9]+}}, s[[S_MIN]], v0
 
 ; CST_BUS_LIM_2: v_max3_i32 v{{[0-9]+}}, s0, s1, v0
 define amdgpu_ps void @test_max3_i32_ssv(i32 inreg %a, i32 inreg %b, i32 %c, i32 addrspace(1)* %out) {
   %max = call i32 @llvm.smax.i32(i32 %a, i32 %b)
   %max3 = call i32 @llvm.smax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_i32_vss:
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[C:[0-9]+]], s1
-; CST_BUS_LIM_1: v_max3_i32 v{{[0-9]+}}, v0, s0, v[[C]]
+; CST_BUS_LIM_1: v_max_i32_e32 v[[MIN:[0-9]+]], s0, v0
+; CST_BUS_LIM_1: v_max_i32_e32 v{{[0-9]+}}, s1, v[[MIN]]
 
 ; CST_BUS_LIM_2: v_max3_i32 v{{[0-9]+}}, v0, s0, s1
 define amdgpu_ps void @test_max3_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c, i32 addrspace(1)* %out) {
   %max = call i32 @llvm.smax.i32(i32 %a, i32 %b)
   %max3 = call i32 @llvm.smax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_i32_sss:
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; CST_BUS_LIM_1: v_max3_i32 v{{[0-9]+}}, s0, v[[B]], v[[C]]
-
-; CST_BUS_LIM_2: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; CST_BUS_LIM_2: v_max3_i32 v{{[0-9]+}}, s0, s1, v[[C]]
+; GCN: s_max_i32 s[[S_MIN:[0-9]+]], s0, s1
+; GCN: s_max_i32 s{{[0-9]+}}, s[[S_MIN]], s2
 define amdgpu_ps void @test_max3_i32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 addrspace(1)* %out) {
   %max = call i32 @llvm.smax.i32(i32 %a, i32 %b)
   %max3 = call i32 @llvm.smax.i32(i32 %max, i32 %c)
   store i32 %max3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_u16_vvv:
define amdgpu_ps void @test_max3_u16_vvs(i16 %a, i16 %b, i16 inreg %c, i16 addrspace(1)* %out) {
   %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
   %max3 = call i16 @llvm.umax.i16(i16 %max, i16 %c)
   store i16 %max3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_i16_ssv:
 ; SI: v_bfe_i32 v[[C:[0-9]+]], v0, 0, 16
-; SI: s_sext_i32_i16 s[[B_TMP:[0-9]+]], s1
+; SI: s_sext_i32_i16 s[[B:[0-9]+]], s1
 ; SI: s_sext_i32_i16 s[[A:[0-9]+]], s0
-; SI: v_mov_b32_e32 v[[B:[0-9]+]], s[[B_TMP]]
-; SI: v_max3_i32 v{{[0-9]+}}, s[[A]], v[[B]], v[[C]]
+; SI: s_max_i32 s[[MAX:[0-9]+]], s[[A]], s[[B]]
+; SI: v_max_i32_e32 v{{[0-9]+}}, s[[MAX]], v[[C]]
 ; VI: v_mov_b32_e32 v[[B:[0-9]+]], s1
 ; VI: v_max_i16_e32 v[[MAX:[0-9]+]], s0, v[[B]]
 ; VI: v_max_i16_e32 v{{[0-9]+}}, v[[MAX]], v0
 ; GFX9: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; GFX9: v_max3_i16 v{{[0-9]+}}, s0, v[[B]], v0
+; GFX9: v_max_i16_e32 v[[MAX:[0-9]+]], s0, v[[B]]
+; GFX9: v_max_i16_e32 v{{[0-9]+}}, v[[MAX]], v0
 ; GFX10: v_max3_i16 v{{[0-9]+}}, s0, s1, v0
 define amdgpu_ps void @test_max3_i16_ssv(i16 inreg %a, i16 inreg %b, i16 %c, i16 addrspace(1)* %out) {
   %max = call i16 @llvm.smax.i16(i16 %a, i16 %b)
   %max3 = call i16 @llvm.smax.i16(i16 %max, i16 %c)
   store i16 %max3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_i16_vss:
-; SI: s_sext_i32_i16 s[[C_TMP:[0-9]+]], s1
+; SI: s_sext_i32_i16 s[[C:[0-9]+]], s1
 ; SI: s_sext_i32_i16 s[[B:[0-9]+]], s0
 ; SI: v_bfe_i32 v[[A:[0-9]+]], v0, 0, 16
-; SI: v_mov_b32_e32 v[[C:[0-9]+]], s[[C_TMP]]
-; SI: v_max3_i32 v{{[0-9]+}}, v[[A]], s[[B]], v[[C]]
+; SI: v_max_i32_e32 v[[MAX:[0-9]+]], s[[B]], v[[A]]
+; SI: v_max_i32_e32 v{{[0-9]+}}, s[[C]], v[[MAX]]
 ; VI: v_max_i16_e32 v[[MAX:[0-9]+]], s0, v0
 ; VI: v_max_i16_e32 v{{[0-9]+}}, s1, v[[MAX]]
-; GFX9: v_mov_b32_e32 v[[C:[0-9]+]], s1
-; GFX9: v_max3_i16 v{{[0-9]+}}, v0, s0, v[[C]]
+; GFX9: v_max_i16_e32 v[[MAX:[0-9]+]], s0, v0
+; GFX9: v_max_i16_e32 v{{[0-9]+}}, s1, v[[MAX]]
 ; GFX10: v_max3_i16 v{{[0-9]+}}, v0, s0, s1
 define amdgpu_ps void @test_max3_i16_vss(i16 %a, i16 inreg %b, i16 inreg %c, i16 addrspace(1)* %out) {
   %max = call i16 @llvm.smax.i16(i16 %a, i16 %b)
   %max3 = call i16 @llvm.smax.i16(i16 %max, i16 %c)
   store i16 %max3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_max3_i16_sss:
-; SI: s_sext_i32_i16 s[[C_TMP:[0-9]+]], s2
-; SI: s_sext_i32_i16 s[[B_TMP:[0-9]+]], s1
+; SI: s_sext_i32_i16 s[[C:[0-9]+]], s2
+; SI: s_sext_i32_i16 s[[B:[0-9]+]], s1
 ; SI: s_sext_i32_i16 s[[A:[0-9]+]], s0
-; SI: v_mov_b32_e32 v[[B:[0-9]+]], s[[B_TMP]]
-; SI: v_mov_b32_e32 v[[C:[0-9]+]], s[[C_TMP]]
-; SI: v_max3_i32 v{{[0-9]+}}, s[[A]], v[[B]], v[[C]]
+; SI: s_max_i32 s[[S_MIN:[0-9]+]], s[[A]], s[[B]]
+; SI: s_max_i32 s{{[0-9]+}}, s[[S_MIN]], s[[C]]
 ; VI: v_mov_b32_e32 v[[B:[0-9]+]], s1
 ; VI: v_max_i16_e32 v[[MAX:[0-9]+]], s0, v[[B]]
 ; VI: v_max_i16_e32 v{{[0-9]+}}, s2, v[[MAX]]
 ; GFX9: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; GFX9: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; GFX9: v_max3_i16 v{{[0-9]+}}, s0, v[[B]], v[[C]]
-; GFX10: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; GFX10: v_max3_i16 v{{[0-9]+}}, s0, s1, v[[C]]
+; GFX9: v_max_i16_e32 v[[MAX:[0-9]+]], s0, v[[B]]
+; GFX9: v_max_i16_e32 v{{[0-9]+}}, s2, v[[MAX]]
+; GFX10: v_max_i16 v[[MAX:[0-9]+]], s0, s1
+; GFX10: v_max_i16 v{{[0-9]+}}, v[[MAX]], s2
 define amdgpu_ps void @test_max3_i16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c, i16 addrspace(1)* %out) {
   %max = call i16 @llvm.smax.i16(i16 %a, i16 %b)
   %max3 = call i16 @llvm.smax.i16(i16 %max, i16 %c)
   store i16 %max3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 declare i32 @llvm.umax.i32(i32, i32)
 declare i32 @llvm.smax.i32(i32, i32)
 declare i16 @llvm.umax.i16(i16, i16)
 declare i16 @llvm.smax.i16(i16, i16)
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone speculatable }

llvm/test/CodeGen/AMDGPU/min3.ll

 define amdgpu_ps void @test_min3_u32_vvs(i32 %a, i32 %b, i32 inreg %c, i32 addrspace(1)* %out) {
   %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
   %min3 = call i32 @llvm.umin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_min3_i32_ssv:
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; CST_BUS_LIM_1: v_min3_i32 v{{[0-9]+}}, s0, v[[B]], v0
+; CST_BUS_LIM_1: s_min_i32 s[[S_MIN:[0-9]+]], s0, s1
+; CST_BUS_LIM_1: v_min_i32_e32 v{{[0-9]+}}, s[[S_MIN]], v0
 
 ; CST_BUS_LIM_2: v_min3_i32 v{{[0-9]+}}, s0, s1, v0
 define amdgpu_ps void @test_min3_i32_ssv(i32 inreg %a, i32 inreg %b, i32 %c, i32 addrspace(1)* %out) {
   %min = call i32 @llvm.smin.i32(i32 %a, i32 %b)
   %min3 = call i32 @llvm.smin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_min3_i32_vss:
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[C:[0-9]+]], s1
-; CST_BUS_LIM_1: v_min3_i32 v{{[0-9]+}}, v0, s0, v[[C]]
+; CST_BUS_LIM_1: v_min_i32_e32 v[[MIN:[0-9]+]], s0, v0
+; CST_BUS_LIM_1: v_min_i32_e32 v{{[0-9]+}}, s1, v[[MIN]]
 
 ; CST_BUS_LIM_2: v_min3_i32 v{{[0-9]+}}, v0, s0, s1
 define amdgpu_ps void @test_min3_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c, i32 addrspace(1)* %out) {
   %min = call i32 @llvm.smin.i32(i32 %a, i32 %b)
   %min3 = call i32 @llvm.smin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_min3_i32_sss:
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; CST_BUS_LIM_1: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; CST_BUS_LIM_1: v_min3_i32 v{{[0-9]+}}, s0, v[[B]], v[[C]]
-
-; CST_BUS_LIM_2: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; CST_BUS_LIM_2: v_min3_i32 v{{[0-9]+}}, s0, s1, v[[C]]
+; GCN: s_min_i32 s[[S_MIN:[0-9]+]], s0, s1
+; GCN: s_min_i32 s{{[0-9]+}}, s[[S_MIN]], s2
 define amdgpu_ps void @test_min3_i32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 addrspace(1)* %out) {
   %min = call i32 @llvm.smin.i32(i32 %a, i32 %b)
   %min3 = call i32 @llvm.smin.i32(i32 %min, i32 %c)
   store i32 %min3, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_min3_u16_vvv:
define amdgpu_ps void @test_min3_u16_vvs(i16 %a, i16 %b, i16 inreg %c, i16 addrspace(1)* %out) {
   %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
   %min3 = call i16 @llvm.umin.i16(i16 %min, i16 %c)
   store i16 %min3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_min3_i16_ssv:
 ; SI: v_bfe_i32 v[[C:[0-9]+]], v0, 0, 16
-; SI: s_sext_i32_i16 s[[B_TMP:[0-9]+]], s1
+; SI: s_sext_i32_i16 s[[B:[0-9]+]], s1
 ; SI: s_sext_i32_i16 s[[A:[0-9]+]], s0
-; SI: v_mov_b32_e32 v[[B:[0-9]+]], s[[B_TMP]]
-; SI: v_min3_i32 v{{[0-9]+}}, s[[A]], v[[B]], v[[C]]
+; SI: s_min_i32 s[[MIN:[0-9]+]], s[[A]], s[[B]]
+; SI: v_min_i32_e32 v{{[0-9]+}}, s[[MIN]], v[[C]]
 ; VI: v_mov_b32_e32 v[[B:[0-9]+]], s1
 ; VI: v_min_i16_e32 v[[MIN:[0-9]+]], s0, v[[B]]
 ; VI: v_min_i16_e32 v{{[0-9]+}}, v[[MIN]], v0
 ; GFX9: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; GFX9: v_min3_i16 v{{[0-9]+}}, s0, v[[B]], v0
+; GFX9: v_min_i16_e32 v[[MIN:[0-9]+]], s0, v[[B]]
+; GFX9: v_min_i16_e32 v{{[0-9]+}}, v[[MIN]], v0
 ; GFX10: v_min3_i16 v{{[0-9]+}}, s0, s1, v0
 define amdgpu_ps void @test_min3_i16_ssv(i16 inreg %a, i16 inreg %b, i16 %c, i16 addrspace(1)* %out) {
   %min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
   %min3 = call i16 @llvm.smin.i16(i16 %min, i16 %c)
   store i16 %min3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_min3_i16_vss:
-; SI: s_sext_i32_i16 s[[C_TMP:[0-9]+]], s1
+; SI: s_sext_i32_i16 s[[C:[0-9]+]], s1
 ; SI: s_sext_i32_i16 s[[B:[0-9]+]], s0
 ; SI: v_bfe_i32 v[[A:[0-9]+]], v0, 0, 16
-; SI: v_mov_b32_e32 v[[C:[0-9]+]], s[[C_TMP]]
-; SI: v_min3_i32 v{{[0-9]+}}, v[[A]], s[[B]], v[[C]]
+; SI: v_min_i32_e32 v[[MIN:[0-9]+]], s[[B]], v[[A]]
+; SI: v_min_i32_e32 v{{[0-9]+}}, s[[C]], v[[MIN]]
 ; VI: v_min_i16_e32 v[[MIN:[0-9]+]], s0, v0
 ; VI: v_min_i16_e32 v{{[0-9]+}}, s1, v[[MIN]]
-; GFX9: v_mov_b32_e32 v[[C:[0-9]+]], s1
-; GFX9: v_min3_i16 v{{[0-9]+}}, v0, s0, v[[C]]
+; GFX9: v_min_i16_e32 v[[MIN:[0-9]+]], s0, v0
+; GFX9: v_min_i16_e32 v{{[0-9]+}}, s1, v[[MIN]]
 ; GFX10: v_min3_i16 v{{[0-9]+}}, v0, s0, s1
 define amdgpu_ps void @test_min3_i16_vss(i16 %a, i16 inreg %b, i16 inreg %c, i16 addrspace(1)* %out) {
   %min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
   %min3 = call i16 @llvm.smin.i16(i16 %min, i16 %c)
   store i16 %min3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_min3_i16_sss:
-; SI: s_sext_i32_i16 s[[C_TMP:[0-9]+]], s2
-; SI: s_sext_i32_i16 s[[B_TMP:[0-9]+]], s1
+; SI: s_sext_i32_i16 s[[C:[0-9]+]], s2
+; SI: s_sext_i32_i16 s[[B:[0-9]+]], s1
 ; SI: s_sext_i32_i16 s[[A:[0-9]+]], s0
-; SI: v_mov_b32_e32 v[[B:[0-9]+]], s[[B_TMP]]
-; SI: v_mov_b32_e32 v[[C:[0-9]+]], s[[C_TMP]]
-; SI: v_min3_i32 v{{[0-9]+}}, s[[A]], v[[B]], v[[C]]
+; SI: s_min_i32 s[[S_MIN:[0-9]+]], s[[A]], s[[B]]
+; SI: s_min_i32 s{{[0-9]+}}, s[[S_MIN]], s[[C]]
 ; VI: v_mov_b32_e32 v[[B:[0-9]+]], s1
 ; VI: v_min_i16_e32 v[[MIN:[0-9]+]], s0, v[[B]]
 ; VI: v_min_i16_e32 v{{[0-9]+}}, s2, v[[MIN]]
 ; GFX9: v_mov_b32_e32 v[[B:[0-9]+]], s1
-; GFX9: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; GFX9: v_min3_i16 v{{[0-9]+}}, s0, v[[B]], v[[C]]
-; GFX10: v_mov_b32_e32 v[[C:[0-9]+]], s2
-; GFX10: v_min3_i16 v{{[0-9]+}}, s0, s1, v[[C]]
+; GFX9: v_min_i16_e32 v[[MIN:[0-9]+]], s0, v[[B]]
+; GFX9: v_min_i16_e32 v{{[0-9]+}}, s2, v[[MIN]]
+; GFX10: v_min_i16 v[[MIN:[0-9]+]], s0, s1
+; GFX10: v_min_i16 v{{[0-9]+}}, v[[MIN]], s2
 define amdgpu_ps void @test_min3_i16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c, i16 addrspace(1)* %out) {
   %min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
   %min3 = call i16 @llvm.smin.i16(i16 %min, i16 %c)
   store i16 %min3, i16 addrspace(1)* %out, align 4
   ret void
 }
 
 declare i32 @llvm.umin.i32(i32, i32)
 declare i32 @llvm.smin.i32(i32, i32)
 declare i16 @llvm.umin.i16(i16, i16)
 declare i16 @llvm.smin.i16(i16, i16)
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone speculatable }