[InstCombine] Sink bin op into hands of select if one hand becomes constant

[xbolva00]

Summary

Restart of https://reviews.llvm.org/D71312 but more general.

[xbolva00]

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

876

HACK just for initial patch.

We have some reverse transformation which creates infinite loop in IC with sub-minmax.ll.

Maybe bail out if matchSelectPattern returns something?

[lebedev.ri]

This review seems to be stuck/dead, consider abandoning if no longer relevant.

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

Value *InstCombinerImpl::SimplifySelectsFeedingBinaryOp(BinaryOperator &I,
   BuilderTy::FastMathFlagGuard Guard(Builder);
   if (isa<FPMathOperator>(&I)) {
     FMF = I.getFastMathFlags();
     Builder.setFastMathFlags(FMF);
   }
 
   Instruction::BinaryOps Opcode = I.getOpcode();
   SimplifyQuery Q = SQ.getWithInstruction(&I);
-
+  SelectInst *InnerSI = nullptr;
   Value *Cond, *True = nullptr, *False = nullptr;
   if (LHSIsSelect && RHSIsSelect && A == D) {
     // (A ? B : C) op (A ? E : F) -> A ? (B op E) : (C op F)
     Cond = A;
     True = SimplifyBinOp(Opcode, B, E, FMF, Q);
     False = SimplifyBinOp(Opcode, C, F, FMF, Q);
 
     if (LHS->hasOneUse() && RHS->hasOneUse()) {
       if (False && !True)
         True = Builder.CreateBinOp(Opcode, B, E);
       else if (True && !False)
         False = Builder.CreateBinOp(Opcode, C, F);
     }
   } else if (LHSIsSelect && LHS->hasOneUse()) {
     // (A ? B : C) op Y -> A ? (B op Y) : (C op Y)
     Cond = A;
+    if (I.getOpcode() == BinaryOperator::Xor) return nullptr;
     True = SimplifyBinOp(Opcode, B, RHS, FMF, Q);
     False = SimplifyBinOp(Opcode, C, RHS, FMF, Q);
+
+    if (isa_and_nonnull<Constant>(False) && !True)
+      True = Builder.CreateBinOp(Opcode, B, RHS);
+    else if (isa_and_nonnull<Constant>(True) && !False)
+      False = Builder.CreateBinOp(Opcode, C, RHS);
+
+    InnerSI = cast<SelectInst>(LHS);
   } else if (RHSIsSelect && RHS->hasOneUse()) {
     // X op (D ? E : F) -> D ? (X op E) : (X op F)
     Cond = D;
     True = SimplifyBinOp(Opcode, LHS, E, FMF, Q);
     False = SimplifyBinOp(Opcode, LHS, F, FMF, Q);
+
+    if (isa_and_nonnull<Constant>(False) && !True)
+      True = Builder.CreateBinOp(Opcode, LHS, E);
+    else if (isa_and_nonnull<Constant>(True) && !False)
+      False = Builder.CreateBinOp(Opcode, LHS, F);
+
+    InnerSI = cast<SelectInst>(RHS);
   }
 
   if (!True || !False)
     return nullptr;
 
-  Value *SI = Builder.CreateSelect(Cond, True, False);
+  SelectInst *SI = cast<SelectInst>(Builder.CreateSelect(Cond, True, False));
   SI->takeName(&I);
+  if (InnerSI)
+    SI->copyMetadata(*InnerSI);
+
   return SI;
 }
 
 /// Freely adapt every user of V as-if V was changed to !V.
 /// WARNING: only if canFreelyInvertAllUsersOf() said this can be done.
 void InstCombinerImpl::freelyInvertAllUsersOf(Value *I) {
   for (User *U : I->users()) {
     switch (cast<Instruction>(U)->getOpcode()) {

llvm/test/Transforms/InstCombine/and2.ll

;
   %and2 = and i1 %and1, %cmp2
   ret i1 %and2
 }
 
 define i1 @test7_logical(i32 %i, i1 %b) {
 ; CHECK-LABEL: @test7_logical(
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[I:%.*]], 1
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[I]], -1
-; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[CMP1]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[AND1]], [[CMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[CMP2]], [[B:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[CMP1]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %cmp1 = icmp slt i32 %i, 1
   %cmp2 = icmp sgt i32 %i, -1
   %and1 = select i1 %cmp1, i1 %b, i1 false
   %and2 = select i1 %and1, i1 %cmp2, i1 false
   ret i1 %and2
 }

llvm/test/Transforms/InstCombine/binop-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 declare void @use(i32)
 
 define i32 @test1(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 [[Y:%.*]]
-; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[COND]], [[X]]
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[C:%.*]], i32 0, i32 [[TMP0]]
 ; CHECK-NEXT:    ret i32 [[ADD]]
 ;
 entry:
   %sub = sub i32 0, %x
   %cond = select i1 %c, i32 %sub, i32 %y
   %add = add i32 %cond, %x
   ret i32 %add
 }
 
 define i32 @test2(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[COND]], [[X]]
+; CHECK-NEXT:    [[TMP0:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[C:%.*]], i32 0, i32 [[TMP0]]
 ; CHECK-NEXT:    ret i32 [[ADD]]
 ;
 entry:
   %sub = sub i32 0, %x
   %cond = select i1 %c, i32 %sub, i32 %x
   %add = add i32 %cond, %x
   ret i32 %add
 }

 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
 entry:
   %cond = select i1 %c, i32 7, i32 %x
   %and = and i32 %cond, %x
   ret i32 %and
 }
 
+; FIXME: We should push div into select.
 define i32 @test7(i1 %c, i32 %x) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SUB:%.*]] = sub i32 0, [[X:%.*]]
 ; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 [[X]], i32 [[SUB]]
 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[X]], [[COND]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
 entry:
   %sub = sub i32 0, %x
   %cond = select i1 %c, i32 %x, i32 %sub
   %div = sdiv i32 %x, %cond
   ret i32 %div
 }
 
-
+; FIXME: We should push div into select.
 define i32 @test8(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]
 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 42, [[COND]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
 entry:
   %cond = select i1 %c, i32 7, i32 %y
   %div = sdiv i32 42, %cond
   ret i32 %div
 }
 
+; FIXME: We should push sub into select.
 define i32 @test9(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 1, i32 [[X:%.*]]
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[COND]]
 ; CHECK-NEXT:    ret i32 [[SUB]]
 ;
 entry:
   %cond = select i1 %c, i32 1, i32 %x
   %sub = sub nsw i32 0, %cond
   ret i32 %sub
 }
 
+; FIXME: We should push div into select.
 define i32 @test10(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test10(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]
 ; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 42, [[COND]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
 entry:
   %cond = select i1 %c, i32 7, i32 %y
   %div = udiv i32 42, %cond
   ret i32 %div
 }
 
+; FIXME: We should push rem op into select.
 define i32 @test11(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test11(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]
 ; CHECK-NEXT:    [[DIV:%.*]] = srem i32 42, [[COND]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
 entry:
   %cond = select i1 %c, i32 7, i32 %y
   %div = srem i32 42, %cond
   ret i32 %div
 }
 
+; FIXME: We should push rem op into select.
 define i32 @test12(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test12(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]
 ; CHECK-NEXT:    [[DIV:%.*]] = urem i32 42, [[COND]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
 entry:

llvm/test/Transforms/InstCombine/icmp-add.ll

 
 ; In the following 4 tests, we could push the inc/dec
 ; through the min/max, but we should not break up the
 ; min/max idiom by using different icmp and select
 ; operands.
 
 define i32 @increment_max(i32 %x) {
 ; CHECK-LABEL: @increment_max(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 -1
-; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[DOTINV:%.*]] = icmp slt i32 [[X]], 0
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[S]]
 ;
   %a = add nsw i32 %x, 1
   %c = icmp sgt i32 %a, 0
   %s = select i1 %c, i32 %a, i32 0
   ret i32 %s
 }
 
 define i32 @decrement_max(i32 %x) {
 ; CHECK-LABEL: @decrement_max(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 1
-; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[TMP2]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[X]], -1
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 0
 ; CHECK-NEXT:    ret i32 [[S]]
 ;
   %a = add nsw i32 %x, -1
   %c = icmp sgt i32 %a, 0
   %s = select i1 %c, i32 %a, i32 0
   ret i32 %s
 }
 
 define i32 @increment_min(i32 %x) {
 ; CHECK-LABEL: @increment_min(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 -1
-; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 0
 ; CHECK-NEXT:    ret i32 [[S]]
 ;
   %a = add nsw i32 %x, 1
   %c = icmp slt i32 %a, 0
   %s = select i1 %c, i32 %a, i32 0
   ret i32 %s
 }
 
 define i32 @decrement_min(i32 %x) {
 ; CHECK-LABEL: @decrement_min(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 1
-; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[TMP2]], -1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[DOTINV:%.*]] = icmp sgt i32 [[X]], 0
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[DOTINV]], i32 0, i32 [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[S]]
 ;
   %a = add nsw i32 %x, -1
   %c = icmp slt i32 %a, 0
   %s = select i1 %c, i32 %a, i32 0
   ret i32 %s
 }

llvm/test/Transforms/InstCombine/max_known_bits.ll

 
 ; This contains a min/max pair to clamp a value to 12 bits.
 ; By analyzing the clamp pattern, we can tell the add doesn't have signed overflow.
 define i16 @min_max_clamp(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp(
 ; CHECK-NEXT:    [[A:%.*]] = icmp sgt i16 [[X:%.*]], -2048
 ; CHECK-NEXT:    [[B:%.*]] = select i1 [[A]], i16 [[X]], i16 -2048
 ; CHECK-NEXT:    [[C:%.*]] = icmp slt i16 [[B]], 2047
-; CHECK-NEXT:    [[D:%.*]] = select i1 [[C]], i16 [[B]], i16 2047
-; CHECK-NEXT:    [[E:%.*]] = add nsw i16 [[D]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i16 [[B]], 1
+; CHECK-NEXT:    [[E:%.*]] = select i1 [[C]], i16 [[TMP1]], i16 2048
 ; CHECK-NEXT:    ret i16 [[E]]
 ;
   %a = icmp sgt i16 %x, -2048
   %b = select i1 %a, i16 %x, i16 -2048
   %c = icmp slt i16 %b, 2047
   %d = select i1 %c, i16 %b, i16 2047
   %e = add i16 %d, 1
   ret i16 %e
 }
 
 ; Same as above with min/max reversed.
 define i16 @min_max_clamp_2(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_2(
 ; CHECK-NEXT:    [[A:%.*]] = icmp slt i16 [[X:%.*]], 2047
 ; CHECK-NEXT:    [[B:%.*]] = select i1 [[A]], i16 [[X]], i16 2047
-; CHECK-NEXT:    [[C:%.*]] = icmp sgt i16 [[B]], -2048
-; CHECK-NEXT:    [[D:%.*]] = select i1 [[C]], i16 [[B]], i16 -2048
-; CHECK-NEXT:    [[E:%.*]] = add nsw i16 [[D]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw i16 [[B]], 1
+; CHECK-NEXT:    [[C_INV:%.*]] = icmp slt i16 [[B]], -2047
+; CHECK-NEXT:    [[E:%.*]] = select i1 [[C_INV]], i16 -2047, i16 [[TMP1]]
 ; CHECK-NEXT:    ret i16 [[E]]
 ;
   %a = icmp slt i16 %x, 2047
   %b = select i1 %a, i16 %x, i16 2047
   %c = icmp sgt i16 %b, -2048
   %d = select i1 %c, i16 %b, i16 -2048
   %e = add i16 %d, 1
   ret i16 %e
 }
 
 ; This contains a min/max pair to clamp a value to 12 bits.
 ; By analyzing the clamp pattern, we can tell that the second add doesn't
 ; overflow the original type and can be moved before the extend.
 define i32 @min_max_clamp_3(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_3(
 ; CHECK-NEXT:    [[A:%.*]] = icmp sgt i16 [[X:%.*]], -2048
 ; CHECK-NEXT:    [[B:%.*]] = select i1 [[A]], i16 [[X]], i16 -2048
 ; CHECK-NEXT:    [[C:%.*]] = icmp slt i16 [[B]], 2047
-; CHECK-NEXT:    [[D:%.*]] = select i1 [[C]], i16 [[B]], i16 2047
-; CHECK-NEXT:    [[G:%.*]] = sext i16 [[D]] to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = add i16 [[B]], 1
+; CHECK-NEXT:    [[E:%.*]] = select i1 [[C]], i16 [[TMP1]], i16 2048
+; CHECK-NEXT:    [[F:%.*]] = sext i16 [[E]] to i32
+; CHECK-NEXT:    [[G:%.*]] = add nsw i32 [[F]], -1
 ; CHECK-NEXT:    ret i32 [[G]]
 ;
   %a = icmp sgt i16 %x, -2048
   %b = select i1 %a, i16 %x, i16 -2048
   %c = icmp slt i16 %b, 2047
   %d = select i1 %c, i16 %b, i16 2047
   %e = add i16 %d, 1
   %f = sext i16 %e to i32
   %g = add i32 %f, -1
   ret i32 %g
 }
 
 ; Same as above with min/max order reversed
 define i32 @min_max_clamp_4(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_4(
 ; CHECK-NEXT:    [[A:%.*]] = icmp slt i16 [[X:%.*]], 2047
 ; CHECK-NEXT:    [[B:%.*]] = select i1 [[A]], i16 [[X]], i16 2047
-; CHECK-NEXT:    [[C:%.*]] = icmp sgt i16 [[B]], -2048
-; CHECK-NEXT:    [[D:%.*]] = select i1 [[C]], i16 [[B]], i16 -2048
-; CHECK-NEXT:    [[G:%.*]] = sext i16 [[D]] to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw i16 [[B]], 1
+; CHECK-NEXT:    [[C_INV:%.*]] = icmp slt i16 [[B]], -2047
+; CHECK-NEXT:    [[E:%.*]] = select i1 [[C_INV]], i16 -2047, i16 [[TMP1]]
+; CHECK-NEXT:    [[F:%.*]] = sext i16 [[E]] to i32
+; CHECK-NEXT:    [[G:%.*]] = add nsw i32 [[F]], -1
 ; CHECK-NEXT:    ret i32 [[G]]
 ;
   %a = icmp slt i16 %x, 2047
   %b = select i1 %a, i16 %x, i16 2047
   %c = icmp sgt i16 %b, -2048
   %d = select i1 %c, i16 %b, i16 -2048
   %e = add i16 %d, 1
   %f = sext i16 %e to i32
   %g = add i32 %f, -1
   ret i32 %g
 }

llvm/test/Transforms/InstCombine/minmax-demandbits.ll

;
   %l1 = select i1 %l0, i32 12, i32 %A
   %x = and i32 %l1, -32
   ret i32 %x
 }
 
 define i32 @and_umax_more(i32 %A) {
 ; CHECK-LABEL: @and_umax_more(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[A:%.*]], 32
-; CHECK-NEXT:    [[L1:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 32
-; CHECK-NEXT:    [[X:%.*]] = and i32 [[L1]], -32
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[A]], -32
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 32
 ; CHECK-NEXT:    ret i32 [[X]]
 ;
   %l0 = icmp ugt i32 32, %A
   %l1 = select i1 %l0, i32 32, i32 %A
   %x = and i32 %l1, -32
   ret i32 %x
 }
 
;
   %l1 = select i1 %l2, i8 %A, i8 2
   %x = or i8 %l1, 63
   ret i8 %x
 }
 
 define i8 @f_1_1(i8 %A) {
 ; CHECK-LABEL: @f_1_1(
 ; CHECK-NEXT:    [[L2:%.*]] = icmp ugt i8 [[A:%.*]], 1
-; CHECK-NEXT:    [[L1:%.*]] = select i1 [[L2]], i8 [[A]], i8 1
-; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[A]], 1
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[L2]], i8 [[TMP1]], i8 1
 ; CHECK-NEXT:    ret i8 [[X]]
 ;
   %l2 = icmp ugt i8 %A, 1
   %l1 = select i1 %l2, i8 %A, i8 1
   %x = and i8 %l1, 1
   ret i8 %x
 }
 
 define i8 @f_32_32(i8 %A) {
 ; CHECK-LABEL: @f_32_32(
 ; CHECK-NEXT:    [[L2:%.*]] = icmp ugt i8 [[A:%.*]], 32
-; CHECK-NEXT:    [[L1:%.*]] = select i1 [[L2]], i8 [[A]], i8 32
-; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], -32
+; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[A]], -32
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[L2]], i8 [[TMP1]], i8 32
 ; CHECK-NEXT:    ret i8 [[X]]
 ;
   %l2 = icmp ugt i8 %A, 32
   %l1 = select i1 %l2, i8 %A, i8 32
   %x = and i8 %l1, -32
   ret i8 %x
 }
 
 define i8 @f_191_192(i8 %A) {
 ; CHECK-LABEL: @f_191_192(
 ; CHECK-NEXT:    [[L2:%.*]] = icmp ugt i8 [[A:%.*]], -65
-; CHECK-NEXT:    [[L1:%.*]] = select i1 [[L2]], i8 [[A]], i8 -65
-; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], -64
+; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[A]], -64
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[L2]], i8 [[TMP1]], i8 -128
 ; CHECK-NEXT:    ret i8 [[X]]
 ;
   %l2 = icmp ugt i8 %A, 191
   %l1 = select i1 %l2, i8 %A, i8 191
   %x = and i8 %l1, 192
   ret i8 %x
 }
 
 define i8 @f_10_1(i8 %A) {
 ; CHECK-LABEL: @f_10_1(
 ; CHECK-NEXT:    [[L2:%.*]] = icmp ugt i8 [[A:%.*]], 10
-; CHECK-NEXT:    [[L1:%.*]] = select i1 [[L2]], i8 [[A]], i8 10
-; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[A]], 1
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[L2]], i8 [[TMP1]], i8 0
 ; CHECK-NEXT:    ret i8 [[X]]
 ;
   %l2 = icmp ugt i8 %A, 10
   %l1 = select i1 %l2, i8 %A, i8 10
   %x = and i8 %l1, 1
   ret i8 %x
 }
 
 define i32 @and_umin(i32 %A) {
 ; CHECK-LABEL: @and_umin(
-; CHECK-NEXT:    ret i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[A:%.*]], 15
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[A]], -32
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 0
+; CHECK-NEXT:    ret i32 [[X]]
 ;
   %l0 = icmp ult i32 15, %A
   %l1 = select i1 %l0, i32 15, i32 %A
   %x = and i32 %l1, -32
   ret i32 %x
 }
 
 define i32 @or_umin(i32 %A) {
 ; CHECK-LABEL: @or_umin(
-; CHECK-NEXT:    ret i32 31
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[A:%.*]], 15
+; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[A]], 31
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 31
+; CHECK-NEXT:    ret i32 [[X]]
 ;
   %l0 = icmp ult i32 15, %A
   %l1 = select i1 %l0, i32 15, i32 %A
   %x = or i32 %l1, 31
   ret i32 %x
 }
 
 define i8 @or_min_31_30(i8 %A) {
;
   %min = select i1 %l2, i8 %A, i8 -8
   %r = and i8 %min, -8
   ret i8 %r
 }
 
 define i8 @and_min_7_9(i8 %A) {
 ; CHECK-LABEL: @and_min_7_9(
 ; CHECK-NEXT:    [[L2:%.*]] = icmp ult i8 [[A:%.*]], -9
-; CHECK-NEXT:    [[MIN:%.*]] = select i1 [[L2]], i8 [[A]], i8 -9
-; CHECK-NEXT:    [[R:%.*]] = and i8 [[MIN]], -8
+; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[A]], -8
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[L2]], i8 [[TMP1]], i8 -16
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %l2 = icmp ult i8 %A, -9
   %min = select i1 %l2, i8 %A, i8 -9
   %r = and i8 %min, -8
   ret i8 %r
 }
 

llvm/test/Transforms/InstCombine/minmax-fold.ll

;
   %cmp3 = icmp ult i8 %i, 16
   %r = select i1 %cmp3, float %min1, float %min2
   ret float %r
 }
 
 define i32 @add_umin(i32 %x) {
 ; CHECK-LABEL: @add_umin(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], 27
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 27
-; CHECK-NEXT:    [[R:%.*]] = add nuw nsw i32 [[TMP2]], 15
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[X]], 15
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 42
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %a = add nuw i32 %x, 15
   %c = icmp ult i32 %a, 42
   %r = select i1 %c, i32 %a, i32 42
   ret i32 %r
 }
 
;
   %c = icmp ult i32 %a, 42
   %r = select i1 %c, i32 %a, i32 42
   ret i32 %r
 }
 
 define <2 x i16> @add_umin_vec(<2 x i16> %x) {
 ; CHECK-LABEL: @add_umin_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult <2 x i16> [[X:%.*]], <i16 225, i16 225>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[X]], <2 x i16> <i16 225, i16 225>
-; CHECK-NEXT:    [[R:%.*]] = add nuw nsw <2 x i16> [[TMP2]], <i16 15, i16 15>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i16> [[X]], <i16 15, i16 15>
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[TMP2]], <2 x i16> <i16 240, i16 240>
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
   %a = add nuw <2 x i16> %x, <i16 15, i16 15>
   %c = icmp ult <2 x i16> %a, <i16 240, i16 240>
   %r = select <2 x i1> %c, <2 x i16> %a, <2 x i16> <i16 240, i16 240>
   ret <2 x i16> %r
 }
 
 define i37 @add_umax(i37 %x) {
 ; CHECK-LABEL: @add_umax(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i37 [[X:%.*]], 37
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i37 [[X]], i37 37
-; CHECK-NEXT:    [[R:%.*]] = add nuw i37 [[TMP2]], 5
+; CHECK-NEXT:    [[TMP2:%.*]] = add i37 [[X]], 5
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i37 [[TMP2]], i37 42
 ; CHECK-NEXT:    ret i37 [[R]]
 ;
   %a = add nuw i37 %x, 5
   %c = icmp ugt i37 %a, 42
   %r = select i1 %c, i37 %a, i37 42
   ret i37 %r
 }
 
 define i37 @add_umax_constant_limit(i37 %x) {
 ; CHECK-LABEL: @add_umax_constant_limit(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i37 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i37 [[X]], i37 1
-; CHECK-NEXT:    [[R:%.*]] = add nuw i37 [[TMP2]], 81
+; CHECK-NEXT:    [[TMP2:%.*]] = add i37 [[X]], 81
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i37 [[TMP2]], i37 82
 ; CHECK-NEXT:    ret i37 [[R]]
 ;
   %a = add nuw i37 %x, 81
   %c = icmp ugt i37 %a, 82
   %r = select i1 %c, i37 %a, i37 82
   ret i37 %r
 }
 
 ; Negative test
 ; TODO: assert that instsimplify always gets this?
 
 define i37 @add_umax_simplify(i37 %x) {
 ; CHECK-LABEL: @add_umax_simplify(
-; CHECK-NEXT:    [[A:%.*]] = add nuw i37 [[X:%.*]], 42
-; CHECK-NEXT:    ret i37 [[A]]
+; CHECK-NEXT:    [[R:%.*]] = add nuw i37 [[X:%.*]], 42
+; CHECK-NEXT:    ret i37 [[R]]
 ;
   %a = add nuw i37 %x, 42
   %c = icmp ugt i37 %a, 42
   %r = select i1 %c, i37 %a, i37 42
   ret i37 %r
 }
 
 ; Negative test
;
   %c = icmp ugt i32 %a, 42
   %r = select i1 %c, i32 %a, i32 42
   ret i32 %r
 }
 
 define <2 x i33> @add_umax_vec(<2 x i33> %x) {
 ; CHECK-LABEL: @add_umax_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <2 x i33> [[X:%.*]], <i33 235, i33 235>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i33> [[X]], <2 x i33> <i33 235, i33 235>
-; CHECK-NEXT:    [[R:%.*]] = add nuw <2 x i33> [[TMP2]], <i33 5, i33 5>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i33> [[X]], <i33 5, i33 5>
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP1]], <2 x i33> [[TMP2]], <2 x i33> <i33 240, i33 240>
 ; CHECK-NEXT:    ret <2 x i33> [[R]]
 ;
   %a = add nuw <2 x i33> %x, <i33 5, i33 5>
   %c = icmp ugt <2 x i33> %a, <i33 240, i33 240>
   %r = select <2 x i1> %c, <2 x i33> %a, <2 x i33> <i33 240, i33 240>
   ret <2 x i33> %r
 }
 
 define i8 @PR14613_umin(i8 %x) {
 ; CHECK-LABEL: @PR14613_umin(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[X:%.*]], i8 15)
 ; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %u4 = zext i8 %x to i32
   %u5 = add nuw nsw i32 %u4, 15
   %u6 = icmp ult i32 %u5, 255
   %u7 = select i1 %u6, i32 %u5, i32 255
   %r = trunc i32 %u7 to i8
   ret i8 %r
 }
 
 define i8 @PR14613_umax(i8 %x) {
 ; CHECK-LABEL: @PR14613_umax(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], -16
-; CHECK-NEXT:    [[X_OP:%.*]] = add i8 [[X]], 15
-; CHECK-NEXT:    [[U7:%.*]] = select i1 [[TMP1]], i8 [[X_OP]], i8 -1
-; CHECK-NEXT:    ret i8 [[U7]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[X]], 15
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 -1
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %u4 = zext i8 %x to i32
   %u5 = add nuw nsw i32 %u4, 15
   %u6 = icmp ugt i32 %u5, 255
   %u7 = select i1 %u6, i32 %u5, i32 255
   %r = trunc i32 %u7 to i8
   ret i8 %r
 }
 
 define i32 @add_smin(i32 %x) {
 ; CHECK-LABEL: @add_smin(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 27
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 27
-; CHECK-NEXT:    [[R:%.*]] = add nsw i32 [[TMP2]], 15
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[X]], 15
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 42
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %a = add nsw i32 %x, 15
   %c = icmp slt i32 %a, 42
   %r = select i1 %c, i32 %a, i32 42
   ret i32 %r
 }
 
 define i32 @add_smin_constant_limit(i32 %x) {
 ; CHECK-LABEL: @add_smin_constant_limit(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 2147483646
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 2147483646
-; CHECK-NEXT:    [[R:%.*]] = add nsw i32 [[TMP2]], -3
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[X]], -3
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 2147483643
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %a = add nsw i32 %x, -3
   %c = icmp slt i32 %a, 2147483643
   %r = select i1 %c, i32 %a, i32 2147483643
   ret i32 %r
 }
 
;
   %c = icmp slt i32 %a, 42
   %r = select i1 %c, i32 %a, i32 42
   ret i32 %r
 }
 
 define <2 x i16> @add_smin_vec(<2 x i16> %x) {
 ; CHECK-LABEL: @add_smin_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i16> [[X:%.*]], <i16 225, i16 225>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[X]], <2 x i16> <i16 225, i16 225>
-; CHECK-NEXT:    [[R:%.*]] = add nsw <2 x i16> [[TMP2]], <i16 15, i16 15>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i16> [[X]], <i16 15, i16 15>
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[TMP2]], <2 x i16> <i16 240, i16 240>
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
   %a = add nsw <2 x i16> %x, <i16 15, i16 15>
   %c = icmp slt <2 x i16> %a, <i16 240, i16 240>
   %r = select <2 x i1> %c, <2 x i16> %a, <2 x i16> <i16 240, i16 240>
   ret <2 x i16> %r
 }
 
 define i37 @add_smax(i37 %x) {
 ; CHECK-LABEL: @add_smax(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i37 [[X:%.*]], 37
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i37 [[X]], i37 37
-; CHECK-NEXT:    [[R:%.*]] = add nuw nsw i37 [[TMP2]], 5
+; CHECK-NEXT:    [[TMP2:%.*]] = add i37 [[X]], 5
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i37 [[TMP2]], i37 42
 ; CHECK-NEXT:    ret i37 [[R]]
 ;
   %a = add nsw i37 %x, 5
   %c = icmp sgt i37 %a, 42
   %r = select i1 %c, i37 %a, i37 42
   ret i37 %r
 }
 
 define i8 @add_smax_constant_limit(i8 %x) {
 ; CHECK-LABEL: @add_smax_constant_limit(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i8 [[X:%.*]], -127
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 -127
-; CHECK-NEXT:    [[R:%.*]] = add nsw i8 [[TMP2]], 125
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[X]], 125
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 -2
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %a = add nsw i8 %x, 125
   %c = icmp sgt i8 %a, -2
   %r = select i1 %c, i8 %a, i8 -2
   ret i8 %r
 }
 
;
   %c = icmp sgt i32 %a, 42
   %r = select i1 %c, i32 %a, i32 42
   ret i32 %r
 }
 
 define <2 x i33> @add_smax_vec(<2 x i33> %x) {
 ; CHECK-LABEL: @add_smax_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <2 x i33> [[X:%.*]], <i33 235, i33 235>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i33> [[X]], <2 x i33> <i33 235, i33 235>
-; CHECK-NEXT:    [[R:%.*]] = add nuw nsw <2 x i33> [[TMP2]], <i33 5, i33 5>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i33> [[X]], <i33 5, i33 5>
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP1]], <2 x i33> [[TMP2]], <2 x i33> <i33 240, i33 240>
 ; CHECK-NEXT:    ret <2 x i33> [[R]]
 ;
   %a = add nsw <2 x i33> %x, <i33 5, i33 5>
   %c = icmp sgt <2 x i33> %a, <i33 240, i33 240>
   %r = select <2 x i1> %c, <2 x i33> %a, <2 x i33> <i33 240, i33 240>
   ret <2 x i33> %r
 }
 
 define i8 @PR14613_smin(i8 %x) {
 ; CHECK-LABEL: @PR14613_smin(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[X:%.*]], 40
-; CHECK-NEXT:    [[X_OP:%.*]] = add i8 [[X]], 15
-; CHECK-NEXT:    [[U7:%.*]] = select i1 [[TMP1]], i8 [[X_OP]], i8 55
-; CHECK-NEXT:    ret i8 [[U7]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[X]], 15
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 55
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %u4 = sext i8 %x to i32
   %u5 = add nuw nsw i32 %u4, 15
   %u6 = icmp slt i32 %u5, 55
   %u7 = select i1 %u6, i32 %u5, i32 55
   %r = trunc i32 %u7 to i8
   ret i8 %r
 }
 
 define i8 @PR14613_smax(i8 %x) {
 ; CHECK-LABEL: @PR14613_smax(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i8 [[X:%.*]], 40
-; CHECK-NEXT:    [[X_OP:%.*]] = add i8 [[X]], 15
-; CHECK-NEXT:    [[U7:%.*]] = select i1 [[TMP1]], i8 [[X_OP]], i8 55
-; CHECK-NEXT:    ret i8 [[U7]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[X]], 15
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 55
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %u4 = sext i8 %x to i32
   %u5 = add nuw nsw i32 %u4, 15
   %u6 = icmp sgt i32 %u5, 55
   %u7 = select i1 %u6, i32 %u5, i32 55
   %r = trunc i32 %u7 to i8
   ret i8 %r
 }

llvm/test/Transforms/InstCombine/rem.ll

 ;
   %B = srem <2 x i32> %A, <i32 -8, i32 -8>
   %C = icmp ne <2 x i32> %B, zeroinitializer
   ret <2 x i1> %C
 }
 
 define i32 @test4(i32 %X, i1 %C) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C:%.*]], i32 0, i32 7
-; CHECK-NEXT:    [[R:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 7
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i32 0, i32 [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %V = select i1 %C, i32 1, i32 8
   %R = urem i32 %X, %V
   ret i32 %R
 }
 
 define i32 @test5(i32 %X, i8 %B) {

llvm/test/Transforms/InstCombine/saturating-add-sub.ll

 }
 
 declare i32 @get_i32()
 declare <2 x i8> @get_v2i8()
 
 define i32 @unsigned_sat_variable_using_min_add(i32 %x) {
 ; CHECK-LABEL: @unsigned_sat_variable_using_min_add(
 ; CHECK-NEXT:    [[Y:%.*]] = call i32 @get_i32()
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 [[Y]])
-; CHECK-NEXT:    ret i32 [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[Y]], i32 [[X:%.*]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %y = call i32 @get_i32() ; thwart complexity-based canonicalization
   %noty = xor i32 %y, -1
   %c = icmp ult i32 %x, %noty
   %s = select i1 %c, i32 %x, i32 %noty
   %r = add i32 %s, %y
   ret i32 %r
 }
 
 define i32 @unsigned_sat_variable_using_min_commute_add(i32 %x) {
 ; CHECK-LABEL: @unsigned_sat_variable_using_min_commute_add(
 ; CHECK-NEXT:    [[Y:%.*]] = call i32 @get_i32()
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 [[Y]])
-; CHECK-NEXT:    ret i32 [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[Y]], i32 [[X:%.*]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %y = call i32 @get_i32() ; thwart complexity-based canonicalization
   %noty = xor i32 %y, -1
   %c = icmp ult i32 %x, %noty
   %s = select i1 %c, i32 %x, i32 %noty
   %r = add i32 %y, %s
   ret i32 %r
 }
 
 define <2 x i8> @unsigned_sat_variable_using_min_commute_select(<2 x i8> %x) {
 ; CHECK-LABEL: @unsigned_sat_variable_using_min_commute_select(
 ; CHECK-NEXT:    [[Y:%.*]] = call <2 x i8> @get_v2i8()
-; CHECK-NEXT:    [[R:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y]])
-; CHECK-NEXT:    ret <2 x i8> [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[Y]], <2 x i8> [[X:%.*]])
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
 ;
   %y = call <2 x i8> @get_v2i8() ; thwart complexity-based canonicalization
   %noty = xor <2 x i8> %y, <i8 -1, i8 -1>
   %c = icmp ult <2 x i8> %noty, %x
   %s = select <2 x i1> %c, <2 x i8> %noty, <2 x i8> %x
   %r = add <2 x i8> %s, %y
   ret <2 x i8> %r
 }
 
 define <2 x i8> @unsigned_sat_variable_using_min_commute_add_select(<2 x i8> %x) {
 ; CHECK-LABEL: @unsigned_sat_variable_using_min_commute_add_select(
 ; CHECK-NEXT:    [[Y:%.*]] = call <2 x i8> @get_v2i8()
-; CHECK-NEXT:    [[R:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y]])
-; CHECK-NEXT:    ret <2 x i8> [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[Y]], <2 x i8> [[X:%.*]])
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
 ;
   %y = call <2 x i8> @get_v2i8() ; thwart complexity-based canonicalization
   %noty = xor <2 x i8> %y, <i8 -1, i8 -1>
   %c = icmp ult <2 x i8> %noty, %x
   %s = select <2 x i1> %c, <2 x i8> %noty, <2 x i8> %x
   %r = add <2 x i8> %y, %s
   ret <2 x i8> %r
 }
 
 ; Negative test
 
 define i32 @unsigned_sat_variable_using_wrong_min(i32 %x) {
 ; CHECK-LABEL: @unsigned_sat_variable_using_wrong_min(
 ; CHECK-NEXT:    [[Y:%.*]] = call i32 @get_i32()
 ; CHECK-NEXT:    [[NOTY:%.*]] = xor i32 [[Y]], -1
 ; CHECK-NEXT:    [[C:%.*]] = icmp sgt i32 [[NOTY]], [[X:%.*]]
-; CHECK-NEXT:    [[S:%.*]] = select i1 [[C]], i32 [[X]], i32 [[NOTY]]
-; CHECK-NEXT:    [[R:%.*]] = add i32 [[Y]], [[S]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[Y]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C]], i32 [[TMP1]], i32 -1
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %y = call i32 @get_i32() ; thwart complexity-based canonicalization
   %noty = xor i32 %y, -1
   %c = icmp slt i32 %x, %noty
   %s = select i1 %c, i32 %x, i32 %noty
   %r = add i32 %y, %s
   ret i32 %r
;
   %r = add i32 %z, %s
   ret i32 %r
 }
 
 ; If we have a constant operand, there's no commutativity variation.
 
 define i32 @unsigned_sat_constant_using_min(i32 %x) {
 ; CHECK-LABEL: @unsigned_sat_constant_using_min(
-; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 -43)
-; CHECK-NEXT:    ret i32 [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[X:%.*]], i32 -43)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %c = icmp ult i32 %x, 42
   %s = select i1 %c, i32 %x, i32 42
   %r = add i32 %s, -43
   ret i32 %r
 }
 
 define <2 x i32> @unsigned_sat_constant_using_min_splat(<2 x i32> %x) {
 ; CHECK-LABEL: @unsigned_sat_constant_using_min_splat(
-; CHECK-NEXT:    [[R:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 -15, i32 -15>)
-; CHECK-NEXT:    ret <2 x i32> [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[X:%.*]], <2 x i32> <i32 -15, i32 -15>)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %c = icmp ult <2 x i32> %x, <i32 14, i32 14>
   %s = select <2 x i1> %c, <2 x i32> %x, <2 x i32> <i32 14, i32 14>
   %r = add <2 x i32> %s, <i32 -15, i32 -15>
   ret <2 x i32> %r
 }
 
 ; Negative test
 
 define i32 @unsigned_sat_constant_using_min_wrong_constant(i32 %x) {
 ; CHECK-LABEL: @unsigned_sat_constant_using_min_wrong_constant(
-; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[X:%.*]], 42
-; CHECK-NEXT:    [[S:%.*]] = select i1 [[C]], i32 [[X]], i32 42
-; CHECK-NEXT:    [[R:%.*]] = add nsw i32 [[S]], -42
-; CHECK-NEXT:    ret i32 [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.usub.sat.i32(i32 42, i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP2:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %c = icmp ult i32 %x, 42
   %s = select i1 %c, i32 %x, i32 42
   %r = add i32 %s, -42
   ret i32 %r
 }
 
 define i32 @uadd_sat_via_add(i32 %x, i32 %y) {

llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -instcombine %s -S -o - | FileCheck %s
 
 ; Clamp positive to allOnes:
 ; E.g., clamp255 implemented in a shifty way, could be optimized as v > 255 ? 255 : v, where sub hasNoSignedWrap.
 ; int32 clamp255(int32 v) {
 ;   return (((255 - (v)) >> 31) | (v)) & 255;
 ; }
 ;
 
 ; Scalar Types
 
 define i32 @clamp255_i32(i32 %x) {
 ; CHECK-LABEL: @clamp255_i32(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 255
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[OR]], 255
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[X]], 255
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 255
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nsw i32 255, %x
   %shr = ashr i32 %sub, 31
   %or = or i32 %shr, %x
   %and = and i32 %or, 255
   ret i32 %and
 }

llvm/test/Transforms/InstCombine/sub.ll

;
   %C = shl <2 x i32> %B, <i32 1, i32 1>
   %D = sub <2 x i32> <i32 2, i32 2>, %C
   ret <2 x i32> %D
 }
 
 define i32 @test64(i32 %x) {
 ; CHECK-LABEL: @test64(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 255
-; CHECK-NEXT:    [[DOTNEG:%.*]] = add nsw i32 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:    [[DOTNEG:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 256
 ; CHECK-NEXT:    ret i32 [[DOTNEG]]
 ;
   %1 = xor i32 %x, -1
   %2 = icmp sgt i32 %1, -256
   %3 = select i1 %2, i32 %1, i32 -256
   %res = sub i32 0, %3
   ret i32 %res
 }
 
 define i32 @test65(i32 %x) {
 ; CHECK-LABEL: @test65(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -256
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 -256
-; CHECK-NEXT:    [[DOTNEG:%.*]] = add i32 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[DOTINV:%.*]] = icmp slt i32 [[X]], -255
+; CHECK-NEXT:    [[DOTNEG:%.*]] = select i1 [[DOTINV]], i32 -255, i32 [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[DOTNEG]]
 ;
   %1 = xor i32 %x, -1
   %2 = icmp slt i32 %1, 255
   %3 = select i1 %2, i32 %1, i32 255
   %res = sub i32 0, %3
   ret i32 %res
 }
 
 define i32 @test66(i32 %x) {
 ; CHECK-LABEL: @test66(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], -101
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 -101
-; CHECK-NEXT:    [[DOTNEG:%.*]] = add nuw i32 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:    [[DOTNEG:%.*]] = select i1 [[TMP1]], i32 [[TMP2]], i32 -100
 ; CHECK-NEXT:    ret i32 [[DOTNEG]]
 ;
   %1 = xor i32 %x, -1
   %2 = icmp ugt i32 %1, 100
   %3 = select i1 %2, i32 %1, i32 100
   %res = sub i32 0, %3
   ret i32 %res
 }
 
 define i32 @test67(i32 %x) {
 ; CHECK-LABEL: @test67(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], 100
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 100
-; CHECK-NEXT:    [[DOTNEG:%.*]] = add i32 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[DOTINV:%.*]] = icmp ult i32 [[X]], 101
+; CHECK-NEXT:    [[DOTNEG:%.*]] = select i1 [[DOTINV]], i32 101, i32 [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[DOTNEG]]
 ;
   %1 = xor i32 %x, -1
   %2 = icmp ult i32 %1, -101
   %3 = select i1 %2, i32 %1, i32 -101
   %res = sub i32 0, %3
   ret i32 %res
 }
 
 ; Check splat vectors too
 define <2 x i32> @test68(<2 x i32> %x) {
 ; CHECK-LABEL: @test68(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 255, i32 255>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[X]], <2 x i32> <i32 255, i32 255>
-; CHECK-NEXT:    [[DOTNEG:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i32> [[X]], <i32 1, i32 1>
+; CHECK-NEXT:    [[DOTNEG:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 256, i32 256>
 ; CHECK-NEXT:    ret <2 x i32> [[DOTNEG]]
 ;
   %1 = xor <2 x i32> %x, <i32 -1, i32 -1>
   %2 = icmp sgt <2 x i32> %1, <i32 -256, i32 -256>
   %3 = select <2 x i1> %2, <2 x i32> %1, <2 x i32> <i32 -256, i32 -256>
   %res = sub <2 x i32> zeroinitializer, %3
   ret <2 x i32> %res
 }
 
 ; And non-splat constant vectors.
 define <2 x i32> @test69(<2 x i32> %x) {
 ; CHECK-LABEL: @test69(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 255, i32 127>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[X]], <2 x i32> <i32 255, i32 127>
-; CHECK-NEXT:    [[DOTNEG:%.*]] = add <2 x i32> [[TMP2]], <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i32> [[X]], <i32 1, i32 1>
+; CHECK-NEXT:    [[DOTNEG:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[TMP2]], <2 x i32> <i32 256, i32 128>
 ; CHECK-NEXT:    ret <2 x i32> [[DOTNEG]]
 ;
   %1 = xor <2 x i32> %x, <i32 -1, i32 -1>
   %2 = icmp sgt <2 x i32> %1, <i32 -256, i32 -128>
   %3 = select <2 x i1> %2, <2 x i32> %1, <2 x i32> <i32 -256, i32 -128>
   %res = sub <2 x i32> zeroinitializer, %3
   ret <2 x i32> %res
 }

llvm/test/Transforms/InstCombine/with_overflow.ll

;
   %y = or i8 %x, 128
   %a = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %y, i8 2)
   ret { i8, i1 } %a
 }
 
 define { i8, i1 } @sadd_always_overflow(i8 %x) nounwind {
 ; CHECK-LABEL: @sadd_always_overflow(
 ; CHECK-NEXT:    [[C:%.*]] = icmp sgt i8 [[X:%.*]], 100
-; CHECK-NEXT:    [[Y:%.*]] = select i1 [[C]], i8 [[X]], i8 100
-; CHECK-NEXT:    [[A:%.*]] = add nuw i8 [[Y]], 28
-; CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { i8, i1 } { i8 undef, i1 true }, i8 [[A]], 0
-; CHECK-NEXT:    ret { i8, i1 } [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X]], 28
+; CHECK-NEXT:    [[A:%.*]] = select i1 [[C]], i8 [[TMP1]], i8 -128
+; CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { i8, i1 } { i8 undef, i1 true }, i8 [[A]], 0
+; CHECK-NEXT:    ret { i8, i1 } [[TMP2]]
 ;
   %c = icmp sgt i8 %x, 100
   %y = select i1 %c, i8 %x, i8 100
   %a = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %y, i8 28)
   ret { i8, i1 } %a
 }
 
 define { i8, i1 } @ssub_always_overflow(i8 %x) nounwind {
 ; CHECK-LABEL: @ssub_always_overflow(
 ; CHECK-NEXT:    [[C:%.*]] = icmp sgt i8 [[X:%.*]], 29
-; CHECK-NEXT:    [[Y:%.*]] = select i1 [[C]], i8 [[X]], i8 29
-; CHECK-NEXT:    [[A:%.*]] = sub nuw i8 -100, [[Y]]
-; CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { i8, i1 } { i8 undef, i1 true }, i8 [[A]], 0
-; CHECK-NEXT:    ret { i8, i1 } [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = sub i8 -100, [[X]]
+; CHECK-NEXT:    [[A:%.*]] = select i1 [[C]], i8 [[TMP1]], i8 127
+; CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { i8, i1 } { i8 undef, i1 true }, i8 [[A]], 0
+; CHECK-NEXT:    ret { i8, i1 } [[TMP2]]
 ;
   %c = icmp sgt i8 %x, 29
   %y = select i1 %c, i8 %x, i8 29
   %a = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 -100, i8 %y)
   ret { i8, i1 } %a
 }
 
 define { i8, i1 } @smul_always_overflow(i8 %x) nounwind {

llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll

 ; CHECK-NEXT:    [[NEXT_GEP:%.*]] = getelementptr float, float* [[PA]], i32 [[INDEX]]
 ; CHECK-NEXT:    [[NEXT_GEP5:%.*]] = getelementptr float, float* [[PB]], i32 [[INDEX]]
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast float* [[NEXT_GEP]] to <4 x float>*
 ; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[NEXT_GEP5]] to <4 x float>*
 ; CHECK-NEXT:    [[WIDE_LOAD6:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = fcmp fast oeq <4 x float> [[WIDE_LOAD]], zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = fcmp fast oeq <4 x float> [[WIDE_LOAD6]], zeroinitializer
-; CHECK-NEXT:    [[TMP4:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <4 x i1> zeroinitializer
-; CHECK-NEXT:    [[TMP5:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[WIDE_LOAD]])
-; CHECK-NEXT:    [[TMP6:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[WIDE_LOAD6]])
-; CHECK-NEXT:    [[TMP7:%.*]] = fadd fast <4 x float> [[TMP6]], [[TMP5]]
-; CHECK-NEXT:    [[TMP8:%.*]] = fsub fast <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD6]]
-; CHECK-NEXT:    [[TMP9:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP8]])
-; CHECK-NEXT:    [[TMP10:%.*]] = fdiv fast <4 x float> [[TMP9]], [[TMP7]]
-; CHECK-NEXT:    [[TMP11:%.*]] = fadd fast <4 x float> [[TMP10]], [[VEC_PHI]]
-; CHECK-NEXT:    [[PREDPHI]] = select <4 x i1> [[TMP4]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP11]]
+; CHECK-NEXT:    [[TMP4:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[WIDE_LOAD]])
+; CHECK-NEXT:    [[TMP5:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[WIDE_LOAD6]])
+; CHECK-NEXT:    [[TMP6:%.*]] = fadd fast <4 x float> [[TMP5]], [[TMP4]]
+; CHECK-NEXT:    [[TMP7:%.*]] = fsub fast <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP7]])
+; CHECK-NEXT:    [[TMP9:%.*]] = fdiv fast <4 x float> [[TMP8]], [[TMP6]]
+; CHECK-NEXT:    [[TMP10:%.*]] = fadd fast <4 x float> [[TMP9]], [[VEC_PHI]]
+; CHECK-NEXT:    [[TMP11:%.*]] = select <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <4 x i1> zeroinitializer
+; CHECK-NEXT:    [[PREDPHI]] = select <4 x i1> [[TMP11]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP10]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
 ; CHECK-NEXT:    br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
 ; CHECK:       middle.block:
 ; CHECK-NEXT:    [[TMP13:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[PREDPHI]])
 ; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[N_VEC]], [[BLOCKSIZE]]
 ; CHECK-NEXT:    br i1 [[CMP_N]], label [[WHILE_END]], label [[SCALAR_PH]]
 ; CHECK:       scalar.ph: