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[Codegen][TLI][X86] SimplifyMultipleUseDemandedBits(): 0'th vec subreg widening is free, try to perform it earlier
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Authored by lebedev.ri on Sep 1 2021, 10:42 AM.

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Summary

I believe, the profitability reasoning here is correct?
subreg is already located within the 0'th subreg of wider reg,
so if we have suvector insertion at index 0 into undef,
then it's always free do to?

After this, D109065 finally avoids the regression in D108382.

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Event Timeline

lebedev.ri created this revision.Sep 1 2021, 10:42 AM
lebedev.ri requested review of this revision.Sep 1 2021, 10:42 AM

Don't try to change DemandedBits width - this can't change elt width. NFC.

RKSimon added inline comments.Sep 1 2021, 2:22 PM
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
821–822

Move the comment down now that we do other things as well.

832

Isn't this the same as DemandedElts.extractBits(NumSubElts, Idx)? Reuse a common variable?

lebedev.ri updated this revision to Diff 370062.Sep 1 2021, 2:32 PM
lebedev.ri marked 2 inline comments as done.

@RKSimon thanks for taking a look!
Address review notes.

RKSimon accepted this revision.Sep 1 2021, 2:38 PM

LGTM with one minor - cheers

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
827

There is only one use of SubVT again, so you can revert this back to:

unsigned NumSubElts = Sub.getValueType().getVectorNumElements();
This revision is now accepted and ready to land.Sep 1 2021, 2:38 PM
lebedev.ri updated this revision to Diff 370069.Sep 1 2021, 2:41 PM
lebedev.ri marked an inline comment as done.

Thank you for the review!

Address nit.

This revision was landed with ongoing or failed builds.Sep 1 2021, 2:54 PM
This revision was automatically updated to reflect the committed changes.