[MipsISelLowering] avoid emitting libcalls to __multi3

[nickdesaulniers]

Summary

Similar to D108842 and D108844.

has_builtin(builtin_mul_overflow) returns true for 32b MIPS targets,
but Clang is deferring to compiler RT when encountering long long types.
This breaks MIPS malta_defconfig builds of the Linux kernel that are
using builtin_mul_overflow with these types for these targets.

If the semantics of __has_builtin mean "the compiler resolves these,
always" then we shouldn't conditionally emit a libcall.

This will still need to be worked around in the Linux kernel in order to
continue to support malta_defconfig builds of the Linux kernel for this
target with older releases of clang.

Link: https://bugs.llvm.org/show_bug.cgi?id=28629
Link: https://github.com/ClangBuiltLinux/linux/issues/1438

[rengolin]

Why is multi3 a problem for MIPS but not Arm or x64_32?

[craig.topper]

In D108926#2972755, @rengolin wrote:

Why is multi3 a problem for MIPS but not Arm or x64_32?

Both ARM and 32-bit x86 have this line already

setLibcallName(RTLIB::MUL_I128, nullptr);

[nickdesaulniers]

I need to update llvm/tests/CodeGen/Mips/llvm-ir/mul.ll and llvm/tests/CodeGen/Mips/urem-seteq-illegal-types.ll.

[nickdesaulniers]

• fix up tests

[nickdesaulniers]

llvm/test/CodeGen/Mips/llvm-ir/mul.ll

252

perhaps it's more interesting to encode what the code actually being generated is, but I found it to be a tangly mess of spaghetti for this test in particular. GP32 and MM32 refer to multiple targets respectively; each have divergent code implementing 128b multiplication (and a lot of it).

[nickdesaulniers]

Bumping for review; as you can see, our CI for mips build of linux-next kernel tree are failing without this patch:
https://github.com/ClangBuiltLinux/continuous-integration2/runs/3484727038?check_suite_focus=true
https://github.com/ClangBuiltLinux/continuous-integration2/runs/3484726954?check_suite_focus=true

[rengolin]

LGTM, thanks!

llvm/lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setTargetDAGCombine(ISD::AssertZext);
   setTargetDAGCombine(ISD::SHL);
 
   if (ABI.IsO32()) {
     // These libcalls are not available in 32-bit.
     setLibcallName(RTLIB::SHL_I128, nullptr);
     setLibcallName(RTLIB::SRL_I128, nullptr);
     setLibcallName(RTLIB::SRA_I128, nullptr);
+    setLibcallName(RTLIB::MUL_I128, nullptr);
     setLibcallName(RTLIB::MULO_I64, nullptr);
     setLibcallName(RTLIB::MULO_I128, nullptr);
   }
 
   setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4));
 
   // The arguments on the stack are defined in terms of 4-byte slots on O32
   // and 8-byte slots on N32/N64.

llvm/test/CodeGen/Mips/llvm-ir/mul.ll

; ALL-LABEL: mul_i64:
   %r = mul i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: mul_i128:
 
-  ; GP32:           lw      $25, %call16(__multi3)($gp)
+  ; GP32-NOT:       lw      $25, %call16(__multi3)($gp)
 
   ; GP64-NOT-R6:    dmult   $4, $7
   ; GP64-NOT-R6:    mflo    $[[T0:[0-9]+]]
   ; GP64-NOT-R6:    dmult   $5, $6
   ; GP64-NOT-R6:    mflo    $[[T1:[0-9]+]]
   ; GP64-NOT-R6:    dmultu  $5, $7
   ; GP64-NOT-R6:    mflo    $3
   ; GP64-NOT-R6:    mfhi    $[[T2:[0-9]+]]
   ; GP64-NOT-R6:    daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; GP64-NOT-R6:    daddu   $2, $[[T3:[0-9]+]], $[[T0]]
 
   ; 64R6-DAG:       dmul    $[[T1:[0-9]+]], $5, $6
   ; 64R6:           dmuhu   $[[T2:[0-9]+]], $5, $7
   ; 64R6:           daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; 64R6-DAG:       dmul    $[[T0:[0-9]+]], $4, $7
   ; 64R6:           daddu   $2, $[[T1]], $[[T0]]
   ; 64R6-DAG:       dmul    $3, $5, $7
 
-  ; MM32:           lw      $25, %call16(__multi3)($16)
+  ; MM32-NOT:       lw      $25, %call16(__multi3)($16)
 
   %r = mul i128 %a, %b
   ret i128 %r
 }

llvm/test/CodeGen/Mips/overflow-intrinsic-optimizations.ll

 ; RUN: llc %s -mtriple=mipsel -o - | FileCheck %s
 
 define i1 @no__mulodi4(i32 %a, i64 %b, i32* %c) {
 ; CHECK-LABEL: no__mulodi4
 ; CHECK-NOT: jal __mulodi4
+; CHECK-NOT: jal __multi3
 entry:
   %0 = sext i32 %a to i64
   %1 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %0, i64 %b)
   %2 = extractvalue { i64, i1 } %1, 1
   %3 = extractvalue { i64, i1 } %1, 0
   %4 = trunc i64 %3 to i32
   %5 = sext i32 %4 to i64
   %6 = icmp ne i64 %3, %5
   %7 = or i1 %2, %6
   store i32 %4, i32* %c, align 4
   ret i1 %7
 }
 
 declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)

llvm/test/CodeGen/Mips/urem-seteq-illegal-types.ll

 ;   %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
 ;   %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
 ;   ret <3 x i1> %cmp
 ; }
 
 define i1 @test_urem_oversized(i66 %X) nounwind {
 ; MIPSEL-LABEL: test_urem_oversized:
 ; MIPSEL:       # %bb.0:
-; MIPSEL-NEXT:    addiu $sp, $sp, -40
-; MIPSEL-NEXT:    sw $ra, 36($sp) # 4-byte Folded Spill
-; MIPSEL-NEXT:    move $7, $6
-; MIPSEL-NEXT:    move $6, $5
-; MIPSEL-NEXT:    move $5, $4
 ; MIPSEL-NEXT:    lui $1, 12057
 ; MIPSEL-NEXT:    ori $1, $1, 37186
-; MIPSEL-NEXT:    lui $2, 52741
-; MIPSEL-NEXT:    ori $2, $2, 40665
-; MIPSEL-NEXT:    sw $2, 28($sp)
-; MIPSEL-NEXT:    sw $1, 24($sp)
-; MIPSEL-NEXT:    addiu $1, $zero, 2
-; MIPSEL-NEXT:    sw $1, 20($sp)
-; MIPSEL-NEXT:    sw $zero, 16($sp)
-; MIPSEL-NEXT:    jal __multi3
-; MIPSEL-NEXT:    addiu $4, $zero, 0
-; MIPSEL-NEXT:    sll $1, $4, 31
-; MIPSEL-NEXT:    srl $2, $5, 1
-; MIPSEL-NEXT:    or $1, $2, $1
-; MIPSEL-NEXT:    lui $2, 60010
-; MIPSEL-NEXT:    ori $2, $2, 61135
-; MIPSEL-NEXT:    sltu $1, $1, $2
-; MIPSEL-NEXT:    srl $2, $4, 1
-; MIPSEL-NEXT:    andi $3, $3, 3
-; MIPSEL-NEXT:    sll $4, $3, 31
-; MIPSEL-NEXT:    or $4, $2, $4
+; MIPSEL-NEXT:    multu $6, $1
+; MIPSEL-NEXT:    mflo $2
+; MIPSEL-NEXT:    mfhi $3
+; MIPSEL-NEXT:    lui $7, 52741
+; MIPSEL-NEXT:    ori $7, $7, 40665
+; MIPSEL-NEXT:    multu $6, $7
+; MIPSEL-NEXT:    mflo $8
+; MIPSEL-NEXT:    mfhi $9
+; MIPSEL-NEXT:    multu $5, $7
+; MIPSEL-NEXT:    mfhi $10
+; MIPSEL-NEXT:    mflo $11
+; MIPSEL-NEXT:    addu $9, $11, $9
+; MIPSEL-NEXT:    addu $12, $2, $9
+; MIPSEL-NEXT:    sltu $9, $9, $11
+; MIPSEL-NEXT:    sll $11, $12, 31
+; MIPSEL-NEXT:    sltu $2, $12, $2
+; MIPSEL-NEXT:    srl $13, $8, 1
+; MIPSEL-NEXT:    sll $8, $8, 1
+; MIPSEL-NEXT:    addu $2, $3, $2
+; MIPSEL-NEXT:    or $3, $13, $11
+; MIPSEL-NEXT:    srl $11, $12, 1
+; MIPSEL-NEXT:    addu $9, $10, $9
+; MIPSEL-NEXT:    mul $4, $4, $7
+; MIPSEL-NEXT:    mul $1, $5, $1
+; MIPSEL-NEXT:    sll $5, $6, 1
+; MIPSEL-NEXT:    lui $6, 60010
+; MIPSEL-NEXT:    ori $6, $6, 61135
+; MIPSEL-NEXT:    addu $2, $9, $2
+; MIPSEL-NEXT:    addu $1, $1, $2
+; MIPSEL-NEXT:    addu $2, $5, $4
+; MIPSEL-NEXT:    addu $1, $1, $2
+; MIPSEL-NEXT:    andi $1, $1, 3
+; MIPSEL-NEXT:    sll $2, $1, 31
+; MIPSEL-NEXT:    or $4, $11, $2
 ; MIPSEL-NEXT:    sltiu $2, $4, 13
 ; MIPSEL-NEXT:    xori $4, $4, 13
-; MIPSEL-NEXT:    movz $2, $1, $4
-; MIPSEL-NEXT:    sll $1, $5, 1
-; MIPSEL-NEXT:    srl $3, $3, 1
-; MIPSEL-NEXT:    or $1, $3, $1
+; MIPSEL-NEXT:    sltu $3, $3, $6
+; MIPSEL-NEXT:    movz $2, $3, $4
+; MIPSEL-NEXT:    srl $1, $1, 1
+; MIPSEL-NEXT:    or $1, $1, $8
 ; MIPSEL-NEXT:    andi $1, $1, 3
-; MIPSEL-NEXT:    movn $2, $zero, $1
-; MIPSEL-NEXT:    lw $ra, 36($sp) # 4-byte Folded Reload
 ; MIPSEL-NEXT:    jr $ra
-; MIPSEL-NEXT:    addiu $sp, $sp, 40
+; MIPSEL-NEXT:    movn $2, $zero, $1
 ;
 ; MIPS64EL-LABEL: test_urem_oversized:
 ; MIPS64EL:       # %bb.0:
 ; MIPS64EL-NEXT:    lui $1, 6029
 ; MIPS64EL-NEXT:    daddiu $1, $1, -14175
 ; MIPS64EL-NEXT:    dsll $1, $1, 16
 ; MIPS64EL-NEXT:    daddiu $1, $1, 26371
 ; MIPS64EL-NEXT:    dsll $1, $1, 17