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Differential D108915

[RISCV][test] Add new tests for optimization with SH*ADD in the zba extension
ClosedPublic

Authored by benshi001 on Aug 30 2021, 6:19 AM.

Details

Reviewers
asb
craig.topper
luismarques
jrtc27
Commits
rGe47ab56398c3: [RISCV][test] Add tests for optimization with SH*ADD in the zba extension

Diff Detail

Event Timeline

benshi001 created this revision.Aug 30 2021, 6:19 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 21 others. · View Herald TranscriptAug 30 2021, 6:19 AM
benshi001 requested review of this revision.Aug 30 2021, 6:19 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 30 2021, 6:19 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
benshi001 added a child revision: D108916: [RISCV] Optimize (add (shl x, c0), (shl y, c1)) with SH*ADD.Aug 30 2021, 6:23 AM
Harbormaster completed remote builds in B121733: Diff 369433.Aug 30 2021, 6:58 AM
benshi001 updated this revision to Diff 369606.Aug 30 2021, 7:37 PM
Harbormaster completed remote builds in B121866: Diff 369606.Aug 30 2021, 7:38 PM
benshi001 updated this revision to Diff 369615.Aug 30 2021, 8:22 PM
asb accepted this revision.Sep 2 2021, 1:51 AM
This revision is now accepted and ready to land.Sep 2 2021, 1:51 AM
This revision was landed with ongoing or failed builds.Sep 2 2021, 2:30 AM
Closed by commit rGe47ab56398c3: [RISCV][test] Add tests for optimization with SH*ADD in the zba extension (authored by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGe47ab56398c3: [RISCV][test] Add tests for optimization with SH*ADD in the zba extension.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
81 lines
162 lines

Diff 370207

llvm/test/CodeGen/RISCV/rv32zba.ll

Show First 20 Lines • Show All 779 Lines • ▼ Show 20 Lines
; RV32ZBA-LABEL: add8208: ; RV32ZBA-LABEL: add8208:
; RV32ZBA: # %bb.0: ; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 1026 ; RV32ZBA-NEXT: addi a1, zero, 1026
; RV32ZBA-NEXT: sh3add a0, a1, a0 ; RV32ZBA-NEXT: sh3add a0, a1, a0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
%c = add i32 %a, 8208 %c = add i32 %a, 8208
ret i32 %c ret i32 %c
} }
define i32 @addshl_5_6(i32 %a, i32 %b) {
; RV32I-LABEL: addshl_5_6:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: slli a1, a1, 6
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32B-LABEL: addshl_5_6:
; RV32B: # %bb.0:
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: slli a1, a1, 6
; RV32B-NEXT: add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addshl_5_6:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: slli a1, a1, 6
; RV32ZBA-NEXT: add a0, a0, a1
; RV32ZBA-NEXT: ret
%c = shl i32 %a, 5
%d = shl i32 %b, 6
%e = add i32 %c, %d
ret i32 %e
}
define i32 @addshl_5_7(i32 %a, i32 %b) {
; RV32I-LABEL: addshl_5_7:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: slli a1, a1, 7
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32B-LABEL: addshl_5_7:
; RV32B: # %bb.0:
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: slli a1, a1, 7
; RV32B-NEXT: add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addshl_5_7:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: slli a1, a1, 7
; RV32ZBA-NEXT: add a0, a0, a1
; RV32ZBA-NEXT: ret
%c = shl i32 %a, 5
%d = shl i32 %b, 7
%e = add i32 %c, %d
ret i32 %e
}
define i32 @addshl_5_8(i32 %a, i32 %b) {
; RV32I-LABEL: addshl_5_8:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32B-LABEL: addshl_5_8:
; RV32B: # %bb.0:
; RV32B-NEXT: slli a0, a0, 5
; RV32B-NEXT: slli a1, a1, 8
; RV32B-NEXT: add a0, a0, a1
; RV32B-NEXT: ret
;
; RV32ZBA-LABEL: addshl_5_8:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: slli a0, a0, 5
; RV32ZBA-NEXT: slli a1, a1, 8
; RV32ZBA-NEXT: add a0, a0, a1
; RV32ZBA-NEXT: ret
%c = shl i32 %a, 5
%d = shl i32 %b, 8
%e = add i32 %c, %d
ret i32 %e
}

llvm/test/CodeGen/RISCV/rv64zba.ll

Show First 20 Lines • Show All 1,393 Lines • ▼ Show 20 Lines
; RV64ZBA-LABEL: add8208: ; RV64ZBA-LABEL: add8208:
; RV64ZBA: # %bb.0: ; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 1026 ; RV64ZBA-NEXT: addi a1, zero, 1026
; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
%c = add i64 %a, 8208 %c = add i64 %a, 8208
ret i64 %c ret i64 %c
} }
define signext i32 @addshl32_5_6(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addshl32_5_6:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 5
; RV64I-NEXT: slliw a1, a1, 6
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64B-LABEL: addshl32_5_6:
; RV64B: # %bb.0:
; RV64B-NEXT: slliw a0, a0, 5
; RV64B-NEXT: slliw a1, a1, 6
; RV64B-NEXT: addw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl32_5_6:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slliw a0, a0, 5
; RV64ZBA-NEXT: slliw a1, a1, 6
; RV64ZBA-NEXT: addw a0, a0, a1
; RV64ZBA-NEXT: ret
%c = shl i32 %a, 5
%d = shl i32 %b, 6
%e = add i32 %c, %d
ret i32 %e
}
define i64 @addshl64_5_6(i64 %a, i64 %b) {
; RV64I-LABEL: addshl64_5_6:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: slli a1, a1, 6
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64B-LABEL: addshl64_5_6:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: slli a1, a1, 6
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl64_5_6:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: slli a1, a1, 6
; RV64ZBA-NEXT: add a0, a0, a1
; RV64ZBA-NEXT: ret
%c = shl i64 %a, 5
%d = shl i64 %b, 6
%e = add i64 %c, %d
ret i64 %e
}
define signext i32 @addshl32_5_7(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addshl32_5_7:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 5
; RV64I-NEXT: slliw a1, a1, 7
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64B-LABEL: addshl32_5_7:
; RV64B: # %bb.0:
; RV64B-NEXT: slliw a0, a0, 5
; RV64B-NEXT: slliw a1, a1, 7
; RV64B-NEXT: addw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl32_5_7:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slliw a0, a0, 5
; RV64ZBA-NEXT: slliw a1, a1, 7
; RV64ZBA-NEXT: addw a0, a0, a1
; RV64ZBA-NEXT: ret
%c = shl i32 %a, 5
%d = shl i32 %b, 7
%e = add i32 %c, %d
ret i32 %e
}
define i64 @addshl64_5_7(i64 %a, i64 %b) {
; RV64I-LABEL: addshl64_5_7:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: slli a1, a1, 7
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64B-LABEL: addshl64_5_7:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: slli a1, a1, 7
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl64_5_7:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: slli a1, a1, 7
; RV64ZBA-NEXT: add a0, a0, a1
; RV64ZBA-NEXT: ret
%c = shl i64 %a, 5
%d = shl i64 %b, 7
%e = add i64 %c, %d
ret i64 %e
}
define signext i32 @addshl32_5_8(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addshl32_5_8:
; RV64I: # %bb.0:
; RV64I-NEXT: slliw a0, a0, 5
; RV64I-NEXT: slliw a1, a1, 8
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64B-LABEL: addshl32_5_8:
; RV64B: # %bb.0:
; RV64B-NEXT: slliw a0, a0, 5
; RV64B-NEXT: slliw a1, a1, 8
; RV64B-NEXT: addw a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl32_5_8:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slliw a0, a0, 5
; RV64ZBA-NEXT: slliw a1, a1, 8
; RV64ZBA-NEXT: addw a0, a0, a1
; RV64ZBA-NEXT: ret
%c = shl i32 %a, 5
%d = shl i32 %b, 8
%e = add i32 %c, %d
ret i32 %e
}
define i64 @addshl64_5_8(i64 %a, i64 %b) {
; RV64I-LABEL: addshl64_5_8:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: slli a1, a1, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64B-LABEL: addshl64_5_8:
; RV64B: # %bb.0:
; RV64B-NEXT: slli a0, a0, 5
; RV64B-NEXT: slli a1, a1, 8
; RV64B-NEXT: add a0, a0, a1
; RV64B-NEXT: ret
;
; RV64ZBA-LABEL: addshl64_5_8:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: slli a0, a0, 5
; RV64ZBA-NEXT: slli a1, a1, 8
; RV64ZBA-NEXT: add a0, a0, a1
; RV64ZBA-NEXT: ret
%c = shl i64 %a, 5
%d = shl i64 %b, 8
%e = add i64 %c, %d
ret i64 %e
}