[PowerPC] Mark splat immediate instructions as rematerializable

[NeHuang]

Summary

This patch marks splat immediate instructions XXSPLTIDP and XXSPLTI32DX as rematerializable to prevent MachineLICM from moving them out of loops.

[amyk]

A question I have is, I noticed there are some test case changes involving xxspltidp and xxsplti32dx, but are additional tests needed for xxspltiw?

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

1880

nit: Update this comment to include xxspltiw and xxspltidp.

[lei]

LGTM
Thx.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
   case PPC::ADDIStocHA8:
   case PPC::ADDItocL:
   case PPC::LOAD_STACK_GUARD:
   case PPC::XXLXORz:
   case PPC::XXLXORspz:
   case PPC::XXLXORdpz:
   case PPC::XXLEQVOnes:
   case PPC::XXSPLTI32DX:
+  case PPC::XXSPLTIW:
+  case PPC::XXSPLTIDP:
   case PPC::V_SET0B:
   case PPC::V_SET0H:
   case PPC::V_SET0:
   case PPC::V_SETALLONESB:
   case PPC::V_SETALLONESH:
   case PPC::V_SETALLONES:
   case PPC::CRSET:
   case PPC::CRUNSET:

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [PCRelativeMemops] in {
   def : Pat<(PPCtlsdynamatpcreladdr PCRelForm:$addr), (PADDI8pc 0, $addr)>;
   // PPCtlslocalexecmataddr node is used for TLS local exec models to
   // materialize tls global address with paddi instruction.
   def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)),
             (PADDI8 $in, $addr)>;
 }
 
 let Predicates = [PrefixInstrs] in {
-  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
-                                     (ins i32imm:$IMM32),
-                                     "xxspltiw $XT, $IMM32", IIC_VecGeneral,
-                                     []>;
-  def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
-                                      (ins i32imm:$IMM32),
-                                      "xxspltidp $XT, $IMM32", IIC_VecGeneral,
-                                      [(set v2f64:$XT,
-                                            (PPCxxspltidp i32:$IMM32))]>;
   def XXPERMX :
     8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
                             vsrc:$XC, u3imm:$UIM),
                             "xxpermx $XT, $XA, $XB, $XC, $UIM",
                             IIC_VecPerm, []>;
   def XXBLENDVB :
     8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
                        vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
                        IIC_VecGeneral, []>;
   def XXBLENDVH :
     8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
                        vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
                        IIC_VecGeneral, []>;
   def XXBLENDVW :
     8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
                        vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
                        IIC_VecGeneral, []>;
   def XXBLENDVD :
     8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
                        vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
                        IIC_VecGeneral, []>;
 }
 
-// XXSPLI32DX needs extra flags to make sure the compiler does not attempt
+// XXSPLTIW/DP/32DX need extra flags to make sure the compiler does not attempt
 // to spill part of the instruction when the values are similar.
-let isReMaterializable = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
+  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
+                                     (ins i32imm:$IMM32),
+                                     "xxspltiw $XT, $IMM32", IIC_VecGeneral,
+                                     []>;
+  def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
+                                      (ins i32imm:$IMM32),
+                                      "xxspltidp $XT, $IMM32", IIC_VecGeneral,
+                                      [(set v2f64:$XT,
+                                            (PPCxxspltidp i32:$IMM32))]>;
   def XXSPLTI32DX :
       8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
                              (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32),
                              "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral,
                              [(set v2i64:$XT,
                                    (PPCxxsplti32dx v2i64:$XTi, i32:$IX,
                                                    i32:$IMM32))]>,
                              RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;

llvm/test/CodeGen/PowerPC/constant-pool.ll

 ; CHECK-LABEL: three_constants_ppcf128:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset v31, -16
+; CHECK-NEXT:    xxlxor f4, f4, f4
+; CHECK-NEXT:    xxsplti32dx vs3, 0, 1074935889
 ; CHECK-NEXT:    stxv vs63, 32(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    xxsplti32dx vs63, 0, 1074935889
-; CHECK-NEXT:    xxlxor f4, f4, f4
-; CHECK-NEXT:    xxlor vs3, vs63, vs63
 ; CHECK-NEXT:    xxsplti32dx vs3, 1, -343597384
 ; CHECK-NEXT:    # kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:    bl __gcc_qadd@notoc
-; CHECK-NEXT:    xxlor vs3, vs63, vs63
 ; CHECK-NEXT:    xxlxor f4, f4, f4
+; CHECK-NEXT:    xxsplti32dx vs3, 0, 1074935889
 ; CHECK-NEXT:    xxsplti32dx vs3, 1, -1719329096
 ; CHECK-NEXT:    # kill: def $f3 killed $f3 killed $vsl3
 ; CHECK-NEXT:    bl __gcc_qadd@notoc
 ; CHECK-NEXT:    xxsplti32dx vs63, 1, 8724152
 ; CHECK-NEXT:    xxlxor f4, f4, f4
 ; CHECK-NEXT:    xscpsgndp f3, vs63, vs63
 ; CHECK-NEXT:    bl __gcc_qadd@notoc
 ; CHECK-NEXT:    lxv vs63, 32(r1) # 16-byte Folded Reload

llvm/test/CodeGen/PowerPC/p10-spill-crun.ll

 declare i32 @call_2(%2*, %1*) local_unnamed_addr
 declare i32 @call_3(%2*, %1*) local_unnamed_addr
 declare %3* @call_4(%4*, i32, i32, i32, i32, i32, i16, i16, %2*, %1*, i32, float, float, float, float, i8*) local_unnamed_addr
 declare i32 @call_5(i8*) local_unnamed_addr
 declare i8 @call_6(%1*, i32) local_unnamed_addr
 
 define dso_local void @P10_Spill_CR_UN(%2* %arg, %1* %arg1, i32 %arg2) local_unnamed_addr {
 ; CHECK-LABEL: P10_Spill_CR_UN:
-; CHECK:         .localentry P10_Spill_CR_UN, 1
-; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    mfcr r12
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stw r12, 8(r1)
 ; CHECK-NEXT:    stdu r1, -224(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 224
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset r27, -40

 ; CHECK-NEXT:    xsmulsp f0, f1, f0
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    b .LBB0_15
 ; CHECK-NEXT:  .LBB0_14: # %bb41
 ; CHECK-NEXT:    # implicit-def: $r3
 ; CHECK-NEXT:  .LBB0_15: # %bb50
 ; CHECK-NEXT:    li r4, 0
-; CHECK-NEXT:    xxspltidp vs3, -1082130432
 ; CHECK-NEXT:    extsh r9, r3
 ; CHECK-NEXT:    extsw r6, r28
 ; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    xxspltidp vs3, -1082130432
+; CHECK-NEXT:    xxspltidp vs4, -1082130432
 ; CHECK-NEXT:    std r30, 104(r1)
 ; CHECK-NEXT:    std r29, 96(r1)
 ; CHECK-NEXT:    li r7, 0
 ; CHECK-NEXT:    li r8, 0
 ; CHECK-NEXT:    li r10, 0
-; CHECK-NEXT:    fmr f4, f3
-; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    std r4, 152(r1)
 ; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    std r4, 112(r1)
 ; CHECK-NEXT:    li r4, 1024
 ; CHECK-NEXT:    bl call_4@notoc
 ; CHECK-NEXT:  .LBB0_16: # %bb54
 ; CHECK-NEXT:    bc 12, 4*cr2+un, .LBB0_19
 ; CHECK-NEXT:  # %bb.17: # %bb56
 ; CHECK-NEXT:    ld r30, 208(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r29, 200(r1) # 8-byte Folded Reload

 ; CHECK-BE-NEXT:    xsmulsp f0, f1, f0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    b .LBB0_15
 ; CHECK-BE-NEXT:  .LBB0_14: # %bb41
 ; CHECK-BE-NEXT:    # implicit-def: $r3
 ; CHECK-BE-NEXT:  .LBB0_15: # %bb50
 ; CHECK-BE-NEXT:    li r4, 0
-; CHECK-BE-NEXT:    xxspltidp vs3, -1082130432
 ; CHECK-BE-NEXT:    extsh r9, r3
 ; CHECK-BE-NEXT:    extsw r6, r28
 ; CHECK-BE-NEXT:    li r5, 0
+; CHECK-BE-NEXT:    xxspltidp vs3, -1082130432
+; CHECK-BE-NEXT:    xxspltidp vs4, -1082130432
 ; CHECK-BE-NEXT:    std r30, 120(r1)
 ; CHECK-BE-NEXT:    std r29, 112(r1)
 ; CHECK-BE-NEXT:    li r7, 0
 ; CHECK-BE-NEXT:    li r8, 0
 ; CHECK-BE-NEXT:    li r10, 0
-; CHECK-BE-NEXT:    fmr f4, f3
-; CHECK-BE-NEXT:    xxlxor f1, f1, f1
 ; CHECK-BE-NEXT:    std r4, 168(r1)
 ; CHECK-BE-NEXT:    li r4, -1
+; CHECK-BE-NEXT:    xxlxor f1, f1, f1
 ; CHECK-BE-NEXT:    std r4, 128(r1)
 ; CHECK-BE-NEXT:    li r4, 1024
 ; CHECK-BE-NEXT:    bl call_4
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:  .LBB0_16: # %bb54
 ; CHECK-BE-NEXT:    bc 12, 4*cr2+un, .LBB0_19
 ; CHECK-BE-NEXT:  # %bb.17: # %bb56
 ; CHECK-BE-NEXT:    ld r30, 224(r1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/p10-splatImm.ll

 entry:
   ret <2 x double> <double 0x7FF0000000000000, double 0x7FF0000000000000>
 }
 
 define dso_local float @testFloatScalar() local_unnamed_addr {
 ; CHECK-LABEL: testFloatScalar:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxspltidp vs1, 1135290941
-; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 
 entry:
   ret float 0x40756547A0000000
 }
 
 define dso_local float @testFloatZeroScalar() local_unnamed_addr {
 ; CHECK-LABEL: testFloatZeroScalar:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    blr
 
 entry:
   ret float 0.000000e+00
 }
 
 define dso_local double @testDoubleRepresentableScalar() local_unnamed_addr {
 ; CHECK-LABEL: testDoubleRepresentableScalar:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxspltidp vs1, 1135290941
-; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 
 entry:
   ret double 0x40756547A0000000
 }
 
 define dso_local double @testDoubleZeroScalar() local_unnamed_addr {
 ; CHECK-LABEL: testDoubleZeroScalar: