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Differential D108606

[RISCV][test] Add more tests for (add (mul x, c0), c1)
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Authored by benshi001 on Aug 23 2021, 8:50 PM.

Details

Reviewers
asb
luismarques
jrtc27
craig.topper
Commits
rG9621bbdf62d3: [RISCV][test] Add more tests for (mul (add x, c1), c2)

Diff Detail

Event Timeline

benshi001 created this revision.Aug 23 2021, 8:50 PM
Herald added subscribers: vkmr, frasercrmck, evandro and 21 others. · View Herald TranscriptAug 23 2021, 8:50 PM
benshi001 requested review of this revision.Aug 23 2021, 8:50 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2021, 8:50 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
benshi001 added a child revision: D108607: [RISCV] Optimize (add (mul x, c0), c1).Aug 23 2021, 8:54 PM
Harbormaster completed remote builds in B120905: Diff 368262.Aug 23 2021, 9:18 PM
benshi001 updated this revision to Diff 368334.Aug 24 2021, 6:58 AM
Harbormaster completed remote builds in B120951: Diff 368334.Aug 24 2021, 7:37 AM
benshi001 added a comment.Aug 30 2021, 6:54 PM

ping ...

asb accepted this revision.Sep 2 2021, 1:55 AM
This revision is now accepted and ready to land.Sep 2 2021, 1:55 AM
Closed by commit rG9621bbdf62d3: [RISCV][test] Add more tests for (mul (add x, c1), c2) (authored by benshi001). · Explain WhySep 2 2021, 2:30 AM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG9621bbdf62d3: [RISCV][test] Add more tests for (mul (add x, c1), c2).

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
148 lines

Diff 368262

llvm/test/CodeGen/RISCV/addimm-mulimm.ll

Show First 20 Lines • Show All 332 Lines • ▼ Show 20 Lines
; RV64IMB-NEXT: addi a0, a0, 1000 ; RV64IMB-NEXT: addi a0, a0, 1000
; RV64IMB-NEXT: sh1add a0, a0, a0 ; RV64IMB-NEXT: sh1add a0, a0, a0
; RV64IMB-NEXT: slli a0, a0, 6 ; RV64IMB-NEXT: slli a0, a0, 6
; RV64IMB-NEXT: ret ; RV64IMB-NEXT: ret
%tmp0 = add i64 %x, 1000 %tmp0 = add i64 %x, 1000
%tmp1 = mul i64 %tmp0, 192 %tmp1 = mul i64 %tmp0, 192
ret i64 %tmp1 ret i64 %tmp1
} }
define i32 @add_mul_combine_reject_e1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_e1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 14
; RV32IMB-NEXT: addi a1, a1, -185
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_e1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -185
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 29
%tmp1 = add i32 %tmp0, 57159
ret i32 %tmp1
}
define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_reject_e2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 14
; RV32IMB-NEXT: addi a1, a1, -185
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_e2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -185
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 29
%tmp1 = add i32 %tmp0, 57159
ret i32 %tmp1
}
define i64 @add_mul_combine_reject_e3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_e3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 29
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 14
; RV32IMB-NEXT: addi a0, a0, -185
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_e3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -185
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, 29
%tmp1 = add i64 %tmp0, 57159
ret i64 %tmp1
}
define i32 @add_mul_combine_reject_f1(i32 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_f1:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 14
; RV32IMB-NEXT: addi a1, a1, -145
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_f1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -145
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 29
%tmp1 = add i32 %tmp0, 57199
ret i32 %tmp1
}
define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
; RV32IMB-LABEL: add_mul_combine_reject_f2:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a1, zero, 29
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 14
; RV32IMB-NEXT: addi a1, a1, -145
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_f2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -145
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 29
%tmp1 = add i32 %tmp0, 57199
ret i32 %tmp1
}
define i64 @add_mul_combine_reject_f3(i64 %x) {
; RV32IMB-LABEL: add_mul_combine_reject_f3:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: addi a2, zero, 29
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 14
; RV32IMB-NEXT: addi a0, a0, -145
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: add_mul_combine_reject_f3:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addi a1, zero, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 14
; RV64IMB-NEXT: addiw a1, a1, -145
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, 29
%tmp1 = add i64 %tmp0, 57199
ret i64 %tmp1
}