[AArch64] Lower fpto*i.sat intrinsics for NEON.

[jbramley]

Summary

Following on from D102353, extend the fpto*i.sat intrinsics to use NEON
fcvt* instructions.

[jbramley]

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

991

I omitted this suggestion, applying the golden rule. The 450 lines of diff made the actual change non-obvious (with default diff options), but I can include it if that's preferred.

[dmgreen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3396

I don't think this "Warning" adds much. It's OK to remove for now.

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

1084

This would need tests, and is probably best left for a separate commit. I think there would need to be more general FP_TO_SINT_SAT costing changes, it won't ever get here at the moment as they are intrinsics not cast instructions.

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

2

Can you add a run line with fp16 too.

[jbramley]

Thanks for the review!

[jbramley]

Address review comments.

[dmgreen]

LGTM.

llvm/lib/Target/AArch64/AArch64ISelLowering.h

private:
   SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (Subtarget->hasNEON()) {
     setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
 
     setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
     setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
     setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
     setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
     setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
 
+    setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v1i64, Expand);
+    setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v1i64, Expand);
+
     setOperationAction(ISD::MUL, MVT::v1i64, Expand);
 
     // AArch64 doesn't have a direct vector ->f32 conversion instructions for
     // elements smaller than i32, so promote the input to i32 first.
     setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32);
     setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32);
     setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32);
     setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32);
void AArch64TargetLowering::addTypeForNEON(MVT VT) {
   setOperationAction(ISD::UDIV, VT, Expand);
   setOperationAction(ISD::SDIV, VT, Expand);
   setOperationAction(ISD::UREM, VT, Expand);
   setOperationAction(ISD::SREM, VT, Expand);
   setOperationAction(ISD::FREM, VT, Expand);
 
   setOperationAction(ISD::FP_TO_SINT, VT, Custom);
   setOperationAction(ISD::FP_TO_UINT, VT, Custom);
+  setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
+  setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
 
   if (!VT.isFloatingPoint())
     setOperationAction(ISD::ABS, VT, Legal);
 
   // [SU][MIN|MAX] are available for all NEON types apart from i64.
   if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64)
     for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
       setOperationAction(Opcode, VT, Legal);
SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
   if (SrcVal.getValueType() != MVT::f128) {
     // It's legal except when f128 is involved
     return Op;
   }
 
   return SDValue();
 }
 
+SDValue
+AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
+                                                SelectionDAG &DAG) const {
+  // AArch64 FP-to-int conversions saturate to the destination element size, so
+  // we can lower common saturating conversions to simple instructions.
+  //
+  // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
+  // Any additional optimization in this function should be recorded
+  // in the cost tables.
+  SDValue SrcVal = Op.getOperand(0);
+  EVT SrcVT = SrcVal.getValueType();
+  EVT DstVT = Op.getValueType();
+  EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+
+  uint64_t SrcElementWidth = SrcVT.getScalarSizeInBits();
+  uint64_t DstElementWidth = DstVT.getScalarSizeInBits();
+  uint64_t SatWidth = SatVT.getScalarSizeInBits();
+  assert(SatWidth <= DstElementWidth &&
+         "Saturation width cannot exceed result width");
+
+  // TODO: Consider lowering to SVE operations, as in LowerVectorFP_TO_INT.
+  // Currently, the `llvm.fpto[su]i.sat.*` instrinsics don't accept scalable
+  // types, so this is hard to reach.
+  if (DstVT.isScalableVector())
+    return SDValue();
+
+  // TODO: Saturate to SatWidth explicitly.
+  if (SatWidth != DstElementWidth)
+    return SDValue();
+
+  EVT SrcElementVT = SrcVT.getVectorElementType();
+
+  // In the absence of FP16 support, promote f16 to f32, like
+  // LowerVectorFP_TO_INT().
+  if (SrcElementVT == MVT::f16 && !Subtarget->hasFullFP16()) {
+    MVT F32VT = MVT::getVectorVT(MVT::f32, SrcVT.getVectorNumElements());
+    return DAG.getNode(Op.getOpcode(), SDLoc(Op), DstVT,
+                       DAG.getNode(ISD::FP_EXTEND, SDLoc(Op), F32VT, SrcVal),
+                       Op.getOperand(1));
+  }
+
+  // Cases that we can emit directly.
+  if ((SrcElementWidth == DstElementWidth) &&
+      (SrcElementVT == MVT::f64 || SrcElementVT == MVT::f32 ||
+       (SrcElementVT == MVT::f16 && Subtarget->hasFullFP16()))) {
+    return Op;
+  }
+
+  // For all other cases, fall back on the expanded form.
+  return SDValue();
+}
+
 SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
                                                   SelectionDAG &DAG) const {
   // AArch64 FP-to-int conversions saturate to the destination register size, so
   // we can lower common saturating conversions to simple instructions.
   SDValue SrcVal = Op.getOperand(0);
-
   EVT SrcVT = SrcVal.getValueType();
-  EVT DstVT = Op.getValueType();
 
+  if (SrcVT.isVector())
+    return LowerVectorFP_TO_INT_SAT(Op, DAG);
+
+  EVT DstVT = Op.getValueType();
   EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
   uint64_t SatWidth = SatVT.getScalarSizeInBits();
   uint64_t DstWidth = DstVT.getScalarSizeInBits();
   assert(SatWidth <= DstWidth && "Saturation width cannot exceed result width");
 
-  // TODO: Support lowering of NEON and SVE conversions.
-  if (SrcVT.isVector())
-    return SDValue();
-
   // TODO: Saturate to SatWidth explicitly.
   if (SatWidth != DstWidth)
     return SDValue();
 
-  // In the absence of FP16 support, promote f32 to f16, like LowerFP_TO_INT().
+  // In the absence of FP16 support, promote f16 to f32, like LowerFP_TO_INT().
   if (SrcVT == MVT::f16 && !Subtarget->hasFullFP16())
-    return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
+    return DAG.getNode(Op.getOpcode(), SDLoc(Op), DstVT,
                        DAG.getNode(ISD::FP_EXTEND, SDLoc(Op), MVT::f32, SrcVal),
                        Op.getOperand(1));
 
   // Cases that we can emit directly.
   if ((SrcVT == MVT::f64 || SrcVT == MVT::f32 ||
        (SrcVT == MVT::f16 && Subtarget->hasFullFP16())) &&
       (DstVT == MVT::i64 || DstVT == MVT::i32))
     return Op;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))),
           (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
                                         int_aarch64_neon_fcvtxn>;
 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
 
+// AArch64's FCVT instructions saturate when out of range.
+multiclass SIMDTwoVectorFPToIntSatPats<SDNode to_int_sat, string INST> {
+  def : Pat<(v4i16 (to_int_sat v4f16:$Rn, i16)),
+            (!cast<Instruction>(INST # v4f16) v4f16:$Rn)>;
+  def : Pat<(v8i16 (to_int_sat v8f16:$Rn, i16)),
+            (!cast<Instruction>(INST # v8f16) v8f16:$Rn)>;
+  def : Pat<(v2i32 (to_int_sat v2f32:$Rn, i32)),
+            (!cast<Instruction>(INST # v2f32) v2f32:$Rn)>;
+  def : Pat<(v4i32 (to_int_sat v4f32:$Rn, i32)),
+            (!cast<Instruction>(INST # v4f32) v4f32:$Rn)>;
+  def : Pat<(v2i64 (to_int_sat v2f64:$Rn, i64)),
+            (!cast<Instruction>(INST # v2f64) v2f64:$Rn)>;
+}
+defm : SIMDTwoVectorFPToIntSatPats<fp_to_sint_sat, "FCVTZS">;
+defm : SIMDTwoVectorFPToIntSatPats<fp_to_uint_sat, "FCVTZU">;
+
 def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>;
 def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>;
 def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>;
 def : Pat<(v4i32 (int_aarch64_neon_fcvtzs v4f32:$Rn)), (FCVTZSv4f32 $Rn)>;
 def : Pat<(v2i64 (int_aarch64_neon_fcvtzs v2f64:$Rn)), (FCVTZSv2f64 $Rn)>;
 
 def : Pat<(v4i16 (int_aarch64_neon_fcvtzu v4f16:$Rn)), (FCVTZUv4f16 $Rn)>;
 def : Pat<(v8i16 (int_aarch64_neon_fcvtzu v8f16:$Rn)), (FCVTZUv8f16 $Rn)>;

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
 
   EVT SrcTy = TLI->getValueType(DL, Src);
   EVT DstTy = TLI->getValueType(DL, Dst);
 
   if (!SrcTy.isSimple() || !DstTy.isSimple())
     return AdjustCost(
         BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I));
 
   static const TypeConversionCostTblEntry
   ConversionTbl[] = {
     { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32,  1 },
     { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64,  0 },
     { ISD::TRUNCATE, MVT::v8i8,  MVT::v8i32,  3 },
     { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
 
     // Truncations on nxvmiN
     { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i16, 1 },
ConversionTbl[] = {
     // LowerVectorFP_TO_INT
     { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
     { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
     { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
     { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
     { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
     { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
 
+    // LowerVectorFP_TO_INT_SAT
+    { ISD::FP_TO_SINT_SAT, MVT::v2i32, MVT::v2f32, 1 },
+    { ISD::FP_TO_SINT_SAT, MVT::v4i32, MVT::v4f32, 1 },
+    { ISD::FP_TO_SINT_SAT, MVT::v2i64, MVT::v2f64, 1 },
+    { ISD::FP_TO_UINT_SAT, MVT::v2i32, MVT::v2f32, 1 },
+    { ISD::FP_TO_UINT_SAT, MVT::v4i32, MVT::v4f32, 1 },
+    { ISD::FP_TO_UINT_SAT, MVT::v2i64, MVT::v2f64, 1 },
+
     // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
     { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
     { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
     { ISD::FP_TO_SINT, MVT::v2i8,  MVT::v2f32, 1 },
     { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
     { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
     { ISD::FP_TO_UINT, MVT::v2i8,  MVT::v2f32, 1 },
 

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
 
 ;
 ; Float to signed 32-bit -- Vector size variation
 ;
 
 declare <1 x i32> @llvm.fptosi.sat.v1f32.v1i32 (<1 x float>)
 declare <2 x i32> @llvm.fptosi.sat.v2f32.v2i32 (<2 x float>)
 declare <3 x i32> @llvm.fptosi.sat.v3f32.v3i32 (<3 x float>)
 declare <4 x i32> @llvm.fptosi.sat.v4f32.v4i32 (<4 x float>)
 declare <5 x i32> @llvm.fptosi.sat.v5f32.v5i32 (<5 x float>)
 declare <6 x i32> @llvm.fptosi.sat.v6f32.v6i32 (<6 x float>)
 declare <7 x i32> @llvm.fptosi.sat.v7f32.v7i32 (<7 x float>)
 declare <8 x i32> @llvm.fptosi.sat.v8f32.v8i32 (<8 x float>)
 
 define <1 x i32> @test_signed_v1f32_v1i32(<1 x float> %f) {
 ; CHECK-LABEL: test_signed_v1f32_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptosi.sat.v1f32.v1i32(<1 x float> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_signed_v2f32_v2i32(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_signed_v3f32_v3i32(<3 x float> %f) {
 ; CHECK-LABEL: test_signed_v3f32_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov s2, v0.s[2]
-; CHECK-NEXT:    mov s3, v0.s[3]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcvtzs w9, s2
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptosi.sat.v3f32.v3i32(<3 x float> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_signed_v4f32_v4i32(<4 x float> %f) {
 ; CHECK-LABEL: test_signed_v4f32_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov s2, v0.s[2]
-; CHECK-NEXT:    mov s3, v0.s[3]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcvtzs w9, s2
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) {
 ; CHECK-LABEL: test_signed_v5f32_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzs w0, s0
-; CHECK-NEXT:    fcvtzs w1, s1
-; CHECK-NEXT:    fcvtzs w2, s2
-; CHECK-NEXT:    fcvtzs w3, s3
-; CHECK-NEXT:    fcvtzs w4, s4
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzs v4.4s, v4.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w4, s4
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
 ; CHECK-LABEL: test_signed_v6f32_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzs w8, s4
-; CHECK-NEXT:    fcvtzs w5, s5
-; CHECK-NEXT:    fcvtzs w0, s0
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w5
-; CHECK-NEXT:    fcvtzs w1, s1
-; CHECK-NEXT:    fcvtzs w2, s2
-; CHECK-NEXT:    fcvtzs w3, s3
-; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v4.s[1], v5.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzs v1.4s, v4.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
 ; CHECK-LABEL: test_signed_v7f32_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzs w8, s4
-; CHECK-NEXT:    fcvtzs w9, s5
-; CHECK-NEXT:    fcvtzs w0, s0
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w6, s6
-; CHECK-NEXT:    mov v0.s[1], w9
-; CHECK-NEXT:    mov v0.s[2], w6
-; CHECK-NEXT:    fcvtzs w1, s1
-; CHECK-NEXT:    fcvtzs w2, s2
-; CHECK-NEXT:    fcvtzs w3, s3
-; CHECK-NEXT:    mov w5, v0.s[1]
-; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s6 killed $s6 def $q6
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v4.s[1], v5.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v4.s[2], v6.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzs v1.4s, v4.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    mov w6, v1.s[2]
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) {
 ; CHECK-LABEL: test_signed_v8f32_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov s2, v0.s[1]
-; CHECK-NEXT:    mov s3, v0.s[2]
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    mov s2, v1.s[1]
-; CHECK-NEXT:    fcvtzs w11, s3
-; CHECK-NEXT:    mov s3, v1.s[2]
-; CHECK-NEXT:    fcvtzs w12, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fmov s3, w9
-; CHECK-NEXT:    mov v2.s[1], w10
-; CHECK-NEXT:    mov v3.s[1], w12
-; CHECK-NEXT:    mov s0, v0.s[3]
-; CHECK-NEXT:    mov v2.s[2], w11
-; CHECK-NEXT:    mov s1, v1.s[3]
-; CHECK-NEXT:    mov v3.s[2], w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov v2.s[3], w8
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    mov v3.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v2.16b
-; CHECK-NEXT:    mov v1.16b, v3.16b
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptosi.sat.v8f32.v8i32(<8 x float> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; Double to signed 32-bit -- Vector size variation
 ;

 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptosi.sat.v1f16.v1i32(<1 x half> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_signed_v2f16_v2i32(<2 x half> %f) {
 ; CHECK-LABEL: test_signed_v2f16_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h0, v0.h[1]
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f16.v2i32(<2 x half> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_signed_v3f16_v3i32(<3 x half> %f) {
 ; CHECK-LABEL: test_signed_v3f16_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov v1.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptosi.sat.v3f16.v3i32(<3 x half> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_signed_v4f16_v4i32(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov v1.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_signed_v5f16_v5i32(<5 x half> %f) {
 ; CHECK-LABEL: test_signed_v5f16_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    fcvtzs w0, s1
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w4, s1
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w1, s1
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fcvtzs w2, s1
-; CHECK-NEXT:    fcvtzs w3, s0
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptosi.sat.v5f16.v5i32(<5 x half> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_signed_v6f16_v6i32(<6 x half> %f) {
 ; CHECK-LABEL: test_signed_v6f16_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fcvtzs w0, s2
-; CHECK-NEXT:    fcvt s2, h1
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvtzs w1, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    mov h1, v1.h[1]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzs w2, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzs w5, s1
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v2.s[1], w5
-; CHECK-NEXT:    fcvtzs w3, s0
-; CHECK-NEXT:    fmov w4, s2
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptosi.sat.v6f16.v6i32(<6 x half> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_signed_v7f16_v7i32(<7 x half> %f) {
 ; CHECK-LABEL: test_signed_v7f16_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    fcvtzs w0, s2
-; CHECK-NEXT:    fcvt s2, h1
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    fcvtzs w1, s3
-; CHECK-NEXT:    mov h3, v1.h[1]
-; CHECK-NEXT:    mov h1, v1.h[2]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w2, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzs w6, s1
-; CHECK-NEXT:    mov v2.s[1], w8
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v2.s[2], w6
-; CHECK-NEXT:    fcvtzs w3, s0
-; CHECK-NEXT:    mov w5, v2.s[1]
-; CHECK-NEXT:    fmov w4, s2
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    mov w6, v0.s[2]
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptosi.sat.v7f16.v7i32(<7 x half> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_signed_v8f16_v8i32(<8 x half> %f) {
 ; CHECK-LABEL: test_signed_v8f16_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcvt s1, h3
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    mov h2, v3.h[1]
-; CHECK-NEXT:    fcvtzs w11, s1
-; CHECK-NEXT:    mov h1, v3.h[2]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w12, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    mov h3, v3.h[3]
-; CHECK-NEXT:    mov v1.s[1], w12
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    mov v2.s[1], w10
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    mov v2.s[2], w11
-; CHECK-NEXT:    mov v1.s[3], w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov v2.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fcvtl2 v1.4s, v0.8h
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; 2-Vector float to signed integer -- result size variation
 ;

 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptosi.sat.v2f32.v2i19(<2 x float> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_signed_v2f32_v2i32_duplicate(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzs v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_signed_v2f32_v2i50(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i50:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptosi.sat.v2f64.v2i50(<2 x double> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzs x8, d0
-; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    fcvtzs x8, d1
-; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i100:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call <4 x i13> @llvm.fptosi.sat.v4f16.v4i13(<4 x half> %f)
     ret <4 x i13> %x
 }
 
 define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i16:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-NEXT:    mov w8, #-956301312
 ; CHECK-NEXT:    mov w9, #65024
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    movk w9, #18175, lsl #16
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fmaxnm s5, s2, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fminnm s5, s5, s4
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov h5, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvt s6, h0
-; CHECK-NEXT:    fmaxnm s0, s1, s3
-; CHECK-NEXT:    fminnm s0, s0, s4
-; CHECK-NEXT:    fcvt s5, h5
+; CHECK-NEXT:    mov s1, v0.s[1]
+; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fmov s3, w9
 ; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    fmaxnm s0, s5, s3
+; CHECK-NEXT:    fmaxnm s1, s1, s2
+; CHECK-NEXT:    fmaxnm s4, s0, s2
+; CHECK-NEXT:    fminnm s1, s1, s3
+; CHECK-NEXT:    mov s5, v0.s[2]
+; CHECK-NEXT:    fminnm s4, s4, s3
+; CHECK-NEXT:    fcvtzs w9, s1
+; CHECK-NEXT:    fcvtzs w8, s4
+; CHECK-NEXT:    mov s4, v0.s[3]
+; CHECK-NEXT:    fmaxnm s1, s5, s2
 ; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmaxnm s1, s6, s3
-; CHECK-NEXT:    fminnm s3, s0, s4
+; CHECK-NEXT:    fcmp s0, s0
+; CHECK-NEXT:    fmaxnm s2, s4, s2
+; CHECK-NEXT:    fminnm s1, s1, s3
 ; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fminnm s1, s1, s4
+; CHECK-NEXT:    fminnm s2, s2, s3
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzs w8, s3
+; CHECK-NEXT:    fcvtzs w8, s1
 ; CHECK-NEXT:    fcmp s5, s5
 ; CHECK-NEXT:    mov v0.h[1], w9
-; CHECK-NEXT:    fcvtzs w9, s1
+; CHECK-NEXT:    fcvtzs w9, s2
 ; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s6, s6
+; CHECK-NEXT:    fcmp s4, s4
 ; CHECK-NEXT:    mov v0.h[2], w8
 ; CHECK-NEXT:    csel w8, wzr, w9, vs
 ; CHECK-NEXT:    mov v0.h[3], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <4 x i16> @llvm.fptosi.sat.v4f16.v4i16(<4 x half> %f)
     ret <4 x i16> %x
 }

 ; CHECK-NEXT:    ret
     %x = call <4 x i19> @llvm.fptosi.sat.v4f16.v4i19(<4 x half> %f)
     ret <4 x i19> %x
 }
 
 define <4 x i32> @test_signed_v4f16_v4i32_duplicate(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov v1.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <4 x i50> @test_signed_v4f16_v4i50(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i50:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

 declare <5 x i32> @llvm.fptoui.sat.v5f32.v5i32 (<5 x float>)
 declare <6 x i32> @llvm.fptoui.sat.v6f32.v6i32 (<6 x float>)
 declare <7 x i32> @llvm.fptoui.sat.v7f32.v7i32 (<7 x float>)
 declare <8 x i32> @llvm.fptoui.sat.v8f32.v8i32 (<8 x float>)
 
 define <1 x i32> @test_unsigned_v1f32_v1i32(<1 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v1f32_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptoui.sat.v1f32.v1i32(<1 x float> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_unsigned_v2f32_v2i32(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_unsigned_v3f32_v3i32(<3 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v3f32_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov s2, v0.s[2]
-; CHECK-NEXT:    mov s3, v0.s[3]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptoui.sat.v3f32.v3i32(<3 x float> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_unsigned_v4f32_v4i32(<4 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v4f32_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov s2, v0.s[2]
-; CHECK-NEXT:    mov s3, v0.s[3]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v5f32_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzu w0, s0
-; CHECK-NEXT:    fcvtzu w1, s1
-; CHECK-NEXT:    fcvtzu w2, s2
-; CHECK-NEXT:    fcvtzu w3, s3
-; CHECK-NEXT:    fcvtzu w4, s4
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzu v4.4s, v4.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w4, s4
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v6f32_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzu w8, s4
-; CHECK-NEXT:    fcvtzu w5, s5
-; CHECK-NEXT:    fcvtzu w0, s0
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w5
-; CHECK-NEXT:    fcvtzu w1, s1
-; CHECK-NEXT:    fcvtzu w2, s2
-; CHECK-NEXT:    fcvtzu w3, s3
-; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v4.s[1], v5.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzu v1.4s, v4.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v7f32_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzu w8, s4
-; CHECK-NEXT:    fcvtzu w9, s5
-; CHECK-NEXT:    fcvtzu w0, s0
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w6, s6
-; CHECK-NEXT:    mov v0.s[1], w9
-; CHECK-NEXT:    mov v0.s[2], w6
-; CHECK-NEXT:    fcvtzu w1, s1
-; CHECK-NEXT:    fcvtzu w2, s2
-; CHECK-NEXT:    fcvtzu w3, s3
-; CHECK-NEXT:    mov w5, v0.s[1]
-; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT:    // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT:    // kill: def $s6 killed $s6 def $q6
+; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT:    mov v0.s[1], v1.s[0]
+; CHECK-NEXT:    mov v4.s[1], v5.s[0]
+; CHECK-NEXT:    mov v0.s[2], v2.s[0]
+; CHECK-NEXT:    mov v4.s[2], v6.s[0]
+; CHECK-NEXT:    mov v0.s[3], v3.s[0]
+; CHECK-NEXT:    fcvtzu v1.4s, v4.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v1.s[1]
+; CHECK-NEXT:    mov w6, v1.s[2]
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    mov w2, v0.s[2]
+; CHECK-NEXT:    mov w3, v0.s[3]
+; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v8f32_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov s2, v0.s[1]
-; CHECK-NEXT:    mov s3, v0.s[2]
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcvtzu w10, s2
-; CHECK-NEXT:    mov s2, v1.s[1]
-; CHECK-NEXT:    fcvtzu w11, s3
-; CHECK-NEXT:    mov s3, v1.s[2]
-; CHECK-NEXT:    fcvtzu w12, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    fmov s3, w9
-; CHECK-NEXT:    mov v2.s[1], w10
-; CHECK-NEXT:    mov v3.s[1], w12
-; CHECK-NEXT:    mov s0, v0.s[3]
-; CHECK-NEXT:    mov v2.s[2], w11
-; CHECK-NEXT:    mov s1, v1.s[3]
-; CHECK-NEXT:    mov v3.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov v2.s[3], w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v3.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v2.16b
-; CHECK-NEXT:    mov v1.16b, v3.16b
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptoui.sat.v8f32.v8i32(<8 x float> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; Double to unsigned 32-bit -- Vector size variation
 ;

 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptoui.sat.v1f16.v1i32(<1 x half> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_unsigned_v2f16_v2i32(<2 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v2f16_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h0, v0.h[1]
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f16.v2i32(<2 x half> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_unsigned_v3f16_v3i32(<3 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v3f16_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov v1.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptoui.sat.v3f16.v3i32(<3 x half> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_unsigned_v4f16_v4i32(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov v1.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_unsigned_v5f16_v5i32(<5 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v5f16_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    fcvtzu w0, s1
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w4, s1
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w1, s1
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fcvtzu w2, s1
-; CHECK-NEXT:    fcvtzu w3, s0
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptoui.sat.v5f16.v5i32(<5 x half> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_unsigned_v6f16_v6i32(<6 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v6f16_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fcvtzu w0, s2
-; CHECK-NEXT:    fcvt s2, h1
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvtzu w1, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    mov h1, v1.h[1]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzu w2, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w5, s1
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v2.s[1], w5
-; CHECK-NEXT:    fcvtzu w3, s0
-; CHECK-NEXT:    fmov w4, s2
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_unsigned_v7f16_v7i32(<7 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v7f16_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    fcvtzu w0, s2
-; CHECK-NEXT:    fcvt s2, h1
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    fcvtzu w1, s3
-; CHECK-NEXT:    mov h3, v1.h[1]
-; CHECK-NEXT:    mov h1, v1.h[2]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w2, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzu w6, s1
-; CHECK-NEXT:    mov v2.s[1], w8
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v2.s[2], w6
-; CHECK-NEXT:    fcvtzu w3, s0
-; CHECK-NEXT:    mov w5, v2.s[1]
-; CHECK-NEXT:    fmov w4, s2
+; CHECK-NEXT:    fcvtl v1.4s, v0.4h
+; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    mov w6, v0.s[2]
+; CHECK-NEXT:    mov w1, v1.s[1]
+; CHECK-NEXT:    mov w2, v1.s[2]
+; CHECK-NEXT:    mov w3, v1.s[3]
+; CHECK-NEXT:    fmov w4, s0
+; CHECK-NEXT:    fmov w0, s1
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptoui.sat.v7f16.v7i32(<7 x half> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_unsigned_v8f16_v8i32(<8 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v8f16_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcvt s1, h3
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w10, s2
-; CHECK-NEXT:    mov h2, v3.h[1]
-; CHECK-NEXT:    fcvtzu w11, s1
-; CHECK-NEXT:    mov h1, v3.h[2]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w12, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    mov h3, v3.h[3]
-; CHECK-NEXT:    mov v1.s[1], w12
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    mov v2.s[1], w10
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, s3
-; CHECK-NEXT:    mov v2.s[2], w11
-; CHECK-NEXT:    mov v1.s[3], w8
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov v2.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fcvtl2 v1.4s, v0.8h
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; 2-Vector float to unsigned integer -- result size variation
 ;

 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptoui.sat.v2f32.v2i19(<2 x float> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_unsigned_v2f32_v2i32_duplicate(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_unsigned_v2f32_v2i50(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i50:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptoui.sat.v2f64.v2i50(<2 x double> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvtzu x8, d0
-; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    fcvtzu x8, d1
-; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i100:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call <4 x i13> @llvm.fptoui.sat.v4f16.v4i13(<4 x half> %f)
     ret <4 x i13> %x
 }
 
 define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    mov w8, #65280
-; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    mov h4, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    movi d2, #0000000000000000
 ; CHECK-NEXT:    movk w8, #18303, lsl #16
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmaxnm s1, s1, s2
-; CHECK-NEXT:    fmaxnm s3, s3, s2
-; CHECK-NEXT:    fmaxnm s4, s4, s2
-; CHECK-NEXT:    fmaxnm s0, s0, s2
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fminnm s1, s1, s2
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fminnm s1, s3, s2
-; CHECK-NEXT:    fminnm s3, s4, s2
-; CHECK-NEXT:    fminnm s2, s0, s2
+; CHECK-NEXT:    fmaxnm s2, s0, s1
+; CHECK-NEXT:    mov s3, v0.s[1]
+; CHECK-NEXT:    mov s4, v0.s[2]
+; CHECK-NEXT:    mov s0, v0.s[3]
+; CHECK-NEXT:    fmaxnm s3, s3, s1
+; CHECK-NEXT:    fmaxnm s4, s4, s1
+; CHECK-NEXT:    fmaxnm s0, s0, s1
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fminnm s2, s2, s1
+; CHECK-NEXT:    fcvtzu w8, s2
+; CHECK-NEXT:    fminnm s2, s3, s1
+; CHECK-NEXT:    fminnm s3, s4, s1
+; CHECK-NEXT:    fminnm s1, s0, s1
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, s1
+; CHECK-NEXT:    fcvtzu w8, s2
 ; CHECK-NEXT:    mov v0.h[1], w8
 ; CHECK-NEXT:    fcvtzu w8, s3
 ; CHECK-NEXT:    mov v0.h[2], w8
-; CHECK-NEXT:    fcvtzu w8, s2
+; CHECK-NEXT:    fcvtzu w8, s1
 ; CHECK-NEXT:    mov v0.h[3], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <4 x i16> @llvm.fptoui.sat.v4f16.v4i16(<4 x half> %f)
     ret <4 x i16> %x
 }
 
 define <4 x i19> @test_unsigned_v4f16_v4i19(<4 x half> %f) {

 ; CHECK-NEXT:    ret
     %x = call <4 x i19> @llvm.fptoui.sat.v4f16.v4i19(<4 x half> %f)
     ret <4 x i19> %x
 }
 
 define <4 x i32> @test_unsigned_v4f16_v4i32_duplicate(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov h2, v0.h[1]
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    mov v1.s[3], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <4 x i50> @test_unsigned_v4f16_v4i50(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i50:
 ; CHECK:       // %bb.0: