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Differential D108378

[ARM] Add patterns for store(fptosisat(..))
ClosedPublic

Authored by dmgreen on Aug 19 2021, 8:05 AM.

Details

Reviewers
samtebbs
SjoerdMeijer
NickGuy
ostannard
simon_tatham
Commits
rGadfd12e6d17c: [ARM] Add patterns for store(fptosisat(..))
Summary

As an extension to D107866, this adds store(fptosisat(..)) patterns, similar to the existing fptosi patterns, to prevent unnecessarily moving into gpr regs where we can use fp stores directly.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 19 2021, 8:05 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptAug 19 2021, 8:05 AM
dmgreen requested review of this revision.Aug 19 2021, 8:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 19 2021, 8:05 AM
dmgreen added a parent revision: D107866: [ARM] Add VFP lowering for fptosi.sat.Aug 19 2021, 8:05 AM
Harbormaster completed remote builds in B120337: Diff 367499.Aug 19 2021, 8:05 AM
samtebbs accepted this revision.Aug 31 2021, 8:50 AM

LGTM. Sorry for the delay on this one.

This revision is now accepted and ready to land.Aug 31 2021, 8:50 AM
dmgreen added a comment.Sep 1 2021, 5:30 AM
In D108378#2974801, @samtebbs wrote:

LGTM. Sorry for the delay on this one.

Thanks. There is another dependent patch in D107865 that would need review before this one can land.

This revision was landed with ongoing or failed builds.Sep 3 2021, 11:22 AM
Closed by commit rGadfd12e6d17c: [ARM] Add patterns for store(fptosisat(..)) (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rGadfd12e6d17c: [ARM] Add patterns for store(fptosisat(..)).

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
10 lines
test/
CodeGen/
ARM/
18 lines
Thumb2/
32 lines
32 lines

Diff 370631

llvm/lib/Target/ARM/ARMInstrVFP.td

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let Predicates=[HasVFP2, HasDPVFP] in { let Predicates=[HasVFP2, HasDPVFP] in {
def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))), def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))),
(COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
def : VFPPat<(i32 (fp_to_sint_sat (f64 DPR:$a), i32)), def : VFPPat<(i32 (fp_to_sint_sat (f64 DPR:$a), i32)),
(COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>;
def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr), def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr),
(VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f64 DPR:$a), i32)), addrmode5:$ptr),
(VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>;
} }
def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
(outs SPR:$Sd), (ins SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sm),
IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
[]>, []>,
Sched<[WriteFPCVT]> { Sched<[WriteFPCVT]> {
let Inst{7} = 1; // Z bit let Inst{7} = 1; // Z bit
// Some single precision VFP instructions may be executed on both NEON and // Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8. // VFP pipelines on A8.
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
} }
def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)), def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
(COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
def : VFPPat<(i32 (fp_to_sint_sat SPR:$a, i32)), def : VFPPat<(i32 (fp_to_sint_sat SPR:$a, i32)),
(COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))), def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
addrmode5:$ptr), addrmode5:$ptr),
(VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f32 SPR:$a), i32)),
addrmode5:$ptr),
(VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
(outs SPR:$Sd), (ins HPR:$Sm), (outs SPR:$Sd), (ins HPR:$Sm),
IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm", IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
[]>, []>,
Sched<[WriteFPCVT]> { Sched<[WriteFPCVT]> {
let Inst{7} = 1; // Z bit let Inst{7} = 1; // Z bit
let isUnpredicable = 1; let isUnpredicable = 1;
Show All 15 Lines
let Predicates=[HasVFP2, HasDPVFP] in { let Predicates=[HasVFP2, HasDPVFP] in {
def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))), def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))),
(COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
def : VFPPat<(i32 (fp_to_uint_sat (f64 DPR:$a), i32)), def : VFPPat<(i32 (fp_to_uint_sat (f64 DPR:$a), i32)),
(COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>;
def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr), def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr),
(VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f64 DPR:$a), i32)), addrmode5:$ptr),
(VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>;
} }
def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
(outs SPR:$Sd), (ins SPR:$Sm), (outs SPR:$Sd), (ins SPR:$Sm),
IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
[]>, []>,
Sched<[WriteFPCVT]> { Sched<[WriteFPCVT]> {
let Inst{7} = 1; // Z bit let Inst{7} = 1; // Z bit
// Some single precision VFP instructions may be executed on both NEON and // Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8. // VFP pipelines on A8.
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
} }
def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)), def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
(COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
def : VFPPat<(i32 (fp_to_uint_sat SPR:$a, i32)), def : VFPPat<(i32 (fp_to_uint_sat SPR:$a, i32)),
(COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))), def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
addrmode5:$ptr), addrmode5:$ptr),
(VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f32 SPR:$a), i32)),
addrmode5:$ptr),
(VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
(outs SPR:$Sd), (ins HPR:$Sm), (outs SPR:$Sd), (ins HPR:$Sm),
IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm", IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
[]>, []>,
Sched<[WriteFPCVT]> { Sched<[WriteFPCVT]> {
let Inst{7} = 1; // Z bit let Inst{7} = 1; // Z bit
let isUnpredicable = 1; let isUnpredicable = 1;
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llvm/test/CodeGen/ARM/fptoi-sat-store.ll

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; SOFT-NEXT: .long 1325400063 @ 0x4effffff ; SOFT-NEXT: .long 1325400063 @ 0x4effffff
; SOFT-NEXT: .LCPI0_1: ; SOFT-NEXT: .LCPI0_1:
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP-LABEL: test_signed_i32_f32: ; VFP-LABEL: test_signed_i32_f32:
; VFP: @ %bb.0: ; VFP: @ %bb.0:
; VFP-NEXT: vmov s0, r1 ; VFP-NEXT: vmov s0, r1
; VFP-NEXT: vcvt.s32.f32 s0, s0 ; VFP-NEXT: vcvt.s32.f32 s0, s0
; VFP-NEXT: vmov r1, s0 ; VFP-NEXT: vstr s0, [r0]
; VFP-NEXT: str r1, [r0]
; VFP-NEXT: bx lr ; VFP-NEXT: bx lr
%r = call i32 @llvm.fptosi.sat.i32.f32(float %f) %r = call i32 @llvm.fptosi.sat.i32.f32(float %f)
store i32 %r, i32* %d, align 4 store i32 %r, i32* %d, align 4
ret void ret void
} }
define void @test_signed_i32_f64(i32* %d, double %f) nounwind { define void @test_signed_i32_f64(i32* %d, double %f) nounwind {
; SOFT-LABEL: test_signed_i32_f64: ; SOFT-LABEL: test_signed_i32_f64:
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; SOFT-NEXT: .long 3252682752 @ 0xc1e00000 ; SOFT-NEXT: .long 3252682752 @ 0xc1e00000
; SOFT-NEXT: .LCPI1_3: ; SOFT-NEXT: .LCPI1_3:
; SOFT-NEXT: .long 2147483647 @ 0x7fffffff ; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
; ;
; VFP2-LABEL: test_signed_i32_f64: ; VFP2-LABEL: test_signed_i32_f64:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: vmov d16, r2, r3 ; VFP2-NEXT: vmov d16, r2, r3
; VFP2-NEXT: vcvt.s32.f64 s0, d16 ; VFP2-NEXT: vcvt.s32.f64 s0, d16
; VFP2-NEXT: vmov r1, s0 ; VFP2-NEXT: vstr s0, [r0]
; VFP2-NEXT: str r1, [r0]
; VFP2-NEXT: bx lr ; VFP2-NEXT: bx lr
; ;
; FP16-LABEL: test_signed_i32_f64: ; FP16-LABEL: test_signed_i32_f64:
; FP16: @ %bb.0: ; FP16: @ %bb.0:
; FP16-NEXT: vmov d0, r2, r3 ; FP16-NEXT: vmov d0, r2, r3
; FP16-NEXT: vcvt.s32.f64 s0, d0 ; FP16-NEXT: vcvt.s32.f64 s0, d0
; FP16-NEXT: vmov r1, s0 ; FP16-NEXT: vstr s0, [r0]
; FP16-NEXT: str r1, [r0]
; FP16-NEXT: bx lr ; FP16-NEXT: bx lr
%r = call i32 @llvm.fptosi.sat.i32.f64(double %f) %r = call i32 @llvm.fptosi.sat.i32.f64(double %f)
store i32 %r, i32* %d, align 4 store i32 %r, i32* %d, align 4
ret void ret void
} }
define void @test_unsigned_i32_f32(i32* %d, float %f) nounwind { define void @test_unsigned_i32_f32(i32* %d, float %f) nounwind {
; SOFT-LABEL: test_unsigned_i32_f32: ; SOFT-LABEL: test_unsigned_i32_f32:
Show All 33 Lines
; SOFT-NEXT: @ %bb.5: ; SOFT-NEXT: @ %bb.5:
; SOFT-NEXT: .LCPI2_0: ; SOFT-NEXT: .LCPI2_0:
; SOFT-NEXT: .long 1333788671 @ 0x4f7fffff ; SOFT-NEXT: .long 1333788671 @ 0x4f7fffff
; ;
; VFP-LABEL: test_unsigned_i32_f32: ; VFP-LABEL: test_unsigned_i32_f32:
; VFP: @ %bb.0: ; VFP: @ %bb.0:
; VFP-NEXT: vmov s0, r1 ; VFP-NEXT: vmov s0, r1
; VFP-NEXT: vcvt.u32.f32 s0, s0 ; VFP-NEXT: vcvt.u32.f32 s0, s0
; VFP-NEXT: vmov r1, s0 ; VFP-NEXT: vstr s0, [r0]
; VFP-NEXT: str r1, [r0]
; VFP-NEXT: bx lr ; VFP-NEXT: bx lr
%r = call i32 @llvm.fptoui.sat.i32.f32(float %f) %r = call i32 @llvm.fptoui.sat.i32.f32(float %f)
store i32 %r, i32* %d, align 4 store i32 %r, i32* %d, align 4
ret void ret void
} }
define void @test_unsigned_i32_f64(i32* %d, double %f) nounwind { define void @test_unsigned_i32_f64(i32* %d, double %f) nounwind {
; SOFT-LABEL: test_unsigned_i32_f64: ; SOFT-LABEL: test_unsigned_i32_f64:
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; SOFT-NEXT: .long 4292870144 @ 0xffe00000 ; SOFT-NEXT: .long 4292870144 @ 0xffe00000
; SOFT-NEXT: .LCPI3_1: ; SOFT-NEXT: .LCPI3_1:
; SOFT-NEXT: .long 1106247679 @ 0x41efffff ; SOFT-NEXT: .long 1106247679 @ 0x41efffff
; ;
; VFP2-LABEL: test_unsigned_i32_f64: ; VFP2-LABEL: test_unsigned_i32_f64:
; VFP2: @ %bb.0: ; VFP2: @ %bb.0:
; VFP2-NEXT: vmov d16, r2, r3 ; VFP2-NEXT: vmov d16, r2, r3
; VFP2-NEXT: vcvt.u32.f64 s0, d16 ; VFP2-NEXT: vcvt.u32.f64 s0, d16
; VFP2-NEXT: vmov r1, s0 ; VFP2-NEXT: vstr s0, [r0]
; VFP2-NEXT: str r1, [r0]
; VFP2-NEXT: bx lr ; VFP2-NEXT: bx lr
; ;
; FP16-LABEL: test_unsigned_i32_f64: ; FP16-LABEL: test_unsigned_i32_f64:
; FP16: @ %bb.0: ; FP16: @ %bb.0:
; FP16-NEXT: vmov d0, r2, r3 ; FP16-NEXT: vmov d0, r2, r3
; FP16-NEXT: vcvt.u32.f64 s0, d0 ; FP16-NEXT: vcvt.u32.f64 s0, d0
; FP16-NEXT: vmov r1, s0 ; FP16-NEXT: vstr s0, [r0]
; FP16-NEXT: str r1, [r0]
; FP16-NEXT: bx lr ; FP16-NEXT: bx lr
%r = call i32 @llvm.fptoui.sat.i32.f64(double %f) %r = call i32 @llvm.fptoui.sat.i32.f64(double %f)
store i32 %r, i32* %d, align 4 store i32 %r, i32* %d, align 4
ret void ret void
} }

llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll

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; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f) %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define arm_aapcs_vfpcc <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) { define arm_aapcs_vfpcc <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) {
; CHECK-MVE-LABEL: test_signed_v5f32_v5i32: ; CHECK-MVE-LABEL: test_signed_v5f32_v5i32:
; CHECK-MVE: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s3
; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s1
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-MVE-NEXT: vmov r2, s0
; CHECK-MVE-NEXT: str r1, [r0, #16]
; CHECK-MVE-NEXT: vmov r1, s2 ; CHECK-MVE-NEXT: vmov r1, s2
; CHECK-MVE-NEXT: vmov r2, s0
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmov r2, s8 ; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
; CHECK-MVE-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-MVE-NEXT: vstr s4, [r0, #16]
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: test_signed_v5f32_v5i32: ; CHECK-MVEFP-LABEL: test_signed_v5f32_v5i32:
; CHECK-MVEFP: @ %bb.0: ; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov r1, s4 ; CHECK-MVEFP-NEXT: vmov r1, s4
; CHECK-MVEFP-NEXT: str r1, [r0, #16] ; CHECK-MVEFP-NEXT: str r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0] ; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
%x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f) %x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f)
ret <5 x i32> %x ret <5 x i32> %x
} }
define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) { define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
; CHECK-MVE-LABEL: test_signed_v6f32_v6i32: ; CHECK-MVE-LABEL: test_signed_v6f32_v6i32:
; CHECK-MVE: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s5
; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3
; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s1
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s5
; CHECK-MVE-NEXT: vmov r2, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-MVE-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVE-NEXT: vmov r1, s2 ; CHECK-MVE-NEXT: vmov r1, s2
; CHECK-MVE-NEXT: vmov r2, s0 ; CHECK-MVE-NEXT: vmov r2, s0
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vmov r1, s8
; CHECK-MVE-NEXT: vmov r2, s10 ; CHECK-MVE-NEXT: vmov r2, s10
; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
; CHECK-MVE-NEXT: vstr s6, [r0, #20]
; CHECK-MVE-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-MVE-NEXT: vstr s4, [r0, #16]
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: test_signed_v6f32_v6i32: ; CHECK-MVEFP-LABEL: test_signed_v6f32_v6i32:
; CHECK-MVEFP: @ %bb.0: ; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s6, s5 ; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
; CHECK-MVEFP-NEXT: vmov r2, s4 ; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r1, s6 ; CHECK-MVEFP-NEXT: vmov r1, s6
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16] ; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0] ; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
%x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f) %x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x ret <6 x i32> %x
} }
define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) { define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
; CHECK-MVE-LABEL: test_signed_v7f32_v7i32: ; CHECK-MVE-LABEL: test_signed_v7f32_v7i32:
; CHECK-MVE: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s5
; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s3
; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s1
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s5
; CHECK-MVE-NEXT: vmov r2, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-MVE-NEXT: vmov r3, s6 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
; CHECK-MVE-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVE-NEXT: vmov r1, s2 ; CHECK-MVE-NEXT: vmov r1, s2
; CHECK-MVE-NEXT: vmov r2, s0 ; CHECK-MVE-NEXT: vmov r2, s0
; CHECK-MVE-NEXT: str r3, [r0, #24]
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
; CHECK-MVE-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
; CHECK-MVE-NEXT: vstr s8, [r0, #20]
; CHECK-MVE-NEXT: vstr s4, [r0, #16]
; CHECK-MVE-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-MVE-NEXT: vstr s6, [r0, #24]
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: test_signed_v7f32_v7i32: ; CHECK-MVEFP-LABEL: test_signed_v7f32_v7i32:
; CHECK-MVEFP: @ %bb.0: ; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s10, s5 ; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
; CHECK-MVEFP-NEXT: vmov r2, s4 ; CHECK-MVEFP-NEXT: vmov r2, s4
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llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll

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; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f) %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define arm_aapcs_vfpcc <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) { define arm_aapcs_vfpcc <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) {
; CHECK-MVE-LABEL: test_unsigned_v5f32_v5i32: ; CHECK-MVE-LABEL: test_unsigned_v5f32_v5i32:
; CHECK-MVE: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2
; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s3
; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s1
; CHECK-MVE-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-MVE-NEXT: vmov r2, s0
; CHECK-MVE-NEXT: str r1, [r0, #16]
; CHECK-MVE-NEXT: vmov r1, s2 ; CHECK-MVE-NEXT: vmov r1, s2
; CHECK-MVE-NEXT: vmov r2, s0
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmov r2, s8 ; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
; CHECK-MVE-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-MVE-NEXT: vstr s4, [r0, #16]
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: test_unsigned_v5f32_v5i32: ; CHECK-MVEFP-LABEL: test_unsigned_v5f32_v5i32:
; CHECK-MVEFP: @ %bb.0: ; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1 ; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov r1, s4 ; CHECK-MVEFP-NEXT: vmov r1, s4
; CHECK-MVEFP-NEXT: str r1, [r0, #16] ; CHECK-MVEFP-NEXT: str r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0] ; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
%x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f) %x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f)
ret <5 x i32> %x ret <5 x i32> %x
} }
define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) { define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
; CHECK-MVE-LABEL: test_unsigned_v6f32_v6i32: ; CHECK-MVE-LABEL: test_unsigned_v6f32_v6i32:
; CHECK-MVE: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s5
; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2
; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s3
; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s1
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s5
; CHECK-MVE-NEXT: vmov r2, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-MVE-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVE-NEXT: vmov r1, s2 ; CHECK-MVE-NEXT: vmov r1, s2
; CHECK-MVE-NEXT: vmov r2, s0 ; CHECK-MVE-NEXT: vmov r2, s0
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vmov r1, s8
; CHECK-MVE-NEXT: vmov r2, s10 ; CHECK-MVE-NEXT: vmov r2, s10
; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
; CHECK-MVE-NEXT: vstr s6, [r0, #20]
; CHECK-MVE-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-MVE-NEXT: vstr s4, [r0, #16]
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: test_unsigned_v6f32_v6i32: ; CHECK-MVEFP-LABEL: test_unsigned_v6f32_v6i32:
; CHECK-MVEFP: @ %bb.0: ; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1 ; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s6, s5 ; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
; CHECK-MVEFP-NEXT: vmov r2, s4 ; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r1, s6 ; CHECK-MVEFP-NEXT: vmov r1, s6
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16] ; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0] ; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
%x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f) %x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x ret <6 x i32> %x
} }
define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) { define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
; CHECK-MVE-LABEL: test_unsigned_v7f32_v7i32: ; CHECK-MVE-LABEL: test_unsigned_v7f32_v7i32:
; CHECK-MVE: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s5
; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s6
; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2
; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s3
; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s1
; CHECK-MVE-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s5
; CHECK-MVE-NEXT: vmov r2, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-MVE-NEXT: vmov r3, s6 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s6
; CHECK-MVE-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVE-NEXT: vmov r1, s2 ; CHECK-MVE-NEXT: vmov r1, s2
; CHECK-MVE-NEXT: vmov r2, s0 ; CHECK-MVE-NEXT: vmov r2, s0
; CHECK-MVE-NEXT: str r3, [r0, #24]
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r2, r1
; CHECK-MVE-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r1
; CHECK-MVE-NEXT: vstr s8, [r0, #20]
; CHECK-MVE-NEXT: vstr s4, [r0, #16]
; CHECK-MVE-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-MVE-NEXT: vstr s6, [r0, #24]
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: test_unsigned_v7f32_v7i32: ; CHECK-MVEFP-LABEL: test_unsigned_v7f32_v7i32:
; CHECK-MVEFP: @ %bb.0: ; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1 ; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s10, s5 ; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
; CHECK-MVEFP-NEXT: vmov r2, s4 ; CHECK-MVEFP-NEXT: vmov r2, s4
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