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Differential D107865

[ARM] Add MVE lowering for fptosi.sat
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Authored by dmgreen on Aug 10 2021, 1:05 PM.

Details

Reviewers
samtebbs
SjoerdMeijer
ostannard
NickGuy
simon_tatham
Commits
rG49476a4d66b3: [ARM] Add MVE lowering for fptosi.sat
Summary

This adds lowering of the llvm.fptosi.sat and llvm.fptoui.sat intinsics, selecting a VCVT instruction which under MVE will inherently perform the saturate.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 10 2021, 1:05 PM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptAug 10 2021, 1:05 PM
dmgreen requested review of this revision.Aug 10 2021, 1:05 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2021, 1:05 PM
Harbormaster completed remote builds in B118965: Diff 365592.Aug 10 2021, 1:06 PM
dmgreen mentioned this in D107866: [ARM] Add VFP lowering for fptosi.sat.Aug 10 2021, 1:10 PM
dmgreen added a child revision: D107866: [ARM] Add VFP lowering for fptosi.sat.
dmgreen mentioned this in D108378: [ARM] Add patterns for store(fptosisat(..)).Sep 1 2021, 5:30 AM
samtebbs accepted this revision.Sep 1 2021, 9:08 AM

Very nice

This revision is now accepted and ready to land.Sep 1 2021, 9:08 AM
This revision was landed with ongoing or failed builds.Sep 1 2021, 2:39 PM
Closed by commit rG49476a4d66b3: [ARM] Add MVE lowering for fptosi.sat (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG49476a4d66b3: [ARM] Add MVE lowering for fptosi.sat.
dmgreen mentioned this in rGf37e132263e4: [ARM] Add VFP lowering for fptosi.sat.Sep 3 2021, 10:11 AM

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
31 lines
11 lines
test/
CodeGen/
Thumb2/
2461 lines
1621 lines

Diff 370068

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 295 Lines • ▼ Show 20 Lines for (auto VT : IntTypes) {
setOperationAction(ISD::VECREDUCE_OR, VT, Custom); setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
if (!HasMVEFP) { if (!HasMVEFP) {
setOperationAction(ISD::SINT_TO_FP, VT, Expand); setOperationAction(ISD::SINT_TO_FP, VT, Expand);
setOperationAction(ISD::UINT_TO_FP, VT, Expand); setOperationAction(ISD::UINT_TO_FP, VT, Expand);
setOperationAction(ISD::FP_TO_SINT, VT, Expand); setOperationAction(ISD::FP_TO_SINT, VT, Expand);
setOperationAction(ISD::FP_TO_UINT, VT, Expand); setOperationAction(ISD::FP_TO_UINT, VT, Expand);
} else {
setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
} }
// Pre and Post inc are supported on loads and stores // Pre and Post inc are supported on loads and stores
for (unsigned im = (unsigned)ISD::PRE_INC; for (unsigned im = (unsigned)ISD::PRE_INC;
im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
setIndexedLoadAction(im, VT, Legal); setIndexedLoadAction(im, VT, Legal);
setIndexedStoreAction(im, VT, Legal); setIndexedStoreAction(im, VT, Legal);
setIndexedMaskedLoadAction(im, VT, Legal); setIndexedMaskedLoadAction(im, VT, Legal);
▲ Show 20 Lines • Show All 5,504 Lines • ▼ Show 20 Lines SDValue Result =
: ISD::FP_TO_UINT, : ISD::FP_TO_UINT,
Loc, Op.getValueType(), SrcVal); Loc, Op.getValueType(), SrcVal);
return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc); return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
} }
return Op; return Op;
} }
static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
EVT ToVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
EVT FromVT = Op.getOperand(0).getValueType();
if (VT == MVT::v4i32 && ToVT == MVT::i32 && FromVT == MVT::v4f32)
return Op;
if (VT == MVT::v8i16 && ToVT == MVT::i16 && FromVT == MVT::v8f16)
return Op;
if (FromVT != MVT::v4f32 && FromVT != MVT::v8f16)
return SDValue();
SDLoc DL(Op);
bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
unsigned BW = ToVT.getScalarSizeInBits() - IsSigned;
SDValue CVT = DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
DAG.getValueType(VT.getScalarType()));
SDValue Max = DAG.getNode(IsSigned ? ISD::SMIN : ISD::UMIN, DL, VT, CVT,
DAG.getConstant((1 << BW) - 1, DL, VT));
if (IsSigned)
Max = DAG.getNode(ISD::SMAX, DL, VT, Max,
DAG.getConstant(-(1 << BW), DL, VT));
return Max;
}
static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDLoc dl(Op); SDLoc dl(Op);
if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) { if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
if (VT.getVectorElementType() == MVT::f32) if (VT.getVectorElementType() == MVT::f32)
return Op; return Op;
return DAG.UnrollVectorOp(Op.getNode()); return DAG.UnrollVectorOp(Op.getNode());
▲ Show 20 Lines • Show All 4,327 Lines • ▼ Show 20 LinesSDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
case ISD::SINT_TO_FP: case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
case ISD::STRICT_FP_TO_SINT: case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT: case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT: case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT: return LowerFP_TO_INT_SAT(Op, DAG);
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG); case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG, Subtarget); case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG, Subtarget);
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
▲ Show 20 Lines • Show All 10,855 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,043 Lines • ▼ Show 20 Lines
defm MVE_VCVTs32f32z : MVE_VCVT_fp_int_m<MVE_v4s32, MVE_v4f32, fp_to_sint>; defm MVE_VCVTs32f32z : MVE_VCVT_fp_int_m<MVE_v4s32, MVE_v4f32, fp_to_sint>;
defm MVE_VCVTu32f32z : MVE_VCVT_fp_int_m<MVE_v4u32, MVE_v4f32, fp_to_uint>; defm MVE_VCVTu32f32z : MVE_VCVT_fp_int_m<MVE_v4u32, MVE_v4f32, fp_to_uint>;
// Whereas VCVT for int->float rounds to nearest // Whereas VCVT for int->float rounds to nearest
defm MVE_VCVTf16s16n : MVE_VCVT_fp_int_m<MVE_v8f16, MVE_v8s16, sint_to_fp>; defm MVE_VCVTf16s16n : MVE_VCVT_fp_int_m<MVE_v8f16, MVE_v8s16, sint_to_fp>;
defm MVE_VCVTf16u16n : MVE_VCVT_fp_int_m<MVE_v8f16, MVE_v8u16, uint_to_fp>; defm MVE_VCVTf16u16n : MVE_VCVT_fp_int_m<MVE_v8f16, MVE_v8u16, uint_to_fp>;
defm MVE_VCVTf32s32n : MVE_VCVT_fp_int_m<MVE_v4f32, MVE_v4s32, sint_to_fp>; defm MVE_VCVTf32s32n : MVE_VCVT_fp_int_m<MVE_v4f32, MVE_v4s32, sint_to_fp>;
defm MVE_VCVTf32u32n : MVE_VCVT_fp_int_m<MVE_v4f32, MVE_v4u32, uint_to_fp>; defm MVE_VCVTf32u32n : MVE_VCVT_fp_int_m<MVE_v4f32, MVE_v4u32, uint_to_fp>;
let Predicates = [HasMVEFloat] in {
def : Pat<(v4i32 (fp_to_sint_sat v4f32:$src, i32)),
(MVE_VCVTs32f32z v4f32:$src)>;
def : Pat<(v4i32 (fp_to_uint_sat v4f32:$src, i32)),
(MVE_VCVTu32f32z v4f32:$src)>;
def : Pat<(v8i16 (fp_to_sint_sat v8f16:$src, i16)),
(MVE_VCVTs16f16z v8f16:$src)>;
def : Pat<(v8i16 (fp_to_uint_sat v8f16:$src, i16)),
(MVE_VCVTu16f16z v8f16:$src)>;
}
class MVE_VABSNEG_fp<string iname, string suffix, bits<2> size, bit negate, class MVE_VABSNEG_fp<string iname, string suffix, bits<2> size, bit negate,
list<dag> pattern=[]> list<dag> pattern=[]>
: MVE_float<iname, suffix, (outs MQPR:$Qd), : MVE_float<iname, suffix, (outs MQPR:$Qd),
(ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> { (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
bits<4> Qd; bits<4> Qd;
let Inst{28} = 0b1; let Inst{28} = 0b1;
let Inst{25-23} = 0b111; let Inst{25-23} = 0b111;
▲ Show 20 Lines • Show All 3,411 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP
; ;
; Float to signed 32-bit -- Vector size variation ; Float to signed 32-bit -- Vector size variation
; ;
declare <1 x i32> @llvm.fptosi.sat.v1f32.v1i32 (<1 x float>) declare <1 x i32> @llvm.fptosi.sat.v1f32.v1i32 (<1 x float>)
declare <2 x i32> @llvm.fptosi.sat.v2f32.v2i32 (<2 x float>) declare <2 x i32> @llvm.fptosi.sat.v2f32.v2i32 (<2 x float>)
declare <3 x i32> @llvm.fptosi.sat.v3f32.v3i32 (<3 x float>) declare <3 x i32> @llvm.fptosi.sat.v3f32.v3i32 (<3 x float>)
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9
; CHECK-NEXT: .LCPI1_1: ; CHECK-NEXT: .LCPI1_1:
; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 ; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9
%x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f) %x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define arm_aapcs_vfpcc <3 x i32> @test_signed_v3f32_v3i32(<3 x float> %f) { define arm_aapcs_vfpcc <3 x i32> @test_signed_v3f32_v3i32(<3 x float> %f) {
; CHECK-LABEL: test_signed_v3f32_v3i32: ; CHECK-MVE-LABEL: test_signed_v3f32_v3i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.s32.f32 s12, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s2
; CHECK-NEXT: vldr s6, .LCPI2_0 ; CHECK-MVE-NEXT: vldr s6, .LCPI2_0
; CHECK-NEXT: vcvt.s32.f32 s14, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s0
; CHECK-NEXT: vldr s10, .LCPI2_1 ; CHECK-MVE-NEXT: vldr s10, .LCPI2_1
; CHECK-NEXT: vcvt.s32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3
; CHECK-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s10 ; CHECK-MVE-NEXT: vcmp.f32 s2, s10
; CHECK-NEXT: vcvt.s32.f32 s4, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s1
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r0, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r0, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r0, #-2147483648 ; CHECK-MVE-NEXT: mvngt r0, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, s6 ; CHECK-MVE-NEXT: vcmp.f32 s0, s6
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-NEXT: vcmp.f32 s0, s10 ; CHECK-MVE-NEXT: vcmp.f32 s0, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s6 ; CHECK-MVE-NEXT: vcmp.f32 s3, s6
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s8 ; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-NEXT: vcmp.f32 s3, s10 ; CHECK-MVE-NEXT: vcmp.f32 s3, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r2, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r2, #-2147483648 ; CHECK-MVE-NEXT: mvngt r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s4 ; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vcmp.f32 s1, s6 ; CHECK-MVE-NEXT: vcmp.f32 s1, s6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r3, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r3, #-2147483648
; CHECK-NEXT: vcmp.f32 s1, s10 ; CHECK-MVE-NEXT: vcmp.f32 s1, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r3, #-2147483648 ; CHECK-MVE-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI2_0: ; CHECK-MVE-NEXT: .LCPI2_0:
; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-MVE-NEXT: .long 0xcf000000 @ float -2.14748365E+9
; CHECK-NEXT: .LCPI2_1: ; CHECK-MVE-NEXT: .LCPI2_1:
; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 ; CHECK-MVE-NEXT: .long 0x4effffff @ float 2.14748352E+9
;
; CHECK-MVEFP-LABEL: test_signed_v3f32_v3i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <3 x i32> @llvm.fptosi.sat.v3f32.v3i32(<3 x float> %f) %x = call <3 x i32> @llvm.fptosi.sat.v3f32.v3i32(<3 x float> %f)
ret <3 x i32> %x ret <3 x i32> %x
} }
define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f32_v4i32(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f32_v4i32(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i32: ; CHECK-MVE-LABEL: test_signed_v4f32_v4i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.s32.f32 s12, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s2
; CHECK-NEXT: vldr s6, .LCPI3_0 ; CHECK-MVE-NEXT: vldr s6, .LCPI3_0
; CHECK-NEXT: vcvt.s32.f32 s14, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s0
; CHECK-NEXT: vldr s10, .LCPI3_1 ; CHECK-MVE-NEXT: vldr s10, .LCPI3_1
; CHECK-NEXT: vcvt.s32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3
; CHECK-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s10 ; CHECK-MVE-NEXT: vcmp.f32 s2, s10
; CHECK-NEXT: vcvt.s32.f32 s4, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s1
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r0, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r0, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r0, #-2147483648 ; CHECK-MVE-NEXT: mvngt r0, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, s6 ; CHECK-MVE-NEXT: vcmp.f32 s0, s6
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-NEXT: vcmp.f32 s0, s10 ; CHECK-MVE-NEXT: vcmp.f32 s0, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s6 ; CHECK-MVE-NEXT: vcmp.f32 s3, s6
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s8 ; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-NEXT: vcmp.f32 s3, s10 ; CHECK-MVE-NEXT: vcmp.f32 s3, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r2, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r2, #-2147483648 ; CHECK-MVE-NEXT: mvngt r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s4 ; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vcmp.f32 s1, s6 ; CHECK-MVE-NEXT: vcmp.f32 s1, s6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r3, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r3, #-2147483648
; CHECK-NEXT: vcmp.f32 s1, s10 ; CHECK-MVE-NEXT: vcmp.f32 s1, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r3, #-2147483648 ; CHECK-MVE-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI3_0: ; CHECK-MVE-NEXT: .LCPI3_0:
; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-MVE-NEXT: .long 0xcf000000 @ float -2.14748365E+9
; CHECK-NEXT: .LCPI3_1: ; CHECK-MVE-NEXT: .LCPI3_1:
; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 ; CHECK-MVE-NEXT: .long 0x4effffff @ float 2.14748352E+9
;
; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f) %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define arm_aapcs_vfpcc <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) { define arm_aapcs_vfpcc <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) {
; CHECK-LABEL: test_signed_v5f32_v5i32: ; CHECK-MVE-LABEL: test_signed_v5f32_v5i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.s32.f32 s5, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s4
; CHECK-NEXT: vldr s10, .LCPI4_0 ; CHECK-MVE-NEXT: vldr s10, .LCPI4_0
; CHECK-NEXT: vcvt.s32.f32 s7, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s7, s3
; CHECK-NEXT: vldr s14, .LCPI4_1 ; CHECK-MVE-NEXT: vldr s14, .LCPI4_1
; CHECK-NEXT: vcvt.s32.f32 s12, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s1
; CHECK-NEXT: vcmp.f32 s4, s10 ; CHECK-MVE-NEXT: vcmp.f32 s4, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s4, s14 ; CHECK-MVE-NEXT: vcmp.f32 s4, s14
; CHECK-NEXT: vcvt.s32.f32 s8, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s2
; CHECK-NEXT: vcvt.s32.f32 s6, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s0
; CHECK-NEXT: vmov r1, s5 ; CHECK-MVE-NEXT: vmov r1, s5
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s4, s4 ; CHECK-MVE-NEXT: vcmp.f32 s4, s4
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s10 ; CHECK-MVE-NEXT: vcmp.f32 s3, s10
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s7 ; CHECK-MVE-NEXT: vmov r12, s7
; CHECK-NEXT: str r1, [r0, #16] ; CHECK-MVE-NEXT: str r1, [r0, #16]
; CHECK-NEXT: vcmp.f32 s3, s14 ; CHECK-MVE-NEXT: vcmp.f32 s3, s14
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r12, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r12, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r12, #-2147483648 ; CHECK-MVE-NEXT: mvngt r12, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s10 ; CHECK-MVE-NEXT: vcmp.f32 s1, s10
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w r12, #0 ; CHECK-MVE-NEXT: movvs.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-NEXT: vcmp.f32 s1, s14 ; CHECK-MVE-NEXT: vcmp.f32 s1, s14
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r2, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r2, #-2147483648 ; CHECK-MVE-NEXT: mvngt r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s10 ; CHECK-MVE-NEXT: vcmp.f32 s2, s10
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s8 ; CHECK-MVE-NEXT: vmov r3, s8
; CHECK-NEXT: vcmp.f32 s2, s14 ; CHECK-MVE-NEXT: vcmp.f32 s2, s14
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r3, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r3, #-2147483648 ; CHECK-MVE-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vcmp.f32 s0, s10 ; CHECK-MVE-NEXT: vcmp.f32 s0, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s0, s14 ; CHECK-MVE-NEXT: vcmp.f32 s0, s14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r3 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r3
; CHECK-NEXT: vmov q0[3], q0[1], r2, r12 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r12
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI4_0: ; CHECK-MVE-NEXT: .LCPI4_0:
; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-MVE-NEXT: .long 0xcf000000 @ float -2.14748365E+9
; CHECK-NEXT: .LCPI4_1: ; CHECK-MVE-NEXT: .LCPI4_1:
; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 ; CHECK-MVE-NEXT: .long 0x4effffff @ float 2.14748352E+9
;
; CHECK-MVEFP-LABEL: test_signed_v5f32_v5i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov r1, s4
; CHECK-MVEFP-NEXT: str r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr
%x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f) %x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f)
ret <5 x i32> %x ret <5 x i32> %x
} }
define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) { define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
; CHECK-LABEL: test_signed_v6f32_v6i32: ; CHECK-MVE-LABEL: test_signed_v6f32_v6i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.s32.f32 s9, s5 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s5
; CHECK-NEXT: vldr s10, .LCPI5_0 ; CHECK-MVE-NEXT: vldr s10, .LCPI5_0
; CHECK-NEXT: vcvt.s32.f32 s11, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s4
; CHECK-NEXT: vldr s6, .LCPI5_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI5_1
; CHECK-NEXT: vcvt.s32.f32 s7, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s7, s3
; CHECK-NEXT: vcmp.f32 s5, s10 ; CHECK-MVE-NEXT: vcmp.f32 s5, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s5, s6 ; CHECK-MVE-NEXT: vcmp.f32 s5, s6
; CHECK-NEXT: vcvt.s32.f32 s14, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s1
; CHECK-NEXT: vcvt.s32.f32 s12, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s2
; CHECK-NEXT: vmov r1, s9 ; CHECK-MVE-NEXT: vmov r1, s9
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s5, s5 ; CHECK-MVE-NEXT: vcmp.f32 s5, s5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vcmp.f32 s4, s10 ; CHECK-MVE-NEXT: vcmp.f32 s4, s10
; CHECK-NEXT: str r1, [r0, #20] ; CHECK-MVE-NEXT: str r1, [r0, #20]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s11 ; CHECK-MVE-NEXT: vmov r1, s11
; CHECK-NEXT: vcmp.f32 s4, s6 ; CHECK-MVE-NEXT: vcmp.f32 s4, s6
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s4, s4 ; CHECK-MVE-NEXT: vcmp.f32 s4, s4
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s10 ; CHECK-MVE-NEXT: vcmp.f32 s3, s10
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s7 ; CHECK-MVE-NEXT: vmov r12, s7
; CHECK-NEXT: vcmp.f32 s3, s6 ; CHECK-MVE-NEXT: vcmp.f32 s3, s6
; CHECK-NEXT: str r1, [r0, #16] ; CHECK-MVE-NEXT: str r1, [r0, #16]
; CHECK-NEXT: vcvt.s32.f32 s8, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s0
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r12, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r12, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r12, #-2147483648 ; CHECK-MVE-NEXT: mvngt r12, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s10 ; CHECK-MVE-NEXT: vcmp.f32 s1, s10
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w r12, #0 ; CHECK-MVE-NEXT: movvs.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s14 ; CHECK-MVE-NEXT: vmov r2, s14
; CHECK-NEXT: vcmp.f32 s1, s6 ; CHECK-MVE-NEXT: vcmp.f32 s1, s6
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r2, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r2, #-2147483648 ; CHECK-MVE-NEXT: mvngt r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s10 ; CHECK-MVE-NEXT: vcmp.f32 s2, s10
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s12 ; CHECK-MVE-NEXT: vmov r3, s12
; CHECK-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r3, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r3, #-2147483648 ; CHECK-MVE-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vmov r1, s8
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vcmp.f32 s0, s10 ; CHECK-MVE-NEXT: vcmp.f32 s0, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s0, s6 ; CHECK-MVE-NEXT: vcmp.f32 s0, s6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r3 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r3
; CHECK-NEXT: vmov q0[3], q0[1], r2, r12 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r12
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI5_0: ; CHECK-MVE-NEXT: .LCPI5_0:
; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-MVE-NEXT: .long 0xcf000000 @ float -2.14748365E+9
; CHECK-NEXT: .LCPI5_1: ; CHECK-MVE-NEXT: .LCPI5_1:
; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 ; CHECK-MVE-NEXT: .long 0x4effffff @ float 2.14748352E+9
;
; CHECK-MVEFP-LABEL: test_signed_v6f32_v6i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r1, s6
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr
%x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f) %x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x ret <6 x i32> %x
} }
define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) { define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
; CHECK-LABEL: test_signed_v7f32_v7i32: ; CHECK-MVE-LABEL: test_signed_v7f32_v7i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.s32.f32 s13, s5 ; CHECK-MVE-NEXT: vcvt.s32.f32 s13, s5
; CHECK-NEXT: vldr s12, .LCPI6_0 ; CHECK-MVE-NEXT: vldr s12, .LCPI6_0
; CHECK-NEXT: vcvt.s32.f32 s15, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s4
; CHECK-NEXT: vldr s8, .LCPI6_1 ; CHECK-MVE-NEXT: vldr s8, .LCPI6_1
; CHECK-NEXT: vcmp.f32 s5, s12 ; CHECK-MVE-NEXT: vcmp.f32 s5, s12
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.s32.f32 s11, s6 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s6
; CHECK-NEXT: vcmp.f32 s5, s8 ; CHECK-MVE-NEXT: vcmp.f32 s5, s8
; CHECK-NEXT: vcvt.s32.f32 s9, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s3
; CHECK-NEXT: vcvt.s32.f32 s7, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s7, s1
; CHECK-NEXT: vmov r1, s13 ; CHECK-MVE-NEXT: vmov r1, s13
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s5, s5 ; CHECK-MVE-NEXT: vcmp.f32 s5, s5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: str r1, [r0, #20] ; CHECK-MVE-NEXT: str r1, [r0, #20]
; CHECK-NEXT: vcmp.f32 s4, s12 ; CHECK-MVE-NEXT: vcmp.f32 s4, s12
; CHECK-NEXT: vmov r1, s15 ; CHECK-MVE-NEXT: vmov r1, s15
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s4, s8 ; CHECK-MVE-NEXT: vcmp.f32 s4, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s4, s4 ; CHECK-MVE-NEXT: vcmp.f32 s4, s4
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vcmp.f32 s6, s12 ; CHECK-MVE-NEXT: vcmp.f32 s6, s12
; CHECK-NEXT: str r1, [r0, #16] ; CHECK-MVE-NEXT: str r1, [r0, #16]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s11 ; CHECK-MVE-NEXT: vmov r1, s11
; CHECK-NEXT: vcmp.f32 s6, s8 ; CHECK-MVE-NEXT: vcmp.f32 s6, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s6, s6 ; CHECK-MVE-NEXT: vcmp.f32 s6, s6
; CHECK-NEXT: vcvt.s32.f32 s14, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s2
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s12 ; CHECK-MVE-NEXT: vcmp.f32 s3, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s9 ; CHECK-MVE-NEXT: vmov r12, s9
; CHECK-NEXT: str r1, [r0, #24] ; CHECK-MVE-NEXT: str r1, [r0, #24]
; CHECK-NEXT: vcmp.f32 s3, s8 ; CHECK-MVE-NEXT: vcmp.f32 s3, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r12, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r12, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.s32.f32 s10, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s0
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r12, #-2147483648 ; CHECK-MVE-NEXT: mvngt r12, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s12 ; CHECK-MVE-NEXT: vcmp.f32 s1, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w r12, #0 ; CHECK-MVE-NEXT: movvs.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s7 ; CHECK-MVE-NEXT: vmov r2, s7
; CHECK-NEXT: vcmp.f32 s1, s8 ; CHECK-MVE-NEXT: vcmp.f32 s1, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r2, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r2, #-2147483648 ; CHECK-MVE-NEXT: mvngt r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s12 ; CHECK-MVE-NEXT: vcmp.f32 s2, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s14 ; CHECK-MVE-NEXT: vmov r3, s14
; CHECK-NEXT: vcmp.f32 s2, s8 ; CHECK-MVE-NEXT: vcmp.f32 s2, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r3, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r3, #-2147483648 ; CHECK-MVE-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vcmp.f32 s0, s12 ; CHECK-MVE-NEXT: vcmp.f32 s0, s12
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s0, s8 ; CHECK-MVE-NEXT: vcmp.f32 s0, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r3 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r3
; CHECK-NEXT: vmov q0[3], q0[1], r2, r12 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r12
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI6_0: ; CHECK-MVE-NEXT: .LCPI6_0:
; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-MVE-NEXT: .long 0xcf000000 @ float -2.14748365E+9
; CHECK-NEXT: .LCPI6_1: ; CHECK-MVE-NEXT: .LCPI6_1:
; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 ; CHECK-MVE-NEXT: .long 0x4effffff @ float 2.14748352E+9
;
; CHECK-MVEFP-LABEL: test_signed_v7f32_v7i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r3, s6
; CHECK-MVEFP-NEXT: vmov r1, s10
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: str r3, [r0, #24]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr
%x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f) %x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f)
ret <7 x i32> %x ret <7 x i32> %x
} }
define arm_aapcs_vfpcc <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) { define arm_aapcs_vfpcc <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i32: ; CHECK-MVE-LABEL: test_signed_v8f32_v8i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-NEXT: vcvt.s32.f32 s16, s6 ; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s6
; CHECK-NEXT: vldr s12, .LCPI7_0 ; CHECK-MVE-NEXT: vldr s12, .LCPI7_0
; CHECK-NEXT: vcvt.s32.f32 s18, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s18, s4
; CHECK-NEXT: vldr s10, .LCPI7_1 ; CHECK-MVE-NEXT: vldr s10, .LCPI7_1
; CHECK-NEXT: vcvt.s32.f32 s15, s7 ; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s7
; CHECK-NEXT: vcmp.f32 s6, s12 ; CHECK-MVE-NEXT: vcmp.f32 s6, s12
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s6, s10 ; CHECK-MVE-NEXT: vcmp.f32 s6, s10
; CHECK-NEXT: vcvt.s32.f32 s13, s5 ; CHECK-MVE-NEXT: vcvt.s32.f32 s13, s5
; CHECK-NEXT: vcvt.s32.f32 s11, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s2
; CHECK-NEXT: vmov r12, s16 ; CHECK-MVE-NEXT: vmov r12, s16
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r12, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r12, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s6, s6 ; CHECK-MVE-NEXT: vcmp.f32 s6, s6
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r12, #-2147483648 ; CHECK-MVE-NEXT: mvngt r12, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s4, s12 ; CHECK-MVE-NEXT: vcmp.f32 s4, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w r12, #0 ; CHECK-MVE-NEXT: movvs.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov lr, s18 ; CHECK-MVE-NEXT: vmov lr, s18
; CHECK-NEXT: vcmp.f32 s4, s10 ; CHECK-MVE-NEXT: vcmp.f32 s4, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w lr, #-2147483648 ; CHECK-MVE-NEXT: movlt.w lr, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s4, s4 ; CHECK-MVE-NEXT: vcmp.f32 s4, s4
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt lr, #-2147483648 ; CHECK-MVE-NEXT: mvngt lr, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s7, s12 ; CHECK-MVE-NEXT: vcmp.f32 s7, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w lr, #0 ; CHECK-MVE-NEXT: movvs.w lr, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s15 ; CHECK-MVE-NEXT: vmov r2, s15
; CHECK-NEXT: vcmp.f32 s7, s10 ; CHECK-MVE-NEXT: vcmp.f32 s7, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r2, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s7, s7 ; CHECK-MVE-NEXT: vcmp.f32 s7, s7
; CHECK-NEXT: vcvt.s32.f32 s9, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r2, #-2147483648 ; CHECK-MVE-NEXT: mvngt r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s5, s12 ; CHECK-MVE-NEXT: vcmp.f32 s5, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s13 ; CHECK-MVE-NEXT: vmov r3, s13
; CHECK-NEXT: vcmp.f32 s5, s10 ; CHECK-MVE-NEXT: vcmp.f32 s5, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r3, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s5, s5 ; CHECK-MVE-NEXT: vcmp.f32 s5, s5
; CHECK-NEXT: vcvt.s32.f32 s14, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s3
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r3, #-2147483648 ; CHECK-MVE-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s12 ; CHECK-MVE-NEXT: vcmp.f32 s2, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r0, s11 ; CHECK-MVE-NEXT: vmov r0, s11
; CHECK-NEXT: vmov q1[2], q1[0], lr, r12 ; CHECK-MVE-NEXT: vmov q1[2], q1[0], lr, r12
; CHECK-NEXT: vcmp.f32 s2, s10 ; CHECK-MVE-NEXT: vcmp.f32 s2, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r0, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r0, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.s32.f32 s8, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s1
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r0, #-2147483648 ; CHECK-MVE-NEXT: mvngt r0, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, s12 ; CHECK-MVE-NEXT: vcmp.f32 s0, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s9 ; CHECK-MVE-NEXT: vmov r1, s9
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2 ; CHECK-MVE-NEXT: vmov q1[3], q1[1], r3, r2
; CHECK-NEXT: vcmp.f32 s0, s10 ; CHECK-MVE-NEXT: vcmp.f32 s0, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s12 ; CHECK-MVE-NEXT: vcmp.f32 s3, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r4, s14 ; CHECK-MVE-NEXT: vmov r4, s14
; CHECK-NEXT: vcmp.f32 s3, s10 ; CHECK-MVE-NEXT: vcmp.f32 s3, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r4, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r4, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r4, #-2147483648 ; CHECK-MVE-NEXT: mvngt r4, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r5, s8 ; CHECK-MVE-NEXT: vmov r5, s8
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r4, #0 ; CHECK-MVE-NEXT: movvs r4, #0
; CHECK-NEXT: vcmp.f32 s1, s12 ; CHECK-MVE-NEXT: vcmp.f32 s1, s12
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r5, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r5, #-2147483648
; CHECK-NEXT: vcmp.f32 s1, s10 ; CHECK-MVE-NEXT: vcmp.f32 s1, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r5, #-2147483648 ; CHECK-MVE-NEXT: mvngt r5, #-2147483648
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r5, #0 ; CHECK-MVE-NEXT: movvs r5, #0
; CHECK-NEXT: vmov q0[3], q0[1], r5, r4 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r5, r4
; CHECK-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI7_0: ; CHECK-MVE-NEXT: .LCPI7_0:
; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-MVE-NEXT: .long 0xcf000000 @ float -2.14748365E+9
; CHECK-NEXT: .LCPI7_1: ; CHECK-MVE-NEXT: .LCPI7_1:
; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 ; CHECK-MVE-NEXT: .long 0x4effffff @ float 2.14748352E+9
;
; CHECK-MVEFP-LABEL: test_signed_v8f32_v8i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: bx lr
%x = call <8 x i32> @llvm.fptosi.sat.v8f32.v8i32(<8 x float> %f) %x = call <8 x i32> @llvm.fptosi.sat.v8f32.v8i32(<8 x float> %f)
ret <8 x i32> %x ret <8 x i32> %x
} }
; ;
; Double to signed 32-bit -- Vector size variation ; Double to signed 32-bit -- Vector size variation
; ;
▲ Show 20 Lines • Show All 1,776 Lines • ▼ Show 20 Lines
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI22_0: ; CHECK-NEXT: .LCPI22_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
%x = call <4 x i1> @llvm.fptosi.sat.v4f32.v4i1(<4 x float> %f) %x = call <4 x i1> @llvm.fptosi.sat.v4f32.v4i1(<4 x float> %f)
ret <4 x i1> %x ret <4 x i1> %x
} }
define arm_aapcs_vfpcc <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i8: ; CHECK-MVE-LABEL: test_signed_v4f32_v4i8:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s4, .LCPI23_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI23_0
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: vldr s6, .LCPI23_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI23_1
; CHECK-NEXT: vmaxnm.f32 s12, s2, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
; CHECK-NEXT: vmaxnm.f32 s10, s0, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-NEXT: vminnm.f32 s12, s12, s6 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
; CHECK-NEXT: vmaxnm.f32 s8, s1, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s1, s4
; CHECK-NEXT: vminnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
; CHECK-NEXT: vmaxnm.f32 s4, s3, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s3, s4
; CHECK-NEXT: vcvt.s32.f32 s12, s12 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
; CHECK-NEXT: vminnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-NEXT: vminnm.f32 s4, s4, s6 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
; CHECK-NEXT: vcvt.s32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
; CHECK-NEXT: vcvt.s32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.s32.f32 s4, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s4 ; CHECK-MVE-NEXT: vmov r2, s4
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov r3, s8 ; CHECK-MVE-NEXT: vmov r3, s8
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI23_0: ; CHECK-MVE-NEXT: .LCPI23_0:
; CHECK-NEXT: .long 0xc3000000 @ float -128 ; CHECK-MVE-NEXT: .long 0xc3000000 @ float -128
; CHECK-NEXT: .LCPI23_1: ; CHECK-MVE-NEXT: .LCPI23_1:
; CHECK-NEXT: .long 0x42fe0000 @ float 127 ; CHECK-MVE-NEXT: .long 0x42fe0000 @ float 127
;
; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i8:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x7f
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmvn.i32 q2, #0x7f
; CHECK-MVEFP-NEXT: vmin.s32 q0, q0, q1
; CHECK-MVEFP-NEXT: vmax.s32 q0, q0, q2
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i8> @llvm.fptosi.sat.v4f32.v4i8(<4 x float> %f) %x = call <4 x i8> @llvm.fptosi.sat.v4f32.v4i8(<4 x float> %f)
ret <4 x i8> %x ret <4 x i8> %x
} }
define arm_aapcs_vfpcc <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i13: ; CHECK-MVE-LABEL: test_signed_v4f32_v4i13:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s4, .LCPI24_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI24_0
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: vldr s6, .LCPI24_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI24_1
; CHECK-NEXT: vmaxnm.f32 s12, s2, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
; CHECK-NEXT: vmaxnm.f32 s10, s0, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-NEXT: vminnm.f32 s12, s12, s6 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
; CHECK-NEXT: vmaxnm.f32 s8, s1, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s1, s4
; CHECK-NEXT: vminnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
; CHECK-NEXT: vmaxnm.f32 s4, s3, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s3, s4
; CHECK-NEXT: vcvt.s32.f32 s12, s12 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
; CHECK-NEXT: vminnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-NEXT: vminnm.f32 s4, s4, s6 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
; CHECK-NEXT: vcvt.s32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
; CHECK-NEXT: vcvt.s32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.s32.f32 s4, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s4 ; CHECK-MVE-NEXT: vmov r2, s4
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov r3, s8 ; CHECK-MVE-NEXT: vmov r3, s8
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI24_0: ; CHECK-MVE-NEXT: .LCPI24_0:
; CHECK-NEXT: .long 0xc5800000 @ float -4096 ; CHECK-MVE-NEXT: .long 0xc5800000 @ float -4096
; CHECK-NEXT: .LCPI24_1: ; CHECK-MVE-NEXT: .LCPI24_1:
; CHECK-NEXT: .long 0x457ff000 @ float 4095 ; CHECK-MVE-NEXT: .long 0x457ff000 @ float 4095
;
; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i13:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vmov.i32 q1, #0xfff
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmvn.i32 q2, #0xfff
; CHECK-MVEFP-NEXT: vmin.s32 q0, q0, q1
; CHECK-MVEFP-NEXT: vmax.s32 q0, q0, q2
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i13> @llvm.fptosi.sat.v4f32.v4i13(<4 x float> %f) %x = call <4 x i13> @llvm.fptosi.sat.v4f32.v4i13(<4 x float> %f)
ret <4 x i13> %x ret <4 x i13> %x
} }
define arm_aapcs_vfpcc <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16: ; CHECK-MVE-LABEL: test_signed_v4f32_v4i16:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s4, .LCPI25_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI25_0
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: vldr s6, .LCPI25_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI25_1
; CHECK-NEXT: vmaxnm.f32 s12, s2, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
; CHECK-NEXT: vmaxnm.f32 s10, s0, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-NEXT: vminnm.f32 s12, s12, s6 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
; CHECK-NEXT: vmaxnm.f32 s8, s1, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s1, s4
; CHECK-NEXT: vminnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
; CHECK-NEXT: vmaxnm.f32 s4, s3, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s3, s4
; CHECK-NEXT: vcvt.s32.f32 s12, s12 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
; CHECK-NEXT: vminnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-NEXT: vminnm.f32 s4, s4, s6 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
; CHECK-NEXT: vcvt.s32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
; CHECK-NEXT: vcvt.s32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.s32.f32 s4, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s4 ; CHECK-MVE-NEXT: vmov r2, s4
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov r3, s8 ; CHECK-MVE-NEXT: vmov r3, s8
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI25_0: ; CHECK-MVE-NEXT: .LCPI25_0:
; CHECK-NEXT: .long 0xc7000000 @ float -32768 ; CHECK-MVE-NEXT: .long 0xc7000000 @ float -32768
; CHECK-NEXT: .LCPI25_1: ; CHECK-MVE-NEXT: .LCPI25_1:
; CHECK-NEXT: .long 0x46fffe00 @ float 32767 ; CHECK-MVE-NEXT: .long 0x46fffe00 @ float 32767
;
; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i16:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vqmovnb.s32 q0, q0
; CHECK-MVEFP-NEXT: vmovlb.s16 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i16> @llvm.fptosi.sat.v4f32.v4i16(<4 x float> %f) %x = call <4 x i16> @llvm.fptosi.sat.v4f32.v4i16(<4 x float> %f)
ret <4 x i16> %x ret <4 x i16> %x
} }
define arm_aapcs_vfpcc <4 x i19> @test_signed_v4f32_v4i19(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i19> @test_signed_v4f32_v4i19(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i19: ; CHECK-MVE-LABEL: test_signed_v4f32_v4i19:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s4, .LCPI26_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI26_0
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: vldr s6, .LCPI26_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI26_1
; CHECK-NEXT: vmaxnm.f32 s12, s2, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
; CHECK-NEXT: vmaxnm.f32 s10, s0, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-NEXT: vminnm.f32 s12, s12, s6 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
; CHECK-NEXT: vmaxnm.f32 s8, s1, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s1, s4
; CHECK-NEXT: vminnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
; CHECK-NEXT: vmaxnm.f32 s4, s3, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s3, s4
; CHECK-NEXT: vcvt.s32.f32 s12, s12 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
; CHECK-NEXT: vminnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-NEXT: vminnm.f32 s4, s4, s6 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
; CHECK-NEXT: vcvt.s32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
; CHECK-NEXT: vcvt.s32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.s32.f32 s4, s4 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s4 ; CHECK-MVE-NEXT: vmov r2, s4
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov r3, s8 ; CHECK-MVE-NEXT: vmov r3, s8
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI26_0: ; CHECK-MVE-NEXT: .LCPI26_0:
; CHECK-NEXT: .long 0xc8800000 @ float -262144 ; CHECK-MVE-NEXT: .long 0xc8800000 @ float -262144
; CHECK-NEXT: .LCPI26_1: ; CHECK-MVE-NEXT: .LCPI26_1:
; CHECK-NEXT: .long 0x487fffc0 @ float 262143 ; CHECK-MVE-NEXT: .long 0x487fffc0 @ float 262143
;
; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i19:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: movs r0, #0
; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x3ffff
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: movt r0, #65532
; CHECK-MVEFP-NEXT: vmin.s32 q0, q0, q1
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
; CHECK-MVEFP-NEXT: vmax.s32 q0, q0, q1
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i19> @llvm.fptosi.sat.v4f32.v4i19(<4 x float> %f) %x = call <4 x i19> @llvm.fptosi.sat.v4f32.v4i19(<4 x float> %f)
ret <4 x i19> %x ret <4 x i19> %x
} }
define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f32_v4i32_duplicate(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f32_v4i32_duplicate(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i32_duplicate: ; CHECK-MVE-LABEL: test_signed_v4f32_v4i32_duplicate:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.s32.f32 s12, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s2
; CHECK-NEXT: vldr s6, .LCPI27_0 ; CHECK-MVE-NEXT: vldr s6, .LCPI27_0
; CHECK-NEXT: vcvt.s32.f32 s14, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s0
; CHECK-NEXT: vldr s10, .LCPI27_1 ; CHECK-MVE-NEXT: vldr s10, .LCPI27_1
; CHECK-NEXT: vcvt.s32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3
; CHECK-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s10 ; CHECK-MVE-NEXT: vcmp.f32 s2, s10
; CHECK-NEXT: vcvt.s32.f32 s4, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s1
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r0, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r0, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r0, #-2147483648 ; CHECK-MVE-NEXT: mvngt r0, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, s6 ; CHECK-MVE-NEXT: vcmp.f32 s0, s6
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-NEXT: vcmp.f32 s0, s10 ; CHECK-MVE-NEXT: vcmp.f32 s0, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r1, #-2147483648 ; CHECK-MVE-NEXT: mvngt r1, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s6 ; CHECK-MVE-NEXT: vcmp.f32 s3, s6
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s8 ; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-NEXT: vcmp.f32 s3, s10 ; CHECK-MVE-NEXT: vcmp.f32 s3, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r2, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r2, #-2147483648 ; CHECK-MVE-NEXT: mvngt r2, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s4 ; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vcmp.f32 s1, s6 ; CHECK-MVE-NEXT: vcmp.f32 s1, s6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r3, #-2147483648 ; CHECK-MVE-NEXT: movlt.w r3, #-2147483648
; CHECK-NEXT: vcmp.f32 s1, s10 ; CHECK-MVE-NEXT: vcmp.f32 s1, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: mvngt r3, #-2147483648 ; CHECK-MVE-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI27_0: ; CHECK-MVE-NEXT: .LCPI27_0:
; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-MVE-NEXT: .long 0xcf000000 @ float -2.14748365E+9
; CHECK-NEXT: .LCPI27_1: ; CHECK-MVE-NEXT: .LCPI27_1:
; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 ; CHECK-MVE-NEXT: .long 0x4effffff @ float 2.14748352E+9
;
; CHECK-MVEFP-LABEL: test_signed_v4f32_v4i32_duplicate:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f) %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define arm_aapcs_vfpcc <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i50: ; CHECK-LABEL: test_signed_v4f32_v4i50:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI42_0: ; CHECK-NEXT: .LCPI42_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
%x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f) %x = call <8 x i1> @llvm.fptosi.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x ret <8 x i1> %x
} }
define arm_aapcs_vfpcc <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) { define arm_aapcs_vfpcc <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i8: ; CHECK-MVE-LABEL: test_signed_v8f16_v8i8:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8} ; CHECK-MVE-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8} ; CHECK-MVE-NEXT: vpush {d8}
; CHECK-NEXT: vldr s8, .LCPI43_1 ; CHECK-MVE-NEXT: vldr s8, .LCPI43_1
; CHECK-NEXT: vcvtt.f32.f16 s13, s3 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
; CHECK-NEXT: vcvtb.f32.f16 s3, s3 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
; CHECK-NEXT: vldr s6, .LCPI43_0 ; CHECK-MVE-NEXT: vldr s6, .LCPI43_0
; CHECK-NEXT: vmaxnm.f32 s16, s3, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s8
; CHECK-NEXT: vcvtt.f32.f16 s4, s0 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s4, s0
; CHECK-NEXT: vcvtt.f32.f16 s12, s1 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
; CHECK-NEXT: vcvtt.f32.f16 s7, s2 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
; CHECK-NEXT: vmaxnm.f32 s15, s13, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s8
; CHECK-NEXT: vminnm.f32 s16, s16, s6 ; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s6
; CHECK-NEXT: vcvtb.f32.f16 s0, s0 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s1 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
; CHECK-NEXT: vcvtb.f32.f16 s2, s2 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vmaxnm.f32 s10, s4, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s4, s8
; CHECK-NEXT: vmaxnm.f32 s14, s12, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s8
; CHECK-NEXT: vmaxnm.f32 s5, s0, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s5, s0, s8
; CHECK-NEXT: vmaxnm.f32 s9, s7, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s8
; CHECK-NEXT: vmaxnm.f32 s11, s1, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s11, s1, s8
; CHECK-NEXT: vminnm.f32 s15, s15, s6 ; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s6
; CHECK-NEXT: vcvt.s32.f32 s16, s16 ; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
; CHECK-NEXT: vmaxnm.f32 s8, s2, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s2, s8
; CHECK-NEXT: vminnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
; CHECK-NEXT: vminnm.f32 s14, s14, s6 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s6
; CHECK-NEXT: vminnm.f32 s5, s5, s6 ; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s6
; CHECK-NEXT: vminnm.f32 s9, s9, s6 ; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s6
; CHECK-NEXT: vminnm.f32 s11, s11, s6 ; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s6
; CHECK-NEXT: vminnm.f32 s6, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s6, s8, s6
; CHECK-NEXT: vcvt.s32.f32 s15, s15 ; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
; CHECK-NEXT: vcvt.s32.f32 s6, s6 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
; CHECK-NEXT: vcvt.s32.f32 s9, s9 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
; CHECK-NEXT: vcvt.s32.f32 s11, s11 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
; CHECK-NEXT: vcvt.s32.f32 s14, s14 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
; CHECK-NEXT: vcvt.s32.f32 s5, s5 ; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
; CHECK-NEXT: vcvt.s32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s16 ; CHECK-MVE-NEXT: vmov r12, s16
; CHECK-NEXT: vcmp.f32 s13, s13 ; CHECK-MVE-NEXT: vcmp.f32 s13, s13
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w r12, #0 ; CHECK-MVE-NEXT: movvs.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov lr, s15 ; CHECK-MVE-NEXT: vmov lr, s15
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w lr, #0 ; CHECK-MVE-NEXT: movvs.w lr, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s6 ; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-NEXT: vcmp.f32 s7, s7 ; CHECK-MVE-NEXT: vcmp.f32 s7, s7
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s9 ; CHECK-MVE-NEXT: vmov r3, s9
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r0, s11 ; CHECK-MVE-NEXT: vmov r0, s11
; CHECK-NEXT: vcmp.f32 s12, s12 ; CHECK-MVE-NEXT: vcmp.f32 s12, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-NEXT: vmov r4, s5 ; CHECK-MVE-NEXT: vmov r4, s5
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r4, #0 ; CHECK-MVE-NEXT: movvs r4, #0
; CHECK-NEXT: vcmp.f32 s4, s4 ; CHECK-MVE-NEXT: vcmp.f32 s4, s4
; CHECK-NEXT: vmov.16 q0[0], r4 ; CHECK-MVE-NEXT: vmov.16 q0[0], r4
; CHECK-NEXT: vmov r5, s10 ; CHECK-MVE-NEXT: vmov r5, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r5, #0 ; CHECK-MVE-NEXT: movvs r5, #0
; CHECK-NEXT: vmov.16 q0[1], r5 ; CHECK-MVE-NEXT: vmov.16 q0[1], r5
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov.16 q0[3], r1 ; CHECK-MVE-NEXT: vmov.16 q0[3], r1
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-MVE-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.16 q0[5], r3 ; CHECK-MVE-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: vmov.16 q0[6], r12 ; CHECK-MVE-NEXT: vmov.16 q0[6], r12
; CHECK-NEXT: vmov.16 q0[7], lr ; CHECK-MVE-NEXT: vmov.16 q0[7], lr
; CHECK-NEXT: vpop {d8} ; CHECK-MVE-NEXT: vpop {d8}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI43_0: ; CHECK-MVE-NEXT: .LCPI43_0:
; CHECK-NEXT: .long 0x42fe0000 @ float 127 ; CHECK-MVE-NEXT: .long 0x42fe0000 @ float 127
; CHECK-NEXT: .LCPI43_1: ; CHECK-MVE-NEXT: .LCPI43_1:
; CHECK-NEXT: .long 0xc3000000 @ float -128 ; CHECK-MVE-NEXT: .long 0xc3000000 @ float -128
;
; CHECK-MVEFP-LABEL: test_signed_v8f16_v8i8:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s16.f16 q0, q0
; CHECK-MVEFP-NEXT: vqmovnb.s16 q0, q0
; CHECK-MVEFP-NEXT: vmovlb.s8 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f) %x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x ret <8 x i8> %x
} }
define arm_aapcs_vfpcc <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) { define arm_aapcs_vfpcc <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i13: ; CHECK-MVE-LABEL: test_signed_v8f16_v8i13:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8} ; CHECK-MVE-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8} ; CHECK-MVE-NEXT: vpush {d8}
; CHECK-NEXT: vldr s8, .LCPI44_1 ; CHECK-MVE-NEXT: vldr s8, .LCPI44_1
; CHECK-NEXT: vcvtt.f32.f16 s13, s3 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
; CHECK-NEXT: vcvtb.f32.f16 s3, s3 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
; CHECK-NEXT: vldr s6, .LCPI44_0 ; CHECK-MVE-NEXT: vldr s6, .LCPI44_0
; CHECK-NEXT: vmaxnm.f32 s16, s3, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s8
; CHECK-NEXT: vcvtt.f32.f16 s4, s0 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s4, s0
; CHECK-NEXT: vcvtt.f32.f16 s12, s1 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
; CHECK-NEXT: vcvtt.f32.f16 s7, s2 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
; CHECK-NEXT: vmaxnm.f32 s15, s13, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s8
; CHECK-NEXT: vminnm.f32 s16, s16, s6 ; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s6
; CHECK-NEXT: vcvtb.f32.f16 s0, s0 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s1 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
; CHECK-NEXT: vcvtb.f32.f16 s2, s2 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vmaxnm.f32 s10, s4, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s4, s8
; CHECK-NEXT: vmaxnm.f32 s14, s12, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s8
; CHECK-NEXT: vmaxnm.f32 s5, s0, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s5, s0, s8
; CHECK-NEXT: vmaxnm.f32 s9, s7, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s8
; CHECK-NEXT: vmaxnm.f32 s11, s1, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s11, s1, s8
; CHECK-NEXT: vminnm.f32 s15, s15, s6 ; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s6
; CHECK-NEXT: vcvt.s32.f32 s16, s16 ; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
; CHECK-NEXT: vmaxnm.f32 s8, s2, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s2, s8
; CHECK-NEXT: vminnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
; CHECK-NEXT: vminnm.f32 s14, s14, s6 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s6
; CHECK-NEXT: vminnm.f32 s5, s5, s6 ; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s6
; CHECK-NEXT: vminnm.f32 s9, s9, s6 ; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s6
; CHECK-NEXT: vminnm.f32 s11, s11, s6 ; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s6
; CHECK-NEXT: vminnm.f32 s6, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s6, s8, s6
; CHECK-NEXT: vcvt.s32.f32 s15, s15 ; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
; CHECK-NEXT: vcvt.s32.f32 s6, s6 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
; CHECK-NEXT: vcvt.s32.f32 s9, s9 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
; CHECK-NEXT: vcvt.s32.f32 s11, s11 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
; CHECK-NEXT: vcvt.s32.f32 s14, s14 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
; CHECK-NEXT: vcvt.s32.f32 s5, s5 ; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
; CHECK-NEXT: vcvt.s32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s16 ; CHECK-MVE-NEXT: vmov r12, s16
; CHECK-NEXT: vcmp.f32 s13, s13 ; CHECK-MVE-NEXT: vcmp.f32 s13, s13
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w r12, #0 ; CHECK-MVE-NEXT: movvs.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov lr, s15 ; CHECK-MVE-NEXT: vmov lr, s15
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w lr, #0 ; CHECK-MVE-NEXT: movvs.w lr, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s6 ; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-NEXT: vcmp.f32 s7, s7 ; CHECK-MVE-NEXT: vcmp.f32 s7, s7
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s9 ; CHECK-MVE-NEXT: vmov r3, s9
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r0, s11 ; CHECK-MVE-NEXT: vmov r0, s11
; CHECK-NEXT: vcmp.f32 s12, s12 ; CHECK-MVE-NEXT: vcmp.f32 s12, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-NEXT: vmov r4, s5 ; CHECK-MVE-NEXT: vmov r4, s5
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r4, #0 ; CHECK-MVE-NEXT: movvs r4, #0
; CHECK-NEXT: vcmp.f32 s4, s4 ; CHECK-MVE-NEXT: vcmp.f32 s4, s4
; CHECK-NEXT: vmov.16 q0[0], r4 ; CHECK-MVE-NEXT: vmov.16 q0[0], r4
; CHECK-NEXT: vmov r5, s10 ; CHECK-MVE-NEXT: vmov r5, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r5, #0 ; CHECK-MVE-NEXT: movvs r5, #0
; CHECK-NEXT: vmov.16 q0[1], r5 ; CHECK-MVE-NEXT: vmov.16 q0[1], r5
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov.16 q0[3], r1 ; CHECK-MVE-NEXT: vmov.16 q0[3], r1
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-MVE-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.16 q0[5], r3 ; CHECK-MVE-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: vmov.16 q0[6], r12 ; CHECK-MVE-NEXT: vmov.16 q0[6], r12
; CHECK-NEXT: vmov.16 q0[7], lr ; CHECK-MVE-NEXT: vmov.16 q0[7], lr
; CHECK-NEXT: vpop {d8} ; CHECK-MVE-NEXT: vpop {d8}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI44_0: ; CHECK-MVE-NEXT: .LCPI44_0:
; CHECK-NEXT: .long 0x457ff000 @ float 4095 ; CHECK-MVE-NEXT: .long 0x457ff000 @ float 4095
; CHECK-NEXT: .LCPI44_1: ; CHECK-MVE-NEXT: .LCPI44_1:
; CHECK-NEXT: .long 0xc5800000 @ float -4096 ; CHECK-MVE-NEXT: .long 0xc5800000 @ float -4096
;
; CHECK-MVEFP-LABEL: test_signed_v8f16_v8i13:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vmvn.i16 q1, #0xf000
; CHECK-MVEFP-NEXT: vcvt.s16.f16 q0, q0
; CHECK-MVEFP-NEXT: vmov.i16 q2, #0xf000
; CHECK-MVEFP-NEXT: vmin.s16 q0, q0, q1
; CHECK-MVEFP-NEXT: vmax.s16 q0, q0, q2
; CHECK-MVEFP-NEXT: bx lr
%x = call <8 x i13> @llvm.fptosi.sat.v8f16.v8i13(<8 x half> %f) %x = call <8 x i13> @llvm.fptosi.sat.v8f16.v8i13(<8 x half> %f)
ret <8 x i13> %x ret <8 x i13> %x
} }
define arm_aapcs_vfpcc <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) { define arm_aapcs_vfpcc <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i16: ; CHECK-MVE-LABEL: test_signed_v8f16_v8i16:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8} ; CHECK-MVE-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8} ; CHECK-MVE-NEXT: vpush {d8}
; CHECK-NEXT: vldr s8, .LCPI45_1 ; CHECK-MVE-NEXT: vldr s8, .LCPI45_1
; CHECK-NEXT: vcvtt.f32.f16 s13, s3 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
; CHECK-NEXT: vcvtb.f32.f16 s3, s3 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
; CHECK-NEXT: vldr s6, .LCPI45_0 ; CHECK-MVE-NEXT: vldr s6, .LCPI45_0
; CHECK-NEXT: vmaxnm.f32 s16, s3, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s8
; CHECK-NEXT: vcvtt.f32.f16 s4, s0 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s4, s0
; CHECK-NEXT: vcvtt.f32.f16 s12, s1 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
; CHECK-NEXT: vcvtt.f32.f16 s7, s2 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
; CHECK-NEXT: vmaxnm.f32 s15, s13, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s8
; CHECK-NEXT: vminnm.f32 s16, s16, s6 ; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s6
; CHECK-NEXT: vcvtb.f32.f16 s0, s0 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s1, s1 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
; CHECK-NEXT: vcvtb.f32.f16 s2, s2 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vmaxnm.f32 s10, s4, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s4, s8
; CHECK-NEXT: vmaxnm.f32 s14, s12, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s8
; CHECK-NEXT: vmaxnm.f32 s5, s0, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s5, s0, s8
; CHECK-NEXT: vmaxnm.f32 s9, s7, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s8
; CHECK-NEXT: vmaxnm.f32 s11, s1, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s11, s1, s8
; CHECK-NEXT: vminnm.f32 s15, s15, s6 ; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s6
; CHECK-NEXT: vcvt.s32.f32 s16, s16 ; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
; CHECK-NEXT: vmaxnm.f32 s8, s2, s8 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s2, s8
; CHECK-NEXT: vminnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
; CHECK-NEXT: vminnm.f32 s14, s14, s6 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s6
; CHECK-NEXT: vminnm.f32 s5, s5, s6 ; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s6
; CHECK-NEXT: vminnm.f32 s9, s9, s6 ; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s6
; CHECK-NEXT: vminnm.f32 s11, s11, s6 ; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s6
; CHECK-NEXT: vminnm.f32 s6, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s6, s8, s6
; CHECK-NEXT: vcvt.s32.f32 s15, s15 ; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
; CHECK-NEXT: vcvt.s32.f32 s6, s6 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
; CHECK-NEXT: vcvt.s32.f32 s9, s9 ; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
; CHECK-NEXT: vcvt.s32.f32 s11, s11 ; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
; CHECK-NEXT: vcvt.s32.f32 s14, s14 ; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
; CHECK-NEXT: vcvt.s32.f32 s5, s5 ; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
; CHECK-NEXT: vcvt.s32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
; CHECK-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s16 ; CHECK-MVE-NEXT: vmov r12, s16
; CHECK-NEXT: vcmp.f32 s13, s13 ; CHECK-MVE-NEXT: vcmp.f32 s13, s13
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w r12, #0 ; CHECK-MVE-NEXT: movvs.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov lr, s15 ; CHECK-MVE-NEXT: vmov lr, s15
; CHECK-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs.w lr, #0 ; CHECK-MVE-NEXT: movvs.w lr, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s6 ; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-NEXT: vcmp.f32 s7, s7 ; CHECK-MVE-NEXT: vcmp.f32 s7, s7
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r2, #0 ; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s9 ; CHECK-MVE-NEXT: vmov r3, s9
; CHECK-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r3, #0 ; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r0, s11 ; CHECK-MVE-NEXT: vmov r0, s11
; CHECK-NEXT: vcmp.f32 s12, s12 ; CHECK-MVE-NEXT: vcmp.f32 s12, s12
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r0, #0 ; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-NEXT: vmov r4, s5 ; CHECK-MVE-NEXT: vmov r4, s5
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r1, #0 ; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r4, #0 ; CHECK-MVE-NEXT: movvs r4, #0
; CHECK-NEXT: vcmp.f32 s4, s4 ; CHECK-MVE-NEXT: vcmp.f32 s4, s4
; CHECK-NEXT: vmov.16 q0[0], r4 ; CHECK-MVE-NEXT: vmov.16 q0[0], r4
; CHECK-NEXT: vmov r5, s10 ; CHECK-MVE-NEXT: vmov r5, s10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-NEXT: movvs r5, #0 ; CHECK-MVE-NEXT: movvs r5, #0
; CHECK-NEXT: vmov.16 q0[1], r5 ; CHECK-MVE-NEXT: vmov.16 q0[1], r5
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov.16 q0[3], r1 ; CHECK-MVE-NEXT: vmov.16 q0[3], r1
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-MVE-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.16 q0[5], r3 ; CHECK-MVE-NEXT: vmov.16 q0[5], r3
; CHECK-NEXT: vmov.16 q0[6], r12 ; CHECK-MVE-NEXT: vmov.16 q0[6], r12
; CHECK-NEXT: vmov.16 q0[7], lr ; CHECK-MVE-NEXT: vmov.16 q0[7], lr
; CHECK-NEXT: vpop {d8} ; CHECK-MVE-NEXT: vpop {d8}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI45_0: ; CHECK-MVE-NEXT: .LCPI45_0:
; CHECK-NEXT: .long 0x46fffe00 @ float 32767 ; CHECK-MVE-NEXT: .long 0x46fffe00 @ float 32767
; CHECK-NEXT: .LCPI45_1: ; CHECK-MVE-NEXT: .LCPI45_1:
; CHECK-NEXT: .long 0xc7000000 @ float -32768 ; CHECK-MVE-NEXT: .long 0xc7000000 @ float -32768
;
; CHECK-MVEFP-LABEL: test_signed_v8f16_v8i16:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s16.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f) %x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f)
ret <8 x i16> %x ret <8 x i16> %x
} }
define arm_aapcs_vfpcc <8 x i19> @test_signed_v8f16_v8i19(<8 x half> %f) { define arm_aapcs_vfpcc <8 x i19> @test_signed_v8f16_v8i19(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i19: ; CHECK-LABEL: test_signed_v8f16_v8i19:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
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llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP
; ;
; Float to signed 32-bit -- Vector size variation ; Float to signed 32-bit -- Vector size variation
; ;
declare <1 x i32> @llvm.fptoui.sat.v1f32.v1i32 (<1 x float>) declare <1 x i32> @llvm.fptoui.sat.v1f32.v1i32 (<1 x float>)
declare <2 x i32> @llvm.fptoui.sat.v2f32.v2i32 (<2 x float>) declare <2 x i32> @llvm.fptoui.sat.v2f32.v2i32 (<2 x float>)
declare <3 x i32> @llvm.fptoui.sat.v3f32.v3i32 (<3 x float>) declare <3 x i32> @llvm.fptoui.sat.v3f32.v3i32 (<3 x float>)
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; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI1_0: ; CHECK-NEXT: .LCPI1_0:
; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 ; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
%x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f) %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
ret <2 x i32> %x ret <2 x i32> %x
} }
define arm_aapcs_vfpcc <3 x i32> @test_unsigned_v3f32_v3i32(<3 x float> %f) { define arm_aapcs_vfpcc <3 x i32> @test_unsigned_v3f32_v3i32(<3 x float> %f) {
; CHECK-LABEL: test_unsigned_v3f32_v3i32: ; CHECK-MVE-LABEL: test_unsigned_v3f32_v3i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.u32.f32 s10, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s2
; CHECK-NEXT: vldr s8, .LCPI2_0 ; CHECK-MVE-NEXT: vldr s8, .LCPI2_0
; CHECK-NEXT: vcvt.u32.f32 s12, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s0
; CHECK-NEXT: vcvt.u32.f32 s6, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s3
; CHECK-NEXT: vcvt.u32.f32 s4, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s1
; CHECK-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s8 ; CHECK-MVE-NEXT: vcmp.f32 s2, s8
; CHECK-NEXT: vmov r0, s10 ; CHECK-MVE-NEXT: vmov r0, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r0, #0 ; CHECK-MVE-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1 ; CHECK-MVE-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-NEXT: vcmp.f32 s0, s8 ; CHECK-MVE-NEXT: vcmp.f32 s0, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s6 ; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-NEXT: vcmp.f32 s3, s8 ; CHECK-MVE-NEXT: vcmp.f32 s3, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r2, #0 ; CHECK-MVE-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s4 ; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1 ; CHECK-MVE-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s8 ; CHECK-MVE-NEXT: vcmp.f32 s1, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r3, #0 ; CHECK-MVE-NEXT: movlt r3, #0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1 ; CHECK-MVE-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI2_0: ; CHECK-MVE-NEXT: .LCPI2_0:
; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 ; CHECK-MVE-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
;
; CHECK-MVEFP-LABEL: test_unsigned_v3f32_v3i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <3 x i32> @llvm.fptoui.sat.v3f32.v3i32(<3 x float> %f) %x = call <3 x i32> @llvm.fptoui.sat.v3f32.v3i32(<3 x float> %f)
ret <3 x i32> %x ret <3 x i32> %x
} }
define arm_aapcs_vfpcc <4 x i32> @test_unsigned_v4f32_v4i32(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i32> @test_unsigned_v4f32_v4i32(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i32: ; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.u32.f32 s10, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s2
; CHECK-NEXT: vldr s8, .LCPI3_0 ; CHECK-MVE-NEXT: vldr s8, .LCPI3_0
; CHECK-NEXT: vcvt.u32.f32 s12, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s0
; CHECK-NEXT: vcvt.u32.f32 s6, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s3
; CHECK-NEXT: vcvt.u32.f32 s4, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s1
; CHECK-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s8 ; CHECK-MVE-NEXT: vcmp.f32 s2, s8
; CHECK-NEXT: vmov r0, s10 ; CHECK-MVE-NEXT: vmov r0, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r0, #0 ; CHECK-MVE-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1 ; CHECK-MVE-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-NEXT: vcmp.f32 s0, s8 ; CHECK-MVE-NEXT: vcmp.f32 s0, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s6 ; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-NEXT: vcmp.f32 s3, s8 ; CHECK-MVE-NEXT: vcmp.f32 s3, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r2, #0 ; CHECK-MVE-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s4 ; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1 ; CHECK-MVE-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s8 ; CHECK-MVE-NEXT: vcmp.f32 s1, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r3, #0 ; CHECK-MVE-NEXT: movlt r3, #0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1 ; CHECK-MVE-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI3_0: ; CHECK-MVE-NEXT: .LCPI3_0:
; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 ; CHECK-MVE-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
;
; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f) %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define arm_aapcs_vfpcc <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) { define arm_aapcs_vfpcc <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) {
; CHECK-LABEL: test_unsigned_v5f32_v5i32: ; CHECK-MVE-LABEL: test_unsigned_v5f32_v5i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.u32.f32 s14, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s4
; CHECK-NEXT: vldr s12, .LCPI4_0 ; CHECK-MVE-NEXT: vldr s12, .LCPI4_0
; CHECK-NEXT: vcvt.u32.f32 s5, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s5, s3
; CHECK-NEXT: vcvt.u32.f32 s10, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s1
; CHECK-NEXT: vcvt.u32.f32 s6, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s2
; CHECK-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.u32.f32 s8, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s0
; CHECK-NEXT: vcmp.f32 s4, s12 ; CHECK-MVE-NEXT: vcmp.f32 s4, s12
; CHECK-NEXT: vmov r1, s14 ; CHECK-MVE-NEXT: vmov r1, s14
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s5 ; CHECK-MVE-NEXT: vmov r12, s5
; CHECK-NEXT: vcmp.f32 s3, s12 ; CHECK-MVE-NEXT: vcmp.f32 s3, s12
; CHECK-NEXT: str r1, [r0, #16] ; CHECK-MVE-NEXT: str r1, [r0, #16]
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r12, #0 ; CHECK-MVE-NEXT: movlt.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r12, #-1 ; CHECK-MVE-NEXT: movgt.w r12, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s10 ; CHECK-MVE-NEXT: vmov r2, s10
; CHECK-NEXT: vcmp.f32 s1, s12 ; CHECK-MVE-NEXT: vcmp.f32 s1, s12
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r2, #0 ; CHECK-MVE-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1 ; CHECK-MVE-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s6 ; CHECK-MVE-NEXT: vmov r3, s6
; CHECK-NEXT: vcmp.f32 s2, s12 ; CHECK-MVE-NEXT: vcmp.f32 s2, s12
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r3, #0 ; CHECK-MVE-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s8 ; CHECK-MVE-NEXT: vmov r1, s8
; CHECK-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1 ; CHECK-MVE-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vcmp.f32 s0, s12 ; CHECK-MVE-NEXT: vcmp.f32 s0, s12
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmov q0[2], q0[0], r1, r3 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r3
; CHECK-NEXT: vmov q0[3], q0[1], r2, r12 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r12
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI4_0: ; CHECK-MVE-NEXT: .LCPI4_0:
; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 ; CHECK-MVE-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
;
; CHECK-MVEFP-LABEL: test_unsigned_v5f32_v5i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov r1, s4
; CHECK-MVEFP-NEXT: str r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr
%x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f) %x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f)
ret <5 x i32> %x ret <5 x i32> %x
} }
define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) { define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
; CHECK-LABEL: test_unsigned_v6f32_v6i32: ; CHECK-MVE-LABEL: test_unsigned_v6f32_v6i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.u32.f32 s7, s5 ; CHECK-MVE-NEXT: vcvt.u32.f32 s7, s5
; CHECK-NEXT: vldr s14, .LCPI5_0 ; CHECK-MVE-NEXT: vldr s14, .LCPI5_0
; CHECK-NEXT: vcvt.u32.f32 s9, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s9, s4
; CHECK-NEXT: vcvt.u32.f32 s12, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s3
; CHECK-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-NEXT: vcvt.u32.f32 s6, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s5, s14 ; CHECK-MVE-NEXT: vcmp.f32 s5, s14
; CHECK-NEXT: vcvt.u32.f32 s8, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s2
; CHECK-NEXT: vmov r1, s7 ; CHECK-MVE-NEXT: vmov r1, s7
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s9 ; CHECK-MVE-NEXT: vmov r2, s9
; CHECK-NEXT: vcvt.u32.f32 s10, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s0
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r2, #0 ; CHECK-MVE-NEXT: movlt r2, #0
; CHECK-NEXT: vcmp.f32 s4, s14 ; CHECK-MVE-NEXT: vcmp.f32 s4, s14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1 ; CHECK-MVE-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s12 ; CHECK-MVE-NEXT: vmov r12, s12
; CHECK-NEXT: strd r2, r1, [r0, #16] ; CHECK-MVE-NEXT: strd r2, r1, [r0, #16]
; CHECK-NEXT: vcmp.f32 s3, s14 ; CHECK-MVE-NEXT: vcmp.f32 s3, s14
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r12, #0 ; CHECK-MVE-NEXT: movlt.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r12, #-1 ; CHECK-MVE-NEXT: movgt.w r12, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s6 ; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-NEXT: vcmp.f32 s1, s14 ; CHECK-MVE-NEXT: vcmp.f32 s1, s14
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r2, #0 ; CHECK-MVE-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1 ; CHECK-MVE-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s8 ; CHECK-MVE-NEXT: vmov r3, s8
; CHECK-NEXT: vcmp.f32 s2, s14 ; CHECK-MVE-NEXT: vcmp.f32 s2, s14
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r3, #0 ; CHECK-MVE-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s10 ; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1 ; CHECK-MVE-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vcmp.f32 s0, s14 ; CHECK-MVE-NEXT: vcmp.f32 s0, s14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmov q0[2], q0[0], r1, r3 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r3
; CHECK-NEXT: vmov q0[3], q0[1], r2, r12 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r12
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI5_0: ; CHECK-MVE-NEXT: .LCPI5_0:
; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 ; CHECK-MVE-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
;
; CHECK-MVEFP-LABEL: test_unsigned_v6f32_v6i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r1, s6
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr
%x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f) %x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x ret <6 x i32> %x
} }
define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) { define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
; CHECK-LABEL: test_unsigned_v7f32_v7i32: ; CHECK-MVE-LABEL: test_unsigned_v7f32_v7i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.u32.f32 s11, s5 ; CHECK-MVE-NEXT: vcvt.u32.f32 s11, s5
; CHECK-NEXT: vldr s8, .LCPI6_0 ; CHECK-MVE-NEXT: vldr s8, .LCPI6_0
; CHECK-NEXT: vcvt.u32.f32 s13, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s13, s4
; CHECK-NEXT: vcvt.u32.f32 s9, s6 ; CHECK-MVE-NEXT: vcvt.u32.f32 s9, s6
; CHECK-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-NEXT: vcvt.u32.f32 s10, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s5, s8 ; CHECK-MVE-NEXT: vcmp.f32 s5, s8
; CHECK-NEXT: vcvt.u32.f32 s12, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s1
; CHECK-NEXT: vmov r1, s11 ; CHECK-MVE-NEXT: vmov r1, s11
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: str r1, [r0, #20] ; CHECK-MVE-NEXT: str r1, [r0, #20]
; CHECK-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-NEXT: vmov r1, s13 ; CHECK-MVE-NEXT: vmov r1, s13
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vcmp.f32 s4, s8 ; CHECK-MVE-NEXT: vcmp.f32 s4, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vcvt.u32.f32 s14, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s2
; CHECK-NEXT: str r1, [r0, #16] ; CHECK-MVE-NEXT: str r1, [r0, #16]
; CHECK-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s9 ; CHECK-MVE-NEXT: vmov r1, s9
; CHECK-NEXT: vcvt.u32.f32 s7, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s7, s0
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vcmp.f32 s6, s8 ; CHECK-MVE-NEXT: vcmp.f32 s6, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r12, s10 ; CHECK-MVE-NEXT: vmov r12, s10
; CHECK-NEXT: str r1, [r0, #24] ; CHECK-MVE-NEXT: str r1, [r0, #24]
; CHECK-NEXT: vcmp.f32 s3, s8 ; CHECK-MVE-NEXT: vcmp.f32 s3, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r12, #0 ; CHECK-MVE-NEXT: movlt.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r12, #-1 ; CHECK-MVE-NEXT: movgt.w r12, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-NEXT: vcmp.f32 s1, s8 ; CHECK-MVE-NEXT: vcmp.f32 s1, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r2, #0 ; CHECK-MVE-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1 ; CHECK-MVE-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s14 ; CHECK-MVE-NEXT: vmov r3, s14
; CHECK-NEXT: vcmp.f32 s2, s8 ; CHECK-MVE-NEXT: vcmp.f32 s2, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r3, #0 ; CHECK-MVE-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s7 ; CHECK-MVE-NEXT: vmov r1, s7
; CHECK-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1 ; CHECK-MVE-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vcmp.f32 s0, s8 ; CHECK-MVE-NEXT: vcmp.f32 s0, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmov q0[2], q0[0], r1, r3 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r3
; CHECK-NEXT: vmov q0[3], q0[1], r2, r12 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r2, r12
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-MVE-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI6_0: ; CHECK-MVE-NEXT: .LCPI6_0:
; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 ; CHECK-MVE-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
;
; CHECK-MVEFP-LABEL: test_unsigned_v7f32_v7i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r3, s6
; CHECK-MVEFP-NEXT: vmov r1, s10
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: str r3, [r0, #24]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr
%x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f) %x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f)
ret <7 x i32> %x ret <7 x i32> %x
} }
define arm_aapcs_vfpcc <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) { define arm_aapcs_vfpcc <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) {
; CHECK-LABEL: test_unsigned_v8f32_v8i32: ; CHECK-MVE-LABEL: test_unsigned_v8f32_v8i32:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8} ; CHECK-MVE-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8} ; CHECK-MVE-NEXT: vpush {d8}
; CHECK-NEXT: vcvt.u32.f32 s15, s6 ; CHECK-MVE-NEXT: vcvt.u32.f32 s15, s6
; CHECK-NEXT: vldr s8, .LCPI7_0 ; CHECK-MVE-NEXT: vldr s8, .LCPI7_0
; CHECK-NEXT: vcvt.u32.f32 s16, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s16, s4
; CHECK-NEXT: vcvt.u32.f32 s13, s7 ; CHECK-MVE-NEXT: vcvt.u32.f32 s13, s7
; CHECK-NEXT: vcvt.u32.f32 s12, s5 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s5
; CHECK-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s6, s8 ; CHECK-MVE-NEXT: vcmp.f32 s6, s8
; CHECK-NEXT: vcvt.u32.f32 s14, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s2
; CHECK-NEXT: vmov r12, s15 ; CHECK-MVE-NEXT: vmov r12, s15
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w r12, #0 ; CHECK-MVE-NEXT: movlt.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r12, #-1 ; CHECK-MVE-NEXT: movgt.w r12, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov lr, s16 ; CHECK-MVE-NEXT: vmov lr, s16
; CHECK-NEXT: vcmp.f32 s4, s8 ; CHECK-MVE-NEXT: vcmp.f32 s4, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt.w lr, #0 ; CHECK-MVE-NEXT: movlt.w lr, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.u32.f32 s9, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s9, s0
; CHECK-NEXT: vcmp.f32 s7, #0 ; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w lr, #-1 ; CHECK-MVE-NEXT: movgt.w lr, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s13 ; CHECK-MVE-NEXT: vmov r2, s13
; CHECK-NEXT: vcmp.f32 s7, s8 ; CHECK-MVE-NEXT: vcmp.f32 s7, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r2, #0 ; CHECK-MVE-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcvt.u32.f32 s11, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s11, s3
; CHECK-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1 ; CHECK-MVE-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vcvt.u32.f32 s10, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s12 ; CHECK-MVE-NEXT: vmov r3, s12
; CHECK-NEXT: vcmp.f32 s5, s8 ; CHECK-MVE-NEXT: vcmp.f32 s5, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r3, #0 ; CHECK-MVE-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1 ; CHECK-MVE-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-NEXT: vmov q1[2], q1[0], lr, r12 ; CHECK-MVE-NEXT: vmov q1[2], q1[0], lr, r12
; CHECK-NEXT: vcmp.f32 s2, s8 ; CHECK-MVE-NEXT: vcmp.f32 s2, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r0, #0 ; CHECK-MVE-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1 ; CHECK-MVE-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s9 ; CHECK-MVE-NEXT: vmov r1, s9
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2 ; CHECK-MVE-NEXT: vmov q1[3], q1[1], r3, r2
; CHECK-NEXT: vcmp.f32 s0, s8 ; CHECK-MVE-NEXT: vcmp.f32 s0, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r4, s11 ; CHECK-MVE-NEXT: vmov r4, s11
; CHECK-NEXT: vcmp.f32 s3, s8 ; CHECK-MVE-NEXT: vcmp.f32 s3, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r4, #0 ; CHECK-MVE-NEXT: movlt r4, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r5, s10 ; CHECK-MVE-NEXT: vmov r5, s10
; CHECK-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r4, #-1 ; CHECK-MVE-NEXT: movgt.w r4, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s8 ; CHECK-MVE-NEXT: vcmp.f32 s1, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r5, #0 ; CHECK-MVE-NEXT: movlt r5, #0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r5, #-1 ; CHECK-MVE-NEXT: movgt.w r5, #-1
; CHECK-NEXT: vmov q0[3], q0[1], r5, r4 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r5, r4
; CHECK-NEXT: vpop {d8} ; CHECK-MVE-NEXT: vpop {d8}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI7_0: ; CHECK-MVE-NEXT: .LCPI7_0:
; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 ; CHECK-MVE-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
;
; CHECK-MVEFP-LABEL: test_unsigned_v8f32_v8i32:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: bx lr
%x = call <8 x i32> @llvm.fptoui.sat.v8f32.v8i32(<8 x float> %f) %x = call <8 x i32> @llvm.fptoui.sat.v8f32.v8i32(<8 x float> %f)
ret <8 x i32> %x ret <8 x i32> %x
} }
; ;
; Double to signed 32-bit -- Vector size variation ; Double to signed 32-bit -- Vector size variation
; ;
▲ Show 20 Lines • Show All 1,384 Lines • ▼ Show 20 Lines
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI22_0: ; CHECK-NEXT: .LCPI22_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
%x = call <4 x i1> @llvm.fptoui.sat.v4f32.v4i1(<4 x float> %f) %x = call <4 x i1> @llvm.fptoui.sat.v4f32.v4i1(<4 x float> %f)
ret <4 x i1> %x ret <4 x i1> %x
} }
define arm_aapcs_vfpcc <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i8: ; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i8:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s4, .LCPI23_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI23_0
; CHECK-NEXT: vldr s6, .LCPI23_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI23_1
; CHECK-NEXT: vmaxnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s4
; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s4
; CHECK-NEXT: vmaxnm.f32 s8, s3, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
; CHECK-NEXT: vminnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s6
; CHECK-NEXT: vminnm.f32 s0, s0, s6 ; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s6
; CHECK-NEXT: vmaxnm.f32 s4, s1, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
; CHECK-NEXT: vminnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-NEXT: vminnm.f32 s4, s4, s6 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
; CHECK-NEXT: vcvt.u32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2
; CHECK-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-NEXT: vcvt.u32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8
; CHECK-NEXT: vcvt.u32.f32 s4, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-NEXT: vmov r0, s2 ; CHECK-MVE-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r1, s0 ; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmov r1, s4
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI23_0: ; CHECK-MVE-NEXT: .LCPI23_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
; CHECK-NEXT: .LCPI23_1: ; CHECK-MVE-NEXT: .LCPI23_1:
; CHECK-NEXT: .long 0x437f0000 @ float 255 ; CHECK-MVE-NEXT: .long 0x437f0000 @ float 255
;
; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i8:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vmov.i32 q1, #0xff
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmin.u32 q0, q0, q1
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i8> @llvm.fptoui.sat.v4f32.v4i8(<4 x float> %f) %x = call <4 x i8> @llvm.fptoui.sat.v4f32.v4i8(<4 x float> %f)
ret <4 x i8> %x ret <4 x i8> %x
} }
define arm_aapcs_vfpcc <4 x i13> @test_unsigned_v4f32_v4i13(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i13> @test_unsigned_v4f32_v4i13(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i13: ; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i13:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s4, .LCPI24_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI24_0
; CHECK-NEXT: vldr s6, .LCPI24_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI24_1
; CHECK-NEXT: vmaxnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s4
; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s4
; CHECK-NEXT: vmaxnm.f32 s8, s3, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
; CHECK-NEXT: vminnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s6
; CHECK-NEXT: vminnm.f32 s0, s0, s6 ; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s6
; CHECK-NEXT: vmaxnm.f32 s4, s1, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
; CHECK-NEXT: vminnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-NEXT: vminnm.f32 s4, s4, s6 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
; CHECK-NEXT: vcvt.u32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2
; CHECK-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-NEXT: vcvt.u32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8
; CHECK-NEXT: vcvt.u32.f32 s4, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-NEXT: vmov r0, s2 ; CHECK-MVE-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r1, s0 ; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmov r1, s4
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI24_0: ; CHECK-MVE-NEXT: .LCPI24_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
; CHECK-NEXT: .LCPI24_1: ; CHECK-MVE-NEXT: .LCPI24_1:
; CHECK-NEXT: .long 0x45fff800 @ float 8191 ; CHECK-MVE-NEXT: .long 0x45fff800 @ float 8191
;
; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i13:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x1fff
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmin.u32 q0, q0, q1
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i13> @llvm.fptoui.sat.v4f32.v4i13(<4 x float> %f) %x = call <4 x i13> @llvm.fptoui.sat.v4f32.v4i13(<4 x float> %f)
ret <4 x i13> %x ret <4 x i13> %x
} }
define arm_aapcs_vfpcc <4 x i16> @test_unsigned_v4f32_v4i16(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i16> @test_unsigned_v4f32_v4i16(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i16: ; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i16:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s4, .LCPI25_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI25_0
; CHECK-NEXT: vldr s6, .LCPI25_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI25_1
; CHECK-NEXT: vmaxnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s4
; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s4
; CHECK-NEXT: vmaxnm.f32 s8, s3, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
; CHECK-NEXT: vminnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s6
; CHECK-NEXT: vminnm.f32 s0, s0, s6 ; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s6
; CHECK-NEXT: vmaxnm.f32 s4, s1, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
; CHECK-NEXT: vminnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-NEXT: vminnm.f32 s4, s4, s6 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
; CHECK-NEXT: vcvt.u32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2
; CHECK-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-NEXT: vcvt.u32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8
; CHECK-NEXT: vcvt.u32.f32 s4, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-NEXT: vmov r0, s2 ; CHECK-MVE-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r1, s0 ; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmov r1, s4
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI25_0: ; CHECK-MVE-NEXT: .LCPI25_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
; CHECK-NEXT: .LCPI25_1: ; CHECK-MVE-NEXT: .LCPI25_1:
; CHECK-NEXT: .long 0x477fff00 @ float 65535 ; CHECK-MVE-NEXT: .long 0x477fff00 @ float 65535
;
; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i16:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vqmovnb.u32 q0, q0
; CHECK-MVEFP-NEXT: vmovlb.u16 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i16> @llvm.fptoui.sat.v4f32.v4i16(<4 x float> %f) %x = call <4 x i16> @llvm.fptoui.sat.v4f32.v4i16(<4 x float> %f)
ret <4 x i16> %x ret <4 x i16> %x
} }
define arm_aapcs_vfpcc <4 x i19> @test_unsigned_v4f32_v4i19(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i19> @test_unsigned_v4f32_v4i19(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i19: ; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i19:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s4, .LCPI26_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI26_0
; CHECK-NEXT: vldr s6, .LCPI26_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI26_1
; CHECK-NEXT: vmaxnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s4
; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s4
; CHECK-NEXT: vmaxnm.f32 s8, s3, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
; CHECK-NEXT: vminnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s6
; CHECK-NEXT: vminnm.f32 s0, s0, s6 ; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s6
; CHECK-NEXT: vmaxnm.f32 s4, s1, s4 ; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
; CHECK-NEXT: vminnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-NEXT: vminnm.f32 s4, s4, s6 ; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
; CHECK-NEXT: vcvt.u32.f32 s2, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2
; CHECK-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-NEXT: vcvt.u32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8
; CHECK-NEXT: vcvt.u32.f32 s4, s4 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s4
; CHECK-NEXT: vmov r0, s2 ; CHECK-MVE-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r1, s0 ; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r1, s4 ; CHECK-MVE-NEXT: vmov r1, s4
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI26_0: ; CHECK-MVE-NEXT: .LCPI26_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
; CHECK-NEXT: .LCPI26_1: ; CHECK-MVE-NEXT: .LCPI26_1:
; CHECK-NEXT: .long 0x48ffffe0 @ float 524287 ; CHECK-MVE-NEXT: .long 0x48ffffe0 @ float 524287
;
; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i19:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x7ffff
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmin.u32 q0, q0, q1
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i19> @llvm.fptoui.sat.v4f32.v4i19(<4 x float> %f) %x = call <4 x i19> @llvm.fptoui.sat.v4f32.v4i19(<4 x float> %f)
ret <4 x i19> %x ret <4 x i19> %x
} }
define arm_aapcs_vfpcc <4 x i32> @test_unsigned_v4f32_v4i32_duplicate(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i32> @test_unsigned_v4f32_v4i32_duplicate(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i32_duplicate: ; CHECK-MVE-LABEL: test_unsigned_v4f32_v4i32_duplicate:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vcvt.u32.f32 s10, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s2
; CHECK-NEXT: vldr s8, .LCPI27_0 ; CHECK-MVE-NEXT: vldr s8, .LCPI27_0
; CHECK-NEXT: vcvt.u32.f32 s12, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s0
; CHECK-NEXT: vcvt.u32.f32 s6, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s3
; CHECK-NEXT: vcvt.u32.f32 s4, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s1
; CHECK-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s2, s8 ; CHECK-MVE-NEXT: vcmp.f32 s2, s8
; CHECK-NEXT: vmov r0, s10 ; CHECK-MVE-NEXT: vmov r0, s10
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r0, #0 ; CHECK-MVE-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1 ; CHECK-MVE-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-NEXT: vcmp.f32 s0, s8 ; CHECK-MVE-NEXT: vcmp.f32 s0, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r1, #0 ; CHECK-MVE-NEXT: movlt r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1 ; CHECK-MVE-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r2, s6 ; CHECK-MVE-NEXT: vmov r2, s6
; CHECK-NEXT: vcmp.f32 s3, s8 ; CHECK-MVE-NEXT: vcmp.f32 s3, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r2, #0 ; CHECK-MVE-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r3, s4 ; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1 ; CHECK-MVE-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s1, s8 ; CHECK-MVE-NEXT: vcmp.f32 s1, s8
; CHECK-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-NEXT: movlt r3, #0 ; CHECK-MVE-NEXT: movlt r3, #0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1 ; CHECK-MVE-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmov q0[3], q0[1], r3, r2 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI27_0: ; CHECK-MVE-NEXT: .LCPI27_0:
; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 ; CHECK-MVE-NEXT: .long 0x4f7fffff @ float 4.29496704E+9
;
; CHECK-MVEFP-LABEL: test_unsigned_v4f32_v4i32_duplicate:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f) %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x ret <4 x i32> %x
} }
define arm_aapcs_vfpcc <4 x i50> @test_unsigned_v4f32_v4i50(<4 x float> %f) { define arm_aapcs_vfpcc <4 x i50> @test_unsigned_v4f32_v4i50(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i50: ; CHECK-LABEL: test_unsigned_v4f32_v4i50:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
▲ Show 20 Lines • Show All 2,093 Lines • ▼ Show 20 Lines
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI42_0: ; CHECK-NEXT: .LCPI42_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
%x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f) %x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f)
ret <8 x i1> %x ret <8 x i1> %x
} }
define arm_aapcs_vfpcc <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) { define arm_aapcs_vfpcc <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i8: ; CHECK-MVE-LABEL: test_unsigned_v8f16_v8i8:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s6, .LCPI43_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI43_1
; CHECK-NEXT: vcvtt.f32.f16 s10, s2 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s10, s2
; CHECK-NEXT: vcvtb.f32.f16 s2, s2 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vldr s4, .LCPI43_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI43_0
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvtt.f32.f16 s8, s3 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s8, s3
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vcvtb.f32.f16 s12, s3 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s12, s3
; CHECK-NEXT: vcvt.u32.f32 s5, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s5, s2
; CHECK-NEXT: vcvtt.f32.f16 s2, s0 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s2, s0
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvtb.f32.f16 s0, s0 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vmaxnm.f32 s0, s0, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s6
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s4
; CHECK-NEXT: vcvt.u32.f32 s7, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s7, s2
; CHECK-NEXT: vcvtb.f32.f16 s2, s1 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-NEXT: vcvtt.f32.f16 s14, s1 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s14, s1
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-NEXT: vmaxnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s8, s6
; CHECK-NEXT: vmaxnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s10, s6
; CHECK-NEXT: vmaxnm.f32 s12, s12, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s12, s6
; CHECK-NEXT: vmaxnm.f32 s14, s14, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s14, s6
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vminnm.f32 s8, s8, s4 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s4
; CHECK-NEXT: vminnm.f32 s10, s10, s4 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
; CHECK-NEXT: vminnm.f32 s12, s12, s4 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s4
; CHECK-NEXT: vminnm.f32 s14, s14, s4 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
; CHECK-NEXT: vcvt.u32.f32 s4, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s2
; CHECK-NEXT: vcvt.u32.f32 s14, s14 ; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s14
; CHECK-NEXT: vcvt.u32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s10
; CHECK-NEXT: vcvt.u32.f32 s12, s12 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s12
; CHECK-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-NEXT: vcvt.u32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-MVE-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov r0, s7 ; CHECK-MVE-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-MVE-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-MVE-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov r0, s5 ; CHECK-MVE-NEXT: vmov r0, s5
; CHECK-NEXT: vmov.16 q0[4], r0 ; CHECK-MVE-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s10 ; CHECK-MVE-NEXT: vmov r0, s10
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-MVE-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-MVE-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-MVE-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI43_0: ; CHECK-MVE-NEXT: .LCPI43_0:
; CHECK-NEXT: .long 0x437f0000 @ float 255 ; CHECK-MVE-NEXT: .long 0x437f0000 @ float 255
; CHECK-NEXT: .LCPI43_1: ; CHECK-MVE-NEXT: .LCPI43_1:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
;
; CHECK-MVEFP-LABEL: test_unsigned_v8f16_v8i8:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u16.f16 q0, q0
; CHECK-MVEFP-NEXT: vqmovnb.u16 q0, q0
; CHECK-MVEFP-NEXT: vmovlb.u8 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f) %x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x ret <8 x i8> %x
} }
define arm_aapcs_vfpcc <8 x i13> @test_unsigned_v8f16_v8i13(<8 x half> %f) { define arm_aapcs_vfpcc <8 x i13> @test_unsigned_v8f16_v8i13(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i13: ; CHECK-MVE-LABEL: test_unsigned_v8f16_v8i13:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s6, .LCPI44_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI44_1
; CHECK-NEXT: vcvtt.f32.f16 s10, s2 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s10, s2
; CHECK-NEXT: vcvtb.f32.f16 s2, s2 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vldr s4, .LCPI44_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI44_0
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvtt.f32.f16 s8, s3 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s8, s3
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vcvtb.f32.f16 s12, s3 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s12, s3
; CHECK-NEXT: vcvt.u32.f32 s5, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s5, s2
; CHECK-NEXT: vcvtt.f32.f16 s2, s0 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s2, s0
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvtb.f32.f16 s0, s0 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vmaxnm.f32 s0, s0, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s6
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s4
; CHECK-NEXT: vcvt.u32.f32 s7, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s7, s2
; CHECK-NEXT: vcvtb.f32.f16 s2, s1 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-NEXT: vcvtt.f32.f16 s14, s1 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s14, s1
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-NEXT: vmaxnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s8, s6
; CHECK-NEXT: vmaxnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s10, s6
; CHECK-NEXT: vmaxnm.f32 s12, s12, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s12, s6
; CHECK-NEXT: vmaxnm.f32 s14, s14, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s14, s6
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vminnm.f32 s8, s8, s4 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s4
; CHECK-NEXT: vminnm.f32 s10, s10, s4 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
; CHECK-NEXT: vminnm.f32 s12, s12, s4 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s4
; CHECK-NEXT: vminnm.f32 s14, s14, s4 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
; CHECK-NEXT: vcvt.u32.f32 s4, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s2
; CHECK-NEXT: vcvt.u32.f32 s14, s14 ; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s14
; CHECK-NEXT: vcvt.u32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s10
; CHECK-NEXT: vcvt.u32.f32 s12, s12 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s12
; CHECK-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-NEXT: vcvt.u32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-MVE-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov r0, s7 ; CHECK-MVE-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-MVE-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-MVE-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov r0, s5 ; CHECK-MVE-NEXT: vmov r0, s5
; CHECK-NEXT: vmov.16 q0[4], r0 ; CHECK-MVE-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s10 ; CHECK-MVE-NEXT: vmov r0, s10
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-MVE-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-MVE-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-MVE-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI44_0: ; CHECK-MVE-NEXT: .LCPI44_0:
; CHECK-NEXT: .long 0x45fff800 @ float 8191 ; CHECK-MVE-NEXT: .long 0x45fff800 @ float 8191
; CHECK-NEXT: .LCPI44_1: ; CHECK-MVE-NEXT: .LCPI44_1:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
;
; CHECK-MVEFP-LABEL: test_unsigned_v8f16_v8i13:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vmvn.i16 q1, #0xe000
; CHECK-MVEFP-NEXT: vcvt.u16.f16 q0, q0
; CHECK-MVEFP-NEXT: vmin.u16 q0, q0, q1
; CHECK-MVEFP-NEXT: bx lr
%x = call <8 x i13> @llvm.fptoui.sat.v8f16.v8i13(<8 x half> %f) %x = call <8 x i13> @llvm.fptoui.sat.v8f16.v8i13(<8 x half> %f)
ret <8 x i13> %x ret <8 x i13> %x
} }
define arm_aapcs_vfpcc <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) { define arm_aapcs_vfpcc <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i16: ; CHECK-MVE-LABEL: test_unsigned_v8f16_v8i16:
; CHECK: @ %bb.0: ; CHECK-MVE: @ %bb.0:
; CHECK-NEXT: vldr s6, .LCPI45_1 ; CHECK-MVE-NEXT: vldr s6, .LCPI45_1
; CHECK-NEXT: vcvtt.f32.f16 s10, s2 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s10, s2
; CHECK-NEXT: vcvtb.f32.f16 s2, s2 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vldr s4, .LCPI45_0 ; CHECK-MVE-NEXT: vldr s4, .LCPI45_0
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvtt.f32.f16 s8, s3 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s8, s3
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vcvtb.f32.f16 s12, s3 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s12, s3
; CHECK-NEXT: vcvt.u32.f32 s5, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s5, s2
; CHECK-NEXT: vcvtt.f32.f16 s2, s0 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s2, s0
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvtb.f32.f16 s0, s0 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vmaxnm.f32 s0, s0, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s0, s0, s6
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-MVE-NEXT: vminnm.f32 s0, s0, s4
; CHECK-NEXT: vcvt.u32.f32 s7, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s7, s2
; CHECK-NEXT: vcvtb.f32.f16 s2, s1 ; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-NEXT: vcvtt.f32.f16 s14, s1 ; CHECK-MVE-NEXT: vcvtt.f32.f16 s14, s1
; CHECK-NEXT: vmaxnm.f32 s2, s2, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-NEXT: vmaxnm.f32 s8, s8, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s8, s8, s6
; CHECK-NEXT: vmaxnm.f32 s10, s10, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s10, s10, s6
; CHECK-NEXT: vmaxnm.f32 s12, s12, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s12, s12, s6
; CHECK-NEXT: vmaxnm.f32 s14, s14, s6 ; CHECK-MVE-NEXT: vmaxnm.f32 s14, s14, s6
; CHECK-NEXT: vminnm.f32 s2, s2, s4 ; CHECK-MVE-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: vminnm.f32 s8, s8, s4 ; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s4
; CHECK-NEXT: vminnm.f32 s10, s10, s4 ; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
; CHECK-NEXT: vminnm.f32 s12, s12, s4 ; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s4
; CHECK-NEXT: vminnm.f32 s14, s14, s4 ; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
; CHECK-NEXT: vcvt.u32.f32 s4, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s2
; CHECK-NEXT: vcvt.u32.f32 s14, s14 ; CHECK-MVE-NEXT: vcvt.u32.f32 s14, s14
; CHECK-NEXT: vcvt.u32.f32 s10, s10 ; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s10
; CHECK-NEXT: vcvt.u32.f32 s12, s12 ; CHECK-MVE-NEXT: vcvt.u32.f32 s12, s12
; CHECK-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-NEXT: vcvt.u32.f32 s8, s8 ; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s8
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-MVE-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov r0, s7 ; CHECK-MVE-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.16 q0[1], r0 ; CHECK-MVE-NEXT: vmov.16 q0[1], r0
; CHECK-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-MVE-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov r0, s5 ; CHECK-MVE-NEXT: vmov r0, s5
; CHECK-NEXT: vmov.16 q0[4], r0 ; CHECK-MVE-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s10 ; CHECK-MVE-NEXT: vmov r0, s10
; CHECK-NEXT: vmov.16 q0[5], r0 ; CHECK-MVE-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-MVE-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-MVE-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-MVE-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-MVE-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI45_0: ; CHECK-MVE-NEXT: .LCPI45_0:
; CHECK-NEXT: .long 0x477fff00 @ float 65535 ; CHECK-MVE-NEXT: .long 0x477fff00 @ float 65535
; CHECK-NEXT: .LCPI45_1: ; CHECK-MVE-NEXT: .LCPI45_1:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
;
; CHECK-MVEFP-LABEL: test_unsigned_v8f16_v8i16:
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u16.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr
%x = call <8 x i16> @llvm.fptoui.sat.v8f16.v8i16(<8 x half> %f) %x = call <8 x i16> @llvm.fptoui.sat.v8f16.v8i16(<8 x half> %f)
ret <8 x i16> %x ret <8 x i16> %x
} }
define arm_aapcs_vfpcc <8 x i19> @test_unsigned_v8f16_v8i19(<8 x half> %f) { define arm_aapcs_vfpcc <8 x i19> @test_unsigned_v8f16_v8i19(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i19: ; CHECK-LABEL: test_unsigned_v8f16_v8i19:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
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