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Differential D108306

[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
ClosedPublic

Authored by Petar.Avramovic on Aug 18 2021, 10:14 AM.

Details

Reviewers
arsenm
foad
aemerson
paquette
Commits
rG2bf4eeeeb60d: [GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
Summary

When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc
have the same type (creates COPY) use Src register directly or
use replaceRegOrBuildCopy instead.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Aug 18 2021, 10:14 AM
Herald added subscribers: wenlei, kerbowa, pengfei and 7 others. · View Herald TranscriptAug 18 2021, 10:14 AM
Petar.Avramovic requested review of this revision.Aug 18 2021, 10:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 18 2021, 10:14 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B120149: Diff 367241.Aug 18 2021, 11:00 AM
aemerson added inline comments.Aug 20 2021, 2:35 PM
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
135

should this be else if?

foad accepted this revision.Aug 23 2021, 8:44 AM

LGTM!

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
135

I don't think it needs to be since SextSrc and TruncSrc are mutually exclusive.

This revision is now accepted and ready to land.Aug 23 2021, 8:44 AM
Closed by commit rG2bf4eeeeb60d: [GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner (authored by Petar.Avramovic). · Explain WhyAug 24 2021, 2:12 AM
This revision was automatically updated to reflect the committed changes.
Petar.Avramovic added a commit: rG2bf4eeeeb60d: [GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner.

Large Diff

This large diff affects 214 files. Files without inline comments have been collapsed. Expand All Files

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Diff 367241

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

Context not available.
} }
} }
public: public:
LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI, LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
const LegalizerInfo &LI) const LegalizerInfo &LI)
: Builder(B), MRI(MRI), LI(LI) {} : Builder(B), MRI(MRI), LI(LI) {}
bool tryCombineAnyExt(MachineInstr &MI, bool tryCombineAnyExt(MachineInstr &MI,
SmallVectorImpl<MachineInstr *> &DeadInsts, SmallVectorImpl<MachineInstr *> &DeadInsts,
SmallVectorImpl<Register> &UpdatedDefs) { SmallVectorImpl<Register> &UpdatedDefs,
GISelObserverWrapper &Observer) {
assert(MI.getOpcode() == TargetOpcode::G_ANYEXT); assert(MI.getOpcode() == TargetOpcode::G_ANYEXT);
Builder.setInstrAndDebugLoc(MI); Builder.setInstrAndDebugLoc(MI);
Register DstReg = MI.getOperand(0).getReg(); Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
// aext(trunc x) - > aext/copy/trunc x // aext(trunc x) - > aext/copy/trunc x
Register TruncSrc; Register TruncSrc;
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;); LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
Builder.buildAnyExtOrTrunc(DstReg, TruncSrc); if (MRI.getType(DstReg) == MRI.getType(TruncSrc))
replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs,
Observer);
else
Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
UpdatedDefs.push_back(DstReg); UpdatedDefs.push_back(DstReg);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true; return true;
} }
// aext([asz]ext x) -> [asz]ext x // aext([asz]ext x) -> [asz]ext x
Register ExtSrc; Register ExtSrc;
MachineInstr *ExtMI; MachineInstr *ExtMI;
if (mi_match(SrcReg, MRI, if (mi_match(SrcReg, MRI,
m_all_of(m_MInstr(ExtMI), m_any_of(m_GAnyExt(m_Reg(ExtSrc)), m_all_of(m_MInstr(ExtMI), m_any_of(m_GAnyExt(m_Reg(ExtSrc)),
Context not available.
mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) { mi_match(SrcReg, MRI, m_GSExt(m_Reg(SextSrc)))) {
LLT DstTy = MRI.getType(DstReg); LLT DstTy = MRI.getType(DstReg);
if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) || if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
isConstantUnsupported(DstTy)) isConstantUnsupported(DstTy))
return false; return false;
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;); LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLT SrcTy = MRI.getType(SrcReg); LLT SrcTy = MRI.getType(SrcReg);
APInt MaskVal = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits()); APInt MaskVal = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
auto Mask = Builder.buildConstant( auto Mask = Builder.buildConstant(
DstTy, MaskVal.zext(DstTy.getScalarSizeInBits())); DstTy, MaskVal.zext(DstTy.getScalarSizeInBits()));
auto Extended = SextSrc ? Builder.buildSExtOrTrunc(DstTy, SextSrc) : if (SextSrc && (DstTy != MRI.getType(SextSrc)))
Builder.buildAnyExtOrTrunc(DstTy, TruncSrc); SextSrc = Builder.buildSExtOrTrunc(DstTy, SextSrc).getReg(0);
Builder.buildAnd(DstReg, Extended, Mask); if (TruncSrc && (DstTy != MRI.getType(TruncSrc)))
aemersonUnsubmitted
Not Done
ReplyInline Actions

should this be else if?

aemerson: should this be `else if`?
foadUnsubmitted
Not Done
ReplyInline Actions

I don't think it needs to be since SextSrc and TruncSrc are mutually exclusive.

foad: I don't think it needs to be since SextSrc and TruncSrc are mutually exclusive.
TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
Builder.buildAnd(DstReg, SextSrc ? SextSrc : TruncSrc, Mask);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true; return true;
} }
// zext(zext x) -> (zext x) // zext(zext x) -> (zext x)
Register ZextSrc; Register ZextSrc;
if (mi_match(SrcReg, MRI, m_GZExt(m_Reg(ZextSrc)))) { if (mi_match(SrcReg, MRI, m_GZExt(m_Reg(ZextSrc)))) {
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI); LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
Observer.changingInstr(MI); Observer.changingInstr(MI);
MI.getOperand(1).setReg(ZextSrc); MI.getOperand(1).setReg(ZextSrc);
Context not available.
// sext(trunc x) - > (sext_inreg (aext/copy/trunc x), c) // sext(trunc x) - > (sext_inreg (aext/copy/trunc x), c)
Register TruncSrc; Register TruncSrc;
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
LLT DstTy = MRI.getType(DstReg); LLT DstTy = MRI.getType(DstReg);
if (isInstUnsupported({TargetOpcode::G_SEXT_INREG, {DstTy}})) if (isInstUnsupported({TargetOpcode::G_SEXT_INREG, {DstTy}}))
return false; return false;
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;); LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLT SrcTy = MRI.getType(SrcReg); LLT SrcTy = MRI.getType(SrcReg);
uint64_t SizeInBits = SrcTy.getScalarSizeInBits(); uint64_t SizeInBits = SrcTy.getScalarSizeInBits();
Builder.buildInstr( if (DstTy != MRI.getType(TruncSrc))
TargetOpcode::G_SEXT_INREG, {DstReg}, TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
{Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), SizeInBits}); Builder.buildSExtInReg(DstReg, TruncSrc, SizeInBits);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true; return true;
} }
// sext(zext x) -> (zext x) // sext(zext x) -> (zext x)
// sext(sext x) -> (sext x) // sext(sext x) -> (sext x)
Register ExtSrc; Register ExtSrc;
MachineInstr *ExtMI; MachineInstr *ExtMI;
if (mi_match(SrcReg, MRI, if (mi_match(SrcReg, MRI,
m_all_of(m_MInstr(ExtMI), m_any_of(m_GZExt(m_Reg(ExtSrc)), m_all_of(m_MInstr(ExtMI), m_any_of(m_GZExt(m_Reg(ExtSrc)),
Context not available.
// Put here every vreg that was redefined in such a way that it's at least // Put here every vreg that was redefined in such a way that it's at least
// possible that one (or more) of its users (immediate or COPY-separated) // possible that one (or more) of its users (immediate or COPY-separated)
// could become artifact combinable with the new definition (or the // could become artifact combinable with the new definition (or the
// instruction reachable from it through a chain of copies if any). // instruction reachable from it through a chain of copies if any).
SmallVector<Register, 4> UpdatedDefs; SmallVector<Register, 4> UpdatedDefs;
bool Changed = false; bool Changed = false;
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: default:
return false; return false;
case TargetOpcode::G_ANYEXT: case TargetOpcode::G_ANYEXT:
Changed = tryCombineAnyExt(MI, DeadInsts, UpdatedDefs); Changed = tryCombineAnyExt(MI, DeadInsts, UpdatedDefs, WrapperObserver);
break; break;
case TargetOpcode::G_ZEXT: case TargetOpcode::G_ZEXT:
Changed = tryCombineZExt(MI, DeadInsts, UpdatedDefs, WrapperObserver); Changed = tryCombineZExt(MI, DeadInsts, UpdatedDefs, WrapperObserver);
break; break;
case TargetOpcode::G_SEXT: case TargetOpcode::G_SEXT:
Changed = tryCombineSExt(MI, DeadInsts, UpdatedDefs); Changed = tryCombineSExt(MI, DeadInsts, UpdatedDefs);
break; break;
case TargetOpcode::G_UNMERGE_VALUES: case TargetOpcode::G_UNMERGE_VALUES:
Changed = tryCombineUnmergeValues(cast<GUnmerge>(MI), DeadInsts, Changed = tryCombineUnmergeValues(cast<GUnmerge>(MI), DeadInsts,
UpdatedDefs, WrapperObserver); UpdatedDefs, WrapperObserver);
Context not available.

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir

llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-casts.mir

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir

llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll

llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll

llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir

llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir

llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir

llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir

llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir

llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir

llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll

llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll

llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir

llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir

llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir

llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp