[PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

[NeHuang]

Summary

This patch adds a fix to do early if conversion to select when conditional branch not using physical register to prevent the crash when expanding ISEL instruction.

[lei]

I think there is something wrong with this diff cause there is no context available for PPCInstrInfo.cpp.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

1548

nit: no need for braces

llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll

2

I believe this affects AIX as well.

[amyk]

Please update the patch with full context.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

1546

nit: uses a physical register

llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll

3

Are the target datalayout and target triple necessary?

[NeHuang]

Address review comment.

[kamaub]

This LGTM, small nit on the comment, but that can be fixed on commit

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

1544

nit

[NeHuang]

Address review comments

• typo update
• use proper mcpu in the test case.

[lei]

LGTM
Thx!

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
     return false;
 
+  // If the condition branch uses physical register, then it cannot be turned
+  // into a select.
+  if (Register::isPhysicalRegister(Cond[1].getReg())) {
+    return false;
+  }
+
   // Check register classes.
   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   const TargetRegisterClass *RC =

llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+
+define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vcmpgtsw. 2, 2, 3
+; CHECK-NEXT:    bge 6, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %land.rhs
+; CHECK-NEXT:    vcmpgtsw. 2, 4, 3
+; CHECK-NEXT:    mfocrf 3, 2
+; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:    clrldi 3, 3, 32
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %land.end, label %land.rhs
+
+land.rhs:                                         ; preds = %entry
+  %1 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %c, <4 x i32> %b)
+  %tobool1 = icmp ne i32 %1, 0
+  %phi.cast = zext i1 %tobool1 to i32
+  br label %land.end
+
+land.end:                                         ; preds = %land.rhs, %entry
+  %2 = phi i32 [ 0, %entry ], [ %phi.cast, %land.rhs ]
+  ret i32 %2
+}
+
+; Function Attrs: nofree nosync nounwind readnone
+declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)