[RISCV] Optimize mul in the zba extension with SH*ADD

[benshi001]

Summary

This patch does the following optimization of mul with a constant in RV64.

(sext_inreg (mul x, 3 * power_of_2), i32) -> (SLLIW (SH1ADD x, x), bits)
(sext_inreg (mul x, 5 * power_of_2), i32) -> (SLLIW (SH2ADD x, x), bits)
(sext_inreg (mul x, 9 * power_of_2), i32) -> (SLLIW (SH3ADD x, x), bits)

[craig.topper]

If D107708 is accepted this will no longer be necessary.

[benshi001]

In D107820#2937131, @craig.topper wrote:

If D107708 is accepted this will no longer be necessary.

That is great. And I still suggest D107817 be merged, since we have not checked optimization of SHXADD with i32 type in rv64.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

def : Pat<(i64 (add (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 3)), non_imm12:$rs2)),
           (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
 
 def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 1)), 0x1FFFFFFFF), non_imm12:$rs2)),
           (SH1ADDUW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 2)), 0x3FFFFFFFF), non_imm12:$rs2)),
           (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF), non_imm12:$rs2)),
           (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(i64 (sext_inreg (mul GPR:$r, C3LeftShift:$i), i32)),
+          (SLLIW (SH1ADD GPR:$r, GPR:$r),
+                 (TrailingZerosXForm C3LeftShift:$i))>;
+def : Pat<(i64 (sext_inreg (mul GPR:$r, C5LeftShift:$i), i32)),
+          (SLLIW (SH2ADD GPR:$r, GPR:$r),
+                 (TrailingZerosXForm C5LeftShift:$i))>;
+def : Pat<(i64 (sext_inreg (mul GPR:$r, C9LeftShift:$i), i32)),
+          (SLLIW (SH3ADD GPR:$r, GPR:$r),
+                 (TrailingZerosXForm C9LeftShift:$i))>;
 } // Predicates = [HasStdExtZba, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def : PatGprGpr<riscv_rolw, ROLW>;
 def : PatGprGpr<riscv_rorw, RORW>;
 def : PatGprImm<riscv_rorw, RORIW, uimm5>;
 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
           (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64I-LABEL: mulw192:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 192
 ; RV64I-NEXT:    mulw a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: mulw192:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a1, zero, 192
-; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    sh1add a0, a0, a0
+; RV64IB-NEXT:    slliw a0, a0, 6
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: mulw192:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a1, zero, 192
-; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    sh1add a0, a0, a0
+; RV64IBA-NEXT:    slliw a0, a0, 6
 ; RV64IBA-NEXT:    ret
   %c = mul i32 %a, 192
   ret i32 %c
 }
 
 define signext i32 @mulw320(i32 signext %a) {
 ; RV64I-LABEL: mulw320:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 320
 ; RV64I-NEXT:    mulw a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: mulw320:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a1, zero, 320
-; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    sh2add a0, a0, a0
+; RV64IB-NEXT:    slliw a0, a0, 6
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: mulw320:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a1, zero, 320
-; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    sh2add a0, a0, a0
+; RV64IBA-NEXT:    slliw a0, a0, 6
 ; RV64IBA-NEXT:    ret
   %c = mul i32 %a, 320
   ret i32 %c
 }
 
 define signext i32 @mulw576(i32 signext %a) {
 ; RV64I-LABEL: mulw576:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 576
 ; RV64I-NEXT:    mulw a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: mulw576:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a1, zero, 576
-; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    sh3add a0, a0, a0
+; RV64IB-NEXT:    slliw a0, a0, 6
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: mulw576:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a1, zero, 576
-; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    sh3add a0, a0, a0
+; RV64IBA-NEXT:    slliw a0, a0, 6
 ; RV64IBA-NEXT:    ret
   %c = mul i32 %a, 576
   ret i32 %c
 }