[RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD

[craig.topper]

LGTM

[jrtc27]

llvm/test/CodeGen/RISCV/rv64zba.ll

7

Ugh this is confusing, should be RV64IBZBA, not RV64IBA (which would mean integer, bitmanip and atomics, albeit in a non-canonical order, which makes no sense for this test)

[benshi001]

llvm/test/CodeGen/RISCV/rv64zba.ll

7

Sure. I will correct that before 'git push'

[craig.topper]

llvm/test/CodeGen/RISCV/rv64zba.ll

7

Why RV64IBZBA and not RV64IZBA? Should the M be mentioned for the +m?

All of the B extension tests are like this and have been since they were created.

7

Please don't. All the tests should be corrected at once and not part of this patch.

[jrtc27]

llvm/test/CodeGen/RISCV/rv64zba.ll

7

Oh, yes, RV64IZBA is what I mean here. The M probably should be there too, I think in general we either do something approximating the full arch string or we do just RV64X for the specific extension being tested (i.e. you'd drop the I for the IB and I(Z)BA ones), which would also be fine by me.

[benshi001]

llvm/test/CodeGen/RISCV/rv64zba.ll

7

OK. I will only push the part I have added.

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-b -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64IB
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64IBA
 
 define i64 @slliuw(i64 %a) nounwind {
 ; RV64I-LABEL: slliuw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 31
 ; RV64I-NEXT:    ret
 ;

 ; RV64IBA-LABEL: mul4104:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    slli a1, a0, 12
 ; RV64IBA-NEXT:    sh3add a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 4104
   ret i64 %c
 }
+
+define signext i32 @mulw192(i32 signext %a) {
+; RV64I-LABEL: mulw192:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 192
+; RV64I-NEXT:    mulw a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mulw192:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 192
+; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mulw192:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 192
+; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i32 %a, 192
+  ret i32 %c
+}
+
+define signext i32 @mulw320(i32 signext %a) {
+; RV64I-LABEL: mulw320:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 320
+; RV64I-NEXT:    mulw a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mulw320:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 320
+; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mulw320:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 320
+; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i32 %a, 320
+  ret i32 %c
+}
+
+define signext i32 @mulw576(i32 signext %a) {
+; RV64I-LABEL: mulw576:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 576
+; RV64I-NEXT:    mulw a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mulw576:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    addi a1, zero, 576
+; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mulw576:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    addi a1, zero, 576
+; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i32 %a, 576
+  ret i32 %c
+}