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Differential D107642

[ARM] Enable subreg liveness
ClosedPublic

Authored by dmgreen on Aug 6 2021, 6:25 AM.

Details

Reviewers
SjoerdMeijer
samtebbs
NickGuy
simon_tatham
ostannard
Commits
rG52e0cf9d6161: [ARM] Enable subreg liveness
Summary

This enables subreg liveness in the arm backend when MVE is present, which allows the register allocator to detect when subregister are alive/dead, compared to only acting on full registers. This can helps produce better code on MVE with the way MQPR registers are made up of SPR registers, but is especially helpful for MQQPR and MQQQQPR registers, where there are very few "registers" available and being able to split them up into subregs can help produce much better code.

For MQQPR and MQQQQPR we currently spill them using VLDMDIA with d-subregs for each part. This doesn't pass verifier checks as the constituent parts can sometimes be undefined at point of use. So this patch also adds MQQPRLoad and MQQPRStore pseudo instructions that can take the entire register and be lowered later in the pipeline. They still end up as VLDMIA/VSTMIA instructions, but hold the original larger register. This has the added benefit that we can more easily return the correct value from isStoreToStackSlot, allowing the regallocator to potentially produce better code.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 6 2021, 6:25 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptAug 6 2021, 6:25 AM
dmgreen requested review of this revision.Aug 6 2021, 6:25 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 6 2021, 6:25 AM
dmgreen added a parent revision: D107463: [ARM] Create MQQPR and MQQQQPR register classes.Aug 6 2021, 6:25 AM
Harbormaster completed remote builds in B118369: Diff 364771.Aug 6 2021, 7:26 AM
samtebbs accepted this revision.Aug 9 2021, 5:40 AM

Nice work

This revision is now accepted and ready to land.Aug 9 2021, 5:40 AM
dmgreen mentioned this in rG62e892fa2d4f: [ARM] Add MQQPR and MQQQQPR spill and reload pseudo instructions.Aug 17 2021, 5:51 AM
This revision was landed with ongoing or failed builds.Aug 17 2021, 6:10 AM
Closed by commit rG52e0cf9d6161: [ARM] Enable subreg liveness (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG52e0cf9d6161: [ARM] Enable subreg liveness.

Revision Contents

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llvm/
lib/
Target/
ARM/
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test/
CodeGen/
Thumb2/
LowOverheadLoops/
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Diff 366876

llvm/lib/Target/ARM/ARMSubtarget.cpp

Show First 20 Lines • Show All 383 Lines • ▼ Show 20 Linesbool ARMSubtarget::enableMachineScheduler() const {
// Machine scheduler, relying on the DAG register pressure scheduler instead. // Machine scheduler, relying on the DAG register pressure scheduler instead.
if (isMClass() && hasMinSize()) if (isMClass() && hasMinSize())
return false; return false;
// Enable the MachineScheduler before register allocation for subtargets // Enable the MachineScheduler before register allocation for subtargets
// with the use-misched feature. // with the use-misched feature.
return useMachineScheduler(); return useMachineScheduler();
} }
bool ARMSubtarget::enableSubRegLiveness() const { return EnableSubRegLiveness; } bool ARMSubtarget::enableSubRegLiveness() const {
if (EnableSubRegLiveness.getNumOccurrences())
return EnableSubRegLiveness;
// Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs
// and q subregs for qqqqpr regs.
return hasMVEIntegerOps();
}
// This overrides the PostRAScheduler bit in the SchedModel for any CPU. // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
bool ARMSubtarget::enablePostRAScheduler() const { bool ARMSubtarget::enablePostRAScheduler() const {
if (enableMachineScheduler()) if (enableMachineScheduler())
return false; return false;
if (disablePostRAScheduler()) if (disablePostRAScheduler())
return false; return false;
// Thumb1 cores will generally not benefit from post-ra scheduling // Thumb1 cores will generally not benefit from post-ra scheduling
▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll

Show First 20 Lines • Show All 221 Lines • ▼ Show 20 Lines
; CHECK-NEXT: le lr, .LBB1_2 ; CHECK-NEXT: le lr, .LBB1_2
; CHECK-NEXT: @ %bb.3: @ %middle.block ; CHECK-NEXT: @ %bb.3: @ %middle.block
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vadd.f32 q0, q0, r0 ; CHECK-NEXT: vadd.f32 q0, q0, r0
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .LBB1_4: ; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: vldr s0, .LCPI1_0 ; CHECK-NEXT: vldr s0, .LCPI1_0
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.5: ; CHECK-NEXT: @ %bb.5:
; CHECK-NEXT: .LCPI1_0: ; CHECK-NEXT: .LCPI1_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
entry: entry:
%cmp8 = icmp eq i32 %N, 0 %cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %vector.ph br i1 %cmp8, label %for.cond.cleanup, label %vector.ph
Show All 32 Linesfor.cond.cleanup: ; preds = %middle.block, %entry
%a.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %9, %middle.block ] %a.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %9, %middle.block ]
ret float %a.0.lcssa ret float %a.0.lcssa
} }
define arm_aapcs_vfpcc float @fast_float_half_mac(half* nocapture readonly %b, half* nocapture readonly %c, i32 %N) { define arm_aapcs_vfpcc float @fast_float_half_mac(half* nocapture readonly %b, half* nocapture readonly %c, i32 %N) {
; CHECK-LABEL: fast_float_half_mac: ; CHECK-LABEL: fast_float_half_mac:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: beq.w .LBB2_20 ; CHECK-NEXT: beq.w .LBB2_20
; CHECK-NEXT: @ %bb.1: @ %vector.ph ; CHECK-NEXT: @ %bb.1: @ %vector.ph
; CHECK-NEXT: adds r3, r2, #3 ; CHECK-NEXT: adds r3, r2, #3
; CHECK-NEXT: vmov.i32 q5, #0x0 ; CHECK-NEXT: vmov.i32 q5, #0x0
; CHECK-NEXT: bic r3, r3, #3 ; CHECK-NEXT: bic r3, r3, #3
; CHECK-NEXT: sub.w r12, r3, #4 ; CHECK-NEXT: sub.w r12, r3, #4
; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: movs r3, #1
; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2
; CHECK-NEXT: sub.w r12, r2, #1 ; CHECK-NEXT: sub.w r12, r2, #1
; CHECK-NEXT: adr r2, .LCPI2_1 ; CHECK-NEXT: adr r2, .LCPI2_1
; CHECK-NEXT: mov lr, lr ; CHECK-NEXT: mov lr, lr
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vdup.32 q1, r12 ; CHECK-NEXT: vdup.32 q1, r12
; CHECK-NEXT: vdup.32 q2, r12 ; CHECK-NEXT: vdup.32 q2, r12
; CHECK-NEXT: b .LBB2_3 ; CHECK-NEXT: b .LBB2_3
; CHECK-NEXT: .LBB2_2: @ %else26 ; CHECK-NEXT: .LBB2_2: @ %else26
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vmul.f16 q5, q6, q5 ; CHECK-NEXT: vmul.f16 q5, q6, q5
; CHECK-NEXT: adds r0, #8 ; CHECK-NEXT: adds r0, #8
; CHECK-NEXT: vcvtt.f32.f16 s27, s21 ; CHECK-NEXT: vcvtt.f32.f16 s23, s21
; CHECK-NEXT: vcvtb.f32.f16 s22, s21
; CHECK-NEXT: vcvtt.f32.f16 s21, s20
; CHECK-NEXT: vcvtb.f32.f16 s20, s20
; CHECK-NEXT: adds r1, #8 ; CHECK-NEXT: adds r1, #8
; CHECK-NEXT: vcvtb.f32.f16 s26, s21
; CHECK-NEXT: adds r3, #4 ; CHECK-NEXT: adds r3, #4
; CHECK-NEXT: vcvtt.f32.f16 s25, s20 ; CHECK-NEXT: vadd.f32 q5, q3, q5
; CHECK-NEXT: vcvtb.f32.f16 s24, s20
; CHECK-NEXT: vadd.f32 q5, q3, q6
; CHECK-NEXT: subs.w lr, lr, #1 ; CHECK-NEXT: subs.w lr, lr, #1
; CHECK-NEXT: bne .LBB2_3 ; CHECK-NEXT: bne .LBB2_3
; CHECK-NEXT: b .LBB2_19 ; CHECK-NEXT: b .LBB2_19
; CHECK-NEXT: .LBB2_3: @ %vector.body ; CHECK-NEXT: .LBB2_3: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vadd.i32 q4, q0, r3 ; CHECK-NEXT: vadd.i32 q4, q0, r3
; CHECK-NEXT: vmov q3, q5 ; CHECK-NEXT: vmov q3, q5
; CHECK-NEXT: vcmp.u32 cs, q1, q4 ; CHECK-NEXT: vcmp.u32 cs, q1, q4
Show All 23 Lines
; CHECK-NEXT: lsls r4, r2, #29 ; CHECK-NEXT: lsls r4, r2, #29
; CHECK-NEXT: bmi .LBB2_14 ; CHECK-NEXT: bmi .LBB2_14
; CHECK-NEXT: .LBB2_6: @ %else10 ; CHECK-NEXT: .LBB2_6: @ %else10
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: lsls r2, r2, #28 ; CHECK-NEXT: lsls r2, r2, #28
; CHECK-NEXT: bpl .LBB2_8 ; CHECK-NEXT: bpl .LBB2_8
; CHECK-NEXT: .LBB2_7: @ %cond.load12 ; CHECK-NEXT: .LBB2_7: @ %cond.load12
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s24, [r0, #6] ; CHECK-NEXT: vldr.16 s22, [r0, #6]
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vins.f16 s21, s22
; CHECK-NEXT: .LBB2_8: @ %else13 ; CHECK-NEXT: .LBB2_8: @ %else13
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vcmp.u32 cs, q2, q4 ; CHECK-NEXT: vcmp.u32 cs, q2, q4
; CHECK-NEXT: @ implicit-def: $q6 ; CHECK-NEXT: @ implicit-def: $q6
; CHECK-NEXT: vmrs r4, p0 ; CHECK-NEXT: vmrs r4, p0
; CHECK-NEXT: and r2, r4, #1 ; CHECK-NEXT: and r2, r4, #1
; CHECK-NEXT: rsbs r5, r2, #0 ; CHECK-NEXT: rsbs r5, r2, #0
; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: movs r2, #0
Show All 24 Lines
; CHECK-NEXT: b .LBB2_18 ; CHECK-NEXT: b .LBB2_18
; CHECK-NEXT: .LBB2_12: @ %cond.load ; CHECK-NEXT: .LBB2_12: @ %cond.load
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s20, [r0] ; CHECK-NEXT: vldr.16 s20, [r0]
; CHECK-NEXT: lsls r4, r2, #30 ; CHECK-NEXT: lsls r4, r2, #30
; CHECK-NEXT: bpl .LBB2_5 ; CHECK-NEXT: bpl .LBB2_5
; CHECK-NEXT: .LBB2_13: @ %cond.load6 ; CHECK-NEXT: .LBB2_13: @ %cond.load6
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s24, [r0, #2] ; CHECK-NEXT: vldr.16 s22, [r0, #2]
; CHECK-NEXT: vins.f16 s20, s24 ; CHECK-NEXT: vins.f16 s20, s22
; CHECK-NEXT: lsls r4, r2, #29 ; CHECK-NEXT: lsls r4, r2, #29
; CHECK-NEXT: bpl .LBB2_6 ; CHECK-NEXT: bpl .LBB2_6
; CHECK-NEXT: .LBB2_14: @ %cond.load9 ; CHECK-NEXT: .LBB2_14: @ %cond.load9
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vmovx.f16 s24, s21
; CHECK-NEXT: vldr.16 s21, [r0, #4] ; CHECK-NEXT: vldr.16 s21, [r0, #4]
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vmovx.f16 s22, s0
; CHECK-NEXT: vins.f16 s21, s22
; CHECK-NEXT: lsls r2, r2, #28 ; CHECK-NEXT: lsls r2, r2, #28
; CHECK-NEXT: bmi .LBB2_7 ; CHECK-NEXT: bmi .LBB2_7
; CHECK-NEXT: b .LBB2_8 ; CHECK-NEXT: b .LBB2_8
; CHECK-NEXT: .LBB2_15: @ %cond.load16 ; CHECK-NEXT: .LBB2_15: @ %cond.load16
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s24, [r1] ; CHECK-NEXT: vldr.16 s24, [r1]
; CHECK-NEXT: lsls r4, r2, #30 ; CHECK-NEXT: lsls r4, r2, #30
; CHECK-NEXT: bpl .LBB2_10 ; CHECK-NEXT: bpl .LBB2_10
; CHECK-NEXT: .LBB2_16: @ %cond.load19 ; CHECK-NEXT: .LBB2_16: @ %cond.load19
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s28, [r1, #2] ; CHECK-NEXT: vldr.16 s26, [r1, #2]
; CHECK-NEXT: vins.f16 s24, s28 ; CHECK-NEXT: vins.f16 s24, s26
; CHECK-NEXT: lsls r4, r2, #29 ; CHECK-NEXT: lsls r4, r2, #29
; CHECK-NEXT: bpl .LBB2_11 ; CHECK-NEXT: bpl .LBB2_11
; CHECK-NEXT: .LBB2_17: @ %cond.load22 ; CHECK-NEXT: .LBB2_17: @ %cond.load22
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vmovx.f16 s28, s25
; CHECK-NEXT: vldr.16 s25, [r1, #4] ; CHECK-NEXT: vldr.16 s25, [r1, #4]
; CHECK-NEXT: vins.f16 s25, s28 ; CHECK-NEXT: vmovx.f16 s26, s0
; CHECK-NEXT: vins.f16 s25, s26
; CHECK-NEXT: lsls r2, r2, #28 ; CHECK-NEXT: lsls r2, r2, #28
; CHECK-NEXT: bpl.w .LBB2_2 ; CHECK-NEXT: bpl.w .LBB2_2
; CHECK-NEXT: .LBB2_18: @ %cond.load25 ; CHECK-NEXT: .LBB2_18: @ %cond.load25
; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_3 Depth=1
; CHECK-NEXT: vldr.16 s28, [r1, #6] ; CHECK-NEXT: vldr.16 s26, [r1, #6]
; CHECK-NEXT: vins.f16 s25, s28 ; CHECK-NEXT: vins.f16 s25, s26
; CHECK-NEXT: b .LBB2_2 ; CHECK-NEXT: b .LBB2_2
; CHECK-NEXT: .LBB2_19: @ %middle.block ; CHECK-NEXT: .LBB2_19: @ %middle.block
; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: vcmp.u32 cs, q0, q4 ; CHECK-NEXT: vcmp.u32 cs, q0, q4
; CHECK-NEXT: vpsel q0, q5, q3 ; CHECK-NEXT: vpsel q0, q5, q3
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vadd.f32 q0, q0, r0 ; CHECK-NEXT: vadd.f32 q0, q0, r0
; CHECK-NEXT: b .LBB2_21 ; CHECK-NEXT: b .LBB2_21
; CHECK-NEXT: .LBB2_20: ; CHECK-NEXT: .LBB2_20:
; CHECK-NEXT: vldr s0, .LCPI2_0 ; CHECK-NEXT: vldr s0, .LCPI2_0
; CHECK-NEXT: .LBB2_21: @ %for.cond.cleanup ; CHECK-NEXT: .LBB2_21: @ %for.cond.cleanup
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: add sp, #8 ; CHECK-NEXT: add sp, #8
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.22: ; CHECK-NEXT: @ %bb.22:
; CHECK-NEXT: .LCPI2_1: ; CHECK-NEXT: .LCPI2_1:
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .long 1 @ 0x1 ; CHECK-NEXT: .long 1 @ 0x1
; CHECK-NEXT: .long 2 @ 0x2 ; CHECK-NEXT: .long 2 @ 0x2
; CHECK-NEXT: .long 3 @ 0x3 ; CHECK-NEXT: .long 3 @ 0x3
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -tail-predication=enabled -mtriple=thumbv8.1m.main -mattr=+mve,+mve.fp %s -o - | FileCheck %s ; RUN: llc -O3 -tail-predication=enabled -mtriple=thumbv8.1m.main -mattr=+mve,+mve.fp %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m-arm-none-eabi" target triple = "thumbv8.1m-arm-none-eabi"
; Tests that LSR will not interfere with the VCTP intrinsic, ; Tests that LSR will not interfere with the VCTP intrinsic,
; and that this loop will correctly become tail-predicated. ; and that this loop will correctly become tail-predicated.
define arm_aapcs_vfpcc float @vctpi32(float* %0, i32 %1) { define arm_aapcs_vfpcc float @vctpi32(float* %0, i32 %1) {
; CHECK-LABEL: vctpi32: ; CHECK-LABEL: vctpi32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vmvn.i32 q1, #0x1f ; CHECK-NEXT: vmvn.i32 q1, #0x1f
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: vadd.i32 q1, q3, q1
; CHECK-NEXT: subs r3, r1, #1 ; CHECK-NEXT: subs r3, r1, #1
; CHECK-NEXT: vadd.i32 q1, q3, q1
; CHECK-NEXT: vidup.u32 q2, r2, #8 ; CHECK-NEXT: vidup.u32 q2, r2, #8
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vadd.i32 q1, q2, r0 ; CHECK-NEXT: vadd.i32 q1, q2, r0
; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: dlstp.32 lr, r3 ; CHECK-NEXT: dlstp.32 lr, r3
; CHECK-NEXT: .LBB0_1: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: .LBB0_1: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q2, [q1, #32]! ; CHECK-NEXT: vldrw.u32 q2, [q1, #32]!
; CHECK-NEXT: vadd.f32 q0, q0, q2 ; CHECK-NEXT: vadd.f32 q0, q0, q2
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll

Show All 9 Lines
; CHECK-NEXT: mov r12, r0 ; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: dlstp.32 lr, r1 ; CHECK-NEXT: dlstp.32 lr, r1
; CHECK-NEXT: .LBB0_1: @ %do.body.i ; CHECK-NEXT: .LBB0_1: @ %do.body.i
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r12], #16 ; CHECK-NEXT: vldrw.u32 q1, [r12], #16
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: letp lr, .LBB0_1 ; CHECK-NEXT: letp lr, .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %arm_mean_f32_mve.exit ; CHECK-NEXT: @ %bb.2: @ %arm_mean_f32_mve.exit
; CHECK-NEXT: vmov s4, r1 ; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: vadd.f32 s0, s3, s3 ; CHECK-NEXT: vadd.f32 s2, s3, s3
; CHECK-NEXT: vcvt.f32.u32 s4, s4 ; CHECK-NEXT: vcvt.f32.u32 s0, s0
; CHECK-NEXT: vdiv.f32 s0, s0, s4 ; CHECK-NEXT: vdiv.f32 s0, s2, s0
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: vmov r12, s0
; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: dlstp.32 lr, r1 ; CHECK-NEXT: dlstp.32 lr, r1
; CHECK-NEXT: .LBB0_3: @ %do.body ; CHECK-NEXT: .LBB0_3: @ %do.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: vsub.f32 q1, q1, r12 ; CHECK-NEXT: vsub.f32 q1, q1, r12
; CHECK-NEXT: vfma.f32 q0, q1, q1 ; CHECK-NEXT: vfma.f32 q0, q1, q1
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll

Show First 20 Lines • Show All 980 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.32 q0[0], r9 ; CHECK-NEXT: vmov.32 q0[0], r9
; CHECK-NEXT: ldr.w r10, [r5, #4] ; CHECK-NEXT: ldr.w r10, [r5, #4]
; CHECK-NEXT: vmov.32 q1[0], r7 ; CHECK-NEXT: vmov.32 q1[0], r7
; CHECK-NEXT: vmov.32 q0[1], r8 ; CHECK-NEXT: vmov.32 q0[1], r8
; CHECK-NEXT: adds r4, #8 ; CHECK-NEXT: adds r4, #8
; CHECK-NEXT: vmov.32 q1[1], r10 ; CHECK-NEXT: vmov.32 q1[1], r10
; CHECK-NEXT: adds r5, #8 ; CHECK-NEXT: adds r5, #8
; CHECK-NEXT: vmul.f16 q0, q0, q1 ; CHECK-NEXT: vmul.f16 q0, q0, q1
; CHECK-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vstrb.8 q1, [r6], #16 ; CHECK-NEXT: vstrb.8 q0, [r6], #16
; CHECK-NEXT: le lr, .LBB5_4 ; CHECK-NEXT: le lr, .LBB5_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r12, r3 ; CHECK-NEXT: cmp r12, r3
; CHECK-NEXT: beq .LBB5_8 ; CHECK-NEXT: beq .LBB5_8
; CHECK-NEXT: .LBB5_6: @ %for.body.preheader11 ; CHECK-NEXT: .LBB5_6: @ %for.body.preheader11
; CHECK-NEXT: sub.w lr, r3, r12 ; CHECK-NEXT: sub.w lr, r3, r12
; CHECK-NEXT: add.w r0, r0, r12, lsl #1 ; CHECK-NEXT: add.w r0, r0, r12, lsl #1
; CHECK-NEXT: add.w r1, r1, r12, lsl #1 ; CHECK-NEXT: add.w r1, r1, r12, lsl #1
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; CHECK-NEXT: vmov.32 q0[0], r9 ; CHECK-NEXT: vmov.32 q0[0], r9
; CHECK-NEXT: ldr.w r10, [r5, #4] ; CHECK-NEXT: ldr.w r10, [r5, #4]
; CHECK-NEXT: vmov.32 q1[0], r7 ; CHECK-NEXT: vmov.32 q1[0], r7
; CHECK-NEXT: vmov.32 q0[1], r8 ; CHECK-NEXT: vmov.32 q0[1], r8
; CHECK-NEXT: adds r4, #8 ; CHECK-NEXT: adds r4, #8
; CHECK-NEXT: vmov.32 q1[1], r10 ; CHECK-NEXT: vmov.32 q1[1], r10
; CHECK-NEXT: adds r5, #8 ; CHECK-NEXT: adds r5, #8
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vstrb.8 q1, [r6], #16 ; CHECK-NEXT: vstrb.8 q0, [r6], #16
; CHECK-NEXT: le lr, .LBB6_4 ; CHECK-NEXT: le lr, .LBB6_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r12, r3 ; CHECK-NEXT: cmp r12, r3
; CHECK-NEXT: beq .LBB6_8 ; CHECK-NEXT: beq .LBB6_8
; CHECK-NEXT: .LBB6_6: @ %for.body.preheader11 ; CHECK-NEXT: .LBB6_6: @ %for.body.preheader11
; CHECK-NEXT: sub.w lr, r3, r12 ; CHECK-NEXT: sub.w lr, r3, r12
; CHECK-NEXT: add.w r0, r0, r12, lsl #1 ; CHECK-NEXT: add.w r0, r0, r12, lsl #1
; CHECK-NEXT: add.w r1, r1, r12, lsl #1 ; CHECK-NEXT: add.w r1, r1, r12, lsl #1
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.32 q0[0], r9 ; CHECK-NEXT: vmov.32 q0[0], r9
; CHECK-NEXT: ldr.w r10, [r5, #4] ; CHECK-NEXT: ldr.w r10, [r5, #4]
; CHECK-NEXT: vmov.32 q1[0], r7 ; CHECK-NEXT: vmov.32 q1[0], r7
; CHECK-NEXT: vmov.32 q0[1], r8 ; CHECK-NEXT: vmov.32 q0[1], r8
; CHECK-NEXT: adds r4, #8 ; CHECK-NEXT: adds r4, #8
; CHECK-NEXT: vmov.32 q1[1], r10 ; CHECK-NEXT: vmov.32 q1[1], r10
; CHECK-NEXT: adds r5, #8 ; CHECK-NEXT: adds r5, #8
; CHECK-NEXT: vsub.f16 q0, q0, q1 ; CHECK-NEXT: vsub.f16 q0, q0, q1
; CHECK-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vstrb.8 q1, [r6], #16 ; CHECK-NEXT: vstrb.8 q0, [r6], #16
; CHECK-NEXT: le lr, .LBB7_4 ; CHECK-NEXT: le lr, .LBB7_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r12, r3 ; CHECK-NEXT: cmp r12, r3
; CHECK-NEXT: beq .LBB7_8 ; CHECK-NEXT: beq .LBB7_8
; CHECK-NEXT: .LBB7_6: @ %for.body.preheader11 ; CHECK-NEXT: .LBB7_6: @ %for.body.preheader11
; CHECK-NEXT: sub.w lr, r3, r12 ; CHECK-NEXT: sub.w lr, r3, r12
; CHECK-NEXT: add.w r0, r0, r12, lsl #1 ; CHECK-NEXT: add.w r0, r0, r12, lsl #1
; CHECK-NEXT: add.w r1, r1, r12, lsl #1 ; CHECK-NEXT: add.w r1, r1, r12, lsl #1
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; CHECK-NEXT: vmov r11, r8, d1 ; CHECK-NEXT: vmov r11, r8, d1
; CHECK-NEXT: vmov.16 q0[0], r7 ; CHECK-NEXT: vmov.16 q0[0], r7
; CHECK-NEXT: vmov.16 q0[1], r12 ; CHECK-NEXT: vmov.16 q0[1], r12
; CHECK-NEXT: vmov.32 q1[1], r10 ; CHECK-NEXT: vmov.32 q1[1], r10
; CHECK-NEXT: vmov.16 q0[2], r11 ; CHECK-NEXT: vmov.16 q0[2], r11
; CHECK-NEXT: vmov.16 q0[3], r8 ; CHECK-NEXT: vmov.16 q0[3], r8
; CHECK-NEXT: vcvt.f16.s16 q0, q0 ; CHECK-NEXT: vcvt.f16.s16 q0, q0
; CHECK-NEXT: vmul.f16 q0, q1, q0 ; CHECK-NEXT: vmul.f16 q0, q1, q0
; CHECK-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vstrb.8 q1, [r6], #16 ; CHECK-NEXT: vstrb.8 q0, [r6], #16
; CHECK-NEXT: le lr, .LBB8_4 ; CHECK-NEXT: le lr, .LBB8_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: ldr r7, [sp] @ 4-byte Reload ; CHECK-NEXT: ldr r7, [sp] @ 4-byte Reload
; CHECK-NEXT: cmp r7, r3 ; CHECK-NEXT: cmp r7, r3
; CHECK-NEXT: beq .LBB8_8 ; CHECK-NEXT: beq .LBB8_8
; CHECK-NEXT: .LBB8_6: @ %for.body.preheader13 ; CHECK-NEXT: .LBB8_6: @ %for.body.preheader13
; CHECK-NEXT: sub.w lr, r3, r7 ; CHECK-NEXT: sub.w lr, r3, r7
; CHECK-NEXT: add.w r0, r0, r7, lsl #1 ; CHECK-NEXT: add.w r0, r0, r7, lsl #1
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll

Show First 20 Lines • Show All 234 Lines • ▼ Show 20 Lines
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r7, pc} ; CHECK-NEXT: popeq {r7, pc}
; CHECK-NEXT: .LBB5_1: @ %vector.ph ; CHECK-NEXT: .LBB5_1: @ %vector.ph
; CHECK-NEXT: dlstp.32 lr, r2 ; CHECK-NEXT: dlstp.32 lr, r2
; CHECK-NEXT: .LBB5_2: @ %vector.body ; CHECK-NEXT: .LBB5_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r0], #16 ; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vrintr.f32 s7, s3 ; CHECK-NEXT: vrintr.f32 s3, s3
; CHECK-NEXT: vrintr.f32 s6, s2 ; CHECK-NEXT: vrintr.f32 s2, s2
; CHECK-NEXT: vrintr.f32 s5, s1 ; CHECK-NEXT: vrintr.f32 s1, s1
; CHECK-NEXT: vrintr.f32 s4, s0 ; CHECK-NEXT: vrintr.f32 s0, s0
; CHECK-NEXT: vstrw.32 q1, [r1], #16 ; CHECK-NEXT: vstrw.32 q0, [r1], #16
; CHECK-NEXT: letp lr, .LBB5_2 ; CHECK-NEXT: letp lr, .LBB5_2
; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%cmp5 = icmp eq i32 %n, 0 %cmp5 = icmp eq i32 %n, 0
br i1 %cmp5, label %for.cond.cleanup, label %vector.ph br i1 %cmp5, label %for.cond.cleanup, label %vector.ph
vector.ph: ; preds = %entry vector.ph: ; preds = %entry
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=armv8.1m.main -mattr=+mve -tail-predication=enabled --verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=armv8.1m.main -mattr=+mve -tail-predication=enabled --verify-machineinstrs %s -o - | FileCheck %s
define void @arm_cmplx_mag_squared_q15_mve(i16* %pSrc, i16* %pDst, i32 %blockSize) { define void @arm_cmplx_mag_squared_q15_mve(i16* %pSrc, i16* %pDst, i32 %blockSize) {
; CHECK-LABEL: arm_cmplx_mag_squared_q15_mve: ; CHECK-LABEL: arm_cmplx_mag_squared_q15_mve:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: subs.w r3, r2, #8 ; CHECK-NEXT: subs.w r3, r2, #8
; CHECK-NEXT: dlstp.16 lr, r2 ; CHECK-NEXT: dlstp.16 lr, r2
; CHECK-NEXT: .LBB0_1: @ %do.body ; CHECK-NEXT: .LBB0_1: @ %do.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vld20.16 {q0, q1}, [r0] ; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
; CHECK-NEXT: vld21.16 {q0, q1}, [r0]! ; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!
; CHECK-NEXT: vmulh.s16 q2, q1, q1 ; CHECK-NEXT: vmulh.s16 q1, q1, q1
; CHECK-NEXT: vmulh.s16 q0, q0, q0 ; CHECK-NEXT: vmulh.s16 q0, q0, q0
; CHECK-NEXT: vqadd.s16 q0, q0, q2 ; CHECK-NEXT: vqadd.s16 q0, q0, q1
; CHECK-NEXT: vshr.s16 q0, q0, #1 ; CHECK-NEXT: vshr.s16 q0, q0, #1
; CHECK-NEXT: vstrh.16 q0, [r1], #16 ; CHECK-NEXT: vstrh.16 q0, [r1], #16
; CHECK-NEXT: letp lr, .LBB0_1 ; CHECK-NEXT: letp lr, .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %do.end ; CHECK-NEXT: @ %bb.2: @ %do.end
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
br label %do.body br label %do.body
▲ Show 20 Lines • Show All 162 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/active_lane_mask.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -o - | FileCheck %s
define <4 x i32> @v4i32(i32 %index, i32 %TC, <4 x i32> %V1, <4 x i32> %V2) { define <4 x i32> @v4i32(i32 %index, i32 %TC, <4 x i32> %V1, <4 x i32> %V2) {
; CHECK-LABEL: v4i32: ; CHECK-LABEL: v4i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: adr.w r12, .LCPI0_0 ; CHECK-NEXT: adr.w r12, .LCPI0_0
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vdup.32 q1, r0
; CHECK-NEXT: vldrw.u32 q0, [r12] ; CHECK-NEXT: vldrw.u32 q0, [r12]
; CHECK-NEXT: vadd.i32 q0, q0, r0 ; CHECK-NEXT: vadd.i32 q0, q0, r0
; CHECK-NEXT: add r0, sp, #8 ; CHECK-NEXT: add r0, sp, #8
; CHECK-NEXT: vcmp.u32 hi, q1, q0 ; CHECK-NEXT: vcmp.u32 hi, q1, q0
; CHECK-NEXT: vdup.32 q1, r1 ; CHECK-NEXT: vdup.32 q1, r1
; CHECK-NEXT: vpnot ; CHECK-NEXT: vpnot
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vcmpt.u32 hi, q1, q0 ; CHECK-NEXT: vcmpt.u32 hi, q1, q0
; CHECK-NEXT: vmov d0, r2, r3
; CHECK-NEXT: vldr d1, [sp] ; CHECK-NEXT: vldr d1, [sp]
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov d0, r2, r3
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0: ; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: vmov.16 q3[6], r0 ; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: add r0, sp, #56 ; CHECK-NEXT: add r0, sp, #56
; CHECK-NEXT: vmov.16 q3[7], r1 ; CHECK-NEXT: vmov.16 q3[7], r1
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vcmp.i16 ne, q3, zr ; CHECK-NEXT: vcmp.i16 ne, q3, zr
; CHECK-NEXT: vpnot ; CHECK-NEXT: vpnot
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vcmpt.i16 ne, q0, zr ; CHECK-NEXT: vcmpt.i16 ne, q0, zr
; CHECK-NEXT: vmov d0, r2, r3
; CHECK-NEXT: vldr d1, [sp, #48] ; CHECK-NEXT: vldr d1, [sp, #48]
; CHECK-NEXT: vmov d0, r2, r3
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI2_0: ; CHECK-NEXT: .LCPI2_0:
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.u16 r0, q0[4] ; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.8 q3[12], r0 ; CHECK-NEXT: vmov.8 q3[12], r0
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.8 q3[13], r0 ; CHECK-NEXT: vmov.8 q3[13], r0
; CHECK-NEXT: vmov.u16 r0, q0[6] ; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.8 q3[14], r0 ; CHECK-NEXT: vmov.8 q3[14], r0
; CHECK-NEXT: vmov.u16 r0, q0[7] ; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.8 q3[15], r0 ; CHECK-NEXT: vmov.8 q3[15], r0
; CHECK-NEXT: vmov d0, r2, r3
; CHECK-NEXT: add r0, sp, #88 ; CHECK-NEXT: add r0, sp, #88
; CHECK-NEXT: vcmp.i8 ne, q3, zr ; CHECK-NEXT: vcmp.i8 ne, q3, zr
; CHECK-NEXT: vldr d1, [sp, #80] ; CHECK-NEXT: vldr d1, [sp, #80]
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vpnot ; CHECK-NEXT: vpnot
; CHECK-NEXT: vmov d0, r2, r3
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vcmpt.i8 ne, q2, zr ; CHECK-NEXT: vcmpt.i8 ne, q2, zr
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
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llvm/test/CodeGen/Thumb2/mve-be.ll

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Linesentry:
%a = add <4 x i32> %l1, %src2 %a = add <4 x i32> %l1, %src2
store <4 x i32> %a, <4 x i32>* %src1, align 4 store <4 x i32> %a, <4 x i32>* %src1, align 4
ret void ret void
} }
define <4 x i32> @add_soft(<4 x i32> %src1, <4 x i32> %src2) { define <4 x i32> @add_soft(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LE-LABEL: add_soft: ; CHECK-LE-LABEL: add_soft:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vmov d1, r2, r3
; CHECK-LE-NEXT: vmov d0, r0, r1 ; CHECK-LE-NEXT: vmov d0, r0, r1
; CHECK-LE-NEXT: mov r0, sp ; CHECK-LE-NEXT: mov r0, sp
; CHECK-LE-NEXT: vldrw.u32 q1, [r0] ; CHECK-LE-NEXT: vldrw.u32 q1, [r0]
; CHECK-LE-NEXT: vmov d1, r2, r3
; CHECK-LE-NEXT: vadd.i32 q0, q0, q1 ; CHECK-LE-NEXT: vadd.i32 q0, q0, q1
; CHECK-LE-NEXT: vmov r0, r1, d0 ; CHECK-LE-NEXT: vmov r0, r1, d0
; CHECK-LE-NEXT: vmov r2, r3, d1 ; CHECK-LE-NEXT: vmov r2, r3, d1
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: add_soft: ; CHECK-BE-LABEL: add_soft:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vmov d0, r1, r0 ; CHECK-BE-NEXT: vmov d0, r1, r0
; CHECK-BE-NEXT: mov r0, sp ; CHECK-BE-NEXT: mov r0, sp
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: vldrw.u32 q0, [r0] ; CHECK-BE-NEXT: vldrw.u32 q0, [r0]
; CHECK-BE-NEXT: vadd.i32 q0, q1, q0 ; CHECK-BE-NEXT: vadd.i32 q0, q1, q0
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: vmov r1, r0, d2 ; CHECK-BE-NEXT: vmov r1, r0, d2
; CHECK-BE-NEXT: vmov r3, r2, d3 ; CHECK-BE-NEXT: vmov r3, r2, d3
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
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llvm/test/CodeGen/Thumb2/mve-ctlz.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){ define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){
; CHECK-LABEL: ctlz_2i64_0_t: ; CHECK-LABEL: ctlz_2i64_0_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: clz r0, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r2, ne ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: adds r0, #32 ; CHECK-NEXT: adds r0, #32
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r0, r1 ; CHECK-NEXT: clzne r0, r1
; CHECK-NEXT: vmov s6, r0 ; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vldr s1, .LCPI0_0
; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: clz r0, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r2, ne ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: adds r0, #32 ; CHECK-NEXT: adds r0, #32
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r0, r1 ; CHECK-NEXT: clzne r0, r1
; CHECK-NEXT: vmov s4, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vldr s5, .LCPI0_0
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0: ; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
entry: entry:
%0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0) %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0)
ret <2 x i64> %0 ret <2 x i64> %0
Show All 35 Lines
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: clz r0, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r2, ne ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: adds r0, #32 ; CHECK-NEXT: adds r0, #32
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r0, r1 ; CHECK-NEXT: clzne r0, r1
; CHECK-NEXT: vmov s6, r0 ; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vldr s1, .LCPI4_0
; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: clz r0, r0 ; CHECK-NEXT: clz r0, r0
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cset r2, ne ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: adds r0, #32 ; CHECK-NEXT: adds r0, #32
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r0, r1 ; CHECK-NEXT: clzne r0, r1
; CHECK-NEXT: vmov s4, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vldr s5, .LCPI4_0
; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI4_0: ; CHECK-NEXT: .LCPI4_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
entry: entry:
%0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1) %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1)
ret <2 x i64> %0 ret <2 x i64> %0
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llvm/test/CodeGen/Thumb2/mve-ctpop.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){ define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){
; CHECK-LABEL: ctpop_2i64_t: ; CHECK-LABEL: ctpop_2i64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r1, r2, d1
; CHECK-NEXT: mov.w lr, #1431655765 ; CHECK-NEXT: mov.w lr, #1431655765
; CHECK-NEXT: vmov r3, r4, d0 ; CHECK-NEXT: vmov r3, r4, d0
; CHECK-NEXT: mov.w r12, #858993459 ; CHECK-NEXT: mov.w r12, #858993459
; CHECK-NEXT: vldr s1, .LCPI0_0 ; CHECK-NEXT: vldr s1, .LCPI0_0
; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: and.w r0, lr, r2, lsr #1 ; CHECK-NEXT: and.w r0, lr, r2, lsr #1
; CHECK-NEXT: subs r0, r2, r0 ; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: and.w r2, r12, r0, lsr #2 ; CHECK-NEXT: and.w r2, r12, r0, lsr #2
; CHECK-NEXT: bic r0, r0, #-858993460 ; CHECK-NEXT: bic r0, r0, #-858993460
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: and.w r2, lr, r1, lsr #1 ; CHECK-NEXT: and.w r2, lr, r1, lsr #1
; CHECK-NEXT: subs r1, r1, r2 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: add.w r0, r0, r0, lsr #4 ; CHECK-NEXT: add.w r0, r0, r0, lsr #4
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; CHECK-NEXT: bic r3, r3, #-252645136 ; CHECK-NEXT: bic r3, r3, #-252645136
; CHECK-NEXT: muls r0, r3, r0 ; CHECK-NEXT: muls r0, r3, r0
; CHECK-NEXT: lsrs r1, r1, #24 ; CHECK-NEXT: lsrs r1, r1, #24
; CHECK-NEXT: add.w r1, r1, r5, lsr #24 ; CHECK-NEXT: add.w r1, r1, r5, lsr #24
; CHECK-NEXT: lsrs r2, r2, #24 ; CHECK-NEXT: lsrs r2, r2, #24
; CHECK-NEXT: vmov s2, r1 ; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: add.w r0, r2, r0, lsr #24 ; CHECK-NEXT: add.w r0, r2, r0, lsr #24
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0: ; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
entry: entry:
%0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src) %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src)
ret <2 x i64> %0 ret <2 x i64> %0
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-cttz.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){ define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_0_t(<2 x i64> %src){
; CHECK-LABEL: cttz_2i64_0_t: ; CHECK-LABEL: cttz_2i64_0_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: rbit r1, r1 ; CHECK-NEXT: rbit r1, r1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: clz r1, r1 ; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: cset r2, ne ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: adds r1, #32 ; CHECK-NEXT: adds r1, #32
; CHECK-NEXT: rbit r0, r0 ; CHECK-NEXT: rbit r0, r0
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0 ; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov s2, r1 ; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vldr s1, .LCPI0_0
; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: rbit r1, r1 ; CHECK-NEXT: rbit r1, r1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: clz r1, r1 ; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: cset r2, ne ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: adds r1, #32 ; CHECK-NEXT: adds r1, #32
; CHECK-NEXT: rbit r0, r0 ; CHECK-NEXT: rbit r0, r0
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0 ; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov s0, r1 ; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: vldr s1, .LCPI0_0
; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0: ; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
entry: entry:
%0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 0) %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 0)
ret <2 x i64> %0 ret <2 x i64> %0
Show All 33 Lines
entry: entry:
%0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 0) %0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 0)
ret <16 x i8> %0 ret <16 x i8> %0
} }
define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_1_t(<2 x i64> %src){ define arm_aapcs_vfpcc <2 x i64> @cttz_2i64_1_t(<2 x i64> %src){
; CHECK-LABEL: cttz_2i64_1_t: ; CHECK-LABEL: cttz_2i64_1_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: rbit r1, r1 ; CHECK-NEXT: rbit r1, r1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: clz r1, r1 ; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: cset r2, ne ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: adds r1, #32 ; CHECK-NEXT: adds r1, #32
; CHECK-NEXT: rbit r0, r0 ; CHECK-NEXT: rbit r0, r0
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0 ; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov s2, r1 ; CHECK-NEXT: vmov s2, r1
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vldr s1, .LCPI4_0
; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: rbit r1, r1 ; CHECK-NEXT: rbit r1, r1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: clz r1, r1 ; CHECK-NEXT: clz r1, r1
; CHECK-NEXT: cset r2, ne ; CHECK-NEXT: cset r2, ne
; CHECK-NEXT: adds r1, #32 ; CHECK-NEXT: adds r1, #32
; CHECK-NEXT: rbit r0, r0 ; CHECK-NEXT: rbit r0, r0
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: clzne r1, r0 ; CHECK-NEXT: clzne r1, r0
; CHECK-NEXT: vmov s0, r1 ; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: vldr s1, .LCPI4_0
; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI4_0: ; CHECK-NEXT: .LCPI4_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
entry: entry:
%0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 1) %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 1)
ret <2 x i64> %0 ret <2 x i64> %0
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-div-expand.ll

Show First 20 Lines • Show All 718 Lines • ▼ Show 20 Lines
} }
define arm_aapcs_vfpcc <4 x float> @fdiv_f32(<4 x float> %in1, <4 x float> %in2) { define arm_aapcs_vfpcc <4 x float> @fdiv_f32(<4 x float> %in1, <4 x float> %in2) {
; CHECK-LABEL: fdiv_f32: ; CHECK-LABEL: fdiv_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vdiv.f32 s11, s3, s7 ; CHECK-NEXT: vdiv.f32 s3, s3, s7
; CHECK-NEXT: vdiv.f32 s10, s2, s6 ; CHECK-NEXT: vdiv.f32 s2, s2, s6
; CHECK-NEXT: vdiv.f32 s9, s1, s5 ; CHECK-NEXT: vdiv.f32 s1, s1, s5
; CHECK-NEXT: vdiv.f32 s8, s0, s4 ; CHECK-NEXT: vdiv.f32 s0, s0, s4
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fdiv <4 x float> %in1, %in2 %out = fdiv <4 x float> %in1, %in2
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <4 x float> @frem_f32(<4 x float> %in1, <4 x float> %in2) { define arm_aapcs_vfpcc <4 x float> @frem_f32(<4 x float> %in1, <4 x float> %in2) {
; CHECK-LABEL: frem_f32: ; CHECK-LABEL: frem_f32:
Show All 29 Linesentry:
%out = frem <4 x float> %in1, %in2 %out = frem <4 x float> %in1, %in2
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <8 x half> @fdiv_f16(<8 x half> %in1, <8 x half> %in2) { define arm_aapcs_vfpcc <8 x half> @fdiv_f16(<8 x half> %in1, <8 x half> %in2) {
; CHECK-LABEL: fdiv_f16: ; CHECK-LABEL: fdiv_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmovx.f16 s10, s0
; CHECK-NEXT: vmovx.f16 s0, s4 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vmovx.f16 s2, s8 ; CHECK-NEXT: vdiv.f16 s0, s0, s4
; CHECK-NEXT: vmovx.f16 s14, s9 ; CHECK-NEXT: vdiv.f16 s8, s10, s8
; CHECK-NEXT: vdiv.f16 s12, s2, s0 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vdiv.f16 s0, s8, s4 ; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vins.f16 s0, s12 ; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vmovx.f16 s12, s5 ; CHECK-NEXT: vdiv.f16 s1, s1, s5
; CHECK-NEXT: vdiv.f16 s12, s14, s12 ; CHECK-NEXT: vdiv.f16 s4, s8, s4
; CHECK-NEXT: vdiv.f16 s1, s9, s5 ; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vins.f16 s1, s12 ; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s12, s6 ; CHECK-NEXT: vmovx.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s14, s10 ; CHECK-NEXT: vdiv.f16 s2, s2, s6
; CHECK-NEXT: vdiv.f16 s2, s10, s6 ; CHECK-NEXT: vdiv.f16 s4, s8, s4
; CHECK-NEXT: vdiv.f16 s12, s14, s12 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s14, s11 ; CHECK-NEXT: vmovx.f16 s6, s3
; CHECK-NEXT: vins.f16 s2, s12 ; CHECK-NEXT: vmovx.f16 s4, s7
; CHECK-NEXT: vmovx.f16 s12, s7 ; CHECK-NEXT: vdiv.f16 s3, s3, s7
; CHECK-NEXT: vdiv.f16 s12, s14, s12 ; CHECK-NEXT: vdiv.f16 s4, s6, s4
; CHECK-NEXT: vdiv.f16 s3, s11, s7 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vins.f16 s3, s12
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fdiv <8 x half> %in1, %in2 %out = fdiv <8 x half> %in1, %in2
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) { define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
; CHECK-LABEL: frem_f16: ; CHECK-LABEL: frem_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q5, q0 ; CHECK-NEXT: vmov q5, q0
; CHECK-NEXT: vmov q4, q1 ; CHECK-NEXT: vmov q4, q1
; CHECK-NEXT: vcvtb.f32.f16 s0, s20 ; CHECK-NEXT: vcvtb.f32.f16 s0, s20
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vcvtt.f32.f16 s0, s20 ; CHECK-NEXT: vcvtt.f32.f16 s0, s20
; CHECK-NEXT: vmov s24, r0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s24, s24 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s24, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s21 ; CHECK-NEXT: vcvtb.f32.f16 s0, s21
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s25, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s21 ; CHECK-NEXT: vcvtt.f32.f16 s0, s21
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s25, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s22 ; CHECK-NEXT: vcvtb.f32.f16 s0, s22
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s26, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s22 ; CHECK-NEXT: vcvtt.f32.f16 s0, s22
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s26, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s23 ; CHECK-NEXT: vcvtb.f32.f16 s0, s23
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s27, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s23 ; CHECK-NEXT: vcvtt.f32.f16 s0, s23
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s27, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q6 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%out = frem <8 x half> %in1, %in2 %out = frem <8 x half> %in1, %in2
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <2 x double> @fdiv_f64(<2 x double> %in1, <2 x double> %in2) { define arm_aapcs_vfpcc <2 x double> @fdiv_f64(<2 x double> %in1, <2 x double> %in2) {
; CHECK-LABEL: fdiv_f64: ; CHECK-LABEL: fdiv_f64:
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-float16regloops.ll

Show First 20 Lines • Show All 1,416 Lines • ▼ Show 20 Lines
%struct.arm_biquad_cascade_df2T_instance_f16 = type { i8, half*, half* } %struct.arm_biquad_cascade_df2T_instance_f16 = type { i8, half*, half* }
define void @arm_biquad_cascade_df2T_f16(%struct.arm_biquad_cascade_df2T_instance_f16* nocapture readonly %S, half* nocapture readonly %pSrc, half* nocapture %pDst, i32 %blockSize) { define void @arm_biquad_cascade_df2T_f16(%struct.arm_biquad_cascade_df2T_instance_f16* nocapture readonly %S, half* nocapture readonly %pSrc, half* nocapture %pDst, i32 %blockSize) {
; CHECK-LABEL: arm_biquad_cascade_df2T_f16: ; CHECK-LABEL: arm_biquad_cascade_df2T_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: ldrd r12, r6, [r0, #4] ; CHECK-NEXT: ldrd r12, r6, [r0, #4]
; CHECK-NEXT: and r8, r3, #1 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: ldrb r0, [r0] ; CHECK-NEXT: ldrb r0, [r0]
; CHECK-NEXT: vldr.16 s4, .LCPI17_0 ; CHECK-NEXT: and r8, r3, #1
; CHECK-NEXT: vldr.16 s0, .LCPI17_0
; CHECK-NEXT: lsr.w r9, r3, #1 ; CHECK-NEXT: lsr.w r9, r3, #1
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: b .LBB17_3 ; CHECK-NEXT: b .LBB17_3
; CHECK-NEXT: .LBB17_1: @ %if.else ; CHECK-NEXT: .LBB17_1: @ %if.else
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: vstr.16 s8, [r12] ; CHECK-NEXT: vmovx.f16 s5, s4
; CHECK-NEXT: vmovx.f16 s9, s8 ; CHECK-NEXT: vstr.16 s4, [r12]
; CHECK-NEXT: .LBB17_2: @ %if.end ; CHECK-NEXT: .LBB17_2: @ %if.end
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: vstr.16 s9, [r12, #2] ; CHECK-NEXT: vstr.16 s5, [r12, #2]
; CHECK-NEXT: adds r6, #10 ; CHECK-NEXT: adds r6, #10
; CHECK-NEXT: subs r0, #1 ; CHECK-NEXT: subs r0, #1
; CHECK-NEXT: add.w r12, r12, #4 ; CHECK-NEXT: add.w r12, r12, #4
; CHECK-NEXT: mov r1, r2 ; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: beq .LBB17_8 ; CHECK-NEXT: beq .LBB17_8
; CHECK-NEXT: .LBB17_3: @ %do.body ; CHECK-NEXT: .LBB17_3: @ %do.body
; CHECK-NEXT: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB17_5 Depth 2 ; CHECK-NEXT: @ Child Loop BB17_5 Depth 2
; CHECK-NEXT: vldrh.u16 q3, [r6] ; CHECK-NEXT: vldrh.u16 q2, [r6]
; CHECK-NEXT: movs r5, #0 ; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: vmov q4, q2
; CHECK-NEXT: vshlc q4, r5, #16
; CHECK-NEXT: vldrh.u16 q3, [r6, #4]
; CHECK-NEXT: vmov q5, q3 ; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vshlc q5, r5, #16 ; CHECK-NEXT: vshlc q5, r5, #16
; CHECK-NEXT: vldrh.u16 q4, [r6, #4] ; CHECK-NEXT: vldrh.u16 q1, [r12]
; CHECK-NEXT: vmov q6, q4 ; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vshlc q6, r5, #16
; CHECK-NEXT: vldrh.u16 q2, [r12]
; CHECK-NEXT: vmov.f32 s9, s1
; CHECK-NEXT: mov r5, r2 ; CHECK-NEXT: mov r5, r2
; CHECK-NEXT: wls lr, r9, .LBB17_6 ; CHECK-NEXT: wls lr, r9, .LBB17_6
; CHECK-NEXT: @ %bb.4: @ %while.body.preheader ; CHECK-NEXT: @ %bb.4: @ %while.body.preheader
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: mov r5, r2 ; CHECK-NEXT: mov r5, r2
; CHECK-NEXT: .LBB17_5: @ %while.body ; CHECK-NEXT: .LBB17_5: @ %while.body
; CHECK-NEXT: @ Parent Loop BB17_3 Depth=1 ; CHECK-NEXT: @ Parent Loop BB17_3 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: ldrh r7, [r1], #4 ; CHECK-NEXT: ldrh r7, [r1], #4
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vfma.f16 q2, q3, r7 ; CHECK-NEXT: vfma.f16 q1, q2, r7
; CHECK-NEXT: ldrh r4, [r1, #-2] ; CHECK-NEXT: ldrh r4, [r1, #-2]
; CHECK-NEXT: vmov.u16 r7, q2[0] ; CHECK-NEXT: vmov.u16 r7, q1[0]
; CHECK-NEXT: vfma.f16 q2, q4, r7 ; CHECK-NEXT: vfma.f16 q1, q3, r7
; CHECK-NEXT: vins.f16 s9, s4 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vfma.f16 q2, q5, r4 ; CHECK-NEXT: vfma.f16 q1, q4, r4
; CHECK-NEXT: vmov.u16 r4, q2[1] ; CHECK-NEXT: vmov.u16 r4, q1[1]
; CHECK-NEXT: vfma.f16 q2, q6, r4 ; CHECK-NEXT: vfma.f16 q1, q5, r4
; CHECK-NEXT: strh r4, [r5, #2] ; CHECK-NEXT: strh r4, [r5, #2]
; CHECK-NEXT: vmov.f32 s8, s9 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: strh r7, [r5], #4 ; CHECK-NEXT: strh r7, [r5], #4
; CHECK-NEXT: vmov.16 q2[2], r3 ; CHECK-NEXT: vmov.16 q1[2], r3
; CHECK-NEXT: le lr, .LBB17_5 ; CHECK-NEXT: le lr, .LBB17_5
; CHECK-NEXT: .LBB17_6: @ %while.end ; CHECK-NEXT: .LBB17_6: @ %while.end
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: cmp.w r8, #0
; CHECK-NEXT: beq .LBB17_1 ; CHECK-NEXT: beq .LBB17_1
; CHECK-NEXT: @ %bb.7: @ %if.then ; CHECK-NEXT: @ %bb.7: @ %if.then
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: ldrh r1, [r1] ; CHECK-NEXT: ldrh r1, [r1]
; CHECK-NEXT: vfma.f16 q2, q3, r1 ; CHECK-NEXT: vfma.f16 q1, q2, r1
; CHECK-NEXT: vmov.u16 r1, q2[0] ; CHECK-NEXT: vmov.u16 r1, q1[0]
; CHECK-NEXT: vfma.f16 q2, q4, r1 ; CHECK-NEXT: vfma.f16 q1, q3, r1
; CHECK-NEXT: strh r1, [r5] ; CHECK-NEXT: strh r1, [r5]
; CHECK-NEXT: vmovx.f16 s6, s8 ; CHECK-NEXT: vmovx.f16 s2, s4
; CHECK-NEXT: vstr.16 s6, [r12] ; CHECK-NEXT: vstr.16 s2, [r12]
; CHECK-NEXT: b .LBB17_2 ; CHECK-NEXT: b .LBB17_2
; CHECK-NEXT: .LBB17_8: @ %do.end ; CHECK-NEXT: .LBB17_8: @ %do.end
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: .p2align 1
; CHECK-NEXT: @ %bb.9: ; CHECK-NEXT: @ %bb.9:
; CHECK-NEXT: .LCPI17_0: ; CHECK-NEXT: .LCPI17_0:
; CHECK-NEXT: .short 0x0000 @ half 0 ; CHECK-NEXT: .short 0x0000 @ half 0
entry: entry:
%pState1 = getelementptr inbounds %struct.arm_biquad_cascade_df2T_instance_f16, %struct.arm_biquad_cascade_df2T_instance_f16* %S, i32 0, i32 1 %pState1 = getelementptr inbounds %struct.arm_biquad_cascade_df2T_instance_f16, %struct.arm_biquad_cascade_df2T_instance_f16* %S, i32 0, i32 1
▲ Show 20 Lines • Show All 136 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-float32regloops.ll

Show First 20 Lines • Show All 1,410 Lines • ▼ Show 20 Lines
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: movs r5, #2 ; CHECK-NEXT: movs r5, #2
; CHECK-NEXT: viwdup.u32 q0, r4, r5, #1 ; CHECK-NEXT: viwdup.u32 q0, r4, r5, #1
; CHECK-NEXT: mov r4, sp ; CHECK-NEXT: mov r4, sp
; CHECK-NEXT: .LBB17_2: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: .LBB17_2: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB17_3 Depth 2 ; CHECK-NEXT: @ Child Loop BB17_3 Depth 2
; CHECK-NEXT: ldrd r5, r7, [r0] ; CHECK-NEXT: ldrd r5, r7, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r3] ; CHECK-NEXT: vldrw.u32 q1, [r3]
; CHECK-NEXT: vldr s8, [r0, #8]
; CHECK-NEXT: ldr r6, [r0, #12] ; CHECK-NEXT: ldr r6, [r0, #12]
; CHECK-NEXT: vldr s8, [r0, #8]
; CHECK-NEXT: vstrw.32 q1, [r4] ; CHECK-NEXT: vstrw.32 q1, [r4]
; CHECK-NEXT: vdup.32 q1, r7 ; CHECK-NEXT: vdup.32 q1, r7
; CHECK-NEXT: vldr s12, [r0, #16] ; CHECK-NEXT: vldr s12, [r0, #16]
; CHECK-NEXT: vmov.f32 s6, s8 ; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: dls lr, r8 ; CHECK-NEXT: dls lr, r8
; CHECK-NEXT: vmov.f32 s7, s8 ; CHECK-NEXT: vmov.f32 s7, s8
; CHECK-NEXT: vdup.32 q2, r6 ; CHECK-NEXT: vdup.32 q2, r6
; CHECK-NEXT: vmov.f32 s10, s12 ; CHECK-NEXT: vmov.f32 s10, s12
▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
; CHECK-LABEL: arm_biquad_cascade_df1_f32: ; CHECK-LABEL: arm_biquad_cascade_df1_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #64 ; CHECK-NEXT: .pad #48
; CHECK-NEXT: sub sp, #64 ; CHECK-NEXT: sub sp, #48
; CHECK-NEXT: ldrd r12, r10, [r0] ; CHECK-NEXT: ldrd r12, r10, [r0]
; CHECK-NEXT: @ implicit-def: $s2 ; CHECK-NEXT: @ implicit-def: $s2
; CHECK-NEXT: and r7, r3, #3 ; CHECK-NEXT: and r7, r3, #3
; CHECK-NEXT: ldr.w r9, [r0, #8] ; CHECK-NEXT: ldr.w r9, [r0, #8]
; CHECK-NEXT: lsrs r0, r3, #2 ; CHECK-NEXT: lsrs r0, r3, #2
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill ; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: str r7, [sp, #4] @ 4-byte Spill ; CHECK-NEXT: str r7, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: str r2, [sp, #44] @ 4-byte Spill ; CHECK-NEXT: str r2, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: b .LBB19_3 ; CHECK-NEXT: b .LBB19_3
; CHECK-NEXT: .LBB19_1: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: .LBB19_1: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: vmov.f32 s14, s7 ; CHECK-NEXT: vmov.f32 s14, s7
; CHECK-NEXT: ldr r2, [sp, #44] @ 4-byte Reload ; CHECK-NEXT: vmov.f32 s4, s3
; CHECK-NEXT: vmov.f32 s0, s10
; CHECK-NEXT: vmov.f32 s7, s6 ; CHECK-NEXT: vmov.f32 s7, s6
; CHECK-NEXT: .LBB19_2: @ %if.end69 ; CHECK-NEXT: .LBB19_2: @ %if.end69
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: vstr s8, [r10] ; CHECK-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: subs.w r12, r12, #1 ; CHECK-NEXT: subs.w r12, r12, #1
; CHECK-NEXT: vstr s0, [r10, #4] ; CHECK-NEXT: vstr s1, [r10]
; CHECK-NEXT: add.w r9, r9, #128 ; CHECK-NEXT: add.w r9, r9, #128
; CHECK-NEXT: vstr s4, [r10, #4]
; CHECK-NEXT: vstr s14, [r10, #8] ; CHECK-NEXT: vstr s14, [r10, #8]
; CHECK-NEXT: mov r1, r2 ; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: vstr s7, [r10, #12] ; CHECK-NEXT: vstr s7, [r10, #12]
; CHECK-NEXT: add.w r10, r10, #16 ; CHECK-NEXT: add.w r10, r10, #16
; CHECK-NEXT: beq.w .LBB19_13 ; CHECK-NEXT: beq.w .LBB19_13
; CHECK-NEXT: .LBB19_3: @ %do.body ; CHECK-NEXT: .LBB19_3: @ %do.body
; CHECK-NEXT: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Loop Header: Depth=1
; CHECK-NEXT: @ Child Loop BB19_5 Depth 2 ; CHECK-NEXT: @ Child Loop BB19_5 Depth 2
; CHECK-NEXT: vldr s7, [r10, #8]
; CHECK-NEXT: mov r5, r2
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload ; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: vldr s8, [r10] ; CHECK-NEXT: mov r5, r2
; CHECK-NEXT: vldr s10, [r10, #4] ; CHECK-NEXT: vldr s1, [r10]
; CHECK-NEXT: vldr s3, [r10, #4]
; CHECK-NEXT: vldr s7, [r10, #8]
; CHECK-NEXT: vldr s6, [r10, #12] ; CHECK-NEXT: vldr s6, [r10, #12]
; CHECK-NEXT: wls lr, r0, .LBB19_6 ; CHECK-NEXT: wls lr, r0, .LBB19_6
; CHECK-NEXT: @ %bb.4: @ %while.body.lr.ph ; CHECK-NEXT: @ %bb.4: @ %while.body.lr.ph
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: ldr r5, [sp, #44] @ 4-byte Reload ; CHECK-NEXT: ldr r5, [sp, #28] @ 4-byte Reload
; CHECK-NEXT: .LBB19_5: @ %while.body ; CHECK-NEXT: .LBB19_5: @ %while.body
; CHECK-NEXT: @ Parent Loop BB19_3 Depth=1 ; CHECK-NEXT: @ Parent Loop BB19_3 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: vmov r4, s8
; CHECK-NEXT: vldr s8, [r1, #12]
; CHECK-NEXT: vldrw.u32 q0, [r9, #112]
; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: vldr s10, [r1, #8]
; CHECK-NEXT: vmov r7, s7 ; CHECK-NEXT: vmov r7, s7
; CHECK-NEXT: vldrw.u32 q2, [r9, #16]
; CHECK-NEXT: vmov r11, s6 ; CHECK-NEXT: vmov r11, s6
; CHECK-NEXT: vldrw.u32 q1, [r9, #112]
; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: vldr s1, [r1, #12]
; CHECK-NEXT: vmov r3, s3
; CHECK-NEXT: vldr s3, [r1, #8]
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r9] ; CHECK-NEXT: vldrw.u32 q1, [r9]
; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vmov r8, s1
; CHECK-NEXT: vmov r8, s8
; CHECK-NEXT: vldrw.u32 q0, [r9, #16]
; CHECK-NEXT: ldr r6, [r1, #4] ; CHECK-NEXT: ldr r6, [r1, #4]
; CHECK-NEXT: vldrw.u32 q7, [r9, #32] ; CHECK-NEXT: vldrw.u32 q7, [r9, #32]
; CHECK-NEXT: vmul.f32 q1, q1, r8 ; CHECK-NEXT: vmul.f32 q1, q1, r8
; CHECK-NEXT: vmov r0, s10 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vldrw.u32 q3, [r9, #48] ; CHECK-NEXT: vldrw.u32 q3, [r9, #48]
; CHECK-NEXT: vfma.f32 q1, q0, r0 ; CHECK-NEXT: vfma.f32 q1, q2, r0
; CHECK-NEXT: ldr r0, [r1], #16 ; CHECK-NEXT: ldr r0, [r1], #16
; CHECK-NEXT: vfma.f32 q1, q7, r6 ; CHECK-NEXT: vfma.f32 q1, q7, r6
; CHECK-NEXT: vldrw.u32 q6, [r9, #64] ; CHECK-NEXT: vldrw.u32 q6, [r9, #64]
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vfma.f32 q1, q3, r0 ; CHECK-NEXT: vfma.f32 q1, q3, r0
; CHECK-NEXT: vldrw.u32 q5, [r9, #80] ; CHECK-NEXT: vldrw.u32 q5, [r9, #80]
; CHECK-NEXT: vfma.f32 q1, q6, r4 ; CHECK-NEXT: vfma.f32 q1, q6, r4
; CHECK-NEXT: vldrw.u32 q4, [r9, #96] ; CHECK-NEXT: vldrw.u32 q4, [r9, #96]
; CHECK-NEXT: vldrw.u32 q2, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vfma.f32 q1, q5, r3 ; CHECK-NEXT: vfma.f32 q1, q5, r3
; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vfma.f32 q1, q4, r7 ; CHECK-NEXT: vfma.f32 q1, q4, r7
; CHECK-NEXT: vfma.f32 q1, q0, r11 ; CHECK-NEXT: vfma.f32 q1, q2, r11
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vstrb.8 q1, [r5], #16 ; CHECK-NEXT: vstrb.8 q1, [r5], #16
; CHECK-NEXT: le lr, .LBB19_5 ; CHECK-NEXT: le lr, .LBB19_5
; CHECK-NEXT: .LBB19_6: @ %while.end ; CHECK-NEXT: .LBB19_6: @ %while.end
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload ; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: beq .LBB19_1 ; CHECK-NEXT: beq .LBB19_1
; CHECK-NEXT: @ %bb.7: @ %if.then ; CHECK-NEXT: @ %bb.7: @ %if.then
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: vldr s24, [r1]
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vldr s0, [r1, #4]
; CHECK-NEXT: vldrw.u32 q3, [r9]
; CHECK-NEXT: vldr s3, [r1, #12]
; CHECK-NEXT: vldrw.u32 q4, [r9, #32]
; CHECK-NEXT: vldr s1, [r1, #8]
; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: vldrw.u32 q2, [r9, #96] ; CHECK-NEXT: vldrw.u32 q2, [r9, #96]
; CHECK-NEXT: vmov r6, s3 ; CHECK-NEXT: vmov lr, s6
; CHECK-NEXT: vldr s6, [r1, #12]
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vstrw.32 q2, [sp, #8] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r9, #112]
; CHECK-NEXT: vldr s1, [r1, #8]
; CHECK-NEXT: vldrw.u32 q3, [r9]
; CHECK-NEXT: vldr s4, [r1, #4]
; CHECK-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov r6, s6
; CHECK-NEXT: vldrw.u32 q2, [r9, #16]
; CHECK-NEXT: vldr s0, [r1]
; CHECK-NEXT: vmul.f32 q3, q3, r6 ; CHECK-NEXT: vmul.f32 q3, q3, r6
; CHECK-NEXT: vmov r6, s1 ; CHECK-NEXT: vmov r6, s1
; CHECK-NEXT: vstrw.32 q2, [sp, #24] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q4, [r9, #32]
; CHECK-NEXT: vldrw.u32 q2, [r9, #112] ; CHECK-NEXT: vfma.f32 q3, q2, r6
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: vldrw.u32 q5, [r9, #48] ; CHECK-NEXT: vldrw.u32 q5, [r9, #48]
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r9, #80]
; CHECK-NEXT: vldrw.u32 q7, [r9, #64] ; CHECK-NEXT: vldrw.u32 q7, [r9, #64]
; CHECK-NEXT: vmov r3, s24 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vstrw.32 q2, [sp, #8] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r9, #16]
; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: cmp r7, #1
; CHECK-NEXT: vfma.f32 q3, q2, r6
; CHECK-NEXT: vldrw.u32 q2, [sp, #8] @ 16-byte Reload
; CHECK-NEXT: vfma.f32 q3, q4, r4 ; CHECK-NEXT: vfma.f32 q3, q4, r4
; CHECK-NEXT: vmov lr, s6
; CHECK-NEXT: vfma.f32 q3, q5, r3 ; CHECK-NEXT: vfma.f32 q3, q5, r3
; CHECK-NEXT: vldrw.u32 q6, [r9, #80]
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: vfma.f32 q3, q7, r0 ; CHECK-NEXT: vfma.f32 q3, q7, r0
; CHECK-NEXT: vfma.f32 q3, q2, r1 ; CHECK-NEXT: vldrw.u32 q2, [sp, #8] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q2, [sp, #24] @ 16-byte Reload ; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: vfma.f32 q3, q6, r1
; CHECK-NEXT: cmp r7, #1
; CHECK-NEXT: vfma.f32 q3, q2, r2 ; CHECK-NEXT: vfma.f32 q3, q2, r2
; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q2, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vfma.f32 q3, q2, lr ; CHECK-NEXT: vfma.f32 q3, q2, lr
; CHECK-NEXT: bne .LBB19_9 ; CHECK-NEXT: bne .LBB19_9
; CHECK-NEXT: @ %bb.8: @ %if.then58 ; CHECK-NEXT: @ %bb.8: @ %if.then58
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: vstr s12, [r5] ; CHECK-NEXT: vstr s12, [r5]
; CHECK-NEXT: vmov.f32 s8, s24 ; CHECK-NEXT: vmov.f32 s1, s0
; CHECK-NEXT: vmov.f32 s0, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s14, s12
; CHECK-NEXT: b .LBB19_11 ; CHECK-NEXT: b .LBB19_12
; CHECK-NEXT: .LBB19_9: @ %if.else ; CHECK-NEXT: .LBB19_9: @ %if.else
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: cmp r7, #2 ; CHECK-NEXT: cmp r7, #2
; CHECK-NEXT: vstmia r5, {s12, s13} ; CHECK-NEXT: vstmia r5, {s12, s13}
; CHECK-NEXT: bne .LBB19_12 ; CHECK-NEXT: bne .LBB19_11
; CHECK-NEXT: @ %bb.10: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: @ %bb.10: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: vmov.f32 s8, s0 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.f32 s4, s0
; CHECK-NEXT: vmov.f32 s14, s13 ; CHECK-NEXT: vmov.f32 s14, s13
; CHECK-NEXT: vmov.f32 s0, s24
; CHECK-NEXT: vmov.f32 s7, s12 ; CHECK-NEXT: vmov.f32 s7, s12
; CHECK-NEXT: .LBB19_11: @ %if.end69 ; CHECK-NEXT: b .LBB19_12
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: .LBB19_11: @ %if.else64
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: ldr r2, [sp, #44] @ 4-byte Reload
; CHECK-NEXT: b .LBB19_2
; CHECK-NEXT: .LBB19_12: @ %if.else64
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: vmov.f32 s7, s13 ; CHECK-NEXT: vmov.f32 s7, s13
; CHECK-NEXT: ldr r2, [sp, #44] @ 4-byte Reload
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vstr s14, [r5, #8] ; CHECK-NEXT: vstr s14, [r5, #8]
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: .LBB19_12: @ %if.end69
; CHECK-NEXT: @ in Loop: Header=BB19_3 Depth=1
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: b .LBB19_2 ; CHECK-NEXT: b .LBB19_2
; CHECK-NEXT: .LBB19_13: @ %do.end ; CHECK-NEXT: .LBB19_13: @ %do.end
; CHECK-NEXT: add sp, #64 ; CHECK-NEXT: add sp, #48
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
%pState1 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_f32, %struct.arm_biquad_casd_df1_inst_f32* %S, i32 0, i32 1 %pState1 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_f32, %struct.arm_biquad_casd_df1_inst_f32* %S, i32 0, i32 1
%0 = load float*, float** %pState1, align 4 %0 = load float*, float** %pState1, align 4
%pCoeffs2 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_f32, %struct.arm_biquad_casd_df1_inst_f32* %S, i32 0, i32 2 %pCoeffs2 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_f32, %struct.arm_biquad_casd_df1_inst_f32* %S, i32 0, i32 2
%1 = load float*, float** %pCoeffs2, align 4 %1 = load float*, float** %pCoeffs2, align 4
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; CHECK-NEXT: ldrd r12, r6, [r0, #4] ; CHECK-NEXT: ldrd r12, r6, [r0, #4]
; CHECK-NEXT: and r8, r3, #1 ; CHECK-NEXT: and r8, r3, #1
; CHECK-NEXT: ldrb r0, [r0] ; CHECK-NEXT: ldrb r0, [r0]
; CHECK-NEXT: lsrs r3, r3, #1 ; CHECK-NEXT: lsrs r3, r3, #1
; CHECK-NEXT: vldr s0, .LCPI20_0 ; CHECK-NEXT: vldr s0, .LCPI20_0
; CHECK-NEXT: b .LBB20_3 ; CHECK-NEXT: b .LBB20_3
; CHECK-NEXT: .LBB20_1: @ %if.else ; CHECK-NEXT: .LBB20_1: @ %if.else
; CHECK-NEXT: @ in Loop: Header=BB20_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB20_3 Depth=1
; CHECK-NEXT: vstr s4, [r12]
; CHECK-NEXT: vmov.f32 s6, s5 ; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vstr s4, [r12]
; CHECK-NEXT: .LBB20_2: @ %if.end ; CHECK-NEXT: .LBB20_2: @ %if.end
; CHECK-NEXT: @ in Loop: Header=BB20_3 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB20_3 Depth=1
; CHECK-NEXT: vstr s6, [r12, #4] ; CHECK-NEXT: vstr s6, [r12, #4]
; CHECK-NEXT: adds r6, #20 ; CHECK-NEXT: adds r6, #20
; CHECK-NEXT: subs r0, #1 ; CHECK-NEXT: subs r0, #1
; CHECK-NEXT: add.w r12, r12, #8 ; CHECK-NEXT: add.w r12, r12, #8
; CHECK-NEXT: mov r1, r2 ; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: beq .LBB20_8 ; CHECK-NEXT: beq .LBB20_8
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do.end: ; preds = %if.end do.end: ; preds = %if.end
ret void ret void
} }
define arm_aapcs_vfpcc float @vecAddAcrossF32Mve(<4 x float> %in) { define arm_aapcs_vfpcc float @vecAddAcrossF32Mve(<4 x float> %in) {
; CHECK-LABEL: vecAddAcrossF32Mve: ; CHECK-LABEL: vecAddAcrossF32Mve:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f32 s4, s0, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: vadd.f32 s4, s4, s2 ; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: vadd.f32 s0, s4, s3 ; CHECK-NEXT: vadd.f32 s0, s0, s3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = extractelement <4 x float> %in, i32 0 %0 = extractelement <4 x float> %in, i32 0
%1 = extractelement <4 x float> %in, i32 1 %1 = extractelement <4 x float> %in, i32 1
%add = fadd fast float %0, %1 %add = fadd fast float %0, %1
%2 = extractelement <4 x float> %in, i32 2 %2 = extractelement <4 x float> %in, i32 2
%add1 = fadd fast float %add, %2 %add1 = fadd fast float %add, %2
%3 = extractelement <4 x float> %in, i32 3 %3 = extractelement <4 x float> %in, i32 3
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llvm/test/CodeGen/Thumb2/mve-fmas.ll

Show All 16 Lines
; ;
; CHECK-MVE-LABEL: vfma16_v1: ; CHECK-MVE-LABEL: vfma16_v1:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s9 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vins.f16 s0, s13 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s13, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmla.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmla.f16 s1, s5, s9 ; CHECK-MVE-NEXT: vmla.f16 s1, s5, s9
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vins.f16 s1, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s10 ; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vins.f16 s1, s13 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmovx.f16 s13, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmla.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmla.f16 s2, s6, s10 ; CHECK-MVE-NEXT: vmla.f16 s2, s6, s10
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vmovx.f16 s12, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vins.f16 s2, s13 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vmla.f16 s3, s7, s11 ; CHECK-MVE-NEXT: vmla.f16 s3, s7, s11
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s8, s6, s4
; CHECK-MVE-NEXT: vins.f16 s3, s13 ; CHECK-MVE-NEXT: vins.f16 s0, s13
; CHECK-MVE-NEXT: vins.f16 s2, s12
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
ret <8 x half> %1 ret <8 x half> %1
} }
define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) { define arm_aapcs_vfpcc <8 x half> @vfma16_v2(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
Show All 10 Lines
; ;
; CHECK-MVE-LABEL: vfma16_v2: ; CHECK-MVE-LABEL: vfma16_v2:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s9 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vins.f16 s0, s13 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s13, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmla.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmla.f16 s1, s5, s9 ; CHECK-MVE-NEXT: vmla.f16 s1, s5, s9
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vins.f16 s1, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s10 ; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vins.f16 s1, s13 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmovx.f16 s13, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmla.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmla.f16 s2, s6, s10 ; CHECK-MVE-NEXT: vmla.f16 s2, s6, s10
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vmovx.f16 s12, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vins.f16 s2, s13 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vmla.f16 s3, s7, s11 ; CHECK-MVE-NEXT: vmla.f16 s3, s7, s11
; CHECK-MVE-NEXT: vmla.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s8, s6, s4
; CHECK-MVE-NEXT: vins.f16 s3, s13 ; CHECK-MVE-NEXT: vins.f16 s0, s13
; CHECK-MVE-NEXT: vins.f16 s2, s12
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %0, %src1 %1 = fadd <8 x half> %0, %src1
ret <8 x half> %1 ret <8 x half> %1
} }
define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) { define arm_aapcs_vfpcc <8 x half> @vfms16(<8 x half> %src1, <8 x half> %src2, <8 x half> %src3) {
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; ;
; CHECK-MVE-LABEL: vfms16: ; CHECK-MVE-LABEL: vfms16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmls.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s9 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vins.f16 s0, s13 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s13, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmls.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmls.f16 s1, s5, s9 ; CHECK-MVE-NEXT: vmls.f16 s1, s5, s9
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vins.f16 s1, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s10 ; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vins.f16 s1, s13 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmovx.f16 s13, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmls.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmls.f16 s2, s6, s10 ; CHECK-MVE-NEXT: vmls.f16 s2, s6, s10
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vmovx.f16 s12, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vins.f16 s2, s13 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vmovx.f16 s13, s3
; CHECK-MVE-NEXT: vmovx.f16 s14, s7
; CHECK-MVE-NEXT: vmls.f16 s3, s7, s11 ; CHECK-MVE-NEXT: vmls.f16 s3, s7, s11
; CHECK-MVE-NEXT: vmls.f16 s13, s14, s12 ; CHECK-MVE-NEXT: vmls.f16 s8, s6, s4
; CHECK-MVE-NEXT: vins.f16 s3, s13 ; CHECK-MVE-NEXT: vins.f16 s0, s13
; CHECK-MVE-NEXT: vins.f16 s2, s12
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fsub <8 x half> %src1, %0 %1 = fsub <8 x half> %src1, %0
ret <8 x half> %1 ret <8 x half> %1
} }
define arm_aapcs_vfpcc <8 x half> @vfmar16(<8 x half> %src1, <8 x half> %src2, float %src3o) { define arm_aapcs_vfpcc <8 x half> @vfmar16(<8 x half> %src1, <8 x half> %src2, float %src3o) {
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; ;
; CHECK-MVE-LABEL: vfmar16: ; CHECK-MVE-LABEL: vfmar16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmovx.f16 s10, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8 ; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmovx.f16 s10, s5 ; CHECK-MVE-NEXT: vmovx.f16 s10, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmla.f16 s1, s5, s8 ; CHECK-MVE-NEXT: vmla.f16 s1, s5, s8
; CHECK-MVE-NEXT: vins.f16 s1, s12 ; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s12, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s10, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s10
; CHECK-MVE-NEXT: vmovx.f16 s10, s2
; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8
; CHECK-MVE-NEXT: vmla.f16 s2, s6, s8 ; CHECK-MVE-NEXT: vmla.f16 s2, s6, s8
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vmovx.f16 s10, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vins.f16 s2, s12 ; CHECK-MVE-NEXT: vmla.f16 s6, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s12, s3
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s8
; CHECK-MVE-NEXT: vmla.f16 s3, s7, s8 ; CHECK-MVE-NEXT: vmla.f16 s3, s7, s8
; CHECK-MVE-NEXT: vins.f16 s3, s12 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vins.f16 s2, s10
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%0 = fmul <8 x half> %src2, %sp %0 = fmul <8 x half> %src2, %sp
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
ret <8 x half> %1 ret <8 x half> %1
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; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8
; CHECK-MVE-VMLA-NEXT: vfmas.f16 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmas.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16: ; CHECK-MVE-LABEL: vfma16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q3, q0 ; CHECK-MVE-NEXT: vmov q3, q0
; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s8
; CHECK-MVE-NEXT: vmovx.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s2, s12
; CHECK-MVE-NEXT: vmov.f32 s8, s3 ; CHECK-MVE-NEXT: vmov.f32 s8, s3
; CHECK-MVE-NEXT: vmovx.f16 s10, s4 ; CHECK-MVE-NEXT: vmla.f16 s8, s2, s0
; CHECK-MVE-NEXT: vmov.f32 s0, s3 ; CHECK-MVE-NEXT: vmov.f32 s0, s3
; CHECK-MVE-NEXT: vmovx.f16 s9, s12
; CHECK-MVE-NEXT: vmla.f16 s8, s9, s10
; CHECK-MVE-NEXT: vmla.f16 s0, s12, s4 ; CHECK-MVE-NEXT: vmla.f16 s0, s12, s4
; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmov.f32 s9, s3
; CHECK-MVE-NEXT: vmov.f32 s1, s3 ; CHECK-MVE-NEXT: vmov.f32 s1, s3
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmovx.f16 s10, s13 ; CHECK-MVE-NEXT: vmovx.f16 s2, s5
; CHECK-MVE-NEXT: vmovx.f16 s4, s13
; CHECK-MVE-NEXT: vmov.f32 s8, s3
; CHECK-MVE-NEXT: vmla.f16 s8, s4, s2
; CHECK-MVE-NEXT: vmla.f16 s1, s13, s5 ; CHECK-MVE-NEXT: vmla.f16 s1, s13, s5
; CHECK-MVE-NEXT: vmla.f16 s9, s10, s8 ; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vmovx.f16 s2, s6
; CHECK-MVE-NEXT: vins.f16 s1, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s14
; CHECK-MVE-NEXT: vmov.f32 s9, s3 ; CHECK-MVE-NEXT: vmov.f32 s8, s3
; CHECK-MVE-NEXT: vmla.f16 s8, s4, s2
; CHECK-MVE-NEXT: vmov.f32 s2, s3 ; CHECK-MVE-NEXT: vmov.f32 s2, s3
; CHECK-MVE-NEXT: vmovx.f16 s10, s14
; CHECK-MVE-NEXT: vmla.f16 s9, s10, s8
; CHECK-MVE-NEXT: vmla.f16 s2, s14, s6 ; CHECK-MVE-NEXT: vmla.f16 s2, s14, s6
; CHECK-MVE-NEXT: vins.f16 s2, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.f32 s9, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s7 ; CHECK-MVE-NEXT: vmov.f32 s8, s3
; CHECK-MVE-NEXT: vmovx.f16 s10, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmla.f16 s9, s10, s8
; CHECK-MVE-NEXT: vmla.f16 s3, s15, s7 ; CHECK-MVE-NEXT: vmla.f16 s3, s15, s7
; CHECK-MVE-NEXT: vins.f16 s3, s9 ; CHECK-MVE-NEXT: vmla.f16 s8, s6, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%0 = fmul <8 x half> %src1, %src2 %0 = fmul <8 x half> %src1, %src2
%1 = fadd <8 x half> %sp, %0 %1 = fadd <8 x half> %sp, %0
ret <8 x half> %1 ret <8 x half> %1
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; CHECK-MVE-VMLA-LABEL: vfmas32: ; CHECK-MVE-VMLA-LABEL: vfmas32:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vfmas.f32 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmas.f32 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmas32: ; CHECK-MVE-LABEL: vfmas32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: @ kill: def $s8 killed $s8 def $q2
; CHECK-MVE-NEXT: vmov.f32 s11, s8 ; CHECK-MVE-NEXT: vmov.f32 s11, s8
; CHECK-MVE-NEXT: vmla.f32 s11, s3, s7
; CHECK-MVE-NEXT: vmov.f32 s10, s8 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmla.f32 s10, s2, s6
; CHECK-MVE-NEXT: vmov.f32 s9, s8 ; CHECK-MVE-NEXT: vmov.f32 s9, s8
; CHECK-MVE-NEXT: vmla.f32 s9, s1, s5
; CHECK-MVE-NEXT: vmla.f32 s8, s0, s4 ; CHECK-MVE-NEXT: vmla.f32 s8, s0, s4
; CHECK-MVE-NEXT: vmla.f32 s11, s3, s7
; CHECK-MVE-NEXT: vmla.f32 s10, s2, s6
; CHECK-MVE-NEXT: vmla.f32 s9, s1, s5
; CHECK-MVE-NEXT: vmov q0, q2 ; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src3, i32 0 %i = insertelement <4 x float> undef, float %src3, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%0 = fmul <4 x float> %src1, %src2 %0 = fmul <4 x float> %src1, %src2
%1 = fadd <4 x float> %sp, %0 %1 = fadd <4 x float> %sp, %0
ret <4 x float> %1 ret <4 x float> %1
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; CHECK-MVE-VMLA-LABEL: vfma16_v1_pred: ; CHECK-MVE-VMLA-LABEL: vfma16_v1_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v1_pred: ; CHECK-MVE-LABEL: vfma16_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s0 ; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s1 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s16, s9 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s1 ; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s18, s5, s9 ; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s2 ; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s2 ; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s18, s6, s10 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s3 ; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f16 s18, s7, s11 ; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1
ret <8 x half> %s ret <8 x half> %s
} }
Show All 9 Lines
; CHECK-MVE-VMLA-LABEL: vfma16_v2_pred: ; CHECK-MVE-VMLA-LABEL: vfma16_v2_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v2_pred: ; CHECK-MVE-LABEL: vfma16_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s0 ; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s1 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s16, s9 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s1 ; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s18, s5, s9 ; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s2 ; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s2 ; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s18, s6, s10 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmla.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s3 ; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f16 s18, s7, s11 ; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %0, %src1 %1 = fadd <8 x half> %0, %src1
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1
ret <8 x half> %s ret <8 x half> %s
} }
Show All 9 Lines
; CHECK-MVE-VMLA-LABEL: vfms16_pred: ; CHECK-MVE-VMLA-LABEL: vfms16_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmst.f16 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmst.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfms16_pred: ; CHECK-MVE-LABEL: vfms16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s0 ; CHECK-MVE-NEXT: vmls.f16 s14, s4, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmls.f16 s12, s4, s8 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
; CHECK-MVE-NEXT: vseleq.f16 s12, s0, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s1 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s16, s9 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s1 ; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmls.f16 s18, s5, s9 ; CHECK-MVE-NEXT: vmls.f16 s8, s5, s9
; CHECK-MVE-NEXT: vseleq.f16 s13, s1, s18 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vcmp.f16 s18, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s2 ; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s2 ; CHECK-MVE-NEXT: vmls.f16 s8, s6, s10
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmls.f16 s18, s6, s10 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s2, s18 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s7
; CHECK-MVE-NEXT: vcmp.f16 s18, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s20, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s22, s20 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmls.f16 s22, s18, s16 ; CHECK-MVE-NEXT: vmls.f16 s10, s6, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s20, s22 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmov.f32 s18, s3 ; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmls.f16 s18, s7, s11 ; CHECK-MVE-NEXT: vmls.f16 s6, s7, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s3, s18 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fsub <8 x half> %src1, %0 %1 = fsub <8 x half> %src1, %0
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1 %s = select <8 x i1> %c, <8 x half> %1, <8 x half> %src1
ret <8 x half> %s ret <8 x half> %s
} }
Show All 14 Lines
; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8
; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar16_pred: ; CHECK-MVE-LABEL: vfmar16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmovx.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s10, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s10, s0 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-NEXT: vmov.f32 s14, s10 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s12
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s14, s10, s8
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s14 ; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s0 ; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s4, s12 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s10
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmovx.f16 s10, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmov.f32 s12, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s1 ; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s13, s5, s12 ; CHECK-MVE-NEXT: vmla.f16 s10, s5, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s9, s1, s13 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10
; CHECK-MVE-NEXT: vmovx.f16 s13, s2 ; CHECK-MVE-NEXT: vmovx.f16 s10, s2
; CHECK-MVE-NEXT: vins.f16 s9, s14 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s12, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s2 ; CHECK-MVE-NEXT: vmov.f32 s10, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s13, s6, s12 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
; CHECK-MVE-NEXT: vseleq.f16 s10, s2, s13
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s10, s14 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s14, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s13 ; CHECK-MVE-NEXT: vmov.f32 s10, s6
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s3 ; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f16 s13, s7, s12 ; CHECK-MVE-NEXT: vmla.f16 s6, s7, s8
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s11, s3, s13 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
; CHECK-MVE-NEXT: vins.f16 s11, s14 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%0 = fmul <8 x half> %src2, %sp %0 = fmul <8 x half> %src2, %sp
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
Show All 19 Lines
; CHECK-MVE-VMLA-NEXT: vfmast.f16 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmast.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_pred: ; CHECK-MVE-LABEL: vfma16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s10, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s10, #0 ; CHECK-MVE-NEXT: vcmp.f16 s10, #0
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmov.f32 s8, s12 ; CHECK-MVE-NEXT: vmov.f32 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s14, s10 ; CHECK-MVE-NEXT: vmla.f16 s14, s12, s10
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s14, s8 ; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s12 ; CHECK-MVE-NEXT: vmla.f16 s12, s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vseleq.f16 s8, s0, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s5
; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s10
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14 ; CHECK-MVE-NEXT: vmovx.f16 s10, s1
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s12 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s13, s1, s5 ; CHECK-MVE-NEXT: vmla.f16 s10, s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s9, s1, s13 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10
; CHECK-MVE-NEXT: vmovx.f16 s13, s2 ; CHECK-MVE-NEXT: vmovx.f16 s10, s2
; CHECK-MVE-NEXT: vins.f16 s9, s14 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s12 ; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14 ; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s12 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s10, s2, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s13, s2, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
; CHECK-MVE-NEXT: vseleq.f16 s10, s2, s13
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s10, s14 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s14, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s12 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s13, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmla.f16 s15, s13, s14 ; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s3, s7 ; CHECK-MVE-NEXT: vmla.f16 s8, s3, s7
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s11, s3, s12 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s8
; CHECK-MVE-NEXT: vins.f16 s11, s14 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%0 = fmul <8 x half> %src1, %src2 %0 = fmul <8 x half> %src1, %src2
%1 = fadd <8 x half> %sp, %0 %1 = fadd <8 x half> %sp, %0
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
Show All 12 Lines
; CHECK-MVE-VMLA-LABEL: vfma32_v1_pred: ; CHECK-MVE-VMLA-LABEL: vfma32_v1_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma32_v1_pred: ; CHECK-MVE-LABEL: vfma32_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmov.f32 s14, s0 ; CHECK-MVE-NEXT: vmov.f32 s8, s3
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s2 ; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
; CHECK-MVE-NEXT: cset r2, ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov.f32 s5, s2
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s7, #0 ; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmla.f32 s13, s7, s11
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f32 s8, s7, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9 ; CHECK-MVE-NEXT: vmla.f32 s5, s6, s10
; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s8
; CHECK-MVE-NEXT: vmla.f32 s15, s6, s10
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <4 x float> %src2, %src3 %0 = fmul <4 x float> %src2, %src3
%1 = fadd <4 x float> %src1, %0 %1 = fadd <4 x float> %src1, %0
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
ret <4 x float> %s ret <4 x float> %s
} }
Show All 9 Lines
; CHECK-MVE-VMLA-LABEL: vfma32_v2_pred: ; CHECK-MVE-VMLA-LABEL: vfma32_v2_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma32_v2_pred: ; CHECK-MVE-LABEL: vfma32_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmov.f32 s14, s0 ; CHECK-MVE-NEXT: vmov.f32 s8, s3
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s2 ; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
; CHECK-MVE-NEXT: cset r2, ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov.f32 s5, s2
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s7, #0 ; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmla.f32 s13, s7, s11
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f32 s8, s7, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9 ; CHECK-MVE-NEXT: vmla.f32 s5, s6, s10
; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s8
; CHECK-MVE-NEXT: vmla.f32 s15, s6, s10
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <4 x float> %src2, %src3 %0 = fmul <4 x float> %src2, %src3
%1 = fadd <4 x float> %0, %src1 %1 = fadd <4 x float> %0, %src1
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
ret <4 x float> %s ret <4 x float> %s
} }
Show All 9 Lines
; CHECK-MVE-VMLA-LABEL: vfms32_pred: ; CHECK-MVE-VMLA-LABEL: vfms32_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmst.f32 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmst.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfms32_pred: ; CHECK-MVE-LABEL: vfms32_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s13, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: vmls.f32 s14, s4, s8
; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmov.f32 s14, s0 ; CHECK-MVE-NEXT: vmov.f32 s8, s3
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov.f32 s15, s2 ; CHECK-MVE-NEXT: vmls.f32 s12, s5, s9
; CHECK-MVE-NEXT: cset r2, ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov.f32 s5, s2
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s7, #0 ; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmls.f32 s13, s7, s11
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmls.f32 s8, s7, s11
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmls.f32 s12, s5, s9 ; CHECK-MVE-NEXT: vmls.f32 s5, s6, s10
; CHECK-MVE-NEXT: vmls.f32 s14, s4, s8 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s8
; CHECK-MVE-NEXT: vmls.f32 s15, s6, s10
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s13
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s15 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s12 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s14 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <4 x float> %src2, %src3 %0 = fmul <4 x float> %src2, %src3
%1 = fsub <4 x float> %src1, %0 %1 = fsub <4 x float> %src1, %0
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
ret <4 x float> %s ret <4 x float> %s
} }
Show All 12 Lines
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar32_pred: ; CHECK-MVE-LABEL: vfmar32_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s3 ; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vmov.f32 s9, s2 ; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8
; CHECK-MVE-NEXT: vmov.f32 s5, s2
; CHECK-MVE-NEXT: cset r2, ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f32 s7, #0 ; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: movs r3, #0 ; CHECK-MVE-NEXT: movs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vmla.f32 s14, s7, s8
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f32 s14, s7, s8
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8 ; CHECK-MVE-NEXT: vmla.f32 s5, s6, s8
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
; CHECK-MVE-NEXT: vmla.f32 s9, s6, s8
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s14
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s9 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s10 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src3, i32 0 %i = insertelement <4 x float> undef, float %src3, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%0 = fmul <4 x float> %src2, %sp %0 = fmul <4 x float> %src2, %sp
%1 = fadd <4 x float> %src1, %0 %1 = fadd <4 x float> %src1, %0
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
Show All 24 Lines
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s8 ; CHECK-MVE-NEXT: vmov.f32 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s7, #0 ; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: cset r2, ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r3, ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmla.f32 s14, s3, s7 ; CHECK-MVE-NEXT: vmla.f32 s14, s3, s7
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6 ; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6
; CHECK-MVE-NEXT: vseleq.f32 s7, s3, s14 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s6, s2, s8 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s5, s1, s10 ; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s4, s0, s12 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src3, i32 0 %i = insertelement <4 x float> undef, float %src3, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%0 = fmul <4 x float> %src1, %src2 %0 = fmul <4 x float> %src1, %src2
%1 = fadd <4 x float> %sp, %0 %1 = fadd <4 x float> %sp, %0
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
ret <4 x float> %s ret <4 x float> %s
} }

llvm/test/CodeGen/Thumb2/mve-fmath.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @sqrt_float32_t(<4 x float> %src) {
; CHECK-LABEL: sqrt_float32_t: ; CHECK-LABEL: sqrt_float32_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vsqrt.f32 s7, s3 ; CHECK-NEXT: vsqrt.f32 s3, s3
; CHECK-NEXT: vsqrt.f32 s6, s2 ; CHECK-NEXT: vsqrt.f32 s2, s2
; CHECK-NEXT: vsqrt.f32 s5, s1 ; CHECK-NEXT: vsqrt.f32 s1, s1
; CHECK-NEXT: vsqrt.f32 s4, s0 ; CHECK-NEXT: vsqrt.f32 s0, s0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @sqrt_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @sqrt_float16_t(<8 x half> %src) {
; CHECK-LABEL: sqrt_float16_t: ; CHECK-LABEL: sqrt_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s0, s4 ; CHECK-NEXT: vsqrt.f16 s0, s0
; CHECK-NEXT: vsqrt.f16 s8, s0 ; CHECK-NEXT: vsqrt.f16 s4, s4
; CHECK-NEXT: vsqrt.f16 s0, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vins.f16 s0, s8 ; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vmovx.f16 s8, s5 ; CHECK-NEXT: vsqrt.f16 s4, s4
; CHECK-NEXT: vsqrt.f16 s8, s8 ; CHECK-NEXT: vsqrt.f16 s1, s1
; CHECK-NEXT: vsqrt.f16 s1, s5 ; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vins.f16 s1, s8 ; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vmovx.f16 s8, s6 ; CHECK-NEXT: vsqrt.f16 s4, s4
; CHECK-NEXT: vsqrt.f16 s8, s8 ; CHECK-NEXT: vsqrt.f16 s2, s2
; CHECK-NEXT: vsqrt.f16 s2, s6 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vins.f16 s2, s8 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmovx.f16 s8, s7 ; CHECK-NEXT: vsqrt.f16 s4, s4
; CHECK-NEXT: vsqrt.f16 s8, s8 ; CHECK-NEXT: vsqrt.f16 s3, s3
; CHECK-NEXT: vsqrt.f16 s3, s7 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vins.f16 s3, s8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.sqrt.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.sqrt.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @sqrt_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @sqrt_float64_t(<2 x double> %src) {
; CHECK-LABEL: sqrt_float64_t: ; CHECK-LABEL: sqrt_float64_t:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) {
; CHECK-LABEL: cos_float16_t: ; CHECK-LABEL: cos_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov s20, r0 ; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s20, s20 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s20, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s21, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s21, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s22, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s22, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s23, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s23, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @cos_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @cos_float64_t(<2 x double> %src) {
; CHECK-LABEL: cos_float64_t: ; CHECK-LABEL: cos_float64_t:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) {
; CHECK-LABEL: sin_float16_t: ; CHECK-LABEL: sin_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov s20, r0 ; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s20, s20 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s20, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s21, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s21, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s22, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s22, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s23, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s23, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @sin_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @sin_float64_t(<2 x double> %src) {
; CHECK-LABEL: sin_float64_t: ; CHECK-LABEL: sin_float64_t:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) {
; CHECK-LABEL: exp_float16_t: ; CHECK-LABEL: exp_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov s20, r0 ; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s20, s20 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s20, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s21, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s21, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s22, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s22, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s23, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s23, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @exp_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @exp_float64_t(<2 x double> %src) {
; CHECK-LABEL: exp_float64_t: ; CHECK-LABEL: exp_float64_t:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) {
; CHECK-LABEL: exp2_float16_t: ; CHECK-LABEL: exp2_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov s20, r0 ; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s20, s20 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s20, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s21, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s21, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s22, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s22, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s23, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s23, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @exp2_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @exp2_float64_t(<2 x double> %src) {
; CHECK-LABEL: exp2_float64_t: ; CHECK-LABEL: exp2_float64_t:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) {
; CHECK-LABEL: log_float16_t: ; CHECK-LABEL: log_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov s20, r0 ; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s20, s20 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s20, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s21, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s21, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s22, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s22, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s23, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s23, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @log_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @log_float64_t(<2 x double> %src) {
; CHECK-LABEL: log_float64_t: ; CHECK-LABEL: log_float64_t:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) {
; CHECK-LABEL: log2_float16_t: ; CHECK-LABEL: log2_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov s20, r0 ; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s20, s20 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s20, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s21, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s21, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s22, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s22, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s23, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s23, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @log2_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @log2_float64_t(<2 x double> %src) {
; CHECK-LABEL: log2_float64_t: ; CHECK-LABEL: log2_float64_t:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) {
; CHECK-LABEL: log10_float16_t: ; CHECK-LABEL: log10_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov s20, r0 ; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s20, s20 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s20, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s21, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s21, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s22, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s22, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s23, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s23, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @log10_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @log10_float64_t(<2 x double> %src) {
; CHECK-LABEL: log10_float64_t: ; CHECK-LABEL: log10_float64_t:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: pow_float16_t: ; CHECK-LABEL: pow_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q5, q0 ; CHECK-NEXT: vmov q5, q0
; CHECK-NEXT: vmov q4, q1 ; CHECK-NEXT: vmov q4, q1
; CHECK-NEXT: vcvtb.f32.f16 s0, s20 ; CHECK-NEXT: vcvtb.f32.f16 s0, s20
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vcvtt.f32.f16 s0, s20 ; CHECK-NEXT: vcvtt.f32.f16 s0, s20
; CHECK-NEXT: vmov s24, r0
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov s16, r0
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s24, s24 ; CHECK-NEXT: vcvtb.f16.f32 s2, s16
; CHECK-NEXT: vcvtt.f16.f32 s24, s0 ; CHECK-NEXT: vcvtt.f16.f32 s16, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s21 ; CHECK-NEXT: vcvtb.f32.f16 s0, s21
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s25, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s21 ; CHECK-NEXT: vcvtt.f32.f16 s0, s21
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s25, s0 ; CHECK-NEXT: vcvtt.f16.f32 s17, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s22 ; CHECK-NEXT: vcvtb.f32.f16 s0, s22
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s26, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s22 ; CHECK-NEXT: vcvtt.f32.f16 s0, s22
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s26, s0 ; CHECK-NEXT: vcvtt.f16.f32 s18, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s23 ; CHECK-NEXT: vcvtb.f32.f16 s0, s23
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s27, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s23 ; CHECK-NEXT: vcvtt.f32.f16 s0, s23
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtt.f16.f32 s27, s0 ; CHECK-NEXT: vcvtt.f16.f32 s19, s0
; CHECK-NEXT: vmov q0, q6 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2) %0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @pow_float64_t(<2 x double> %src1, <2 x double> %src2) { define arm_aapcs_vfpcc <2 x double> @pow_float64_t(<2 x double> %src1, <2 x double> %src2) {
; CHECK-LABEL: pow_float64_t: ; CHECK-LABEL: pow_float64_t:
Show All 34 Lines
; CHECK-NEXT: lsrs r1, r1, #31 ; CHECK-NEXT: lsrs r1, r1, #31
; CHECK-NEXT: bfi r0, r1, #31, #1 ; CHECK-NEXT: bfi r0, r1, #31, #1
; CHECK-NEXT: lsrs r1, r2, #31 ; CHECK-NEXT: lsrs r1, r2, #31
; CHECK-NEXT: bfi r4, r1, #31, #1 ; CHECK-NEXT: bfi r4, r1, #31, #1
; CHECK-NEXT: lsr.w r1, lr, #31 ; CHECK-NEXT: lsr.w r1, lr, #31
; CHECK-NEXT: bfi r5, r1, #31, #1 ; CHECK-NEXT: bfi r5, r1, #31, #1
; CHECK-NEXT: lsr.w r1, r12, #31 ; CHECK-NEXT: lsr.w r1, r12, #31
; CHECK-NEXT: bfi r3, r1, #31, #1 ; CHECK-NEXT: bfi r3, r1, #31, #1
; CHECK-NEXT: vmov s3, r5
; CHECK-NEXT: vmov s2, r4 ; CHECK-NEXT: vmov s2, r4
; CHECK-NEXT: vmov s3, r5
; CHECK-NEXT: vmov s1, r0 ; CHECK-NEXT: vmov s1, r0
; CHECK-NEXT: vmov s0, r3 ; CHECK-NEXT: vmov s0, r3
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = call fast <4 x float> @llvm.copysign.v4f32(<4 x float> %src1, <4 x float> %src2) %0 = call fast <4 x float> @llvm.copysign.v4f32(<4 x float> %src1, <4 x float> %src2)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @copysign_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: copysign_float16_t: ; CHECK-LABEL: copysign_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #32
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmovx.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vstr.16 s8, [sp, #24] ; CHECK-NEXT: vstr.16 s8, [sp, #24]
; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vstr.16 s4, [sp, #28] ; CHECK-NEXT: vstr.16 s4, [sp, #28]
; CHECK-NEXT: vstr.16 s8, [sp, #16] ; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vmovx.f16 s8, s6 ; CHECK-NEXT: vstr.16 s4, [sp, #16]
; CHECK-NEXT: vmovx.f16 s4, s6
; CHECK-NEXT: vstr.16 s5, [sp, #20] ; CHECK-NEXT: vstr.16 s5, [sp, #20]
; CHECK-NEXT: vstr.16 s8, [sp, #8] ; CHECK-NEXT: vstr.16 s4, [sp, #8]
; CHECK-NEXT: vmovx.f16 s8, s7 ; CHECK-NEXT: vmovx.f16 s4, s7
; CHECK-NEXT: vstr.16 s6, [sp, #12] ; CHECK-NEXT: vstr.16 s6, [sp, #12]
; CHECK-NEXT: vstr.16 s8, [sp] ; CHECK-NEXT: vstr.16 s4, [sp]
; CHECK-NEXT: vstr.16 s7, [sp, #4] ; CHECK-NEXT: vstr.16 s7, [sp, #4]
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: ldrb.w r0, [sp, #25] ; CHECK-NEXT: ldrb.w r0, [sp, #25]
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vabs.f16 s4, s4 ; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: vneg.f16 s6, s4 ; CHECK-NEXT: vabs.f16 s0, s0
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #29] ; CHECK-NEXT: ldrb.w r0, [sp, #29]
; CHECK-NEXT: vseleq.f16 s8, s4, s6 ; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: vabs.f16 s4, s0 ; CHECK-NEXT: vneg.f16 s6, s0
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vabs.f16 s0, s3
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #17] ; CHECK-NEXT: ldrb.w r0, [sp, #17]
; CHECK-NEXT: vseleq.f16 s4, s4, s6 ; CHECK-NEXT: vseleq.f16 s0, s0, s6
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vabs.f16 s8, s8 ; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #21] ; CHECK-NEXT: ldrb.w r0, [sp, #21]
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: vabs.f16 s10, s1 ; CHECK-NEXT: vabs.f16 s6, s1
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s12, s10 ; CHECK-NEXT: vneg.f16 s8, s6
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #9] ; CHECK-NEXT: ldrb.w r0, [sp, #9]
; CHECK-NEXT: vseleq.f16 s5, s10, s12 ; CHECK-NEXT: vseleq.f16 s1, s6, s8
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vins.f16 s5, s8 ; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vabs.f16 s8, s8 ; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #13] ; CHECK-NEXT: ldrb.w r0, [sp, #13]
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: vabs.f16 s10, s2 ; CHECK-NEXT: vabs.f16 s2, s2
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s12, s10 ; CHECK-NEXT: vneg.f16 s6, s2
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #1] ; CHECK-NEXT: ldrb.w r0, [sp, #1]
; CHECK-NEXT: vseleq.f16 s6, s10, s12 ; CHECK-NEXT: vseleq.f16 s2, s2, s6
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vins.f16 s6, s8 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s8, s3 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vabs.f16 s8, s8 ; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ldrb.w r0, [sp, #5] ; CHECK-NEXT: ldrb.w r0, [sp, #5]
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: vabs.f16 s6, s3
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s8, s6
; CHECK-NEXT: cset r0, ne ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vseleq.f16 s7, s0, s2 ; CHECK-NEXT: vseleq.f16 s3, s6, s8
; CHECK-NEXT: vins.f16 s7, s8 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.copysign.v8f16(<8 x half> %src1, <8 x half> %src2) %0 = call fast <8 x half> @llvm.copysign.v8f16(<8 x half> %src1, <8 x half> %src2)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @copysign_float64_t(<2 x double> %src1, <2 x double> %src2) { define arm_aapcs_vfpcc <2 x double> @copysign_float64_t(<2 x double> %src1, <2 x double> %src2) {
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fneg_float16_t: ; CHECK-MVE-LABEL: fneg_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s0, s4 ; CHECK-MVE-NEXT: vneg.f16 s0, s0
; CHECK-MVE-NEXT: vneg.f16 s8, s0 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
; CHECK-MVE-NEXT: vneg.f16 s0, s4 ; CHECK-MVE-NEXT: vins.f16 s0, s4
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
; CHECK-MVE-NEXT: vneg.f16 s8, s8 ; CHECK-MVE-NEXT: vneg.f16 s1, s1
; CHECK-MVE-NEXT: vneg.f16 s1, s5 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vins.f16 s1, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
; CHECK-MVE-NEXT: vneg.f16 s8, s8 ; CHECK-MVE-NEXT: vneg.f16 s2, s2
; CHECK-MVE-NEXT: vneg.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vins.f16 s2, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s8, s7 ; CHECK-MVE-NEXT: vneg.f16 s4, s4
; CHECK-MVE-NEXT: vneg.f16 s8, s8 ; CHECK-MVE-NEXT: vneg.f16 s3, s3
; CHECK-MVE-NEXT: vneg.f16 s3, s7 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fneg_float16_t: ; CHECK-MVEFP-LABEL: fneg_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vneg.f16 q0, q0 ; CHECK-MVEFP-NEXT: vneg.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src %0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: fneg_float32_t: ; CHECK-MVE-LABEL: fneg_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vneg.f32 s7, s3 ; CHECK-MVE-NEXT: vneg.f32 s3, s3
; CHECK-MVE-NEXT: vneg.f32 s6, s2 ; CHECK-MVE-NEXT: vneg.f32 s2, s2
; CHECK-MVE-NEXT: vneg.f32 s5, s1 ; CHECK-MVE-NEXT: vneg.f32 s1, s1
; CHECK-MVE-NEXT: vneg.f32 s4, s0 ; CHECK-MVE-NEXT: vneg.f32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fneg_float32_t: ; CHECK-MVEFP-LABEL: fneg_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vneg.f32 q0, q0 ; CHECK-MVEFP-NEXT: vneg.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fsub nnan ninf nsz <4 x float> <float 0.0e0, float 0.0e0, float 0.0e0, float 0.0e0>, %src %0 = fsub nnan ninf nsz <4 x float> <float 0.0e0, float 0.0e0, float 0.0e0, float 0.0e0>, %src
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entry: entry:
%0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src %0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src
ret <2 x double> %0 ret <2 x double> %0
} }
define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fabs_float16_t: ; CHECK-MVE-LABEL: fabs_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s0, s4 ; CHECK-MVE-NEXT: vabs.f16 s0, s0
; CHECK-MVE-NEXT: vabs.f16 s8, s0 ; CHECK-MVE-NEXT: vabs.f16 s4, s4
; CHECK-MVE-NEXT: vabs.f16 s0, s4 ; CHECK-MVE-NEXT: vins.f16 s0, s4
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vabs.f16 s4, s4
; CHECK-MVE-NEXT: vabs.f16 s8, s8 ; CHECK-MVE-NEXT: vabs.f16 s1, s1
; CHECK-MVE-NEXT: vabs.f16 s1, s5 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vins.f16 s1, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vabs.f16 s4, s4
; CHECK-MVE-NEXT: vabs.f16 s8, s8 ; CHECK-MVE-NEXT: vabs.f16 s2, s2
; CHECK-MVE-NEXT: vabs.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vins.f16 s2, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s8, s7 ; CHECK-MVE-NEXT: vabs.f16 s4, s4
; CHECK-MVE-NEXT: vabs.f16 s8, s8 ; CHECK-MVE-NEXT: vabs.f16 s3, s3
; CHECK-MVE-NEXT: vabs.f16 s3, s7 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fabs_float16_t: ; CHECK-MVEFP-LABEL: fabs_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vabs.f16 q0, q0 ; CHECK-MVEFP-NEXT: vabs.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src) %0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: fabs_float32_t: ; CHECK-MVE-LABEL: fabs_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vabs.f32 s7, s3 ; CHECK-MVE-NEXT: vabs.f32 s3, s3
; CHECK-MVE-NEXT: vabs.f32 s6, s2 ; CHECK-MVE-NEXT: vabs.f32 s2, s2
; CHECK-MVE-NEXT: vabs.f32 s5, s1 ; CHECK-MVE-NEXT: vabs.f32 s1, s1
; CHECK-MVE-NEXT: vabs.f32 s4, s0 ; CHECK-MVE-NEXT: vabs.f32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fabs_float32_t: ; CHECK-MVEFP-LABEL: fabs_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vabs.f32 q0, q0 ; CHECK-MVEFP-NEXT: vabs.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call nnan ninf nsz <4 x float> @llvm.fabs.v4f32(<4 x float> %src) %0 = call nnan ninf nsz <4 x float> @llvm.fabs.v4f32(<4 x float> %src)
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llvm/test/CodeGen/Thumb2/mve-frint.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <4 x float> @fceil_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @fceil_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: fceil_float32_t: ; CHECK-MVE-LABEL: fceil_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vrintp.f32 s7, s3 ; CHECK-MVE-NEXT: vrintp.f32 s3, s3
; CHECK-MVE-NEXT: vrintp.f32 s6, s2 ; CHECK-MVE-NEXT: vrintp.f32 s2, s2
; CHECK-MVE-NEXT: vrintp.f32 s5, s1 ; CHECK-MVE-NEXT: vrintp.f32 s1, s1
; CHECK-MVE-NEXT: vrintp.f32 s4, s0 ; CHECK-MVE-NEXT: vrintp.f32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fceil_float32_t: ; CHECK-MVEFP-LABEL: fceil_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintp.f32 q0, q0 ; CHECK-MVEFP-NEXT: vrintp.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @fceil_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fceil_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fceil_float16_t: ; CHECK-MVE-LABEL: fceil_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s0, s4 ; CHECK-MVE-NEXT: vrintp.f16 s0, s0
; CHECK-MVE-NEXT: vrintp.f16 s8, s0 ; CHECK-MVE-NEXT: vrintp.f16 s4, s4
; CHECK-MVE-NEXT: vrintp.f16 s0, s4 ; CHECK-MVE-NEXT: vins.f16 s0, s4
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vrintp.f16 s4, s4
; CHECK-MVE-NEXT: vrintp.f16 s8, s8 ; CHECK-MVE-NEXT: vrintp.f16 s1, s1
; CHECK-MVE-NEXT: vrintp.f16 s1, s5 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vins.f16 s1, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vrintp.f16 s4, s4
; CHECK-MVE-NEXT: vrintp.f16 s8, s8 ; CHECK-MVE-NEXT: vrintp.f16 s2, s2
; CHECK-MVE-NEXT: vrintp.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vins.f16 s2, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s8, s7 ; CHECK-MVE-NEXT: vrintp.f16 s4, s4
; CHECK-MVE-NEXT: vrintp.f16 s8, s8 ; CHECK-MVE-NEXT: vrintp.f16 s3, s3
; CHECK-MVE-NEXT: vrintp.f16 s3, s7 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fceil_float16_t: ; CHECK-MVEFP-LABEL: fceil_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintp.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrintp.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.ceil.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.ceil.v8f16(<8 x half> %src)
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entry: entry:
%0 = call fast <2 x double> @llvm.ceil.v2f64(<2 x double> %src) %0 = call fast <2 x double> @llvm.ceil.v2f64(<2 x double> %src)
ret <2 x double> %0 ret <2 x double> %0
} }
define arm_aapcs_vfpcc <4 x float> @ftrunc_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @ftrunc_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: ftrunc_float32_t: ; CHECK-MVE-LABEL: ftrunc_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vrintz.f32 s7, s3 ; CHECK-MVE-NEXT: vrintz.f32 s3, s3
; CHECK-MVE-NEXT: vrintz.f32 s6, s2 ; CHECK-MVE-NEXT: vrintz.f32 s2, s2
; CHECK-MVE-NEXT: vrintz.f32 s5, s1 ; CHECK-MVE-NEXT: vrintz.f32 s1, s1
; CHECK-MVE-NEXT: vrintz.f32 s4, s0 ; CHECK-MVE-NEXT: vrintz.f32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: ftrunc_float32_t: ; CHECK-MVEFP-LABEL: ftrunc_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintz.f32 q0, q0 ; CHECK-MVEFP-NEXT: vrintz.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <4 x float> @llvm.trunc.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.trunc.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @ftrunc_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @ftrunc_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: ftrunc_float16_t: ; CHECK-MVE-LABEL: ftrunc_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s0, s4 ; CHECK-MVE-NEXT: vrintz.f16 s0, s0
; CHECK-MVE-NEXT: vrintz.f16 s8, s0 ; CHECK-MVE-NEXT: vrintz.f16 s4, s4
; CHECK-MVE-NEXT: vrintz.f16 s0, s4 ; CHECK-MVE-NEXT: vins.f16 s0, s4
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vrintz.f16 s4, s4
; CHECK-MVE-NEXT: vrintz.f16 s8, s8 ; CHECK-MVE-NEXT: vrintz.f16 s1, s1
; CHECK-MVE-NEXT: vrintz.f16 s1, s5 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vins.f16 s1, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vrintz.f16 s4, s4
; CHECK-MVE-NEXT: vrintz.f16 s8, s8 ; CHECK-MVE-NEXT: vrintz.f16 s2, s2
; CHECK-MVE-NEXT: vrintz.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vins.f16 s2, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s8, s7 ; CHECK-MVE-NEXT: vrintz.f16 s4, s4
; CHECK-MVE-NEXT: vrintz.f16 s8, s8 ; CHECK-MVE-NEXT: vrintz.f16 s3, s3
; CHECK-MVE-NEXT: vrintz.f16 s3, s7 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: ftrunc_float16_t: ; CHECK-MVEFP-LABEL: ftrunc_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintz.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrintz.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.trunc.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.trunc.v8f16(<8 x half> %src)
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entry: entry:
%0 = call fast <2 x double> @llvm.trunc.v2f64(<2 x double> %src) %0 = call fast <2 x double> @llvm.trunc.v2f64(<2 x double> %src)
ret <2 x double> %0 ret <2 x double> %0
} }
define arm_aapcs_vfpcc <4 x float> @frint_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @frint_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: frint_float32_t: ; CHECK-MVE-LABEL: frint_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vrintx.f32 s7, s3 ; CHECK-MVE-NEXT: vrintx.f32 s3, s3
; CHECK-MVE-NEXT: vrintx.f32 s6, s2 ; CHECK-MVE-NEXT: vrintx.f32 s2, s2
; CHECK-MVE-NEXT: vrintx.f32 s5, s1 ; CHECK-MVE-NEXT: vrintx.f32 s1, s1
; CHECK-MVE-NEXT: vrintx.f32 s4, s0 ; CHECK-MVE-NEXT: vrintx.f32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: frint_float32_t: ; CHECK-MVEFP-LABEL: frint_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintx.f32 q0, q0 ; CHECK-MVEFP-NEXT: vrintx.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <4 x float> @llvm.rint.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.rint.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @frint_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @frint_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: frint_float16_t: ; CHECK-MVE-LABEL: frint_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s0, s4 ; CHECK-MVE-NEXT: vrintx.f16 s0, s0
; CHECK-MVE-NEXT: vrintx.f16 s8, s0 ; CHECK-MVE-NEXT: vrintx.f16 s4, s4
; CHECK-MVE-NEXT: vrintx.f16 s0, s4 ; CHECK-MVE-NEXT: vins.f16 s0, s4
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vrintx.f16 s4, s4
; CHECK-MVE-NEXT: vrintx.f16 s8, s8 ; CHECK-MVE-NEXT: vrintx.f16 s1, s1
; CHECK-MVE-NEXT: vrintx.f16 s1, s5 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vins.f16 s1, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vrintx.f16 s4, s4
; CHECK-MVE-NEXT: vrintx.f16 s8, s8 ; CHECK-MVE-NEXT: vrintx.f16 s2, s2
; CHECK-MVE-NEXT: vrintx.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vins.f16 s2, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s8, s7 ; CHECK-MVE-NEXT: vrintx.f16 s4, s4
; CHECK-MVE-NEXT: vrintx.f16 s8, s8 ; CHECK-MVE-NEXT: vrintx.f16 s3, s3
; CHECK-MVE-NEXT: vrintx.f16 s3, s7 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: frint_float16_t: ; CHECK-MVEFP-LABEL: frint_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintx.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrintx.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.rint.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.rint.v8f16(<8 x half> %src)
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entry: entry:
%0 = call fast <2 x double> @llvm.rint.v2f64(<2 x double> %src) %0 = call fast <2 x double> @llvm.rint.v2f64(<2 x double> %src)
ret <2 x double> %0 ret <2 x double> %0
} }
define arm_aapcs_vfpcc <4 x float> @fnearbyint_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @fnearbyint_float32_t(<4 x float> %src) {
; CHECK-LABEL: fnearbyint_float32_t: ; CHECK-LABEL: fnearbyint_float32_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vrintr.f32 s7, s3 ; CHECK-NEXT: vrintr.f32 s3, s3
; CHECK-NEXT: vrintr.f32 s6, s2 ; CHECK-NEXT: vrintr.f32 s2, s2
; CHECK-NEXT: vrintr.f32 s5, s1 ; CHECK-NEXT: vrintr.f32 s1, s1
; CHECK-NEXT: vrintr.f32 s4, s0 ; CHECK-NEXT: vrintr.f32 s0, s0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = call fast <4 x float> @llvm.nearbyint.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.nearbyint.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @fnearbyint_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fnearbyint_float16_t(<8 x half> %src) {
; CHECK-LABEL: fnearbyint_float16_t: ; CHECK-LABEL: fnearbyint_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s0, s4 ; CHECK-NEXT: vrintr.f16 s0, s0
; CHECK-NEXT: vrintr.f16 s8, s0 ; CHECK-NEXT: vrintr.f16 s4, s4
; CHECK-NEXT: vrintr.f16 s0, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vins.f16 s0, s8 ; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vmovx.f16 s8, s5 ; CHECK-NEXT: vrintr.f16 s4, s4
; CHECK-NEXT: vrintr.f16 s8, s8 ; CHECK-NEXT: vrintr.f16 s1, s1
; CHECK-NEXT: vrintr.f16 s1, s5 ; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vins.f16 s1, s8 ; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vmovx.f16 s8, s6 ; CHECK-NEXT: vrintr.f16 s4, s4
; CHECK-NEXT: vrintr.f16 s8, s8 ; CHECK-NEXT: vrintr.f16 s2, s2
; CHECK-NEXT: vrintr.f16 s2, s6 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vins.f16 s2, s8 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmovx.f16 s8, s7 ; CHECK-NEXT: vrintr.f16 s4, s4
; CHECK-NEXT: vrintr.f16 s8, s8 ; CHECK-NEXT: vrintr.f16 s3, s3
; CHECK-NEXT: vrintr.f16 s3, s7 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vins.f16 s3, s8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.nearbyint.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.nearbyint.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @fnearbyint_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @fnearbyint_float64_t(<2 x double> %src) {
; CHECK-LABEL: fnearbyint_float64_t: ; CHECK-LABEL: fnearbyint_float64_t:
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entry: entry:
%0 = call fast <2 x double> @llvm.nearbyint.v2f64(<2 x double> %src) %0 = call fast <2 x double> @llvm.nearbyint.v2f64(<2 x double> %src)
ret <2 x double> %0 ret <2 x double> %0
} }
define arm_aapcs_vfpcc <4 x float> @ffloor_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @ffloor_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: ffloor_float32_t: ; CHECK-MVE-LABEL: ffloor_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vrintm.f32 s7, s3 ; CHECK-MVE-NEXT: vrintm.f32 s3, s3
; CHECK-MVE-NEXT: vrintm.f32 s6, s2 ; CHECK-MVE-NEXT: vrintm.f32 s2, s2
; CHECK-MVE-NEXT: vrintm.f32 s5, s1 ; CHECK-MVE-NEXT: vrintm.f32 s1, s1
; CHECK-MVE-NEXT: vrintm.f32 s4, s0 ; CHECK-MVE-NEXT: vrintm.f32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: ffloor_float32_t: ; CHECK-MVEFP-LABEL: ffloor_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintm.f32 q0, q0 ; CHECK-MVEFP-NEXT: vrintm.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <4 x float> @llvm.floor.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.floor.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @ffloor_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @ffloor_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: ffloor_float16_t: ; CHECK-MVE-LABEL: ffloor_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s0, s4 ; CHECK-MVE-NEXT: vrintm.f16 s0, s0
; CHECK-MVE-NEXT: vrintm.f16 s8, s0 ; CHECK-MVE-NEXT: vrintm.f16 s4, s4
; CHECK-MVE-NEXT: vrintm.f16 s0, s4 ; CHECK-MVE-NEXT: vins.f16 s0, s4
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vrintm.f16 s4, s4
; CHECK-MVE-NEXT: vrintm.f16 s8, s8 ; CHECK-MVE-NEXT: vrintm.f16 s1, s1
; CHECK-MVE-NEXT: vrintm.f16 s1, s5 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vins.f16 s1, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vrintm.f16 s4, s4
; CHECK-MVE-NEXT: vrintm.f16 s8, s8 ; CHECK-MVE-NEXT: vrintm.f16 s2, s2
; CHECK-MVE-NEXT: vrintm.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vins.f16 s2, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s8, s7 ; CHECK-MVE-NEXT: vrintm.f16 s4, s4
; CHECK-MVE-NEXT: vrintm.f16 s8, s8 ; CHECK-MVE-NEXT: vrintm.f16 s3, s3
; CHECK-MVE-NEXT: vrintm.f16 s3, s7 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: ffloor_float16_t: ; CHECK-MVEFP-LABEL: ffloor_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintm.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrintm.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.floor.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.floor.v8f16(<8 x half> %src)
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entry: entry:
%0 = call fast <2 x double> @llvm.floor.v2f64(<2 x double> %src) %0 = call fast <2 x double> @llvm.floor.v2f64(<2 x double> %src)
ret <2 x double> %0 ret <2 x double> %0
} }
define arm_aapcs_vfpcc <4 x float> @fround_float32_t(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @fround_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: fround_float32_t: ; CHECK-MVE-LABEL: fround_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vrinta.f32 s7, s3 ; CHECK-MVE-NEXT: vrinta.f32 s3, s3
; CHECK-MVE-NEXT: vrinta.f32 s6, s2 ; CHECK-MVE-NEXT: vrinta.f32 s2, s2
; CHECK-MVE-NEXT: vrinta.f32 s5, s1 ; CHECK-MVE-NEXT: vrinta.f32 s1, s1
; CHECK-MVE-NEXT: vrinta.f32 s4, s0 ; CHECK-MVE-NEXT: vrinta.f32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fround_float32_t: ; CHECK-MVEFP-LABEL: fround_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrinta.f32 q0, q0 ; CHECK-MVEFP-NEXT: vrinta.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <4 x float> @llvm.round.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.round.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @fround_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @fround_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: fround_float16_t: ; CHECK-MVE-LABEL: fround_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s0, s4 ; CHECK-MVE-NEXT: vrinta.f16 s0, s0
; CHECK-MVE-NEXT: vrinta.f16 s8, s0 ; CHECK-MVE-NEXT: vrinta.f16 s4, s4
; CHECK-MVE-NEXT: vrinta.f16 s0, s4 ; CHECK-MVE-NEXT: vins.f16 s0, s4
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vrinta.f16 s4, s4
; CHECK-MVE-NEXT: vrinta.f16 s8, s8 ; CHECK-MVE-NEXT: vrinta.f16 s1, s1
; CHECK-MVE-NEXT: vrinta.f16 s1, s5 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vins.f16 s1, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vrinta.f16 s4, s4
; CHECK-MVE-NEXT: vrinta.f16 s8, s8 ; CHECK-MVE-NEXT: vrinta.f16 s2, s2
; CHECK-MVE-NEXT: vrinta.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vins.f16 s2, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s8, s7 ; CHECK-MVE-NEXT: vrinta.f16 s4, s4
; CHECK-MVE-NEXT: vrinta.f16 s8, s8 ; CHECK-MVE-NEXT: vrinta.f16 s3, s3
; CHECK-MVE-NEXT: vrinta.f16 s3, s7 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: fround_float16_t: ; CHECK-MVEFP-LABEL: fround_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrinta.f16 q0, q0 ; CHECK-MVEFP-NEXT: vrinta.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = call fast <8 x half> @llvm.round.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.round.v8f16(<8 x half> %src)
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llvm/test/CodeGen/Thumb2/mve-gather-ind16-scaled.ll

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Linesentry:
ret <8 x i16> %gather ret <8 x i16> %gather
} }
define arm_aapcs_vfpcc <8 x half> @scaled_v8f16_sext(i16* %base, <8 x i16>* %offptr) { define arm_aapcs_vfpcc <8 x half> @scaled_v8f16_sext(i16* %base, <8 x i16>* %offptr) {
; CHECK-LABEL: scaled_v8f16_sext: ; CHECK-LABEL: scaled_v8f16_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r1] ; CHECK-NEXT: vldrh.s32 q0, [r1]
; CHECK-NEXT: vshl.i32 q0, q0, #1 ; CHECK-NEXT: vshl.i32 q0, q0, #1
; CHECK-NEXT: vadd.i32 q1, q0, r0 ; CHECK-NEXT: vadd.i32 q0, q0, r0
; CHECK-NEXT: vmov r2, r3, d2 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: vldr.16 s8, [r3]
; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vmov r2, r3, d3
; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vldr.16 s4, [r3] ; CHECK-NEXT: vldr.16 s4, [r3]
; CHECK-NEXT: vldr.16 s1, [r2] ; CHECK-NEXT: vldr.16 s0, [r2]
; CHECK-NEXT: vins.f16 s1, s4 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vldrh.s32 q1, [r1, #8] ; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
; CHECK-NEXT: vldr.16 s2, [r3]
; CHECK-NEXT: vldr.16 s1, [r2]
; CHECK-NEXT: vshl.i32 q1, q1, #1 ; CHECK-NEXT: vshl.i32 q1, q1, #1
; CHECK-NEXT: vadd.i32 q1, q1, r0 ; CHECK-NEXT: vadd.i32 q1, q1, r0
; CHECK-NEXT: vins.f16 s1, s2
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: vldr.16 s8, [r1] ; CHECK-NEXT: vldr.16 s4, [r1]
; CHECK-NEXT: vldr.16 s2, [r0] ; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vins.f16 s2, s8 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vldr.16 s4, [r1] ; CHECK-NEXT: vldr.16 s4, [r1]
; CHECK-NEXT: vldr.16 s3, [r0] ; CHECK-NEXT: vldr.16 s3, [r0]
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <8 x i16>, <8 x i16>* %offptr, align 2 %offs = load <8 x i16>, <8 x i16>* %offptr, align 2
%offs.sext = sext <8 x i16> %offs to <8 x i32> %offs.sext = sext <8 x i16> %offs to <8 x i32>
%i16_ptrs = getelementptr inbounds i16, i16* %base, <8 x i32> %offs.sext %i16_ptrs = getelementptr inbounds i16, i16* %base, <8 x i32> %offs.sext
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llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov r12, r2, d1 ; CHECK-NEXT: vmov r12, r2, d1
; CHECK-NEXT: vmov lr, r1, d0 ; CHECK-NEXT: vmov lr, r1, d0
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov r0, r3, d1 ; CHECK-NEXT: vmov r0, r3, d1
; CHECK-NEXT: vmov r4, r5, d0 ; CHECK-NEXT: vmov r4, r5, d0
; CHECK-NEXT: vldr s3, [r2] ; CHECK-NEXT: vldr s3, [r2]
; CHECK-NEXT: vldr s2, [r12] ; CHECK-NEXT: vldr s2, [r12]
; CHECK-NEXT: vldr s1, [r1] ; CHECK-NEXT: vldr s1, [r1]
; CHECK-NEXT: vldr s0, [lr]
; CHECK-NEXT: vldr s7, [r3] ; CHECK-NEXT: vldr s7, [r3]
; CHECK-NEXT: vldr s6, [r0] ; CHECK-NEXT: vldr s6, [r0]
; CHECK-NEXT: vldr s5, [r5] ; CHECK-NEXT: vldr s5, [r5]
; CHECK-NEXT: vldr s0, [lr]
; CHECK-NEXT: vldr s4, [r4] ; CHECK-NEXT: vldr s4, [r4]
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%offs = load <8 x float*>, <8 x float*>* %offptr, align 4 %offs = load <8 x float*>, <8 x float*>* %offptr, align 4
%gather = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %offs, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef) %gather = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %offs, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef)
ret <8 x float> %gather ret <8 x float> %gather
} }
▲ Show 20 Lines • Show All 221 Lines • ▼ Show 20 Linesentry:
ret <8 x i32> %ext ret <8 x i32> %ext
} }
; f16 ; f16
define arm_aapcs_vfpcc <8 x half> @ptr_f16(<8 x half*>* %offptr) { define arm_aapcs_vfpcc <8 x half> @ptr_f16(<8 x half*>* %offptr) {
; CHECK-LABEL: ptr_f16: ; CHECK-LABEL: ptr_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmov r1, r2, d2 ; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: vldr.16 s8, [r2]
; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vmov r1, r2, d3
; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vldr.16 s4, [r2] ; CHECK-NEXT: vldr.16 s4, [r2]
; CHECK-NEXT: vldr.16 s1, [r1] ; CHECK-NEXT: vldr.16 s0, [r1]
; CHECK-NEXT: vins.f16 s1, s4 ; CHECK-NEXT: vmov r1, r2, d1
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldr.16 s1, [r1]
; CHECK-NEXT: vldr.16 s2, [r2]
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: vldr.16 s8, [r1] ; CHECK-NEXT: vins.f16 s1, s2
; CHECK-NEXT: vldr.16 s4, [r1]
; CHECK-NEXT: vldr.16 s2, [r0] ; CHECK-NEXT: vldr.16 s2, [r0]
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vldr.16 s4, [r1]
; CHECK-NEXT: vldr.16 s3, [r0] ; CHECK-NEXT: vldr.16 s3, [r0]
; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vldr.16 s4, [r1]
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <8 x half*>, <8 x half*>* %offptr, align 4 %offs = load <8 x half*>, <8 x half*>* %offptr, align 4
%gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef) %gather = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x half> undef)
ret <8 x half> %gather ret <8 x half> %gather
} }
define arm_aapcs_vfpcc <4 x half> @ptr_v4f16(<4 x half*>* %offptr) { define arm_aapcs_vfpcc <4 x half> @ptr_v4f16(<4 x half*>* %offptr) {
; CHECK-LABEL: ptr_v4f16: ; CHECK-LABEL: ptr_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vldr.16 s8, [r1]
; CHECK-NEXT: vldr.16 s0, [r0]
; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vldr.16 s4, [r1] ; CHECK-NEXT: vldr.16 s4, [r1]
; CHECK-NEXT: vldr.16 s0, [r0]
; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vldr.16 s2, [r1]
; CHECK-NEXT: vldr.16 s1, [r0] ; CHECK-NEXT: vldr.16 s1, [r0]
; CHECK-NEXT: vins.f16 s1, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vins.f16 s1, s2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <4 x half*>, <4 x half*>* %offptr, align 4 %offs = load <4 x half*>, <4 x half*>* %offptr, align 4
%gather = call <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x half> undef) %gather = call <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x half> undef)
ret <4 x half> %gather ret <4 x half> %gather
} }
; i8 ; i8
▲ Show 20 Lines • Show All 479 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-intrinsics/vld24.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesentry:
ret i8* %2 ret i8* %2
} }
declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0i8(i8*) declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.mve.vld4q.v16i8.p0i8(i8*)
define arm_aapcs_vfpcc void @test_vst2q_u32(i32* %addr, %struct.uint32x4x2_t %value.coerce) { define arm_aapcs_vfpcc void @test_vst2q_u32(i32* %addr, %struct.uint32x4x2_t %value.coerce) {
; CHECK-LABEL: test_vst2q_u32: ; CHECK-LABEL: test_vst2q_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT: vst20.32 {q0, q1}, [r0] ; CHECK-NEXT: vst20.32 {q0, q1}, [r0]
; CHECK-NEXT: vst21.32 {q0, q1}, [r0] ; CHECK-NEXT: vst21.32 {q0, q1}, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%value.coerce.fca.0.0.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 0 %value.coerce.fca.0.0.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 0
%value.coerce.fca.0.1.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 1 %value.coerce.fca.0.1.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 1
tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 0) tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 0)
tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 1) tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 1)
ret void ret void
} }
define arm_aapcs_vfpcc i32* @test_vst2q_u32_post(i32* %addr, %struct.uint32x4x2_t %value.coerce) { define arm_aapcs_vfpcc i32* @test_vst2q_u32_post(i32* %addr, %struct.uint32x4x2_t %value.coerce) {
; CHECK-LABEL: test_vst2q_u32_post: ; CHECK-LABEL: test_vst2q_u32_post:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT: vst20.32 {q0, q1}, [r0] ; CHECK-NEXT: vst20.32 {q0, q1}, [r0]
; CHECK-NEXT: vst21.32 {q0, q1}, [r0]! ; CHECK-NEXT: vst21.32 {q0, q1}, [r0]!
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%value.coerce.fca.0.0.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 0 %value.coerce.fca.0.0.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 0
%value.coerce.fca.0.1.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 1 %value.coerce.fca.0.1.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 1
tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 0) tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 0)
tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 1) tail call void @llvm.arm.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coerce.fca.0.1.extract, i32 1)
%g = getelementptr i32, i32 *%addr, i32 8 %g = getelementptr i32, i32 *%addr, i32 8
ret i32* %g ret i32* %g
} }
declare void @llvm.arm.mve.vst2q.p0i32.v4i32(i32*, <4 x i32>, <4 x i32>, i32) declare void @llvm.arm.mve.vst2q.p0i32.v4i32(i32*, <4 x i32>, <4 x i32>, i32)
define arm_aapcs_vfpcc void @test_vst2q_f16(half* %addr, %struct.float16x8x2_t %value.coerce) { define arm_aapcs_vfpcc void @test_vst2q_f16(half* %addr, %struct.float16x8x2_t %value.coerce) {
; CHECK-LABEL: test_vst2q_f16: ; CHECK-LABEL: test_vst2q_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT: vst20.16 {q0, q1}, [r0] ; CHECK-NEXT: vst20.16 {q0, q1}, [r0]
; CHECK-NEXT: vst21.16 {q0, q1}, [r0] ; CHECK-NEXT: vst21.16 {q0, q1}, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%value.coerce.fca.0.0.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 0 %value.coerce.fca.0.0.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 0
%value.coerce.fca.0.1.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 1 %value.coerce.fca.0.1.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 1
call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 0) call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 0)
call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 1) call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 1)
ret void ret void
} }
define arm_aapcs_vfpcc half* @test_vst2q_f16_post(half* %addr, %struct.float16x8x2_t %value.coerce) { define arm_aapcs_vfpcc half* @test_vst2q_f16_post(half* %addr, %struct.float16x8x2_t %value.coerce) {
; CHECK-LABEL: test_vst2q_f16_post: ; CHECK-LABEL: test_vst2q_f16_post:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT: vst20.16 {q0, q1}, [r0] ; CHECK-NEXT: vst20.16 {q0, q1}, [r0]
; CHECK-NEXT: vst21.16 {q0, q1}, [r0]! ; CHECK-NEXT: vst21.16 {q0, q1}, [r0]!
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%value.coerce.fca.0.0.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 0 %value.coerce.fca.0.0.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 0
%value.coerce.fca.0.1.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 1 %value.coerce.fca.0.1.extract = extractvalue %struct.float16x8x2_t %value.coerce, 0, 1
call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 0) call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 0)
call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 1) call void @llvm.arm.mve.vst2q.p0f16.v8f16(half* %addr, <8 x half> %value.coerce.fca.0.0.extract, <8 x half> %value.coerce.fca.0.1.extract, i32 1)
%g = getelementptr half, half *%addr, i32 16 %g = getelementptr half, half *%addr, i32 16
ret half* %g ret half* %g
} }
declare void @llvm.arm.mve.vst2q.p0f16.v8f16(half*, <8 x half>, <8 x half>, i32) declare void @llvm.arm.mve.vst2q.p0f16.v8f16(half*, <8 x half>, <8 x half>, i32)
define arm_aapcs_vfpcc void @test_vst4q_s8(i8* %addr, %struct.int8x16x4_t %value.coerce) { define arm_aapcs_vfpcc void @test_vst4q_s8(i8* %addr, %struct.int8x16x4_t %value.coerce) {
; CHECK-LABEL: test_vst4q_s8: ; CHECK-LABEL: test_vst4q_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: vst40.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst40.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst41.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst41.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst42.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst42.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst43.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst43.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%value.coerce.fca.0.0.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 0 %value.coerce.fca.0.0.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 0
%value.coerce.fca.0.1.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 1 %value.coerce.fca.0.1.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 1
%value.coerce.fca.0.2.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 2 %value.coerce.fca.0.2.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 2
%value.coerce.fca.0.3.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 3 %value.coerce.fca.0.3.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 3
tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 0) tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 0)
tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 1) tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 1)
tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 2) tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 2)
tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 3) tail call void @llvm.arm.mve.vst4q.p0i8.v16i8(i8* %addr, <16 x i8> %value.coerce.fca.0.0.extract, <16 x i8> %value.coerce.fca.0.1.extract, <16 x i8> %value.coerce.fca.0.2.extract, <16 x i8> %value.coerce.fca.0.3.extract, i32 3)
ret void ret void
} }
define arm_aapcs_vfpcc i8* @test_vst4q_s8_post(i8* %addr, %struct.int8x16x4_t %value.coerce) { define arm_aapcs_vfpcc i8* @test_vst4q_s8_post(i8* %addr, %struct.int8x16x4_t %value.coerce) {
; CHECK-LABEL: test_vst4q_s8_post: ; CHECK-LABEL: test_vst4q_s8_post:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3
; CHECK-NEXT: vst40.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst40.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst41.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst41.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst42.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst42.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst43.8 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vst43.8 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%value.coerce.fca.0.0.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 0 %value.coerce.fca.0.0.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 0
%value.coerce.fca.0.1.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 1 %value.coerce.fca.0.1.extract = extractvalue %struct.int8x16x4_t %value.coerce, 0, 1
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llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
define arm_aapcs_vfpcc <4 x i32> @loads_i32(<4 x i32> *%A, <4 x i32> *%B, <4 x i32> *%C) { define arm_aapcs_vfpcc <4 x i32> @loads_i32(<4 x i32> *%A, <4 x i32> *%B, <4 x i32> *%C) {
; CHECK-LABEL: loads_i32: ; CHECK-LABEL: loads_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d9}
; CHECK-NEXT: vldrw.u32 q1, [r1] ; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: vldrw.u32 q5, [r2]
; CHECK-NEXT: vmov.f32 s8, s6 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s6, s5 ; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vand q2, q2, q0 ; CHECK-NEXT: vand q3, q2, q0
; CHECK-NEXT: vand q0, q1, q0 ; CHECK-NEXT: vand q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov r4, r1, d4
; CHECK-NEXT: vmov.f32 s12, s6
; CHECK-NEXT: vmov.f32 s14, s7
; CHECK-NEXT: vmov r5, s12
; CHECK-NEXT: vmov.f32 s16, s22
; CHECK-NEXT: vmov.f32 s18, s23
; CHECK-NEXT: vmov r3, lr, d0 ; CHECK-NEXT: vmov r3, lr, d0
; CHECK-NEXT: vmov.f32 s6, s5 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov r0, r12, d5 ; CHECK-NEXT: vmov r4, r1, d6
; CHECK-NEXT: vmov.f32 s8, s20 ; CHECK-NEXT: vmov r0, r12, d7
; CHECK-NEXT: vmov.f32 s10, s21 ; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov r5, s0
; CHECK-NEXT: vmov.f32 s0, s12
; CHECK-NEXT: vmov.f32 s6, s13
; CHECK-NEXT: adds r2, r5, r4 ; CHECK-NEXT: adds r2, r5, r4
; CHECK-NEXT: vmov r4, s16 ; CHECK-NEXT: vmov r4, s8
; CHECK-NEXT: asr.w r6, r5, #31 ; CHECK-NEXT: asr.w r6, r5, #31
; CHECK-NEXT: adcs r1, r6 ; CHECK-NEXT: adcs r1, r6
; CHECK-NEXT: asrl r2, r1, r4 ; CHECK-NEXT: asrl r2, r1, r4
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: adds r6, r1, r3 ; CHECK-NEXT: adds r6, r1, r3
; CHECK-NEXT: vmov r3, s8 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: asr.w r4, r1, #31 ; CHECK-NEXT: asr.w r4, r1, #31
; CHECK-NEXT: adc.w r1, r4, lr ; CHECK-NEXT: adc.w r1, r4, lr
; CHECK-NEXT: asrl r6, r1, r3 ; CHECK-NEXT: asrl r6, r1, r3
; CHECK-NEXT: vmov r5, r4, d1 ; CHECK-NEXT: vmov r5, r4, d1
; CHECK-NEXT: vmov r1, s14 ; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: vmov q0[2], q0[0], r6, r2 ; CHECK-NEXT: vmov q0[2], q0[0], r6, r2
; CHECK-NEXT: adds r0, r0, r1 ; CHECK-NEXT: adds r0, r0, r1
; CHECK-NEXT: asr.w r3, r1, #31 ; CHECK-NEXT: asr.w r3, r1, #31
; CHECK-NEXT: adc.w r1, r3, r12 ; CHECK-NEXT: adc.w r1, r3, r12
; CHECK-NEXT: vmov r3, s18 ; CHECK-NEXT: vmov r3, s18
; CHECK-NEXT: asrl r0, r1, r3 ; CHECK-NEXT: asrl r0, r1, r3
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s14
; CHECK-NEXT: adds r6, r1, r5 ; CHECK-NEXT: adds r6, r1, r5
; CHECK-NEXT: asr.w r2, r1, #31 ; CHECK-NEXT: asr.w r2, r1, #31
; CHECK-NEXT: adc.w r1, r2, r4 ; CHECK-NEXT: adc.w r1, r2, r4
; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: asrl r6, r1, r2 ; CHECK-NEXT: asrl r6, r1, r2
; CHECK-NEXT: vmov q0[3], q0[1], r6, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r0
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d9}
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%a = load <4 x i32>, <4 x i32> *%A, align 4 %a = load <4 x i32>, <4 x i32> *%A, align 4
%b = load <4 x i32>, <4 x i32> *%B, align 4 %b = load <4 x i32>, <4 x i32> *%B, align 4
%c = load <4 x i32>, <4 x i32> *%C, align 4 %c = load <4 x i32>, <4 x i32> *%C, align 4
%sa = sext <4 x i32> %a to <4 x i64> %sa = sext <4 x i32> %a to <4 x i64>
%sb = zext <4 x i32> %b to <4 x i64> %sb = zext <4 x i32> %b to <4 x i64>
%sc = zext <4 x i32> %c to <4 x i64> %sc = zext <4 x i32> %c to <4 x i64>
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define arm_aapcs_vfpcc void @load_store_i32(<4 x i32> *%A, <4 x i32> *%B, <4 x i32> *%C, <4 x i32> *%D) { define arm_aapcs_vfpcc void @load_store_i32(<4 x i32> *%A, <4 x i32> *%B, <4 x i32> *%C, <4 x i32> *%D) {
; CHECK-LABEL: load_store_i32: ; CHECK-LABEL: load_store_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d9}
; CHECK-NEXT: vldrw.u32 q2, [r1] ; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: vldrw.u32 q5, [r2] ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s6, s11 ; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov.f32 s10, s9 ; CHECK-NEXT: vand q3, q2, q0
; CHECK-NEXT: vand q1, q1, q0 ; CHECK-NEXT: vand q1, q1, q0
; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmov r5, r1, d2 ; CHECK-NEXT: vmov r4, lr, d2
; CHECK-NEXT: vmov.f32 s12, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov r5, r1, d6
; CHECK-NEXT: vmov r6, s12 ; CHECK-NEXT: vmov r0, r12, d7
; CHECK-NEXT: vmov.f32 s16, s22 ; CHECK-NEXT: vldrw.u32 q3, [r2]
; CHECK-NEXT: vmov.f32 s18, s23 ; CHECK-NEXT: vmov.f32 s10, s3
; CHECK-NEXT: vmov r4, lr, d4 ; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s2, s1 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmov r0, r12, d3 ; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov.f32 s4, s20 ; CHECK-NEXT: vmov r6, s4
; CHECK-NEXT: vmov.f32 s6, s21 ; CHECK-NEXT: vmov.f32 s4, s12
; CHECK-NEXT: vmov.f32 s2, s13
; CHECK-NEXT: adds r2, r6, r5 ; CHECK-NEXT: adds r2, r6, r5
; CHECK-NEXT: vmov r5, s16 ; CHECK-NEXT: vmov r5, s8
; CHECK-NEXT: asr.w r7, r6, #31 ; CHECK-NEXT: asr.w r7, r6, #31
; CHECK-NEXT: adcs r1, r7 ; CHECK-NEXT: adcs r1, r7
; CHECK-NEXT: asrl r2, r1, r5 ; CHECK-NEXT: asrl r2, r1, r5
; CHECK-NEXT: vmov r7, s4 ; CHECK-NEXT: vmov r7, s4
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: adds r4, r4, r1 ; CHECK-NEXT: adds r4, r4, r1
; CHECK-NEXT: asr.w r5, r1, #31 ; CHECK-NEXT: asr.w r5, r1, #31
; CHECK-NEXT: adc.w r1, r5, lr ; CHECK-NEXT: adc.w r1, r5, lr
; CHECK-NEXT: asrl r4, r1, r7 ; CHECK-NEXT: asrl r4, r1, r7
; CHECK-NEXT: vmov r6, r5, d5 ; CHECK-NEXT: vmov r6, r5, d3
; CHECK-NEXT: vmov r1, s14 ; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: vmov q2[2], q2[0], r4, r2 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r2
; CHECK-NEXT: adds r0, r0, r1 ; CHECK-NEXT: adds r0, r0, r1
; CHECK-NEXT: asr.w r7, r1, #31 ; CHECK-NEXT: asr.w r7, r1, #31
; CHECK-NEXT: adc.w r1, r7, r12 ; CHECK-NEXT: adc.w r1, r7, r12
; CHECK-NEXT: vmov r7, s18 ; CHECK-NEXT: vmov r7, s18
; CHECK-NEXT: asrl r0, r1, r7 ; CHECK-NEXT: asrl r0, r1, r7
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s14
; CHECK-NEXT: adds r6, r6, r1 ; CHECK-NEXT: adds r6, r6, r1
; CHECK-NEXT: asr.w r2, r1, #31 ; CHECK-NEXT: asr.w r2, r1, #31
; CHECK-NEXT: adc.w r1, r2, r5 ; CHECK-NEXT: adc.w r1, r2, r5
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: asrl r6, r1, r2 ; CHECK-NEXT: asrl r6, r1, r2
; CHECK-NEXT: vmov q2[3], q2[1], r6, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r6, r0
; CHECK-NEXT: vstrw.32 q2, [r3] ; CHECK-NEXT: vstrw.32 q1, [r3]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop {r4, r5, r6, r7, pc} ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
entry: entry:
%a = load <4 x i32>, <4 x i32> *%A, align 4 %a = load <4 x i32>, <4 x i32> *%A, align 4
%b = load <4 x i32>, <4 x i32> *%B, align 4 %b = load <4 x i32>, <4 x i32> *%B, align 4
%c = load <4 x i32>, <4 x i32> *%C, align 4 %c = load <4 x i32>, <4 x i32> *%C, align 4
%sa = sext <4 x i32> %a to <4 x i64> %sa = sext <4 x i32> %a to <4 x i64>
%sb = zext <4 x i32> %b to <4 x i64> %sb = zext <4 x i32> %b to <4 x i64>
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define arm_aapcs_vfpcc void @load_one_store_i32(<4 x i32> *%A, <4 x i32> *%D) { define arm_aapcs_vfpcc void @load_one_store_i32(<4 x i32> *%A, <4 x i32> *%D) {
; CHECK-LABEL: load_one_store_i32: ; CHECK-LABEL: load_one_store_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s6, s3 ; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov.f32 s2, s1 ; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: adds.w r12, r2, r2 ; CHECK-NEXT: adds.w r12, r2, r2
; CHECK-NEXT: asr.w r3, r2, #31 ; CHECK-NEXT: asr.w r3, r2, #31
; CHECK-NEXT: adc.w r7, r3, r2, asr #31 ; CHECK-NEXT: adc.w r7, r3, r2, asr #31
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: asrl r12, r7, r2 ; CHECK-NEXT: asrl r12, r7, r2
; CHECK-NEXT: adds r0, r3, r3 ; CHECK-NEXT: adds r0, r3, r3
; CHECK-NEXT: asr.w r5, r3, #31 ; CHECK-NEXT: asr.w r5, r3, #31
; CHECK-NEXT: adc.w r5, r5, r3, asr #31 ; CHECK-NEXT: adc.w r5, r5, r3, asr #31
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} }
define arm_aapcs_vfpcc void @mul_i32(<4 x i32> *%A, <4 x i32> *%B, i64 %C, <4 x i32> *%D) { define arm_aapcs_vfpcc void @mul_i32(<4 x i32> *%A, <4 x i32> *%B, i64 %C, <4 x i32> *%D) {
; CHECK-LABEL: mul_i32: ; CHECK-LABEL: mul_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: ldr.w lr, [sp, #20] ; CHECK-NEXT: ldr.w lr, [sp, #20]
; CHECK-NEXT: vmov.f32 s8, s0
; CHECK-NEXT: vmov.f32 s12, s4
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov.f32 s10, s1 ; CHECK-NEXT: vmov.f32 s10, s1
; CHECK-NEXT: vmov r5, s12 ; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov r1, s14 ; CHECK-NEXT: vmov r5, s4
; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov r0, s10 ; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: vmov r1, s14
; CHECK-NEXT: smull r12, r3, r1, r0 ; CHECK-NEXT: smull r12, r3, r1, r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.f32 s8, s2 ; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vmov.f32 s10, s3 ; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmullb.s32 q2, q1, q0
; CHECK-NEXT: asrl r12, r3, r2 ; CHECK-NEXT: asrl r12, r3, r2
; CHECK-NEXT: vmov.f32 s2, s7 ; CHECK-NEXT: vmov r6, r1, d4
; CHECK-NEXT: vmullb.s32 q1, q0, q2 ; CHECK-NEXT: vmov r4, r7, d5
; CHECK-NEXT: vmov r6, r1, d2
; CHECK-NEXT: vmov r4, r7, d3
; CHECK-NEXT: asrl r6, r1, r2 ; CHECK-NEXT: asrl r6, r1, r2
; CHECK-NEXT: asrl r4, r7, r2 ; CHECK-NEXT: asrl r4, r7, r2
; CHECK-NEXT: smull r0, r5, r5, r0 ; CHECK-NEXT: smull r0, r5, r5, r0
; CHECK-NEXT: asrl r0, r5, r2 ; CHECK-NEXT: asrl r0, r5, r2
; CHECK-NEXT: vmov q0[2], q0[0], r0, r6 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r6
; CHECK-NEXT: vmov q0[3], q0[1], r12, r4 ; CHECK-NEXT: vmov q0[3], q0[1], r12, r4
; CHECK-NEXT: vstrw.32 q0, [lr] ; CHECK-NEXT: vstrw.32 q0, [lr]
; CHECK-NEXT: pop {r4, r5, r6, r7, pc} ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Linesentry:
%t = trunc <16 x i16> %sa to <16 x i8> %t = trunc <16 x i16> %sa to <16 x i8>
ret <16 x i8> %t ret <16 x i8> %t
} }
define arm_aapcs_vfpcc <4 x i32> @ext_add_trunc_i32(<4 x i32> %a, <4 x i32> %b) { define arm_aapcs_vfpcc <4 x i32> @ext_add_trunc_i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: ext_add_trunc_i32: ; CHECK-LABEL: ext_add_trunc_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s6 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s12, s2 ; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r1, s12 ; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s2, s1 ; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov.f32 s6, s5 ; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vmov r2, s14 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r3, s2 ; CHECK-NEXT: vmov.f32 s2, s5
; CHECK-NEXT: add.w r12, r1, r0 ; CHECK-NEXT: add.w r12, r1, r0
; CHECK-NEXT: vmov r1, s10 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: add r1, r2 ; CHECK-NEXT: add r1, r2
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: add r0, r3 ; CHECK-NEXT: add r0, r3
; CHECK-NEXT: vmov q0[2], q0[0], r0, r12 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r12
; CHECK-NEXT: vmov q0[3], q0[1], r2, r1 ; CHECK-NEXT: vmov q0[3], q0[1], r2, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%sa = sext <4 x i32> %a to <4 x i64> %sa = sext <4 x i32> %a to <4 x i64>
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <4 x i32> @ext_add_ashr_trunc_i32(<4 x i32> %a, <4 x i32> %b) { define arm_aapcs_vfpcc <4 x i32> @ext_add_ashr_trunc_i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: ext_add_ashr_trunc_i32: ; CHECK-LABEL: ext_add_ashr_trunc_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: vmov.f32 s12, s6 ; CHECK-NEXT: vmov.f32 s12, s6
; CHECK-NEXT: vmov.i64 q2, #0xffffffff ; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vmov.f32 s14, s7
; CHECK-NEXT: vmov.f32 s6, s5 ; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vand q3, q3, q2 ; CHECK-NEXT: vmov.f32 s14, s7
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s10, s3
; CHECK-NEXT: vmov r4, s8
; CHECK-NEXT: vmov r0, r1, d6
; CHECK-NEXT: vmov r2, r3, d2 ; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: vmov.f32 s2, s1 ; CHECK-NEXT: vand q3, q3, q2
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov r0, r1, d6
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov.f32 s10, s1
; CHECK-NEXT: vmov r12, lr, d7 ; CHECK-NEXT: vmov r12, lr, d7
; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: adds r0, r0, r4 ; CHECK-NEXT: adds r0, r0, r4
; CHECK-NEXT: asr.w r5, r4, #31 ; CHECK-NEXT: asr.w r5, r4, #31
; CHECK-NEXT: adcs r1, r5 ; CHECK-NEXT: adcs r1, r5
; CHECK-NEXT: lsrl r0, r1, #1 ; CHECK-NEXT: lsrl r0, r1, #1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: adds r2, r2, r1 ; CHECK-NEXT: adds r2, r2, r1
; CHECK-NEXT: asr.w r4, r1, #31 ; CHECK-NEXT: asr.w r4, r1, #31
; CHECK-NEXT: adcs r3, r4 ; CHECK-NEXT: adcs r3, r4
; CHECK-NEXT: lsrl r2, r3, #1 ; CHECK-NEXT: lsrl r2, r3, #1
; CHECK-NEXT: vmov r1, r5, d3 ; CHECK-NEXT: vmov r1, r5, d3
; CHECK-NEXT: vmov r3, s10 ; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: adds.w r4, r3, r12 ; CHECK-NEXT: adds.w r4, r3, r12
; CHECK-NEXT: asr.w r6, r3, #31 ; CHECK-NEXT: asr.w r6, r3, #31
; CHECK-NEXT: adc.w r3, r6, lr ; CHECK-NEXT: adc.w r3, r6, lr
; CHECK-NEXT: asrs r2, r0, #31 ; CHECK-NEXT: asrs r2, r0, #31
; CHECK-NEXT: adds r0, r0, r1 ; CHECK-NEXT: adds r0, r0, r1
; CHECK-NEXT: adc.w r1, r2, r5 ; CHECK-NEXT: adc.w r1, r2, r5
; CHECK-NEXT: lsrl r4, r3, #1 ; CHECK-NEXT: lsrl r4, r3, #1
; CHECK-NEXT: lsrl r0, r1, #1 ; CHECK-NEXT: lsrl r0, r1, #1
; CHECK-NEXT: vmov q1[3], q1[1], r0, r4 ; CHECK-NEXT: vmov q0[3], q0[1], r0, r4
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%sa = sext <4 x i32> %a to <4 x i64> %sa = sext <4 x i32> %a to <4 x i64>
%sb = zext <4 x i32> %b to <4 x i64> %sb = zext <4 x i32> %b to <4 x i64>
%add = add <4 x i64> %sa, %sb %add = add <4 x i64> %sa, %sb
%sh = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1> %sh = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
%t = trunc <4 x i64> %sh to <4 x i32> %t = trunc <4 x i64> %sh to <4 x i32>
ret <4 x i32> %t ret <4 x i32> %t
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: vmov.f32 s8, s6 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.i64 q3, #0xffffffff ; CHECK-NEXT: vmov.i64 q3, #0xffffffff
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s6, s5 ; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: vmov.f32 s12, s2 ; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov r12, r2, d5 ; CHECK-NEXT: vmov r12, r2, d5
; CHECK-NEXT: vmov r8, r9, d3 ; CHECK-NEXT: vmov r8, r9, d3
; CHECK-NEXT: vmov r1, s14 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov lr, s2 ; CHECK-NEXT: vmov lr, s2
; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill ; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: adds.w r4, r1, r12 ; CHECK-NEXT: adds.w r4, r1, r12
; CHECK-NEXT: asr.w r0, r1, #31 ; CHECK-NEXT: asr.w r0, r1, #31
; CHECK-NEXT: adc.w r5, r0, r2 ; CHECK-NEXT: adc.w r5, r0, r2
; CHECK-NEXT: asrl r4, r5, r12 ; CHECK-NEXT: asrl r4, r5, r12
; CHECK-NEXT: subs.w r0, r4, r12 ; CHECK-NEXT: subs.w r0, r4, r12
; CHECK-NEXT: sbc.w r2, r5, r2 ; CHECK-NEXT: sbc.w r2, r5, r2
; CHECK-NEXT: asr.w r5, lr, #31
; CHECK-NEXT: umull r0, r4, r0, r12 ; CHECK-NEXT: umull r0, r4, r0, r12
; CHECK-NEXT: adds.w r6, lr, r8 ; CHECK-NEXT: adds.w r6, lr, r8
; CHECK-NEXT: mla r3, r2, r12, r4
; CHECK-NEXT: asr.w r5, lr, #31
; CHECK-NEXT: adc.w r5, r5, r9 ; CHECK-NEXT: adc.w r5, r5, r9
; CHECK-NEXT: rsbs r2, r1, #0
; CHECK-NEXT: asrl r6, r5, r8 ; CHECK-NEXT: asrl r6, r5, r8
; CHECK-NEXT: mla r3, r2, r12, r4 ; CHECK-NEXT: lsll r0, r3, r2
; CHECK-NEXT: subs.w r7, r6, r8 ; CHECK-NEXT: subs.w r7, r6, r8
; CHECK-NEXT: vmov r6, r2, d4
; CHECK-NEXT: sbc.w r10, r5, r9 ; CHECK-NEXT: sbc.w r10, r5, r9
; CHECK-NEXT: rsbs r2, r1, #0
; CHECK-NEXT: vmov r5, s12 ; CHECK-NEXT: vmov r5, s12
; CHECK-NEXT: lsll r0, r3, r2
; CHECK-NEXT: vmov r6, r2, d4
; CHECK-NEXT: lsll r0, r3, r12 ; CHECK-NEXT: lsll r0, r3, r12
; CHECK-NEXT: asrs r3, r5, #31
; CHECK-NEXT: adds r4, r5, r6 ; CHECK-NEXT: adds r4, r5, r6
; CHECK-NEXT: asr.w r3, r5, #31
; CHECK-NEXT: adcs r3, r2 ; CHECK-NEXT: adcs r3, r2
; CHECK-NEXT: asrl r4, r3, r6 ; CHECK-NEXT: asrl r4, r3, r6
; CHECK-NEXT: subs r4, r4, r6 ; CHECK-NEXT: subs r4, r4, r6
; CHECK-NEXT: sbc.w r2, r3, r2 ; CHECK-NEXT: sbc.w r2, r3, r2
; CHECK-NEXT: umull r4, r3, r4, r6 ; CHECK-NEXT: umull r4, r3, r4, r6
; CHECK-NEXT: mla r3, r2, r6, r3 ; CHECK-NEXT: mla r3, r2, r6, r3
; CHECK-NEXT: rsbs r2, r5, #0 ; CHECK-NEXT: rsbs r2, r5, #0
; CHECK-NEXT: lsll r4, r3, r2 ; CHECK-NEXT: lsll r4, r3, r2
▲ Show 20 Lines • Show All 287 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll

Show First 20 Lines • Show All 845 Lines • ▼ Show 20 Lines
; CHECK-LE-NEXT: bmi .LBB18_7 ; CHECK-LE-NEXT: bmi .LBB18_7
; CHECK-LE-NEXT: .LBB18_2: @ %else2 ; CHECK-LE-NEXT: .LBB18_2: @ %else2
; CHECK-LE-NEXT: lsls r3, r1, #29 ; CHECK-LE-NEXT: lsls r3, r1, #29
; CHECK-LE-NEXT: bmi .LBB18_8 ; CHECK-LE-NEXT: bmi .LBB18_8
; CHECK-LE-NEXT: .LBB18_3: @ %else5 ; CHECK-LE-NEXT: .LBB18_3: @ %else5
; CHECK-LE-NEXT: lsls r1, r1, #28 ; CHECK-LE-NEXT: lsls r1, r1, #28
; CHECK-LE-NEXT: bpl .LBB18_5 ; CHECK-LE-NEXT: bpl .LBB18_5
; CHECK-LE-NEXT: .LBB18_4: @ %cond.load7 ; CHECK-LE-NEXT: .LBB18_4: @ %cond.load7
; CHECK-LE-NEXT: vldr.16 s4, [r2, #6] ; CHECK-LE-NEXT: vldr.16 s2, [r2, #6]
; CHECK-LE-NEXT: vins.f16 s1, s4 ; CHECK-LE-NEXT: vins.f16 s1, s2
; CHECK-LE-NEXT: .LBB18_5: @ %else8 ; CHECK-LE-NEXT: .LBB18_5: @ %else8
; CHECK-LE-NEXT: vmrs r2, p0 ; CHECK-LE-NEXT: vmrs r2, p0
; CHECK-LE-NEXT: movs r1, #0 ; CHECK-LE-NEXT: movs r1, #0
; CHECK-LE-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-LE-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-LE-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-LE-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-LE-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-LE-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-LE-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-LE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-LE-NEXT: and r3, r2, #1 ; CHECK-LE-NEXT: and r3, r2, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0 ; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
; CHECK-LE-NEXT: ubfx r3, r2, #4, #1 ; CHECK-LE-NEXT: ubfx r3, r2, #4, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0 ; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: bfi r1, r3, #1, #1 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
; CHECK-LE-NEXT: ubfx r3, r2, #8, #1 ; CHECK-LE-NEXT: ubfx r3, r2, #8, #1
; CHECK-LE-NEXT: ubfx r2, r2, #12, #1 ; CHECK-LE-NEXT: ubfx r2, r2, #12, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0 ; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
; CHECK-LE-NEXT: rsbs r2, r2, #0 ; CHECK-LE-NEXT: rsbs r2, r2, #0
; CHECK-LE-NEXT: bfi r1, r2, #3, #1 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: lsls r2, r1, #31 ; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: itt ne ; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: vmovne r2, s4 ; CHECK-LE-NEXT: vmovne r2, s0
; CHECK-LE-NEXT: strne r2, [r0] ; CHECK-LE-NEXT: strne r2, [r0]
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: vmovmi r2, s5 ; CHECK-LE-NEXT: vmovmi r2, s1
; CHECK-LE-NEXT: strmi r2, [r0, #4] ; CHECK-LE-NEXT: strmi r2, [r0, #4]
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: vmovmi r2, s6 ; CHECK-LE-NEXT: vmovmi r2, s2
; CHECK-LE-NEXT: strmi r2, [r0, #8] ; CHECK-LE-NEXT: strmi r2, [r0, #8]
; CHECK-LE-NEXT: lsls r1, r1, #28 ; CHECK-LE-NEXT: lsls r1, r1, #28
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: vmovmi r1, s7 ; CHECK-LE-NEXT: vmovmi r1, s3
; CHECK-LE-NEXT: strmi r1, [r0, #12] ; CHECK-LE-NEXT: strmi r1, [r0, #12]
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r7, pc} ; CHECK-LE-NEXT: pop {r7, pc}
; CHECK-LE-NEXT: .LBB18_6: @ %cond.load ; CHECK-LE-NEXT: .LBB18_6: @ %cond.load
; CHECK-LE-NEXT: vldr.16 s0, [r2] ; CHECK-LE-NEXT: vldr.16 s0, [r2]
; CHECK-LE-NEXT: lsls r3, r1, #30 ; CHECK-LE-NEXT: lsls r3, r1, #30
; CHECK-LE-NEXT: bpl .LBB18_2 ; CHECK-LE-NEXT: bpl .LBB18_2
; CHECK-LE-NEXT: .LBB18_7: @ %cond.load1 ; CHECK-LE-NEXT: .LBB18_7: @ %cond.load1
; CHECK-LE-NEXT: vldr.16 s4, [r2, #2] ; CHECK-LE-NEXT: vldr.16 s2, [r2, #2]
; CHECK-LE-NEXT: vins.f16 s0, s4 ; CHECK-LE-NEXT: vins.f16 s0, s2
; CHECK-LE-NEXT: lsls r3, r1, #29 ; CHECK-LE-NEXT: lsls r3, r1, #29
; CHECK-LE-NEXT: bpl .LBB18_3 ; CHECK-LE-NEXT: bpl .LBB18_3
; CHECK-LE-NEXT: .LBB18_8: @ %cond.load4 ; CHECK-LE-NEXT: .LBB18_8: @ %cond.load4
; CHECK-LE-NEXT: vmovx.f16 s4, s1
; CHECK-LE-NEXT: vldr.16 s1, [r2, #4] ; CHECK-LE-NEXT: vldr.16 s1, [r2, #4]
; CHECK-LE-NEXT: vins.f16 s1, s4 ; CHECK-LE-NEXT: vmovx.f16 s2, s0
; CHECK-LE-NEXT: vins.f16 s1, s2
; CHECK-LE-NEXT: lsls r1, r1, #28 ; CHECK-LE-NEXT: lsls r1, r1, #28
; CHECK-LE-NEXT: bmi .LBB18_4 ; CHECK-LE-NEXT: bmi .LBB18_4
; CHECK-LE-NEXT: b .LBB18_5 ; CHECK-LE-NEXT: b .LBB18_5
; ;
; CHECK-BE-LABEL: foo_v4f32_v4f16: ; CHECK-BE-LABEL: foo_v4f32_v4f16:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r7, lr} ; CHECK-BE-NEXT: .save {r7, lr}
; CHECK-BE-NEXT: push {r7, lr} ; CHECK-BE-NEXT: push {r7, lr}
Show All 23 Lines
; CHECK-BE-NEXT: bmi .LBB18_7 ; CHECK-BE-NEXT: bmi .LBB18_7
; CHECK-BE-NEXT: .LBB18_2: @ %else2 ; CHECK-BE-NEXT: .LBB18_2: @ %else2
; CHECK-BE-NEXT: lsls r3, r1, #30 ; CHECK-BE-NEXT: lsls r3, r1, #30
; CHECK-BE-NEXT: bmi .LBB18_8 ; CHECK-BE-NEXT: bmi .LBB18_8
; CHECK-BE-NEXT: .LBB18_3: @ %else5 ; CHECK-BE-NEXT: .LBB18_3: @ %else5
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB18_5 ; CHECK-BE-NEXT: beq .LBB18_5
; CHECK-BE-NEXT: .LBB18_4: @ %cond.load7 ; CHECK-BE-NEXT: .LBB18_4: @ %cond.load7
; CHECK-BE-NEXT: vldr.16 s4, [r2, #6] ; CHECK-BE-NEXT: vldr.16 s2, [r2, #6]
; CHECK-BE-NEXT: vins.f16 s1, s4 ; CHECK-BE-NEXT: vins.f16 s1, s2
; CHECK-BE-NEXT: .LBB18_5: @ %else8 ; CHECK-BE-NEXT: .LBB18_5: @ %else8
; CHECK-BE-NEXT: vmrs r2, p0 ; CHECK-BE-NEXT: vmrs r2, p0
; CHECK-BE-NEXT: movs r1, #0 ; CHECK-BE-NEXT: movs r1, #0
; CHECK-BE-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-BE-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-BE-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-BE-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-BE-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-BE-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-BE-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-BE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-BE-NEXT: ubfx r3, r2, #12, #1 ; CHECK-BE-NEXT: ubfx r3, r2, #12, #1
; CHECK-BE-NEXT: rsbs r3, r3, #0 ; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
; CHECK-BE-NEXT: ubfx r3, r2, #8, #1 ; CHECK-BE-NEXT: ubfx r3, r2, #8, #1
; CHECK-BE-NEXT: rsbs r3, r3, #0 ; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: bfi r1, r3, #1, #1 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
; CHECK-BE-NEXT: ubfx r3, r2, #4, #1 ; CHECK-BE-NEXT: ubfx r3, r2, #4, #1
; CHECK-BE-NEXT: and r2, r2, #1 ; CHECK-BE-NEXT: and r2, r2, #1
; CHECK-BE-NEXT: rsbs r3, r3, #0 ; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: bfi r1, r3, #2, #1 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: rsbs r2, r2, #0 ; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: bfi r1, r2, #3, #1 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: itt mi ; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: vmovmi r2, s4 ; CHECK-BE-NEXT: vmovmi r2, s0
; CHECK-BE-NEXT: strmi r2, [r0] ; CHECK-BE-NEXT: strmi r2, [r0]
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: itt mi ; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: vmovmi r2, s5 ; CHECK-BE-NEXT: vmovmi r2, s1
; CHECK-BE-NEXT: strmi r2, [r0, #4] ; CHECK-BE-NEXT: strmi r2, [r0, #4]
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: itt mi ; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: vmovmi r2, s6 ; CHECK-BE-NEXT: vmovmi r2, s2
; CHECK-BE-NEXT: strmi r2, [r0, #8] ; CHECK-BE-NEXT: strmi r2, [r0, #8]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: itt ne ; CHECK-BE-NEXT: itt ne
; CHECK-BE-NEXT: vmovne r1, s7 ; CHECK-BE-NEXT: vmovne r1, s3
; CHECK-BE-NEXT: strne r1, [r0, #12] ; CHECK-BE-NEXT: strne r1, [r0, #12]
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: pop {r7, pc} ; CHECK-BE-NEXT: pop {r7, pc}
; CHECK-BE-NEXT: .LBB18_6: @ %cond.load ; CHECK-BE-NEXT: .LBB18_6: @ %cond.load
; CHECK-BE-NEXT: vldr.16 s0, [r2] ; CHECK-BE-NEXT: vldr.16 s0, [r2]
; CHECK-BE-NEXT: lsls r3, r1, #29 ; CHECK-BE-NEXT: lsls r3, r1, #29
; CHECK-BE-NEXT: bpl .LBB18_2 ; CHECK-BE-NEXT: bpl .LBB18_2
; CHECK-BE-NEXT: .LBB18_7: @ %cond.load1 ; CHECK-BE-NEXT: .LBB18_7: @ %cond.load1
; CHECK-BE-NEXT: vldr.16 s4, [r2, #2] ; CHECK-BE-NEXT: vldr.16 s2, [r2, #2]
; CHECK-BE-NEXT: vins.f16 s0, s4 ; CHECK-BE-NEXT: vins.f16 s0, s2
; CHECK-BE-NEXT: lsls r3, r1, #30 ; CHECK-BE-NEXT: lsls r3, r1, #30
; CHECK-BE-NEXT: bpl .LBB18_3 ; CHECK-BE-NEXT: bpl .LBB18_3
; CHECK-BE-NEXT: .LBB18_8: @ %cond.load4 ; CHECK-BE-NEXT: .LBB18_8: @ %cond.load4
; CHECK-BE-NEXT: vmovx.f16 s4, s1
; CHECK-BE-NEXT: vldr.16 s1, [r2, #4] ; CHECK-BE-NEXT: vldr.16 s1, [r2, #4]
; CHECK-BE-NEXT: vins.f16 s1, s4 ; CHECK-BE-NEXT: vmovx.f16 s2, s0
; CHECK-BE-NEXT: vins.f16 s1, s2
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: bne .LBB18_4 ; CHECK-BE-NEXT: bne .LBB18_4
; CHECK-BE-NEXT: b .LBB18_5 ; CHECK-BE-NEXT: b .LBB18_5
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %mask, align 2 %0 = load <4 x i16>, <4 x i16>* %mask, align 2
%1 = icmp sgt <4 x i16> %0, zeroinitializer %1 = icmp sgt <4 x i16> %0, zeroinitializer
%2 = call <4 x half> @llvm.masked.load.v4f16.p0v4f16(<4 x half>* %src, i32 2, <4 x i1> %1, <4 x half> undef) %2 = call <4 x half> @llvm.masked.load.v4f16.p0v4f16(<4 x half>* %src, i32 2, <4 x i1> %1, <4 x half> undef)
%3 = fpext <4 x half> %2 to <4 x float> %3 = fpext <4 x half> %2 to <4 x float>
Show All 32 Lines
; CHECK-LE-NEXT: bmi .LBB19_7 ; CHECK-LE-NEXT: bmi .LBB19_7
; CHECK-LE-NEXT: .LBB19_2: @ %else2 ; CHECK-LE-NEXT: .LBB19_2: @ %else2
; CHECK-LE-NEXT: lsls r3, r1, #29 ; CHECK-LE-NEXT: lsls r3, r1, #29
; CHECK-LE-NEXT: bmi .LBB19_8 ; CHECK-LE-NEXT: bmi .LBB19_8
; CHECK-LE-NEXT: .LBB19_3: @ %else5 ; CHECK-LE-NEXT: .LBB19_3: @ %else5
; CHECK-LE-NEXT: lsls r1, r1, #28 ; CHECK-LE-NEXT: lsls r1, r1, #28
; CHECK-LE-NEXT: bpl .LBB19_5 ; CHECK-LE-NEXT: bpl .LBB19_5
; CHECK-LE-NEXT: .LBB19_4: @ %cond.load7 ; CHECK-LE-NEXT: .LBB19_4: @ %cond.load7
; CHECK-LE-NEXT: vldr.16 s4, [r2, #6] ; CHECK-LE-NEXT: vldr.16 s2, [r2, #6]
; CHECK-LE-NEXT: vins.f16 s1, s4 ; CHECK-LE-NEXT: vins.f16 s1, s2
; CHECK-LE-NEXT: .LBB19_5: @ %else8 ; CHECK-LE-NEXT: .LBB19_5: @ %else8
; CHECK-LE-NEXT: vmrs r2, p0 ; CHECK-LE-NEXT: vmrs r2, p0
; CHECK-LE-NEXT: movs r1, #0 ; CHECK-LE-NEXT: movs r1, #0
; CHECK-LE-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-LE-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-LE-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-LE-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-LE-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-LE-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-LE-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-LE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-LE-NEXT: and r3, r2, #1 ; CHECK-LE-NEXT: and r3, r2, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0 ; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
; CHECK-LE-NEXT: ubfx r3, r2, #4, #1 ; CHECK-LE-NEXT: ubfx r3, r2, #4, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0 ; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: bfi r1, r3, #1, #1 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
; CHECK-LE-NEXT: ubfx r3, r2, #8, #1 ; CHECK-LE-NEXT: ubfx r3, r2, #8, #1
; CHECK-LE-NEXT: ubfx r2, r2, #12, #1 ; CHECK-LE-NEXT: ubfx r2, r2, #12, #1
; CHECK-LE-NEXT: rsbs r3, r3, #0 ; CHECK-LE-NEXT: rsbs r3, r3, #0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
; CHECK-LE-NEXT: rsbs r2, r2, #0 ; CHECK-LE-NEXT: rsbs r2, r2, #0
; CHECK-LE-NEXT: bfi r1, r2, #3, #1 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: lsls r2, r1, #31 ; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: itt ne ; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: vmovne r2, s4 ; CHECK-LE-NEXT: vmovne r2, s0
; CHECK-LE-NEXT: strne r2, [r0] ; CHECK-LE-NEXT: strne r2, [r0]
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: vmovmi r2, s5 ; CHECK-LE-NEXT: vmovmi r2, s1
; CHECK-LE-NEXT: strmi r2, [r0, #4] ; CHECK-LE-NEXT: strmi r2, [r0, #4]
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: vmovmi r2, s6 ; CHECK-LE-NEXT: vmovmi r2, s2
; CHECK-LE-NEXT: strmi r2, [r0, #8] ; CHECK-LE-NEXT: strmi r2, [r0, #8]
; CHECK-LE-NEXT: lsls r1, r1, #28 ; CHECK-LE-NEXT: lsls r1, r1, #28
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: vmovmi r1, s7 ; CHECK-LE-NEXT: vmovmi r1, s3
; CHECK-LE-NEXT: strmi r1, [r0, #12] ; CHECK-LE-NEXT: strmi r1, [r0, #12]
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r7, pc} ; CHECK-LE-NEXT: pop {r7, pc}
; CHECK-LE-NEXT: .LBB19_6: @ %cond.load ; CHECK-LE-NEXT: .LBB19_6: @ %cond.load
; CHECK-LE-NEXT: vldr.16 s0, [r2] ; CHECK-LE-NEXT: vldr.16 s0, [r2]
; CHECK-LE-NEXT: lsls r3, r1, #30 ; CHECK-LE-NEXT: lsls r3, r1, #30
; CHECK-LE-NEXT: bpl .LBB19_2 ; CHECK-LE-NEXT: bpl .LBB19_2
; CHECK-LE-NEXT: .LBB19_7: @ %cond.load1 ; CHECK-LE-NEXT: .LBB19_7: @ %cond.load1
; CHECK-LE-NEXT: vldr.16 s4, [r2, #2] ; CHECK-LE-NEXT: vldr.16 s2, [r2, #2]
; CHECK-LE-NEXT: vins.f16 s0, s4 ; CHECK-LE-NEXT: vins.f16 s0, s2
; CHECK-LE-NEXT: lsls r3, r1, #29 ; CHECK-LE-NEXT: lsls r3, r1, #29
; CHECK-LE-NEXT: bpl .LBB19_3 ; CHECK-LE-NEXT: bpl .LBB19_3
; CHECK-LE-NEXT: .LBB19_8: @ %cond.load4 ; CHECK-LE-NEXT: .LBB19_8: @ %cond.load4
; CHECK-LE-NEXT: vmovx.f16 s4, s1
; CHECK-LE-NEXT: vldr.16 s1, [r2, #4] ; CHECK-LE-NEXT: vldr.16 s1, [r2, #4]
; CHECK-LE-NEXT: vins.f16 s1, s4 ; CHECK-LE-NEXT: vmovx.f16 s2, s0
; CHECK-LE-NEXT: vins.f16 s1, s2
; CHECK-LE-NEXT: lsls r1, r1, #28 ; CHECK-LE-NEXT: lsls r1, r1, #28
; CHECK-LE-NEXT: bmi .LBB19_4 ; CHECK-LE-NEXT: bmi .LBB19_4
; CHECK-LE-NEXT: b .LBB19_5 ; CHECK-LE-NEXT: b .LBB19_5
; ;
; CHECK-BE-LABEL: foo_v4f32_v4f16_unaligned: ; CHECK-BE-LABEL: foo_v4f32_v4f16_unaligned:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r7, lr} ; CHECK-BE-NEXT: .save {r7, lr}
; CHECK-BE-NEXT: push {r7, lr} ; CHECK-BE-NEXT: push {r7, lr}
Show All 23 Lines
; CHECK-BE-NEXT: bmi .LBB19_7 ; CHECK-BE-NEXT: bmi .LBB19_7
; CHECK-BE-NEXT: .LBB19_2: @ %else2 ; CHECK-BE-NEXT: .LBB19_2: @ %else2
; CHECK-BE-NEXT: lsls r3, r1, #30 ; CHECK-BE-NEXT: lsls r3, r1, #30
; CHECK-BE-NEXT: bmi .LBB19_8 ; CHECK-BE-NEXT: bmi .LBB19_8
; CHECK-BE-NEXT: .LBB19_3: @ %else5 ; CHECK-BE-NEXT: .LBB19_3: @ %else5
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB19_5 ; CHECK-BE-NEXT: beq .LBB19_5
; CHECK-BE-NEXT: .LBB19_4: @ %cond.load7 ; CHECK-BE-NEXT: .LBB19_4: @ %cond.load7
; CHECK-BE-NEXT: vldr.16 s4, [r2, #6] ; CHECK-BE-NEXT: vldr.16 s2, [r2, #6]
; CHECK-BE-NEXT: vins.f16 s1, s4 ; CHECK-BE-NEXT: vins.f16 s1, s2
; CHECK-BE-NEXT: .LBB19_5: @ %else8 ; CHECK-BE-NEXT: .LBB19_5: @ %else8
; CHECK-BE-NEXT: vmrs r2, p0 ; CHECK-BE-NEXT: vmrs r2, p0
; CHECK-BE-NEXT: movs r1, #0 ; CHECK-BE-NEXT: movs r1, #0
; CHECK-BE-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-BE-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-BE-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-BE-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-BE-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-BE-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-BE-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-BE-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-BE-NEXT: ubfx r3, r2, #12, #1 ; CHECK-BE-NEXT: ubfx r3, r2, #12, #1
; CHECK-BE-NEXT: rsbs r3, r3, #0 ; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
; CHECK-BE-NEXT: ubfx r3, r2, #8, #1 ; CHECK-BE-NEXT: ubfx r3, r2, #8, #1
; CHECK-BE-NEXT: rsbs r3, r3, #0 ; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: bfi r1, r3, #1, #1 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
; CHECK-BE-NEXT: ubfx r3, r2, #4, #1 ; CHECK-BE-NEXT: ubfx r3, r2, #4, #1
; CHECK-BE-NEXT: and r2, r2, #1 ; CHECK-BE-NEXT: and r2, r2, #1
; CHECK-BE-NEXT: rsbs r3, r3, #0 ; CHECK-BE-NEXT: rsbs r3, r3, #0
; CHECK-BE-NEXT: bfi r1, r3, #2, #1 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: rsbs r2, r2, #0 ; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: bfi r1, r2, #3, #1 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: itt mi ; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: vmovmi r2, s4 ; CHECK-BE-NEXT: vmovmi r2, s0
; CHECK-BE-NEXT: strmi r2, [r0] ; CHECK-BE-NEXT: strmi r2, [r0]
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: itt mi ; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: vmovmi r2, s5 ; CHECK-BE-NEXT: vmovmi r2, s1
; CHECK-BE-NEXT: strmi r2, [r0, #4] ; CHECK-BE-NEXT: strmi r2, [r0, #4]
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: itt mi ; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: vmovmi r2, s6 ; CHECK-BE-NEXT: vmovmi r2, s2
; CHECK-BE-NEXT: strmi r2, [r0, #8] ; CHECK-BE-NEXT: strmi r2, [r0, #8]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: itt ne ; CHECK-BE-NEXT: itt ne
; CHECK-BE-NEXT: vmovne r1, s7 ; CHECK-BE-NEXT: vmovne r1, s3
; CHECK-BE-NEXT: strne r1, [r0, #12] ; CHECK-BE-NEXT: strne r1, [r0, #12]
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: pop {r7, pc} ; CHECK-BE-NEXT: pop {r7, pc}
; CHECK-BE-NEXT: .LBB19_6: @ %cond.load ; CHECK-BE-NEXT: .LBB19_6: @ %cond.load
; CHECK-BE-NEXT: vldr.16 s0, [r2] ; CHECK-BE-NEXT: vldr.16 s0, [r2]
; CHECK-BE-NEXT: lsls r3, r1, #29 ; CHECK-BE-NEXT: lsls r3, r1, #29
; CHECK-BE-NEXT: bpl .LBB19_2 ; CHECK-BE-NEXT: bpl .LBB19_2
; CHECK-BE-NEXT: .LBB19_7: @ %cond.load1 ; CHECK-BE-NEXT: .LBB19_7: @ %cond.load1
; CHECK-BE-NEXT: vldr.16 s4, [r2, #2] ; CHECK-BE-NEXT: vldr.16 s2, [r2, #2]
; CHECK-BE-NEXT: vins.f16 s0, s4 ; CHECK-BE-NEXT: vins.f16 s0, s2
; CHECK-BE-NEXT: lsls r3, r1, #30 ; CHECK-BE-NEXT: lsls r3, r1, #30
; CHECK-BE-NEXT: bpl .LBB19_3 ; CHECK-BE-NEXT: bpl .LBB19_3
; CHECK-BE-NEXT: .LBB19_8: @ %cond.load4 ; CHECK-BE-NEXT: .LBB19_8: @ %cond.load4
; CHECK-BE-NEXT: vmovx.f16 s4, s1
; CHECK-BE-NEXT: vldr.16 s1, [r2, #4] ; CHECK-BE-NEXT: vldr.16 s1, [r2, #4]
; CHECK-BE-NEXT: vins.f16 s1, s4 ; CHECK-BE-NEXT: vmovx.f16 s2, s0
; CHECK-BE-NEXT: vins.f16 s1, s2
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: bne .LBB19_4 ; CHECK-BE-NEXT: bne .LBB19_4
; CHECK-BE-NEXT: b .LBB19_5 ; CHECK-BE-NEXT: b .LBB19_5
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %mask, align 2 %0 = load <4 x i16>, <4 x i16>* %mask, align 2
%1 = icmp sgt <4 x i16> %0, zeroinitializer %1 = icmp sgt <4 x i16> %0, zeroinitializer
%2 = call <4 x half> @llvm.masked.load.v4f16.p0v4f16(<4 x half>* %src, i32 2, <4 x i1> %1, <4 x half> undef) %2 = call <4 x half> @llvm.masked.load.v4f16.p0v4f16(<4 x half>* %src, i32 2, <4 x i1> %1, <4 x half> undef)
%3 = fpext <4 x half> %2 to <4 x float> %3 = fpext <4 x half> %2 to <4 x float>
Show All 24 Lines

llvm/test/CodeGen/Thumb2/mve-masked-store.ll

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Linesentry:
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %a, <4 x i32>* %dest, i32 1, <4 x i1> %c) call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %a, <4 x i32>* %dest, i32 1, <4 x i1> %c)
ret void ret void
} }
define i8* @masked_v4i32_pre(i8* %y, i8* %x, <4 x i32> %a) { define i8* @masked_v4i32_pre(i8* %y, i8* %x, <4 x i32> %a) {
; CHECK-LE-LABEL: masked_v4i32_pre: ; CHECK-LE-LABEL: masked_v4i32_pre:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s32 gt, q0, zr ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4]! ; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4]!
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4i32_pre: ; CHECK-BE-LABEL: masked_v4i32_pre:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
; CHECK-BE-NEXT: vrev64.32 q2, q0 ; CHECK-BE-NEXT: vrev64.32 q2, q0
; CHECK-BE-NEXT: vpt.s32 gt, q2, zr ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4]! ; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4]!
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = bitcast i8* %z to <4 x i32>* %2 = bitcast i8* %z to <4 x i32>*
%c = icmp sgt <4 x i32> %a, zeroinitializer %c = icmp sgt <4 x i32> %a, zeroinitializer
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %1, <4 x i32>* %2, i32 4, <4 x i1> %c) call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %1, <4 x i32>* %2, i32 4, <4 x i1> %c)
ret i8* %z ret i8* %z
} }
define i8* @masked_v4i32_post(i8* %y, i8* %x, <4 x i32> %a) { define i8* @masked_v4i32_post(i8* %y, i8* %x, <4 x i32> %a) {
; CHECK-LE-LABEL: masked_v4i32_post: ; CHECK-LE-LABEL: masked_v4i32_post:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s32 gt, q0, zr ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
; CHECK-LE-NEXT: vstrwt.32 q1, [r0], #4 ; CHECK-LE-NEXT: vstrwt.32 q1, [r0], #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4i32_post: ; CHECK-BE-LABEL: masked_v4i32_post:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
; CHECK-BE-NEXT: vrev64.32 q2, q0 ; CHECK-BE-NEXT: vrev64.32 q2, q0
; CHECK-BE-NEXT: vpt.s32 gt, q2, zr ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
; CHECK-BE-NEXT: vstrwt.32 q1, [r0], #4 ; CHECK-BE-NEXT: vstrwt.32 q1, [r0], #4
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x i32>* %0 = bitcast i8* %x to <4 x i32>*
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Linesentry:
call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %a, <8 x i16>* %dest, i32 1, <8 x i1> %c) call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %a, <8 x i16>* %dest, i32 1, <8 x i1> %c)
ret void ret void
} }
define i8* @masked_v8i16_pre(i8* %y, i8* %x, <8 x i16> %a) { define i8* @masked_v8i16_pre(i8* %y, i8* %x, <8 x i16> %a) {
; CHECK-LE-LABEL: masked_v8i16_pre: ; CHECK-LE-LABEL: masked_v8i16_pre:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s16 gt, q0, zr ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4]! ; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4]!
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v8i16_pre: ; CHECK-BE-LABEL: masked_v8i16_pre:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
; CHECK-BE-NEXT: vrev64.16 q2, q0 ; CHECK-BE-NEXT: vrev64.16 q2, q0
; CHECK-BE-NEXT: vpt.s16 gt, q2, zr ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr
; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4]! ; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4]!
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 4 %1 = load <8 x i16>, <8 x i16>* %0, align 4
%2 = bitcast i8* %z to <8 x i16>* %2 = bitcast i8* %z to <8 x i16>*
%c = icmp sgt <8 x i16> %a, zeroinitializer %c = icmp sgt <8 x i16> %a, zeroinitializer
call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %1, <8 x i16>* %2, i32 2, <8 x i1> %c) call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %1, <8 x i16>* %2, i32 2, <8 x i1> %c)
ret i8* %z ret i8* %z
} }
define i8* @masked_v8i16_post(i8* %y, i8* %x, <8 x i16> %a) { define i8* @masked_v8i16_post(i8* %y, i8* %x, <8 x i16> %a) {
; CHECK-LE-LABEL: masked_v8i16_post: ; CHECK-LE-LABEL: masked_v8i16_post:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s16 gt, q0, zr ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
; CHECK-LE-NEXT: vstrht.16 q1, [r0], #4 ; CHECK-LE-NEXT: vstrht.16 q1, [r0], #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v8i16_post: ; CHECK-BE-LABEL: masked_v8i16_post:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
; CHECK-BE-NEXT: vrev64.16 q2, q0 ; CHECK-BE-NEXT: vrev64.16 q2, q0
; CHECK-BE-NEXT: vpt.s16 gt, q2, zr ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr
; CHECK-BE-NEXT: vstrht.16 q1, [r0], #4 ; CHECK-BE-NEXT: vstrht.16 q1, [r0], #4
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x i16>* %0 = bitcast i8* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 4 %1 = load <8 x i16>, <8 x i16>* %0, align 4
Show All 22 Linesentry:
call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %a, <16 x i8>* %dest, i32 1, <16 x i1> %c) call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %a, <16 x i8>* %dest, i32 1, <16 x i1> %c)
ret void ret void
} }
define i8* @masked_v16i8_pre(i8* %y, i8* %x, <16 x i8> %a) { define i8* @masked_v16i8_pre(i8* %y, i8* %x, <16 x i8> %a) {
; CHECK-LE-LABEL: masked_v16i8_pre: ; CHECK-LE-LABEL: masked_v16i8_pre:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s8 gt, q0, zr ; CHECK-LE-NEXT: vpt.s8 gt, q0, zr
; CHECK-LE-NEXT: vstrbt.8 q1, [r0, #4]! ; CHECK-LE-NEXT: vstrbt.8 q1, [r0, #4]!
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v16i8_pre: ; CHECK-BE-LABEL: masked_v16i8_pre:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrb.u8 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrb.u8 q1, [r1]
; CHECK-BE-NEXT: vrev64.8 q2, q0 ; CHECK-BE-NEXT: vrev64.8 q2, q0
; CHECK-BE-NEXT: vpt.s8 gt, q2, zr ; CHECK-BE-NEXT: vpt.s8 gt, q2, zr
; CHECK-BE-NEXT: vstrbt.8 q1, [r0, #4]! ; CHECK-BE-NEXT: vstrbt.8 q1, [r0, #4]!
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <16 x i8>* %0 = bitcast i8* %x to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0, align 4 %1 = load <16 x i8>, <16 x i8>* %0, align 4
%2 = bitcast i8* %z to <16 x i8>* %2 = bitcast i8* %z to <16 x i8>*
%c = icmp sgt <16 x i8> %a, zeroinitializer %c = icmp sgt <16 x i8> %a, zeroinitializer
call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %1, <16 x i8>* %2, i32 1, <16 x i1> %c) call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %1, <16 x i8>* %2, i32 1, <16 x i1> %c)
ret i8* %z ret i8* %z
} }
define i8* @masked_v16i8_post(i8* %y, i8* %x, <16 x i8> %a) { define i8* @masked_v16i8_post(i8* %y, i8* %x, <16 x i8> %a) {
; CHECK-LE-LABEL: masked_v16i8_post: ; CHECK-LE-LABEL: masked_v16i8_post:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s8 gt, q0, zr ; CHECK-LE-NEXT: vpt.s8 gt, q0, zr
; CHECK-LE-NEXT: vstrbt.8 q1, [r0], #4 ; CHECK-LE-NEXT: vstrbt.8 q1, [r0], #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v16i8_post: ; CHECK-BE-LABEL: masked_v16i8_post:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrb.u8 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrb.u8 q1, [r1]
; CHECK-BE-NEXT: vrev64.8 q2, q0 ; CHECK-BE-NEXT: vrev64.8 q2, q0
; CHECK-BE-NEXT: vpt.s8 gt, q2, zr ; CHECK-BE-NEXT: vpt.s8 gt, q2, zr
; CHECK-BE-NEXT: vstrbt.8 q1, [r0], #4 ; CHECK-BE-NEXT: vstrbt.8 q1, [r0], #4
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <16 x i8>* %0 = bitcast i8* %x to <16 x i8>*
%1 = load <16 x i8>, <16 x i8>* %0, align 4 %1 = load <16 x i8>, <16 x i8>* %0, align 4
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Linesentry:
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %a, <4 x float>* %dest, i32 1, <4 x i1> %c) call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %a, <4 x float>* %dest, i32 1, <4 x i1> %c)
ret void ret void
} }
define i8* @masked_v4f32_pre(i8* %y, i8* %x, <4 x i32> %a) { define i8* @masked_v4f32_pre(i8* %y, i8* %x, <4 x i32> %a) {
; CHECK-LE-LABEL: masked_v4f32_pre: ; CHECK-LE-LABEL: masked_v4f32_pre:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s32 gt, q0, zr ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4]! ; CHECK-LE-NEXT: vstrwt.32 q1, [r0, #4]!
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4f32_pre: ; CHECK-BE-LABEL: masked_v4f32_pre:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
; CHECK-BE-NEXT: vrev64.32 q2, q0 ; CHECK-BE-NEXT: vrev64.32 q2, q0
; CHECK-BE-NEXT: vpt.s32 gt, q2, zr ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4]! ; CHECK-BE-NEXT: vstrwt.32 q1, [r0, #4]!
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x float>* %0 = bitcast i8* %x to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 4 %1 = load <4 x float>, <4 x float>* %0, align 4
%2 = bitcast i8* %z to <4 x float>* %2 = bitcast i8* %z to <4 x float>*
%c = icmp sgt <4 x i32> %a, zeroinitializer %c = icmp sgt <4 x i32> %a, zeroinitializer
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %c) call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %c)
ret i8* %z ret i8* %z
} }
define i8* @masked_v4f32_post(i8* %y, i8* %x, <4 x i32> %a) { define i8* @masked_v4f32_post(i8* %y, i8* %x, <4 x i32> %a) {
; CHECK-LE-LABEL: masked_v4f32_post: ; CHECK-LE-LABEL: masked_v4f32_post:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s32 gt, q0, zr ; CHECK-LE-NEXT: vpt.s32 gt, q0, zr
; CHECK-LE-NEXT: vstrwt.32 q1, [r0], #4 ; CHECK-LE-NEXT: vstrwt.32 q1, [r0], #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4f32_post: ; CHECK-BE-LABEL: masked_v4f32_post:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrw.u32 q1, [r1]
; CHECK-BE-NEXT: vrev64.32 q2, q0 ; CHECK-BE-NEXT: vrev64.32 q2, q0
; CHECK-BE-NEXT: vpt.s32 gt, q2, zr ; CHECK-BE-NEXT: vpt.s32 gt, q2, zr
; CHECK-BE-NEXT: vstrwt.32 q1, [r0], #4 ; CHECK-BE-NEXT: vstrwt.32 q1, [r0], #4
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <4 x float>* %0 = bitcast i8* %x to <4 x float>*
%1 = load <4 x float>, <4 x float>* %0, align 4 %1 = load <4 x float>, <4 x float>* %0, align 4
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; CHECK-LE-NEXT: .LBB16_9: @ %cond.store ; CHECK-LE-NEXT: .LBB16_9: @ %cond.store
; CHECK-LE-NEXT: vstr.16 s0, [sp, #28] ; CHECK-LE-NEXT: vstr.16 s0, [sp, #28]
; CHECK-LE-NEXT: ldrh.w r2, [sp, #28] ; CHECK-LE-NEXT: ldrh.w r2, [sp, #28]
; CHECK-LE-NEXT: strh r2, [r0] ; CHECK-LE-NEXT: strh r2, [r0]
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: bpl .LBB16_2 ; CHECK-LE-NEXT: bpl .LBB16_2
; CHECK-LE-NEXT: .LBB16_10: @ %cond.store1 ; CHECK-LE-NEXT: .LBB16_10: @ %cond.store1
; CHECK-LE-NEXT: vmovx.f16 s4, s0 ; CHECK-LE-NEXT: vmovx.f16 s0, s0
; CHECK-LE-NEXT: vstr.16 s4, [sp, #24] ; CHECK-LE-NEXT: vstr.16 s0, [sp, #24]
; CHECK-LE-NEXT: ldrh.w r2, [sp, #24] ; CHECK-LE-NEXT: ldrh.w r2, [sp, #24]
; CHECK-LE-NEXT: strh r2, [r0, #2] ; CHECK-LE-NEXT: strh r2, [r0, #2]
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
; CHECK-LE-NEXT: bpl .LBB16_3 ; CHECK-LE-NEXT: bpl .LBB16_3
; CHECK-LE-NEXT: .LBB16_11: @ %cond.store3 ; CHECK-LE-NEXT: .LBB16_11: @ %cond.store3
; CHECK-LE-NEXT: vstr.16 s1, [sp, #20] ; CHECK-LE-NEXT: vstr.16 s1, [sp, #20]
; CHECK-LE-NEXT: ldrh.w r2, [sp, #20] ; CHECK-LE-NEXT: ldrh.w r2, [sp, #20]
; CHECK-LE-NEXT: strh r2, [r0, #4] ; CHECK-LE-NEXT: strh r2, [r0, #4]
; CHECK-LE-NEXT: lsls r2, r1, #28 ; CHECK-LE-NEXT: lsls r2, r1, #28
; CHECK-LE-NEXT: bpl .LBB16_4 ; CHECK-LE-NEXT: bpl .LBB16_4
; CHECK-LE-NEXT: .LBB16_12: @ %cond.store5 ; CHECK-LE-NEXT: .LBB16_12: @ %cond.store5
; CHECK-LE-NEXT: vmovx.f16 s4, s1 ; CHECK-LE-NEXT: vmovx.f16 s0, s1
; CHECK-LE-NEXT: vstr.16 s4, [sp, #16] ; CHECK-LE-NEXT: vstr.16 s0, [sp, #16]
; CHECK-LE-NEXT: ldrh.w r2, [sp, #16] ; CHECK-LE-NEXT: ldrh.w r2, [sp, #16]
; CHECK-LE-NEXT: strh r2, [r0, #6] ; CHECK-LE-NEXT: strh r2, [r0, #6]
; CHECK-LE-NEXT: lsls r2, r1, #27 ; CHECK-LE-NEXT: lsls r2, r1, #27
; CHECK-LE-NEXT: bpl .LBB16_5 ; CHECK-LE-NEXT: bpl .LBB16_5
; CHECK-LE-NEXT: .LBB16_13: @ %cond.store7 ; CHECK-LE-NEXT: .LBB16_13: @ %cond.store7
; CHECK-LE-NEXT: vstr.16 s2, [sp, #12] ; CHECK-LE-NEXT: vstr.16 s2, [sp, #12]
; CHECK-LE-NEXT: ldrh.w r2, [sp, #12] ; CHECK-LE-NEXT: ldrh.w r2, [sp, #12]
; CHECK-LE-NEXT: strh r2, [r0, #8] ; CHECK-LE-NEXT: strh r2, [r0, #8]
; CHECK-LE-NEXT: lsls r2, r1, #26 ; CHECK-LE-NEXT: lsls r2, r1, #26
; CHECK-LE-NEXT: bpl .LBB16_6 ; CHECK-LE-NEXT: bpl .LBB16_6
; CHECK-LE-NEXT: .LBB16_14: @ %cond.store9 ; CHECK-LE-NEXT: .LBB16_14: @ %cond.store9
; CHECK-LE-NEXT: vmovx.f16 s4, s2 ; CHECK-LE-NEXT: vmovx.f16 s0, s2
; CHECK-LE-NEXT: vstr.16 s4, [sp, #8] ; CHECK-LE-NEXT: vstr.16 s0, [sp, #8]
; CHECK-LE-NEXT: ldrh.w r2, [sp, #8] ; CHECK-LE-NEXT: ldrh.w r2, [sp, #8]
; CHECK-LE-NEXT: strh r2, [r0, #10] ; CHECK-LE-NEXT: strh r2, [r0, #10]
; CHECK-LE-NEXT: lsls r2, r1, #25 ; CHECK-LE-NEXT: lsls r2, r1, #25
; CHECK-LE-NEXT: bpl .LBB16_7 ; CHECK-LE-NEXT: bpl .LBB16_7
; CHECK-LE-NEXT: .LBB16_15: @ %cond.store11 ; CHECK-LE-NEXT: .LBB16_15: @ %cond.store11
; CHECK-LE-NEXT: vstr.16 s3, [sp, #4] ; CHECK-LE-NEXT: vstr.16 s3, [sp, #4]
; CHECK-LE-NEXT: ldrh.w r2, [sp, #4] ; CHECK-LE-NEXT: ldrh.w r2, [sp, #4]
; CHECK-LE-NEXT: strh r2, [r0, #12] ; CHECK-LE-NEXT: strh r2, [r0, #12]
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Linesentry:
call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %a, <8 x half>* %dest, i32 1, <8 x i1> %c) call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %a, <8 x half>* %dest, i32 1, <8 x i1> %c)
ret void ret void
} }
define i8* @masked_v8f16_pre(i8* %y, i8* %x, <8 x i16> %a) { define i8* @masked_v8f16_pre(i8* %y, i8* %x, <8 x i16> %a) {
; CHECK-LE-LABEL: masked_v8f16_pre: ; CHECK-LE-LABEL: masked_v8f16_pre:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s16 gt, q0, zr ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4]! ; CHECK-LE-NEXT: vstrht.16 q1, [r0, #4]!
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v8f16_pre: ; CHECK-BE-LABEL: masked_v8f16_pre:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
; CHECK-BE-NEXT: vrev64.16 q2, q0 ; CHECK-BE-NEXT: vrev64.16 q2, q0
; CHECK-BE-NEXT: vpt.s16 gt, q2, zr ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr
; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4]! ; CHECK-BE-NEXT: vstrht.16 q1, [r0, #4]!
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 4 %1 = load <8 x half>, <8 x half>* %0, align 4
%2 = bitcast i8* %z to <8 x half>* %2 = bitcast i8* %z to <8 x half>*
%c = icmp sgt <8 x i16> %a, zeroinitializer %c = icmp sgt <8 x i16> %a, zeroinitializer
call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %1, <8 x half>* %2, i32 2, <8 x i1> %c) call void @llvm.masked.store.v8f16.p0v8f16(<8 x half> %1, <8 x half>* %2, i32 2, <8 x i1> %c)
ret i8* %z ret i8* %z
} }
define i8* @masked_v8f16_post(i8* %y, i8* %x, <8 x i16> %a) { define i8* @masked_v8f16_post(i8* %y, i8* %x, <8 x i16> %a) {
; CHECK-LE-LABEL: masked_v8f16_post: ; CHECK-LE-LABEL: masked_v8f16_post:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vldr d1, [sp] ; CHECK-LE-NEXT: vldr d1, [sp]
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vmov d0, r2, r3 ; CHECK-LE-NEXT: vmov d0, r2, r3
; CHECK-LE-NEXT: vldrw.u32 q1, [r1]
; CHECK-LE-NEXT: vpt.s16 gt, q0, zr ; CHECK-LE-NEXT: vpt.s16 gt, q0, zr
; CHECK-LE-NEXT: vstrht.16 q1, [r0], #4 ; CHECK-LE-NEXT: vstrht.16 q1, [r0], #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v8f16_post: ; CHECK-BE-LABEL: masked_v8f16_post:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vldr d1, [sp] ; CHECK-BE-NEXT: vldr d1, [sp]
; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
; CHECK-BE-NEXT: vmov d0, r3, r2 ; CHECK-BE-NEXT: vmov d0, r3, r2
; CHECK-BE-NEXT: vldrh.u16 q1, [r1]
; CHECK-BE-NEXT: vrev64.16 q2, q0 ; CHECK-BE-NEXT: vrev64.16 q2, q0
; CHECK-BE-NEXT: vpt.s16 gt, q2, zr ; CHECK-BE-NEXT: vpt.s16 gt, q2, zr
; CHECK-BE-NEXT: vstrht.16 q1, [r0], #4 ; CHECK-BE-NEXT: vstrht.16 q1, [r0], #4
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%z = getelementptr inbounds i8, i8* %y, i32 4 %z = getelementptr inbounds i8, i8* %y, i32 4
%0 = bitcast i8* %x to <8 x half>* %0 = bitcast i8* %x to <8 x half>*
%1 = load <8 x half>, <8 x half>* %0, align 4 %1 = load <8 x half>, <8 x half>* %0, align 4
▲ Show 20 Lines • Show All 320 Lines • ▼ Show 20 Lines
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: vcmp.f32 s3, #0 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: csetm r3, ne
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: movs r2, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r2, #1 ; CHECK-LE-NEXT: movgt r2, #1
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
; CHECK-LE-NEXT: csetm r2, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: bfi r1, r2, #3, #1 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: lsls r2, r1, #31 ; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: bne .LBB25_5 ; CHECK-LE-NEXT: bne .LBB25_5
; CHECK-LE-NEXT: @ %bb.1: @ %else ; CHECK-LE-NEXT: @ %bb.1: @ %else
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: bmi .LBB25_6 ; CHECK-LE-NEXT: bmi .LBB25_6
; CHECK-LE-NEXT: .LBB25_2: @ %else2 ; CHECK-LE-NEXT: .LBB25_2: @ %else2
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: csetm r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r2, #1 ; CHECK-BE-NEXT: movgt r2, #1
; CHECK-BE-NEXT: cmp r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #2, #1 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: csetm r2, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r2, #3, #1 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7 ; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: bmi .LBB25_5 ; CHECK-BE-NEXT: bmi .LBB25_5
; CHECK-BE-NEXT: @ %bb.1: @ %else ; CHECK-BE-NEXT: @ %bb.1: @ %else
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bmi .LBB25_6 ; CHECK-BE-NEXT: bmi .LBB25_6
; CHECK-BE-NEXT: .LBB25_2: @ %else2 ; CHECK-BE-NEXT: .LBB25_2: @ %else2
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bmi .LBB25_7 ; CHECK-BE-NEXT: bmi .LBB25_7
; CHECK-BE-NEXT: .LBB25_3: @ %else4 ; CHECK-BE-NEXT: .LBB25_3: @ %else4
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: bne .LBB25_8 ; CHECK-BE-NEXT: bne .LBB25_8
; CHECK-BE-NEXT: .LBB25_4: @ %else6 ; CHECK-BE-NEXT: .LBB25_4: @ %else6
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
; CHECK-BE-NEXT: .LBB25_5: @ %cond.store ; CHECK-BE-NEXT: .LBB25_5: @ %cond.store
; CHECK-BE-NEXT: vstr.16 s0, [r0] ; CHECK-BE-NEXT: vstr.16 s0, [r0]
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bpl .LBB25_2 ; CHECK-BE-NEXT: bpl .LBB25_2
; CHECK-BE-NEXT: .LBB25_6: @ %cond.store1 ; CHECK-BE-NEXT: .LBB25_6: @ %cond.store1
; CHECK-BE-NEXT: vmovx.f16 s4, s0 ; CHECK-BE-NEXT: vmovx.f16 s0, s0
; CHECK-BE-NEXT: vstr.16 s4, [r0, #2] ; CHECK-BE-NEXT: vstr.16 s0, [r0, #2]
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bpl .LBB25_3 ; CHECK-BE-NEXT: bpl .LBB25_3
; CHECK-BE-NEXT: .LBB25_7: @ %cond.store3 ; CHECK-BE-NEXT: .LBB25_7: @ %cond.store3
; CHECK-BE-NEXT: vstr.16 s1, [r0, #4] ; CHECK-BE-NEXT: vstr.16 s1, [r0, #4]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB25_4 ; CHECK-BE-NEXT: beq .LBB25_4
; CHECK-BE-NEXT: .LBB25_8: @ %cond.store5 ; CHECK-BE-NEXT: .LBB25_8: @ %cond.store5
; CHECK-BE-NEXT: vmovx.f16 s0, s1 ; CHECK-BE-NEXT: vmovx.f16 s0, s1
Show All 37 Lines
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: vcmp.f32 s3, #0 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: csetm r3, ne
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: movs r2, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r2, #1 ; CHECK-LE-NEXT: movgt r2, #1
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
; CHECK-LE-NEXT: csetm r2, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: bfi r1, r2, #3, #1 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: lsls r2, r1, #31 ; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: bne .LBB26_5 ; CHECK-LE-NEXT: bne .LBB26_5
; CHECK-LE-NEXT: @ %bb.1: @ %else ; CHECK-LE-NEXT: @ %bb.1: @ %else
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: bmi .LBB26_6 ; CHECK-LE-NEXT: bmi .LBB26_6
; CHECK-LE-NEXT: .LBB26_2: @ %else2 ; CHECK-LE-NEXT: .LBB26_2: @ %else2
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: csetm r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r2, #1 ; CHECK-BE-NEXT: movgt r2, #1
; CHECK-BE-NEXT: cmp r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #2, #1 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: csetm r2, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r2, #3, #1 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7 ; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: bmi .LBB26_5 ; CHECK-BE-NEXT: bmi .LBB26_5
; CHECK-BE-NEXT: @ %bb.1: @ %else ; CHECK-BE-NEXT: @ %bb.1: @ %else
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bmi .LBB26_6 ; CHECK-BE-NEXT: bmi .LBB26_6
; CHECK-BE-NEXT: .LBB26_2: @ %else2 ; CHECK-BE-NEXT: .LBB26_2: @ %else2
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bmi .LBB26_7 ; CHECK-BE-NEXT: bmi .LBB26_7
; CHECK-BE-NEXT: .LBB26_3: @ %else4 ; CHECK-BE-NEXT: .LBB26_3: @ %else4
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: bne .LBB26_8 ; CHECK-BE-NEXT: bne .LBB26_8
; CHECK-BE-NEXT: .LBB26_4: @ %else6 ; CHECK-BE-NEXT: .LBB26_4: @ %else6
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
; CHECK-BE-NEXT: .LBB26_5: @ %cond.store ; CHECK-BE-NEXT: .LBB26_5: @ %cond.store
; CHECK-BE-NEXT: vstr.16 s0, [r0] ; CHECK-BE-NEXT: vstr.16 s0, [r0]
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bpl .LBB26_2 ; CHECK-BE-NEXT: bpl .LBB26_2
; CHECK-BE-NEXT: .LBB26_6: @ %cond.store1 ; CHECK-BE-NEXT: .LBB26_6: @ %cond.store1
; CHECK-BE-NEXT: vmovx.f16 s4, s0 ; CHECK-BE-NEXT: vmovx.f16 s0, s0
; CHECK-BE-NEXT: vstr.16 s4, [r0, #2] ; CHECK-BE-NEXT: vstr.16 s0, [r0, #2]
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bpl .LBB26_3 ; CHECK-BE-NEXT: bpl .LBB26_3
; CHECK-BE-NEXT: .LBB26_7: @ %cond.store3 ; CHECK-BE-NEXT: .LBB26_7: @ %cond.store3
; CHECK-BE-NEXT: vstr.16 s1, [r0, #4] ; CHECK-BE-NEXT: vstr.16 s1, [r0, #4]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB26_4 ; CHECK-BE-NEXT: beq .LBB26_4
; CHECK-BE-NEXT: .LBB26_8: @ %cond.store5 ; CHECK-BE-NEXT: .LBB26_8: @ %cond.store5
; CHECK-BE-NEXT: vmovx.f16 s0, s1 ; CHECK-BE-NEXT: vmovx.f16 s0, s1
Show All 37 Lines
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: vcmp.f32 s3, #0 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: csetm r3, ne
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: movs r2, #0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r2, #1 ; CHECK-LE-NEXT: movgt r2, #1
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
; CHECK-LE-NEXT: csetm r2, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: bfi r1, r2, #3, #1 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: lsls r2, r1, #31 ; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: bne .LBB27_5 ; CHECK-LE-NEXT: bne .LBB27_5
; CHECK-LE-NEXT: @ %bb.1: @ %else ; CHECK-LE-NEXT: @ %bb.1: @ %else
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: bmi .LBB27_6 ; CHECK-LE-NEXT: bmi .LBB27_6
; CHECK-LE-NEXT: .LBB27_2: @ %else2 ; CHECK-LE-NEXT: .LBB27_2: @ %else2
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: csetm r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r2, #1 ; CHECK-BE-NEXT: movgt r2, #1
; CHECK-BE-NEXT: cmp r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r3, #2, #1 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: csetm r2, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r2, #3, #1 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7 ; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: bmi .LBB27_5 ; CHECK-BE-NEXT: bmi .LBB27_5
; CHECK-BE-NEXT: @ %bb.1: @ %else ; CHECK-BE-NEXT: @ %bb.1: @ %else
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bmi .LBB27_6 ; CHECK-BE-NEXT: bmi .LBB27_6
; CHECK-BE-NEXT: .LBB27_2: @ %else2 ; CHECK-BE-NEXT: .LBB27_2: @ %else2
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bmi .LBB27_7 ; CHECK-BE-NEXT: bmi .LBB27_7
; CHECK-BE-NEXT: .LBB27_3: @ %else4 ; CHECK-BE-NEXT: .LBB27_3: @ %else4
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: bne .LBB27_8 ; CHECK-BE-NEXT: bne .LBB27_8
; CHECK-BE-NEXT: .LBB27_4: @ %else6 ; CHECK-BE-NEXT: .LBB27_4: @ %else6
; CHECK-BE-NEXT: add sp, #20 ; CHECK-BE-NEXT: add sp, #20
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
; CHECK-BE-NEXT: .LBB27_5: @ %cond.store ; CHECK-BE-NEXT: .LBB27_5: @ %cond.store
; CHECK-BE-NEXT: vstr.16 s0, [sp, #12] ; CHECK-BE-NEXT: vstr.16 s0, [sp, #12]
; CHECK-BE-NEXT: ldrh.w r2, [sp, #12] ; CHECK-BE-NEXT: ldrh.w r2, [sp, #12]
; CHECK-BE-NEXT: strh r2, [r0] ; CHECK-BE-NEXT: strh r2, [r0]
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bpl .LBB27_2 ; CHECK-BE-NEXT: bpl .LBB27_2
; CHECK-BE-NEXT: .LBB27_6: @ %cond.store1 ; CHECK-BE-NEXT: .LBB27_6: @ %cond.store1
; CHECK-BE-NEXT: vmovx.f16 s4, s0 ; CHECK-BE-NEXT: vmovx.f16 s0, s0
; CHECK-BE-NEXT: vstr.16 s4, [sp, #8] ; CHECK-BE-NEXT: vstr.16 s0, [sp, #8]
; CHECK-BE-NEXT: ldrh.w r2, [sp, #8] ; CHECK-BE-NEXT: ldrh.w r2, [sp, #8]
; CHECK-BE-NEXT: strh r2, [r0, #2] ; CHECK-BE-NEXT: strh r2, [r0, #2]
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bpl .LBB27_3 ; CHECK-BE-NEXT: bpl .LBB27_3
; CHECK-BE-NEXT: .LBB27_7: @ %cond.store3 ; CHECK-BE-NEXT: .LBB27_7: @ %cond.store3
; CHECK-BE-NEXT: vstr.16 s1, [sp, #4] ; CHECK-BE-NEXT: vstr.16 s1, [sp, #4]
; CHECK-BE-NEXT: ldrh.w r2, [sp, #4] ; CHECK-BE-NEXT: ldrh.w r2, [sp, #4]
; CHECK-BE-NEXT: strh r2, [r0, #4] ; CHECK-BE-NEXT: strh r2, [r0, #4]
Show All 27 Lines

llvm/test/CodeGen/Thumb2/mve-minmax.ll

Show First 20 Lines • Show All 273 Lines • ▼ Show 20 Linesentry:
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
ret <2 x i64> %1 ret <2 x i64> %1
} }
define arm_aapcs_vfpcc <4 x float> @maxnm_float32_t(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <4 x float> @maxnm_float32_t(<4 x float> %src1, <4 x float> %src2) {
; CHECK-MVE-LABEL: maxnm_float32_t: ; CHECK-MVE-LABEL: maxnm_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmaxnm.f32 s11, s7, s3 ; CHECK-MVE-NEXT: vmaxnm.f32 s3, s7, s3
; CHECK-MVE-NEXT: vmaxnm.f32 s10, s6, s2 ; CHECK-MVE-NEXT: vmaxnm.f32 s2, s6, s2
; CHECK-MVE-NEXT: vmaxnm.f32 s9, s5, s1 ; CHECK-MVE-NEXT: vmaxnm.f32 s1, s5, s1
; CHECK-MVE-NEXT: vmaxnm.f32 s8, s4, s0 ; CHECK-MVE-NEXT: vmaxnm.f32 s0, s4, s0
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: maxnm_float32_t: ; CHECK-MVEFP-LABEL: maxnm_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmaxnm.f32 q0, q1, q0 ; CHECK-MVEFP-NEXT: vmaxnm.f32 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%cmp = fcmp fast ogt <4 x float> %src2, %src1 %cmp = fcmp fast ogt <4 x float> %src2, %src1
%0 = select <4 x i1> %cmp, <4 x float> %src2, <4 x float> %src1 %0 = select <4 x i1> %cmp, <4 x float> %src2, <4 x float> %src1
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @minnm_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @minnm_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: minnm_float16_t: ; CHECK-MVE-LABEL: minnm_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q2, q0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s0
; CHECK-MVE-NEXT: vmovx.f16 s2, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmovx.f16 s0, s8 ; CHECK-MVE-NEXT: vminnm.f16 s0, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vminnm.f16 s8, s10, s8
; CHECK-MVE-NEXT: vminnm.f16 s12, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vminnm.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s12, s9 ; CHECK-MVE-NEXT: vminnm.f16 s1, s5, s1
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vminnm.f16 s4, s8, s4
; CHECK-MVE-NEXT: vminnm.f16 s1, s5, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vins.f16 s1, s12 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s12, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vminnm.f16 s2, s6, s2
; CHECK-MVE-NEXT: vminnm.f16 s2, s6, s10 ; CHECK-MVE-NEXT: vminnm.f16 s4, s8, s4
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s14, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vins.f16 s2, s12 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vmovx.f16 s12, s11 ; CHECK-MVE-NEXT: vminnm.f16 s3, s7, s3
; CHECK-MVE-NEXT: vminnm.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vminnm.f16 s4, s6, s4
; CHECK-MVE-NEXT: vminnm.f16 s3, s7, s11 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s12
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: minnm_float16_t: ; CHECK-MVEFP-LABEL: minnm_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vminnm.f16 q0, q1, q0 ; CHECK-MVEFP-NEXT: vminnm.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%cmp = fcmp fast ogt <8 x half> %src2, %src1 %cmp = fcmp fast ogt <8 x half> %src2, %src1
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llvm/test/CodeGen/Thumb2/mve-nofloat.ll

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
ret <8 x half> %sum ret <8 x half> %sum
} }
define arm_aapcs_vfpcc <4 x float> @vector_add_f32(<4 x float> %lhs, <4 x float> %rhs) { define arm_aapcs_vfpcc <4 x float> @vector_add_f32(<4 x float> %lhs, <4 x float> %rhs) {
; CHECK-NOFP-LABEL: vector_add_f32: ; CHECK-NOFP-LABEL: vector_add_f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: .save {r4, r5, r7, lr} ; CHECK-NOFP-NEXT: .save {r4, r5, r7, lr}
; CHECK-NOFP-NEXT: push {r4, r5, r7, lr} ; CHECK-NOFP-NEXT: push {r4, r5, r7, lr}
; CHECK-NOFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NOFP-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NOFP-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NOFP-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NOFP-NEXT: vmov q5, q1 ; CHECK-NOFP-NEXT: vmov q4, q1
; CHECK-NOFP-NEXT: vmov q6, q0 ; CHECK-NOFP-NEXT: vmov q5, q0
; CHECK-NOFP-NEXT: vmov r4, r0, d13 ; CHECK-NOFP-NEXT: vmov r4, r0, d11
; CHECK-NOFP-NEXT: vmov r5, r1, d11 ; CHECK-NOFP-NEXT: vmov r5, r1, d9
; CHECK-NOFP-NEXT: bl __aeabi_fadd ; CHECK-NOFP-NEXT: bl __aeabi_fadd
; CHECK-NOFP-NEXT: vmov s19, r0 ; CHECK-NOFP-NEXT: vmov s19, r0
; CHECK-NOFP-NEXT: mov r0, r4 ; CHECK-NOFP-NEXT: mov r0, r4
; CHECK-NOFP-NEXT: mov r1, r5 ; CHECK-NOFP-NEXT: mov r1, r5
; CHECK-NOFP-NEXT: bl __aeabi_fadd ; CHECK-NOFP-NEXT: bl __aeabi_fadd
; CHECK-NOFP-NEXT: vmov s18, r0 ; CHECK-NOFP-NEXT: vmov s18, r0
; CHECK-NOFP-NEXT: vmov r4, r0, d12 ; CHECK-NOFP-NEXT: vmov r4, r0, d10
; CHECK-NOFP-NEXT: vmov r5, r1, d10 ; CHECK-NOFP-NEXT: vmov r5, r1, d8
; CHECK-NOFP-NEXT: bl __aeabi_fadd ; CHECK-NOFP-NEXT: bl __aeabi_fadd
; CHECK-NOFP-NEXT: vmov s17, r0 ; CHECK-NOFP-NEXT: vmov s17, r0
; CHECK-NOFP-NEXT: mov r0, r4 ; CHECK-NOFP-NEXT: mov r0, r4
; CHECK-NOFP-NEXT: mov r1, r5 ; CHECK-NOFP-NEXT: mov r1, r5
; CHECK-NOFP-NEXT: bl __aeabi_fadd ; CHECK-NOFP-NEXT: bl __aeabi_fadd
; CHECK-NOFP-NEXT: vmov s16, r0 ; CHECK-NOFP-NEXT: vmov s16, r0
; CHECK-NOFP-NEXT: vmov q0, q4 ; CHECK-NOFP-NEXT: vmov q0, q4
; CHECK-NOFP-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NOFP-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NOFP-NEXT: pop {r4, r5, r7, pc} ; CHECK-NOFP-NEXT: pop {r4, r5, r7, pc}
; ;
; CHECK-FP-LABEL: vector_add_f32: ; CHECK-FP-LABEL: vector_add_f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vadd.f32 q0, q0, q1 ; CHECK-FP-NEXT: vadd.f32 q0, q0, q1
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
entry: entry:
%sum = fadd <4 x float> %lhs, %rhs %sum = fadd <4 x float> %lhs, %rhs
ret <4 x float> %sum ret <4 x float> %sum
} }

llvm/test/CodeGen/Thumb2/mve-phireg.ll

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 Lines
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #408 ; CHECK-NEXT: .pad #408
; CHECK-NEXT: sub sp, #408 ; CHECK-NEXT: sub sp, #408
; CHECK-NEXT: movw r7, :lower16:.L_MergedGlobals ; CHECK-NEXT: movw r7, :lower16:.L_MergedGlobals
; CHECK-NEXT: vldr s12, .LCPI1_0
; CHECK-NEXT: movt r7, :upper16:.L_MergedGlobals
; CHECK-NEXT: vldr s15, .LCPI1_1 ; CHECK-NEXT: vldr s15, .LCPI1_1
; CHECK-NEXT: mov r3, r7 ; CHECK-NEXT: movt r7, :upper16:.L_MergedGlobals
; CHECK-NEXT: mov r4, r7
; CHECK-NEXT: ldr r0, [r3, #4]!
; CHECK-NEXT: movw r2, :lower16:e ; CHECK-NEXT: movw r2, :lower16:e
; CHECK-NEXT: mov r4, r7
; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: ldr r6, [r4, #8]! ; CHECK-NEXT: ldr r6, [r4, #8]!
; CHECK-NEXT: vmov r5, s15
; CHECK-NEXT: vmov s13, r3
; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: movt r2, :upper16:e ; CHECK-NEXT: ldr r0, [r3, #4]!
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: movt r2, :upper16:e
; CHECK-NEXT: vmov r5, s15
; CHECK-NEXT: vmov q0[2], q0[0], r4, r4 ; CHECK-NEXT: vmov q0[2], q0[0], r4, r4
; CHECK-NEXT: vmov s21, r2 ; CHECK-NEXT: vmov s13, r3
; CHECK-NEXT: vmov.f32 s14, s13 ; CHECK-NEXT: vldr s12, .LCPI1_0
; CHECK-NEXT: vmov q0[3], q0[1], r5, r2 ; CHECK-NEXT: vmov q0[3], q0[1], r5, r2
; CHECK-NEXT: vmov.f32 s20, s12
; CHECK-NEXT: vdup.32 q7, r3 ; CHECK-NEXT: vdup.32 q7, r3
; CHECK-NEXT: vmov q6[2], q6[0], r3, r5 ; CHECK-NEXT: vmov q6[2], q6[0], r3, r5
; CHECK-NEXT: vmov.f32 s22, s13
; CHECK-NEXT: vstrw.32 q0, [sp, #92] ; CHECK-NEXT: vstrw.32 q0, [sp, #92]
; CHECK-NEXT: vmov q0, q7 ; CHECK-NEXT: vmov q0, q7
; CHECK-NEXT: vmov q6[3], q6[1], r3, r2 ; CHECK-NEXT: vmov q6[3], q6[1], r3, r2
; CHECK-NEXT: vmov q4, q7 ; CHECK-NEXT: vmov q4, q7
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov.32 q7[1], r2 ; CHECK-NEXT: vmov.32 q7[1], r2
; CHECK-NEXT: vmov.f32 s23, s15 ; CHECK-NEXT: vmov s21, r2
; CHECK-NEXT: movs r1, #64 ; CHECK-NEXT: movs r1, #64
; CHECK-NEXT: vmov.f32 s20, s12
; CHECK-NEXT: str r0, [sp, #40] ; CHECK-NEXT: str r0, [sp, #40]
; CHECK-NEXT: vstrw.32 q5, [r0] ; CHECK-NEXT: vmov.f32 s22, s13
; CHECK-NEXT: str r6, [r0] ; CHECK-NEXT: str r6, [r0]
; CHECK-NEXT: vstrw.32 q7, [r0] ; CHECK-NEXT: vmov.f32 s23, s15
; CHECK-NEXT: str r0, [r0] ; CHECK-NEXT: str r0, [r0]
; CHECK-NEXT: vstrw.32 q5, [r0]
; CHECK-NEXT: vstrw.32 q7, [r0]
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: vstrw.32 q6, [r0] ; CHECK-NEXT: vstrw.32 q6, [r0]
; CHECK-NEXT: mov.w r8, #0 ; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: vmov q1[2], q1[0], r4, r3 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r3
; CHECK-NEXT: vmov q2[2], q2[0], r3, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r3, r3
; CHECK-NEXT: mov.w r12, #4 ; CHECK-NEXT: mov.w r12, #4
; CHECK-NEXT: vmov q1[3], q1[1], r2, r4 ; CHECK-NEXT: vmov q1[3], q1[1], r2, r4
; CHECK-NEXT: vmov.f32 s14, s13
; CHECK-NEXT: vmov q2[3], q2[1], r4, r5 ; CHECK-NEXT: vmov q2[3], q2[1], r4, r5
; CHECK-NEXT: vmov.32 q4[0], r8 ; CHECK-NEXT: vmov.32 q4[0], r8
; CHECK-NEXT: @ implicit-def: $r2 ; CHECK-NEXT: @ implicit-def: $r2
; CHECK-NEXT: str.w r8, [sp, #44] ; CHECK-NEXT: str.w r8, [sp, #44]
; CHECK-NEXT: vstrw.32 q3, [sp, #60] ; CHECK-NEXT: vstrw.32 q3, [sp, #60]
; CHECK-NEXT: strh.w r12, [sp, #406] ; CHECK-NEXT: strh.w r12, [sp, #406]
; CHECK-NEXT: wlstp.8 lr, r1, .LBB1_2 ; CHECK-NEXT: wlstp.8 lr, r1, .LBB1_2
; CHECK-NEXT: .LBB1_1: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: .LBB1_1: @ =>This Inner Loop Header: Depth=1
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llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll

Show All 28 Lines
; CHECK-NEXT: @ Parent Loop BB0_2 Depth=1 ; CHECK-NEXT: @ Parent Loop BB0_2 Depth=1
; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
; CHECK-NEXT: vldrw.u32 q1, [r6], #16 ; CHECK-NEXT: vldrw.u32 q1, [r6], #16
; CHECK-NEXT: vldrw.u32 q2, [r7], #16 ; CHECK-NEXT: vldrw.u32 q2, [r7], #16
; CHECK-NEXT: vfma.f32 q0, q2, q1 ; CHECK-NEXT: vfma.f32 q0, q2, q1
; CHECK-NEXT: letp lr, .LBB0_3 ; CHECK-NEXT: letp lr, .LBB0_3
; CHECK-NEXT: @ %bb.4: @ %middle.block ; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: vadd.f32 s4, s2, s3 ; CHECK-NEXT: vadd.f32 s2, s2, s3
; CHECK-NEXT: add.w r7, r2, r0, lsl #2 ; CHECK-NEXT: add.w r7, r2, r0, lsl #2
; CHECK-NEXT: vadd.f32 s0, s0, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: adds r0, #1 ; CHECK-NEXT: adds r0, #1
; CHECK-NEXT: add r3, r9 ; CHECK-NEXT: add r3, r9
; CHECK-NEXT: cmp r0, r12 ; CHECK-NEXT: cmp r0, r12
; CHECK-NEXT: vadd.f32 s0, s0, s4 ; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: vstr s0, [r7] ; CHECK-NEXT: vstr s0, [r7]
; CHECK-NEXT: bne .LBB0_2 ; CHECK-NEXT: bne .LBB0_2
; CHECK-NEXT: .LBB0_5: @ %for.cond.cleanup ; CHECK-NEXT: .LBB0_5: @ %for.cond.cleanup
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
entry: entry:
%NumInputs = getelementptr inbounds %struct.DCT_InstanceTypeDef, %struct.DCT_InstanceTypeDef* %S, i32 0, i32 2 %NumInputs = getelementptr inbounds %struct.DCT_InstanceTypeDef, %struct.DCT_InstanceTypeDef* %S, i32 0, i32 2
%0 = load i32, i32* %NumInputs, align 4 %0 = load i32, i32* %NumInputs, align 4
%NumFilters = getelementptr inbounds %struct.DCT_InstanceTypeDef, %struct.DCT_InstanceTypeDef* %S, i32 0, i32 1 %NumFilters = getelementptr inbounds %struct.DCT_InstanceTypeDef, %struct.DCT_InstanceTypeDef* %S, i32 0, i32 1
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; CHECK-NEXT: vldrw.u32 q2, [r5], #16 ; CHECK-NEXT: vldrw.u32 q2, [r5], #16
; CHECK-NEXT: vldrw.u32 q3, [r3], #16 ; CHECK-NEXT: vldrw.u32 q3, [r3], #16
; CHECK-NEXT: vfma.f32 q1, q3, q2 ; CHECK-NEXT: vfma.f32 q1, q3, q2
; CHECK-NEXT: vldrw.u32 q3, [r0], #16 ; CHECK-NEXT: vldrw.u32 q3, [r0], #16
; CHECK-NEXT: vfma.f32 q0, q3, q2 ; CHECK-NEXT: vfma.f32 q0, q3, q2
; CHECK-NEXT: letp lr, .LBB1_3 ; CHECK-NEXT: letp lr, .LBB1_3
; CHECK-NEXT: @ %bb.4: @ %middle.block ; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB1_2 Depth=1
; CHECK-NEXT: vadd.f32 s8, s2, s3 ; CHECK-NEXT: vadd.f32 s2, s2, s3
; CHECK-NEXT: add.w r0, r2, r9, lsl #2 ; CHECK-NEXT: add.w r0, r2, r9, lsl #2
; CHECK-NEXT: vadd.f32 s0, s0, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: add r11, r10 ; CHECK-NEXT: add r11, r10
; CHECK-NEXT: vadd.f32 s2, s6, s7 ; CHECK-NEXT: vadd.f32 s6, s6, s7
; CHECK-NEXT: add r6, r10 ; CHECK-NEXT: add r6, r10
; CHECK-NEXT: vadd.f32 s4, s4, s5 ; CHECK-NEXT: vadd.f32 s4, s4, s5
; CHECK-NEXT: vadd.f32 s0, s0, s8 ; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: vadd.f32 s2, s4, s2 ; CHECK-NEXT: vadd.f32 s2, s4, s6
; CHECK-NEXT: vstr s0, [r0] ; CHECK-NEXT: vstr s0, [r0]
; CHECK-NEXT: add.w r0, r2, r4, lsl #2 ; CHECK-NEXT: add.w r0, r2, r4, lsl #2
; CHECK-NEXT: adds r4, #2 ; CHECK-NEXT: adds r4, #2
; CHECK-NEXT: vstr s2, [r0] ; CHECK-NEXT: vstr s2, [r0]
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload ; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
; CHECK-NEXT: cmp r4, r0 ; CHECK-NEXT: cmp r4, r0
; CHECK-NEXT: blo .LBB1_2 ; CHECK-NEXT: blo .LBB1_2
; CHECK-NEXT: .LBB1_5: @ %for.cond.cleanup ; CHECK-NEXT: .LBB1_5: @ %for.cond.cleanup
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; CHECK-NEXT: vfma.f32 q1, q4, q3 ; CHECK-NEXT: vfma.f32 q1, q4, q3
; CHECK-NEXT: vldrw.u32 q4, [r0], #16 ; CHECK-NEXT: vldrw.u32 q4, [r0], #16
; CHECK-NEXT: vfma.f32 q2, q4, q3 ; CHECK-NEXT: vfma.f32 q2, q4, q3
; CHECK-NEXT: vldrw.u32 q4, [r4], #16 ; CHECK-NEXT: vldrw.u32 q4, [r4], #16
; CHECK-NEXT: vfma.f32 q0, q4, q3 ; CHECK-NEXT: vfma.f32 q0, q4, q3
; CHECK-NEXT: letp lr, .LBB2_3 ; CHECK-NEXT: letp lr, .LBB2_3
; CHECK-NEXT: @ %bb.4: @ %middle.block ; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: vadd.f32 s12, s10, s11 ; CHECK-NEXT: vadd.f32 s10, s10, s11
; CHECK-NEXT: adds r0, r5, #1 ; CHECK-NEXT: adds r0, r5, #1
; CHECK-NEXT: vadd.f32 s8, s8, s9 ; CHECK-NEXT: vadd.f32 s8, s8, s9
; CHECK-NEXT: add r10, r11 ; CHECK-NEXT: add r10, r11
; CHECK-NEXT: vadd.f32 s10, s6, s7 ; CHECK-NEXT: vadd.f32 s6, s6, s7
; CHECK-NEXT: add.w r0, r2, r0, lsl #2 ; CHECK-NEXT: add.w r0, r2, r0, lsl #2
; CHECK-NEXT: vadd.f32 s4, s4, s5 ; CHECK-NEXT: vadd.f32 s4, s4, s5
; CHECK-NEXT: add r12, r11 ; CHECK-NEXT: add r12, r11
; CHECK-NEXT: vadd.f32 s6, s2, s3 ; CHECK-NEXT: vadd.f32 s2, s2, s3
; CHECK-NEXT: add r8, r11 ; CHECK-NEXT: add r8, r11
; CHECK-NEXT: vadd.f32 s0, s0, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: vadd.f32 s2, s8, s12 ; CHECK-NEXT: vadd.f32 s8, s8, s10
; CHECK-NEXT: vadd.f32 s4, s4, s10 ; CHECK-NEXT: vadd.f32 s4, s4, s6
; CHECK-NEXT: vadd.f32 s0, s0, s6 ; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: vstr s2, [r0] ; CHECK-NEXT: vstr s8, [r0]
; CHECK-NEXT: add.w r0, r2, r5, lsl #2 ; CHECK-NEXT: add.w r0, r2, r5, lsl #2
; CHECK-NEXT: vstr s4, [r0] ; CHECK-NEXT: vstr s4, [r0]
; CHECK-NEXT: adds r0, r5, #2 ; CHECK-NEXT: adds r0, r5, #2
; CHECK-NEXT: adds r5, #3 ; CHECK-NEXT: adds r5, #3
; CHECK-NEXT: add.w r0, r2, r0, lsl #2 ; CHECK-NEXT: add.w r0, r2, r0, lsl #2
; CHECK-NEXT: vstr s0, [r0] ; CHECK-NEXT: vstr s0, [r0]
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload ; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: cmp r5, r0 ; CHECK-NEXT: cmp r5, r0
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; CHECK-NEXT: vfma.f32 q2, q5, q4 ; CHECK-NEXT: vfma.f32 q2, q5, q4
; CHECK-NEXT: vldrw.u32 q5, [r5], #16 ; CHECK-NEXT: vldrw.u32 q5, [r5], #16
; CHECK-NEXT: vfma.f32 q1, q5, q4 ; CHECK-NEXT: vfma.f32 q1, q5, q4
; CHECK-NEXT: vldrw.u32 q5, [r4], #16 ; CHECK-NEXT: vldrw.u32 q5, [r4], #16
; CHECK-NEXT: vfma.f32 q0, q5, q4 ; CHECK-NEXT: vfma.f32 q0, q5, q4
; CHECK-NEXT: letp lr, .LBB3_3 ; CHECK-NEXT: letp lr, .LBB3_3
; CHECK-NEXT: @ %bb.4: @ %middle.block ; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB3_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB3_2 Depth=1
; CHECK-NEXT: vadd.f32 s16, s14, s15 ; CHECK-NEXT: vadd.f32 s14, s14, s15
; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload ; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: vadd.f32 s12, s12, s13 ; CHECK-NEXT: vadd.f32 s12, s12, s13
; CHECK-NEXT: adds r0, r6, #1 ; CHECK-NEXT: adds r0, r6, #1
; CHECK-NEXT: vadd.f32 s14, s10, s11 ; CHECK-NEXT: vadd.f32 s10, s10, s11
; CHECK-NEXT: vadd.f32 s8, s8, s9 ; CHECK-NEXT: vadd.f32 s8, s8, s9
; CHECK-NEXT: add.w r0, r1, r0, lsl #2 ; CHECK-NEXT: add.w r0, r1, r0, lsl #2
; CHECK-NEXT: vadd.f32 s10, s6, s7 ; CHECK-NEXT: vadd.f32 s6, s6, s7
; CHECK-NEXT: vadd.f32 s4, s4, s5 ; CHECK-NEXT: vadd.f32 s4, s4, s5
; CHECK-NEXT: vadd.f32 s6, s2, s3 ; CHECK-NEXT: vadd.f32 s2, s2, s3
; CHECK-NEXT: vadd.f32 s0, s0, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: vadd.f32 s2, s12, s16 ; CHECK-NEXT: vadd.f32 s12, s12, s14
; CHECK-NEXT: vadd.f32 s8, s8, s14 ; CHECK-NEXT: vadd.f32 s8, s8, s10
; CHECK-NEXT: vadd.f32 s4, s4, s10 ; CHECK-NEXT: vadd.f32 s4, s4, s6
; CHECK-NEXT: vadd.f32 s0, s0, s6 ; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: vstr s2, [r0] ; CHECK-NEXT: vstr s12, [r0]
; CHECK-NEXT: add.w r0, r1, r6, lsl #2 ; CHECK-NEXT: add.w r0, r1, r6, lsl #2
; CHECK-NEXT: vstr s8, [r0] ; CHECK-NEXT: vstr s8, [r0]
; CHECK-NEXT: adds r0, r6, #2 ; CHECK-NEXT: adds r0, r6, #2
; CHECK-NEXT: add.w r0, r1, r0, lsl #2 ; CHECK-NEXT: add.w r0, r1, r0, lsl #2
; CHECK-NEXT: vstr s4, [r0] ; CHECK-NEXT: vstr s4, [r0]
; CHECK-NEXT: adds r0, r6, #3 ; CHECK-NEXT: adds r0, r6, #3
; CHECK-NEXT: adds r6, #4 ; CHECK-NEXT: adds r6, #4
; CHECK-NEXT: add.w r0, r1, r0, lsl #2 ; CHECK-NEXT: add.w r0, r1, r0, lsl #2
▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
; CHECK-NEXT: adds r7, r6, r5 ; CHECK-NEXT: adds r7, r6, r5
; CHECK-NEXT: vldrw.u32 q6, [r6] ; CHECK-NEXT: vldrw.u32 q6, [r6]
; CHECK-NEXT: vfma.f32 q0, q6, q5 ; CHECK-NEXT: vfma.f32 q0, q6, q5
; CHECK-NEXT: vldrw.u32 q6, [r7] ; CHECK-NEXT: vldrw.u32 q6, [r7]
; CHECK-NEXT: vfma.f32 q1, q6, q5 ; CHECK-NEXT: vfma.f32 q1, q6, q5
; CHECK-NEXT: letp lr, .LBB4_3 ; CHECK-NEXT: letp lr, .LBB4_3
; CHECK-NEXT: @ %bb.4: @ %middle.block ; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB4_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB4_2 Depth=1
; CHECK-NEXT: vadd.f32 s20, s18, s19 ; CHECK-NEXT: vadd.f32 s18, s18, s19
; CHECK-NEXT: add.w r3, r2, r11, lsl #2 ; CHECK-NEXT: add.w r3, r2, r11, lsl #2
; CHECK-NEXT: vadd.f32 s16, s16, s17 ; CHECK-NEXT: vadd.f32 s16, s16, s17
; CHECK-NEXT: vadd.f32 s18, s14, s15 ; CHECK-NEXT: vadd.f32 s14, s14, s15
; CHECK-NEXT: vadd.f32 s12, s12, s13 ; CHECK-NEXT: vadd.f32 s12, s12, s13
; CHECK-NEXT: vadd.f32 s14, s6, s7 ; CHECK-NEXT: vadd.f32 s6, s6, s7
; CHECK-NEXT: vadd.f32 s4, s4, s5 ; CHECK-NEXT: vadd.f32 s4, s4, s5
; CHECK-NEXT: vadd.f32 s6, s10, s11 ; CHECK-NEXT: vadd.f32 s10, s10, s11
; CHECK-NEXT: vadd.f32 s8, s8, s9 ; CHECK-NEXT: vadd.f32 s8, s8, s9
; CHECK-NEXT: vadd.f32 s10, s2, s3
; CHECK-NEXT: vadd.f32 s0, s0, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: vadd.f32 s2, s16, s20 ; CHECK-NEXT: vadd.f32 s1, s16, s18
; CHECK-NEXT: vadd.f32 s12, s12, s18 ; CHECK-NEXT: vadd.f32 s12, s12, s14
; CHECK-NEXT: vadd.f32 s4, s4, s14 ; CHECK-NEXT: vadd.f32 s2, s2, s3
; CHECK-NEXT: vadd.f32 s6, s8, s6 ; CHECK-NEXT: vadd.f32 s4, s4, s6
; CHECK-NEXT: vadd.f32 s0, s0, s10 ; CHECK-NEXT: vadd.f32 s6, s8, s10
; CHECK-NEXT: vstr s2, [r3] ; CHECK-NEXT: vstr s1, [r3]
; CHECK-NEXT: add.w r3, r2, r0, lsl #2 ; CHECK-NEXT: add.w r3, r2, r0, lsl #2
; CHECK-NEXT: vstr s12, [r3] ; CHECK-NEXT: vstr s12, [r3]
; CHECK-NEXT: adds r3, r0, #2 ; CHECK-NEXT: adds r3, r0, #2
; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: add.w r3, r2, r3, lsl #2 ; CHECK-NEXT: add.w r3, r2, r3, lsl #2
; CHECK-NEXT: vstr s6, [r3] ; CHECK-NEXT: vstr s6, [r3]
; CHECK-NEXT: adds r3, r0, #3 ; CHECK-NEXT: adds r3, r0, #3
; CHECK-NEXT: add.w r3, r2, r3, lsl #2 ; CHECK-NEXT: add.w r3, r2, r3, lsl #2
; CHECK-NEXT: vstr s0, [r3] ; CHECK-NEXT: vstr s0, [r3]
; CHECK-NEXT: adds r3, r0, #4 ; CHECK-NEXT: adds r3, r0, #4
; CHECK-NEXT: adds r0, #5 ; CHECK-NEXT: adds r0, #5
; CHECK-NEXT: add.w r3, r2, r3, lsl #2 ; CHECK-NEXT: add.w r3, r2, r3, lsl #2
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; CHECK-NEXT: adds r6, r7, r5 ; CHECK-NEXT: adds r6, r7, r5
; CHECK-NEXT: vldrw.u32 q7, [r7] ; CHECK-NEXT: vldrw.u32 q7, [r7]
; CHECK-NEXT: vfma.f32 q3, q7, q6 ; CHECK-NEXT: vfma.f32 q3, q7, q6
; CHECK-NEXT: vldrw.u32 q7, [r6] ; CHECK-NEXT: vldrw.u32 q7, [r6]
; CHECK-NEXT: vfma.f32 q1, q7, q6 ; CHECK-NEXT: vfma.f32 q1, q7, q6
; CHECK-NEXT: letp lr, .LBB5_3 ; CHECK-NEXT: letp lr, .LBB5_3
; CHECK-NEXT: @ %bb.4: @ %middle.block ; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB5_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: vadd.f32 s24, s22, s23 ; CHECK-NEXT: vadd.f32 s22, s22, s23
; CHECK-NEXT: add.w r1, r2, r4, lsl #2 ; CHECK-NEXT: add.w r1, r2, r4, lsl #2
; CHECK-NEXT: vadd.f32 s20, s20, s21 ; CHECK-NEXT: vadd.f32 s20, s20, s21
; CHECK-NEXT: vadd.f32 s22, s18, s19 ; CHECK-NEXT: vadd.f32 s18, s18, s19
; CHECK-NEXT: vadd.f32 s16, s16, s17 ; CHECK-NEXT: vadd.f32 s16, s16, s17
; CHECK-NEXT: vadd.f32 s18, s6, s7 ; CHECK-NEXT: vadd.f32 s10, s10, s11
; CHECK-NEXT: vadd.f32 s4, s4, s5
; CHECK-NEXT: vadd.f32 s6, s14, s15
; CHECK-NEXT: vadd.f32 s12, s12, s13
; CHECK-NEXT: vadd.f32 s14, s10, s11
; CHECK-NEXT: vadd.f32 s8, s8, s9 ; CHECK-NEXT: vadd.f32 s8, s8, s9
; CHECK-NEXT: vadd.f32 s0, s0, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: vadd.f32 s10, s2, s3 ; CHECK-NEXT: vadd.f32 s2, s2, s3
; CHECK-NEXT: vadd.f32 s2, s20, s24 ; CHECK-NEXT: vadd.f32 s1, s20, s22
; CHECK-NEXT: vadd.f32 s1, s16, s22 ; CHECK-NEXT: vadd.f32 s6, s6, s7
; CHECK-NEXT: vadd.f32 s6, s12, s6 ; CHECK-NEXT: vadd.f32 s3, s16, s18
; CHECK-NEXT: vadd.f32 s4, s4, s18 ; CHECK-NEXT: vadd.f32 s4, s4, s5
; CHECK-NEXT: vadd.f32 s8, s8, s14 ; CHECK-NEXT: vadd.f32 s8, s8, s10
; CHECK-NEXT: vadd.f32 s0, s0, s10 ; CHECK-NEXT: vadd.f32 s14, s14, s15
; CHECK-NEXT: vstr s2, [r1] ; CHECK-NEXT: vadd.f32 s12, s12, s13
; CHECK-NEXT: add.w r1, r2, r0, lsl #2
; CHECK-NEXT: vstr s1, [r1] ; CHECK-NEXT: vstr s1, [r1]
; CHECK-NEXT: add.w r1, r2, r0, lsl #2
; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: vstr s3, [r1]
; CHECK-NEXT: adds r1, r0, #2 ; CHECK-NEXT: adds r1, r0, #2
; CHECK-NEXT: vadd.f32 s4, s4, s6
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: vstr s8, [r1] ; CHECK-NEXT: vstr s8, [r1]
; CHECK-NEXT: adds r1, r0, #3 ; CHECK-NEXT: adds r1, r0, #3
; CHECK-NEXT: vadd.f32 s6, s12, s14
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: vstr s0, [r1] ; CHECK-NEXT: vstr s0, [r1]
; CHECK-NEXT: adds r1, r0, #4 ; CHECK-NEXT: adds r1, r0, #4
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: vstr s6, [r1] ; CHECK-NEXT: vstr s6, [r1]
; CHECK-NEXT: adds r1, r0, #5 ; CHECK-NEXT: adds r1, r0, #5
; CHECK-NEXT: adds r0, #6 ; CHECK-NEXT: adds r0, #6
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
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; CHECK-NEXT: vfmat.f32 q6, q0, q7 ; CHECK-NEXT: vfmat.f32 q6, q0, q7
; CHECK-NEXT: vstrw.32 q6, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q6, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vpstt ; CHECK-NEXT: vpstt
; CHECK-NEXT: vldrwt.u32 q0, [r6] ; CHECK-NEXT: vldrwt.u32 q0, [r6]
; CHECK-NEXT: vfmat.f32 q1, q0, q7 ; CHECK-NEXT: vfmat.f32 q1, q0, q7
; CHECK-NEXT: adds r7, r6, r5 ; CHECK-NEXT: adds r7, r6, r5
; CHECK-NEXT: vmov q6, q5 ; CHECK-NEXT: vmov q6, q5
; CHECK-NEXT: vmov q5, q4 ; CHECK-NEXT: vmov q5, q4
; CHECK-NEXT: vmov q4, q2 ; CHECK-NEXT: vmov q4, q3
; CHECK-NEXT: vmov q2, q3
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vldrwt.u32 q0, [r7] ; CHECK-NEXT: vldrwt.u32 q0, [r7]
; CHECK-NEXT: vmov q3, q1 ; CHECK-NEXT: vmov q3, q1
; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: adds r6, r7, r5
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vfmat.f32 q1, q0, q7 ; CHECK-NEXT: vfmat.f32 q1, q0, q7
; CHECK-NEXT: adds r6, r7, r5
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov q1, q3 ; CHECK-NEXT: vmov q1, q3
; CHECK-NEXT: vmov q3, q2 ; CHECK-NEXT: vmov q3, q4
; CHECK-NEXT: vmov q2, q4
; CHECK-NEXT: vmov q4, q5 ; CHECK-NEXT: vmov q4, q5
; CHECK-NEXT: vmov q5, q6 ; CHECK-NEXT: vmov q5, q6
; CHECK-NEXT: vldrw.u32 q6, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q6, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: sub.w r9, r9, #4 ; CHECK-NEXT: sub.w r9, r9, #4
; CHECK-NEXT: adds r7, r6, r5 ; CHECK-NEXT: adds r7, r6, r5
; CHECK-NEXT: vpstt ; CHECK-NEXT: vpstt
; CHECK-NEXT: vldrwt.u32 q0, [r6] ; CHECK-NEXT: vldrwt.u32 q0, [r6]
; CHECK-NEXT: vfmat.f32 q3, q0, q7 ; CHECK-NEXT: vfmat.f32 q3, q0, q7
; CHECK-NEXT: adds r6, r7, r5 ; CHECK-NEXT: adds r6, r7, r5
; CHECK-NEXT: vpstttt ; CHECK-NEXT: vpstttt
; CHECK-NEXT: vldrwt.u32 q0, [r7] ; CHECK-NEXT: vldrwt.u32 q0, [r7]
; CHECK-NEXT: vfmat.f32 q4, q0, q7 ; CHECK-NEXT: vfmat.f32 q4, q0, q7
; CHECK-NEXT: vldrwt.u32 q0, [r6] ; CHECK-NEXT: vldrwt.u32 q0, [r6]
; CHECK-NEXT: vfmat.f32 q2, q0, q7 ; CHECK-NEXT: vfmat.f32 q2, q0, q7
; CHECK-NEXT: le lr, .LBB6_3 ; CHECK-NEXT: le lr, .LBB6_3
; CHECK-NEXT: @ %bb.4: @ %middle.block ; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB6_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB6_2 Depth=1
; CHECK-NEXT: vadd.f32 s0, s26, s27 ; CHECK-NEXT: vadd.f32 s0, s26, s27
; CHECK-NEXT: add.w r1, r2, r12, lsl #2 ; CHECK-NEXT: add.w r1, r2, r12, lsl #2
; CHECK-NEXT: vadd.f32 s2, s24, s25 ; CHECK-NEXT: vadd.f32 s2, s24, s25
; CHECK-NEXT: vadd.f32 s3, s20, s21
; CHECK-NEXT: vadd.f32 s1, s22, s23 ; CHECK-NEXT: vadd.f32 s1, s22, s23
; CHECK-NEXT: vadd.f32 s8, s8, s9 ; CHECK-NEXT: vadd.f32 s3, s20, s21
; CHECK-NEXT: vadd.f32 s20, s10, s11 ; CHECK-NEXT: vadd.f32 s6, s6, s7
; CHECK-NEXT: vadd.f32 s11, s14, s15
; CHECK-NEXT: vadd.f32 s12, s12, s13
; CHECK-NEXT: vadd.f32 s14, s6, s7
; CHECK-NEXT: vadd.f32 s4, s4, s5 ; CHECK-NEXT: vadd.f32 s4, s4, s5
; CHECK-NEXT: vadd.f32 s10, s18, s19 ; CHECK-NEXT: vadd.f32 s10, s10, s11
; CHECK-NEXT: vadd.f32 s9, s16, s17 ; CHECK-NEXT: vadd.f32 s8, s8, s9
; CHECK-NEXT: vadd.f32 s9, s18, s19
; CHECK-NEXT: vadd.f32 s11, s16, s17
; CHECK-NEXT: vldrw.u32 q4, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vadd.f32 s0, s2, s0 ; CHECK-NEXT: vadd.f32 s0, s2, s0
; CHECK-NEXT: vadd.f32 s6, s18, s19 ; CHECK-NEXT: vadd.f32 s5, s18, s19
; CHECK-NEXT: vadd.f32 s5, s16, s17 ; CHECK-NEXT: vadd.f32 s7, s16, s17
; CHECK-NEXT: vadd.f32 s2, s3, s1 ; CHECK-NEXT: vadd.f32 s2, s3, s1
; CHECK-NEXT: vadd.f32 s4, s4, s14 ; CHECK-NEXT: vadd.f32 s4, s4, s6
; CHECK-NEXT: vadd.f32 s12, s12, s11 ; CHECK-NEXT: vadd.f32 s14, s14, s15
; CHECK-NEXT: vadd.f32 s10, s9, s10 ; CHECK-NEXT: vadd.f32 s12, s12, s13
; CHECK-NEXT: vstr s0, [r1] ; CHECK-NEXT: vstr s0, [r1]
; CHECK-NEXT: add.w r1, r2, r0, lsl #2 ; CHECK-NEXT: add.w r1, r2, r0, lsl #2
; CHECK-NEXT: vadd.f32 s8, s8, s20 ; CHECK-NEXT: vadd.f32 s8, s8, s10
; CHECK-NEXT: vadd.f32 s6, s5, s6 ; CHECK-NEXT: vadd.f32 s6, s7, s5
; CHECK-NEXT: vstr s2, [r1] ; CHECK-NEXT: vstr s2, [r1]
; CHECK-NEXT: add.w r1, r2, r4, lsl #2 ; CHECK-NEXT: add.w r1, r2, r4, lsl #2
; CHECK-NEXT: vadd.f32 s10, s11, s9
; CHECK-NEXT: vstr s4, [r1] ; CHECK-NEXT: vstr s4, [r1]
; CHECK-NEXT: adds r1, r0, #3 ; CHECK-NEXT: adds r1, r0, #3
; CHECK-NEXT: vadd.f32 s12, s12, s14
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: vstr s6, [r1] ; CHECK-NEXT: vstr s6, [r1]
; CHECK-NEXT: adds r1, r0, #4 ; CHECK-NEXT: adds r1, r0, #4
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: vstr s12, [r1] ; CHECK-NEXT: vstr s12, [r1]
; CHECK-NEXT: adds r1, r0, #5 ; CHECK-NEXT: adds r1, r0, #5
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: vstr s10, [r1] ; CHECK-NEXT: vstr s10, [r1]
▲ Show 20 Lines • Show All 244 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vldrwt.u32 q1, [r6] ; CHECK-NEXT: vldrwt.u32 q1, [r6]
; CHECK-NEXT: vfmat.f32 q3, q1, q0 ; CHECK-NEXT: vfmat.f32 q3, q1, q0
; CHECK-NEXT: le lr, .LBB7_3 ; CHECK-NEXT: le lr, .LBB7_3
; CHECK-NEXT: @ %bb.4: @ %middle.block ; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: @ in Loop: Header=BB7_2 Depth=1 ; CHECK-NEXT: @ in Loop: Header=BB7_2 Depth=1
; CHECK-NEXT: vadd.f32 s0, s30, s31 ; CHECK-NEXT: vadd.f32 s0, s30, s31
; CHECK-NEXT: add.w r1, r2, r8, lsl #2 ; CHECK-NEXT: add.w r1, r2, r8, lsl #2
; CHECK-NEXT: vadd.f32 s2, s28, s29 ; CHECK-NEXT: vadd.f32 s2, s28, s29
; CHECK-NEXT: vadd.f32 s12, s12, s13
; CHECK-NEXT: vadd.f32 s5, s14, s15
; CHECK-NEXT: vadd.f32 s4, s26, s27 ; CHECK-NEXT: vadd.f32 s4, s26, s27
; CHECK-NEXT: vadd.f32 s6, s24, s25 ; CHECK-NEXT: vadd.f32 s6, s24, s25
; CHECK-NEXT: vadd.f32 s14, s18, s19 ; CHECK-NEXT: vadd.f32 s5, s18, s19
; CHECK-NEXT: vadd.f32 s7, s16, s17 ; CHECK-NEXT: vadd.f32 s7, s16, s17
; CHECK-NEXT: vldrw.u32 q4, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vadd.f32 s10, s10, s11
; CHECK-NEXT: vadd.f32 s8, s8, s9 ; CHECK-NEXT: vadd.f32 s8, s8, s9
; CHECK-NEXT: vadd.f32 s13, s10, s11 ; CHECK-NEXT: vadd.f32 s9, s18, s19
; CHECK-NEXT: vadd.f32 s10, s18, s19 ; CHECK-NEXT: vadd.f32 s11, s16, s17
; CHECK-NEXT: vadd.f32 s9, s16, s17
; CHECK-NEXT: vldrw.u32 q4, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vadd.f32 s0, s2, s0 ; CHECK-NEXT: vadd.f32 s14, s14, s15
; CHECK-NEXT: vadd.f32 s11, s18, s19 ; CHECK-NEXT: vadd.f32 s12, s12, s13
; CHECK-NEXT: vadd.f32 s13, s18, s19
; CHECK-NEXT: vadd.f32 s15, s16, s17 ; CHECK-NEXT: vadd.f32 s15, s16, s17
; CHECK-NEXT: vadd.f32 s0, s2, s0
; CHECK-NEXT: vadd.f32 s2, s6, s4 ; CHECK-NEXT: vadd.f32 s2, s6, s4
; CHECK-NEXT: vadd.f32 s6, s12, s5 ; CHECK-NEXT: vadd.f32 s8, s8, s10
; CHECK-NEXT: vadd.f32 s12, s7, s14 ; CHECK-NEXT: vadd.f32 s10, s11, s9
; CHECK-NEXT: vadd.f32 s10, s9, s10 ; CHECK-NEXT: vadd.f32 s6, s12, s14
; CHECK-NEXT: vadd.f32 s1, s22, s23
; CHECK-NEXT: vadd.f32 s14, s15, s13
; CHECK-NEXT: vstr s0, [r1] ; CHECK-NEXT: vstr s0, [r1]
; CHECK-NEXT: add.w r1, r2, r0, lsl #2 ; CHECK-NEXT: add.w r1, r2, r0, lsl #2
; CHECK-NEXT: vadd.f32 s8, s8, s13 ; CHECK-NEXT: vadd.f32 s3, s20, s21
; CHECK-NEXT: vadd.f32 s14, s15, s11
; CHECK-NEXT: vstr s2, [r1] ; CHECK-NEXT: vstr s2, [r1]
; CHECK-NEXT: add.w r1, r2, r12, lsl #2 ; CHECK-NEXT: add.w r1, r2, r12, lsl #2
; CHECK-NEXT: vadd.f32 s1, s22, s23 ; CHECK-NEXT: vadd.f32 s12, s7, s5
; CHECK-NEXT: vadd.f32 s3, s20, s21
; CHECK-NEXT: vstr s10, [r1] ; CHECK-NEXT: vstr s10, [r1]
; CHECK-NEXT: add.w r1, r2, r4, lsl #2 ; CHECK-NEXT: add.w r1, r2, r4, lsl #2
; CHECK-NEXT: vstr s14, [r1] ; CHECK-NEXT: vstr s14, [r1]
; CHECK-NEXT: adds r1, r0, #4 ; CHECK-NEXT: adds r1, r0, #4
; CHECK-NEXT: add.w r1, r2, r1, lsl #2 ; CHECK-NEXT: add.w r1, r2, r1, lsl #2
; CHECK-NEXT: vadd.f32 s4, s3, s1 ; CHECK-NEXT: vadd.f32 s4, s3, s1
; CHECK-NEXT: vstr s8, [r1] ; CHECK-NEXT: vstr s8, [r1]
; CHECK-NEXT: adds r1, r0, #5 ; CHECK-NEXT: adds r1, r0, #5
▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Linesentry:
ret <16 x i8> %r ret <16 x i8> %r
} }
define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_var0_v2i1: ; CHECK-LABEL: build_var0_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: vldr s10, .LCPI9_0
; CHECK-NEXT: csetm r0, lo ; CHECK-NEXT: csetm r0, lo
; CHECK-NEXT: vmov s8, r0 ; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vldr s10, .LCPI9_0
; CHECK-NEXT: vmov.f32 s9, s8
; CHECK-NEXT: vmov.f32 s11, s10 ; CHECK-NEXT: vmov.f32 s11, s10
; CHECK-NEXT: vmov.f32 s9, s8
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI9_0: ; CHECK-NEXT: .LCPI9_0:
; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .long 0x00000000 @ float 0
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0 %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0
%r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %r ret <2 x i64> %r
} }
define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_var1_v2i1: ; CHECK-LABEL: build_var1_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: vldr s8, .LCPI10_0
; CHECK-NEXT: csetm r0, lo ; CHECK-NEXT: csetm r0, lo
; CHECK-NEXT: vmov s10, r0 ; CHECK-NEXT: vmov s10, r0
; CHECK-NEXT: vldr s8, .LCPI10_0
; CHECK-NEXT: vmov.f32 s9, s8 ; CHECK-NEXT: vmov.f32 s9, s8
; CHECK-NEXT: vmov.f32 s11, s10 ; CHECK-NEXT: vmov.f32 s11, s10
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
Show All 26 Lines

llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Linesentry:
%sh = shufflevector <16 x i1> %c, <16 x i1> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %sh = shufflevector <16 x i1> %c, <16 x i1> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%s = select <16 x i1> %sh, <16 x i8> %a, <16 x i8> %b %s = select <16 x i1> %sh, <16 x i8> %a, <16 x i8> %b
ret <16 x i8> %s ret <16 x i8> %s
} }
define <4 x i32> @shuffle2_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { define <4 x i32> @shuffle2_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: shuffle2_v4i32: ; CHECK-LABEL: shuffle2_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vmov d0, r0, r1 ; CHECK-NEXT: vmov d0, r0, r1
; CHECK-NEXT: add r0, sp, #16 ; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vcmp.i32 eq, q0, zr ; CHECK-NEXT: vcmp.i32 eq, q0, zr
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: mov r0, sp ; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vpsel q0, q1, q0 ; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <4 x i32> %src, zeroinitializer %c = icmp eq <4 x i32> %src, zeroinitializer
%sh = shufflevector <4 x i1> %c, <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %sh = shufflevector <4 x i1> %c, <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%s = select <4 x i1> %sh, <4 x i32> %a, <4 x i32> %b %s = select <4 x i1> %sh, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %s ret <4 x i32> %s
} }
define <8 x i16> @shuffle2_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) { define <8 x i16> @shuffle2_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: shuffle2_v8i16: ; CHECK-LABEL: shuffle2_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vmov d0, r0, r1 ; CHECK-NEXT: vmov d0, r0, r1
; CHECK-NEXT: add r0, sp, #16 ; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vcmp.i16 eq, q0, zr ; CHECK-NEXT: vcmp.i16 eq, q0, zr
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: mov r0, sp ; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vpsel q0, q1, q0 ; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <8 x i16> %src, zeroinitializer %c = icmp eq <8 x i16> %src, zeroinitializer
%sh = shufflevector <8 x i1> %c, <8 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %sh = shufflevector <8 x i1> %c, <8 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%s = select <8 x i1> %sh, <8 x i16> %a, <8 x i16> %b %s = select <8 x i1> %sh, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %s ret <8 x i16> %s
} }
define <16 x i8> @shuffle2_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) { define <16 x i8> @shuffle2_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: shuffle2_v16i8: ; CHECK-LABEL: shuffle2_v16i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vmov d0, r0, r1 ; CHECK-NEXT: vmov d0, r0, r1
; CHECK-NEXT: add r0, sp, #16 ; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vcmp.i8 eq, q0, zr ; CHECK-NEXT: vcmp.i8 eq, q0, zr
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: mov r0, sp ; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vpsel q0, q1, q0 ; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Linesentry:
%sh = shufflevector <16 x i1> %c, <16 x i1> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> %sh = shufflevector <16 x i1> %c, <16 x i1> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%s = select <16 x i1> %sh, <16 x i8> %a, <16 x i8> %b %s = select <16 x i1> %sh, <16 x i8> %a, <16 x i8> %b
ret <16 x i8> %s ret <16 x i8> %s
} }
define <4 x i32> @shuffle4_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) { define <4 x i32> @shuffle4_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: shuffle4_v4i32: ; CHECK-LABEL: shuffle4_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vmov.i8 q1, #0xff
; CHECK-NEXT: vmov d0, r0, r1 ; CHECK-NEXT: vmov d0, r0, r1
; CHECK-NEXT: vmov.i8 q1, #0xff
; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: add r0, sp, #16 ; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vcmp.i32 eq, q0, zr ; CHECK-NEXT: vcmp.i32 eq, q0, zr
; CHECK-NEXT: vmov.i8 q0, #0x0 ; CHECK-NEXT: vmov.i8 q0, #0x0
; CHECK-NEXT: vpsel q0, q1, q0 ; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov.f32 s4, s0 ; CHECK-NEXT: vmov.f32 s4, s0
; CHECK-NEXT: vmov.f32 s5, s0 ; CHECK-NEXT: vmov.f32 s5, s0
; CHECK-NEXT: vmov.f32 s6, s0 ; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s7, s1 ; CHECK-NEXT: vmov.f32 s7, s1
▲ Show 20 Lines • Show All 319 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

Show First 20 Lines • Show All 247 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .LBB1_4: @ %vector.body ; CHECK-NEXT: .LBB1_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q3, [r1], #16 ; CHECK-NEXT: vldrw.u32 q3, [r1], #16
; CHECK-NEXT: vldrw.u32 q2, [r0], #16 ; CHECK-NEXT: vldrw.u32 q2, [r0], #16
; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov.w r2, #-1 ; CHECK-NEXT: mov.w r2, #-1
; CHECK-NEXT: vmov.f32 s16, s10 ; CHECK-NEXT: vmov.f32 s16, s10
; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vmov.f32 s18, s11 ; CHECK-NEXT: vmov.f32 s18, s11
; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vmov.f32 s22, s15 ; CHECK-NEXT: vmov.f32 s22, s15
; CHECK-NEXT: vmullb.s32 q6, q5, q4 ; CHECK-NEXT: vmullb.s32 q6, q5, q4
; CHECK-NEXT: vmov.f32 s14, s13 ; CHECK-NEXT: vmov.f32 s10, s9
; CHECK-NEXT: vmov r4, r7, d13 ; CHECK-NEXT: vmov r4, r7, d13
; CHECK-NEXT: asrl r4, r7, #31 ; CHECK-NEXT: asrl r4, r7, #31
; CHECK-NEXT: vmov.f32 s10, s9
; CHECK-NEXT: rsbs.w r5, r4, #-2147483648
; CHECK-NEXT: vmov r6, s12 ; CHECK-NEXT: vmov r6, s12
; CHECK-NEXT: rsbs.w r5, r4, #-2147483648
; CHECK-NEXT: sbcs.w r5, r2, r7 ; CHECK-NEXT: sbcs.w r5, r2, r7
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: mov.w r5, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r5, #1 ; CHECK-NEXT: movlt r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: vmov r10, r5, d12 ; CHECK-NEXT: vmov r10, r5, d12
; CHECK-NEXT: csetm r8, ne ; CHECK-NEXT: csetm r8, ne
; CHECK-NEXT: asrl r10, r5, #31 ; CHECK-NEXT: asrl r10, r5, #31
Show All 27 Lines
; CHECK-NEXT: vmov r5, s8 ; CHECK-NEXT: vmov r5, s8
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: mov.w r4, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csetm r4, ne ; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: vmov q5[2], q5[0], r3, r4 ; CHECK-NEXT: vmov q5[2], q5[0], r3, r4
; CHECK-NEXT: vmov r3, s10 ; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: vmov r4, s14 ; CHECK-NEXT: vmov.f32 s10, s13
; CHECK-NEXT: vbic q6, q1, q5 ; CHECK-NEXT: vbic q6, q1, q5
; CHECK-NEXT: vand q4, q4, q5 ; CHECK-NEXT: vand q4, q4, q5
; CHECK-NEXT: vorr q4, q4, q6 ; CHECK-NEXT: vorr q4, q4, q6
; CHECK-NEXT: vmov r4, s10
; CHECK-NEXT: smull r6, r5, r6, r5 ; CHECK-NEXT: smull r6, r5, r6, r5
; CHECK-NEXT: asrl r6, r5, #31 ; CHECK-NEXT: asrl r6, r5, #31
; CHECK-NEXT: smull r4, r7, r4, r3 ; CHECK-NEXT: smull r4, r7, r4, r3
; CHECK-NEXT: asrl r4, r7, #31 ; CHECK-NEXT: asrl r4, r7, #31
; CHECK-NEXT: rsbs.w r3, r4, #-2147483648 ; CHECK-NEXT: rsbs.w r3, r4, #-2147483648
; CHECK-NEXT: vmov q5[2], q5[0], r6, r4 ; CHECK-NEXT: vmov q5[2], q5[0], r6, r4
; CHECK-NEXT: sbcs.w r3, r2, r7 ; CHECK-NEXT: sbcs.w r3, r2, r7
; CHECK-NEXT: vmov q5[3], q5[1], r5, r7 ; CHECK-NEXT: vmov q5[3], q5[1], r5, r7
▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .LBB2_2: @ %vector.body ; CHECK-NEXT: .LBB2_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vdup.32 q4, r9 ; CHECK-NEXT: vdup.32 q4, r9
; CHECK-NEXT: add.w r9, r9, #4 ; CHECK-NEXT: add.w r9, r9, #4
; CHECK-NEXT: vorr q4, q4, q0 ; CHECK-NEXT: vorr q4, q4, q0
; CHECK-NEXT: vpt.u32 cs, q1, q4 ; CHECK-NEXT: vpt.u32 cs, q1, q4
; CHECK-NEXT: vldrwt.u32 q4, [r0], #16 ; CHECK-NEXT: vldrwt.u32 q4, [r0], #16
; CHECK-NEXT: vmov.f32 s24, s18
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vldrwt.u32 q5, [r1], #16 ; CHECK-NEXT: vldrwt.u32 q5, [r1], #16
; CHECK-NEXT: vmov.f32 s28, s22 ; CHECK-NEXT: vmov.f32 s24, s18
; CHECK-NEXT: vmov.f32 s26, s19 ; CHECK-NEXT: vmov.f32 s26, s19
; CHECK-NEXT: vmov.f32 s28, s22
; CHECK-NEXT: vmov.f32 s30, s23 ; CHECK-NEXT: vmov.f32 s30, s23
; CHECK-NEXT: vmullb.s32 q0, q7, q6 ; CHECK-NEXT: vmullb.s32 q0, q7, q6
; CHECK-NEXT: vmov.f32 s18, s17
; CHECK-NEXT: vmov r6, r5, d1 ; CHECK-NEXT: vmov r6, r5, d1
; CHECK-NEXT: asrl r6, r5, #31 ; CHECK-NEXT: asrl r6, r5, #31
; CHECK-NEXT: vmov.f32 s22, s21
; CHECK-NEXT: rsbs.w r7, r6, #-2147483648 ; CHECK-NEXT: rsbs.w r7, r6, #-2147483648
; CHECK-NEXT: sbcs.w r7, r12, r5 ; CHECK-NEXT: sbcs.w r7, r12, r5
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: vmov r4, r7, d0 ; CHECK-NEXT: vmov r4, r7, d0
; CHECK-NEXT: csetm r10, ne ; CHECK-NEXT: csetm r10, ne
Show All 26 Lines
; CHECK-NEXT: subs.w r4, r4, r8 ; CHECK-NEXT: subs.w r4, r4, r8
; CHECK-NEXT: sbcs r4, r5, #0 ; CHECK-NEXT: sbcs r4, r5, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: mov.w r4, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csetm r4, ne ; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: vmov q0[2], q0[0], r3, r4 ; CHECK-NEXT: vmov q0[2], q0[0], r3, r4
; CHECK-NEXT: vmov r3, s18
; CHECK-NEXT: vmov r4, s22
; CHECK-NEXT: vbic q7, q3, q0 ; CHECK-NEXT: vbic q7, q3, q0
; CHECK-NEXT: vand q0, q6, q0 ; CHECK-NEXT: vand q0, q6, q0
; CHECK-NEXT: vorr q6, q0, q7 ; CHECK-NEXT: vorr q6, q0, q7
; CHECK-NEXT: vmov.f32 s2, s17
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov.f32 s2, s21
; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: smull r6, r5, r4, r3 ; CHECK-NEXT: smull r6, r5, r4, r3
; CHECK-NEXT: vmov r4, s16 ; CHECK-NEXT: vmov r4, s16
; CHECK-NEXT: asrl r6, r5, #31 ; CHECK-NEXT: asrl r6, r5, #31
; CHECK-NEXT: rsbs.w r3, r6, #-2147483648 ; CHECK-NEXT: rsbs.w r3, r6, #-2147483648
; CHECK-NEXT: sbcs.w r3, r12, r5 ; CHECK-NEXT: sbcs.w r3, r12, r5
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: mov.w r3, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: movlt r3, #1
▲ Show 20 Lines • Show All 2,727 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-scatter-ind16-scaled.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Expand - sext offset ; Expand - sext offset
define arm_aapcs_vfpcc void @scaled_v8f16_sext(i16* %base, <8 x i16>* %offptr, <8 x half> %input) { define arm_aapcs_vfpcc void @scaled_v8f16_sext(i16* %base, <8 x i16>* %offptr, <8 x half> %input) {
; CHECK-LABEL: scaled_v8f16_sext: ; CHECK-LABEL: scaled_v8f16_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q1, [r1] ; CHECK-NEXT: vldrh.s32 q1, [r1]
; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vshl.i32 q2, q1, #1 ; CHECK-NEXT: vshl.i32 q2, q1, #1
; CHECK-NEXT: vldrh.s32 q1, [r1, #8] ; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
; CHECK-NEXT: vadd.i32 q2, q2, r0 ; CHECK-NEXT: vadd.i32 q2, q2, r0
; CHECK-NEXT: vshl.i32 q1, q1, #1
; CHECK-NEXT: vmov r1, r2, d4 ; CHECK-NEXT: vmov r1, r2, d4
; CHECK-NEXT: vshl.i32 q1, q1, #1
; CHECK-NEXT: vstr.16 s0, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vstr.16 s12, [r2] ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r2]
; CHECK-NEXT: vmov r1, r2, d5 ; CHECK-NEXT: vmov r1, r2, d5
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vadd.i32 q1, q1, r0 ; CHECK-NEXT: vadd.i32 q1, q1, r0
; CHECK-NEXT: vstr.16 s1, [r1] ; CHECK-NEXT: vstr.16 s1, [r1]
; CHECK-NEXT: vstr.16 s8, [r2] ; CHECK-NEXT: vstr.16 s0, [r2]
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vstr.16 s2, [r0] ; CHECK-NEXT: vstr.16 s2, [r0]
; CHECK-NEXT: vstr.16 s8, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vmovx.f16 s0, s3 ; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vstr.16 s3, [r0] ; CHECK-NEXT: vstr.16 s3, [r0]
; CHECK-NEXT: vstr.16 s0, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <8 x i16>, <8 x i16>* %offptr, align 2 %offs = load <8 x i16>, <8 x i16>* %offptr, align 2
%offs.sext = sext <8 x i16> %offs to <8 x i32> %offs.sext = sext <8 x i16> %offs to <8 x i32>
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llvm/test/CodeGen/Thumb2/mve-scatter-ind16-unscaled.ll

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
} }
; Expand - sext offsets ; Expand - sext offsets
define arm_aapcs_vfpcc void @unscaled_v8f16_sext(i8* %base, <8 x i16>* %offptr, <8 x half> %input) { define arm_aapcs_vfpcc void @unscaled_v8f16_sext(i8* %base, <8 x i16>* %offptr, <8 x half> %input) {
; CHECK-LABEL: unscaled_v8f16_sext: ; CHECK-LABEL: unscaled_v8f16_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q2, [r1] ; CHECK-NEXT: vldrh.s32 q2, [r1]
; CHECK-NEXT: vldrh.s32 q1, [r1, #8] ; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vadd.i32 q2, q2, r0 ; CHECK-NEXT: vadd.i32 q2, q2, r0
; CHECK-NEXT: vadd.i32 q1, q1, r0 ; CHECK-NEXT: vadd.i32 q1, q1, r0
; CHECK-NEXT: vmov r1, r2, d4 ; CHECK-NEXT: vmov r1, r2, d4
; CHECK-NEXT: vstr.16 s0, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vstr.16 s12, [r2] ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r2]
; CHECK-NEXT: vmov r1, r2, d5 ; CHECK-NEXT: vmov r1, r2, d5
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vstr.16 s1, [r1] ; CHECK-NEXT: vstr.16 s1, [r1]
; CHECK-NEXT: vstr.16 s8, [r2] ; CHECK-NEXT: vstr.16 s0, [r2]
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vstr.16 s2, [r0] ; CHECK-NEXT: vstr.16 s2, [r0]
; CHECK-NEXT: vstr.16 s8, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vmovx.f16 s0, s3 ; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vstr.16 s3, [r0] ; CHECK-NEXT: vstr.16 s3, [r0]
; CHECK-NEXT: vstr.16 s0, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <8 x i16>, <8 x i16>* %offptr, align 2 %offs = load <8 x i16>, <8 x i16>* %offptr, align 2
%offs.sext = sext <8 x i16> %offs to <8 x i32> %offs.sext = sext <8 x i16> %offs to <8 x i32>
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} }
; Expand - i32 offsets ; Expand - i32 offsets
define arm_aapcs_vfpcc void @unscaled_v8f16_noext(i8* %base, <8 x i32>* %offptr, <8 x half> %input) { define arm_aapcs_vfpcc void @unscaled_v8f16_noext(i8* %base, <8 x i32>* %offptr, <8 x half> %input) {
; CHECK-LABEL: unscaled_v8f16_noext: ; CHECK-LABEL: unscaled_v8f16_noext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q2, [r1] ; CHECK-NEXT: vldrw.u32 q2, [r1]
; CHECK-NEXT: vldrw.u32 q1, [r1, #16] ; CHECK-NEXT: vldrw.u32 q1, [r1, #16]
; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vadd.i32 q2, q2, r0 ; CHECK-NEXT: vadd.i32 q2, q2, r0
; CHECK-NEXT: vadd.i32 q1, q1, r0 ; CHECK-NEXT: vadd.i32 q1, q1, r0
; CHECK-NEXT: vmov r1, r2, d4 ; CHECK-NEXT: vmov r1, r2, d4
; CHECK-NEXT: vstr.16 s0, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vstr.16 s12, [r2] ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r2]
; CHECK-NEXT: vmov r1, r2, d5 ; CHECK-NEXT: vmov r1, r2, d5
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vstr.16 s1, [r1] ; CHECK-NEXT: vstr.16 s1, [r1]
; CHECK-NEXT: vstr.16 s8, [r2] ; CHECK-NEXT: vstr.16 s0, [r2]
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vstr.16 s2, [r0] ; CHECK-NEXT: vstr.16 s2, [r0]
; CHECK-NEXT: vstr.16 s8, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vmovx.f16 s0, s3 ; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vstr.16 s3, [r0] ; CHECK-NEXT: vstr.16 s3, [r0]
; CHECK-NEXT: vstr.16 s0, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <8 x i32>, <8 x i32>* %offptr, align 4 %offs = load <8 x i32>, <8 x i32>* %offptr, align 4
%byte_ptrs = getelementptr inbounds i8, i8* %base, <8 x i32> %offs %byte_ptrs = getelementptr inbounds i8, i8* %base, <8 x i32> %offs
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llvm/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll

Show First 20 Lines • Show All 285 Lines • ▼ Show 20 Linesentry:
%t = trunc <4 x i32> %input to <4 x i8> %t = trunc <4 x i32> %input to <4 x i8>
call void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8> %t, <4 x i8*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>) call void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8> %t, <4 x i8*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
ret void ret void
} }
define arm_aapcs_vfpcc void @trunc_signed_unscaled_i64_i8(i8* %base, <4 x i8>* %offptr, <4 x i64> %input) { define arm_aapcs_vfpcc void @trunc_signed_unscaled_i64_i8(i8* %base, <4 x i8>* %offptr, <4 x i64> %input) {
; CHECK-LABEL: trunc_signed_unscaled_i64_i8: ; CHECK-LABEL: trunc_signed_unscaled_i64_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vldrb.s32 q2, [r1] ; CHECK-NEXT: vldrb.s32 q2, [r1]
; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vstrw.32 q0, [r0, q2] ; CHECK-NEXT: vstrw.32 q0, [r0, q2]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1 %offs = load <4 x i8>, <4 x i8>* %offptr, align 1
%offs.sext = sext <4 x i8> %offs to <4 x i32> %offs.sext = sext <4 x i8> %offs to <4 x i32>
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext %byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.sext
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*> %ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
%input.trunc = trunc <4 x i64> %input to <4 x i32> %input.trunc = trunc <4 x i64> %input to <4 x i32>
call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %input.trunc, <4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>) call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %input.trunc, <4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
ret void ret void
} }
define arm_aapcs_vfpcc void @trunc_unsigned_unscaled_i64_i8(i8* %base, <4 x i8>* %offptr, <4 x i64> %input) { define arm_aapcs_vfpcc void @trunc_unsigned_unscaled_i64_i8(i8* %base, <4 x i8>* %offptr, <4 x i64> %input) {
; CHECK-LABEL: trunc_unsigned_unscaled_i64_i8: ; CHECK-LABEL: trunc_unsigned_unscaled_i64_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vldrb.u32 q2, [r1] ; CHECK-NEXT: vldrb.u32 q2, [r1]
; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vstrw.32 q0, [r0, q2] ; CHECK-NEXT: vstrw.32 q0, [r0, q2]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1 %offs = load <4 x i8>, <4 x i8>* %offptr, align 1
%offs.zext = zext <4 x i8> %offs to <4 x i32> %offs.zext = zext <4 x i8> %offs to <4 x i32>
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext %byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
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llvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll

Show First 20 Lines • Show All 306 Lines • ▼ Show 20 Lines
; f16 ; f16
; Expand. ; Expand.
define arm_aapcs_vfpcc void @ptr_f16(<8 x half> %v, <8 x half*>* %offptr) { define arm_aapcs_vfpcc void @ptr_f16(<8 x half> %v, <8 x half*>* %offptr) {
; CHECK-LABEL: ptr_f16: ; CHECK-LABEL: ptr_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vmov r0, r1, d4 ; CHECK-NEXT: vmov r0, r1, d4
; CHECK-NEXT: vstr.16 s0, [r0] ; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: vstr.16 s12, [r1] ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vmov r0, r1, d5 ; CHECK-NEXT: vmov r0, r1, d5
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vstr.16 s1, [r0] ; CHECK-NEXT: vstr.16 s1, [r0]
; CHECK-NEXT: vstr.16 s8, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vstr.16 s2, [r0] ; CHECK-NEXT: vstr.16 s2, [r0]
; CHECK-NEXT: vstr.16 s8, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vmovx.f16 s0, s3 ; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vstr.16 s3, [r0] ; CHECK-NEXT: vstr.16 s3, [r0]
; CHECK-NEXT: vstr.16 s0, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <8 x half*>, <8 x half*>* %offptr, align 4 %offs = load <8 x half*>, <8 x half*>* %offptr, align 4
call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %v, <8 x half*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>) call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %v, <8 x half*> %offs, i32 2, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
ret void ret void
} }
define arm_aapcs_vfpcc void @ptr_v4f16(<4 x half> %v, <4 x half*>* %offptr) { define arm_aapcs_vfpcc void @ptr_v4f16(<4 x half> %v, <4 x half*>* %offptr) {
; CHECK-LABEL: ptr_v4f16: ; CHECK-LABEL: ptr_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: vstr.16 s0, [r0] ; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: vstr.16 s8, [r1] ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: vmovx.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vstr.16 s1, [r0] ; CHECK-NEXT: vstr.16 s1, [r0]
; CHECK-NEXT: vstr.16 s0, [r1] ; CHECK-NEXT: vstr.16 s0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%offs = load <4 x half*>, <4 x half*>* %offptr, align 4 %offs = load <4 x half*>, <4 x half*>* %offptr, align 4
call void @llvm.masked.scatter.v4f16.v4p0f16(<4 x half> %v, <4 x half*> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>) call void @llvm.masked.scatter.v4f16.v4p0f16(<4 x half> %v, <4 x half*> %offs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
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llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <4 x double> @foo_v4i32(<4 x i32>* nocapture readonly %pSrc, i32 %blockSize, <4 x i32> %a) { define arm_aapcs_vfpcc <4 x double> @foo_v4i32(<4 x i32>* nocapture readonly %pSrc, i32 %blockSize, <4 x i32> %a) {
; CHECK-LABEL: foo_v4i32: ; CHECK-LABEL: foo_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vpt.s32 lt, q0, zr ; CHECK-NEXT: vpt.s32 lt, q0, zr
; CHECK-NEXT: vldrwt.u32 q5, [r0] ; CHECK-NEXT: vldrwt.u32 q5, [r0]
; CHECK-NEXT: vmov.f64 d8, d10 ; CHECK-NEXT: vmov.f32 s2, s21
; CHECK-NEXT: vmov.f32 s18, s21 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: asrs r1, r0, #31 ; CHECK-NEXT: asrs r1, r0, #31
; CHECK-NEXT: bl __aeabi_l2d ; CHECK-NEXT: bl __aeabi_l2d
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmov d9, r0, r1 ; CHECK-NEXT: vmov d9, r0, r1
; CHECK-NEXT: asrs r3, r2, #31 ; CHECK-NEXT: asrs r3, r2, #31
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r3 ; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: bl __aeabi_l2d ; CHECK-NEXT: bl __aeabi_l2d
; CHECK-NEXT: vmov.f64 d12, d11 ; CHECK-NEXT: vmov.f32 s2, s23
; CHECK-NEXT: vmov.f32 s26, s23
; CHECK-NEXT: vmov d8, r0, r1 ; CHECK-NEXT: vmov d8, r0, r1
; CHECK-NEXT: vmov r2, s26 ; CHECK-NEXT: vmov.f32 s20, s22
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: asrs r3, r2, #31 ; CHECK-NEXT: asrs r3, r2, #31
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r3 ; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: bl __aeabi_l2d ; CHECK-NEXT: bl __aeabi_l2d
; CHECK-NEXT: vmov r2, s24 ; CHECK-NEXT: vmov r2, s20
; CHECK-NEXT: vmov d11, r0, r1 ; CHECK-NEXT: vmov d11, r0, r1
; CHECK-NEXT: asrs r3, r2, #31 ; CHECK-NEXT: asrs r3, r2, #31
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r3 ; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: bl __aeabi_l2d ; CHECK-NEXT: bl __aeabi_l2d
; CHECK-NEXT: vmov d10, r0, r1 ; CHECK-NEXT: vmov d10, r0, r1
; CHECK-NEXT: vmov q0, q4 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vmov q1, q5 ; CHECK-NEXT: vmov q1, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%active.lane.mask = icmp slt <4 x i32> %a, zeroinitializer %active.lane.mask = icmp slt <4 x i32> %a, zeroinitializer
%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %pSrc, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef) %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %pSrc, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
%0 = sitofp <4 x i32> %wide.masked.load to <4 x double> %0 = sitofp <4 x i32> %wide.masked.load to <4 x double>
ret <4 x double> %0 ret <4 x double> %0
} }
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>) declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>) declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>)
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)

llvm/test/CodeGen/Thumb2/mve-shuffle.ll

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <4 x i32> @shuffle2step_i32(<8 x i32> %src) { define arm_aapcs_vfpcc <4 x i32> @shuffle2step_i32(<8 x i32> %src) {
; CHECK-LABEL: shuffle2step_i32: ; CHECK-LABEL: shuffle2step_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f32 s9, s3 ; CHECK-NEXT: vmov.f32 s9, s3
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s10, s5 ; CHECK-NEXT: vmov.f32 s10, s5
; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s11, s7 ; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vadd.i32 q0, q0, q2 ; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %s1 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s2 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %s2 = shufflevector <8 x i32> %src, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%r = add <4 x i32> %s1, %s2 %r = add <4 x i32> %s1, %s2
ret <4 x i32> %r ret <4 x i32> %r
} }
define arm_aapcs_vfpcc <4 x i32> @shuffle3step_i32(<16 x i32> %src) { define arm_aapcs_vfpcc <4 x i32> @shuffle3step_i32(<16 x i32> %src) {
; CHECK-LABEL: shuffle3step_i32: ; CHECK-LABEL: shuffle3step_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vmov.f32 s16, s0
; CHECK-NEXT: vmov.f32 s13, s4 ; CHECK-NEXT: vmov.f32 s13, s4
; CHECK-NEXT: vmov.f32 s17, s3
; CHECK-NEXT: vmov.f32 s14, s7 ; CHECK-NEXT: vmov.f32 s14, s7
; CHECK-NEXT: vmov.f32 s18, s6 ; CHECK-NEXT: vmov.f32 s18, s6
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vmov.f32 s15, s10 ; CHECK-NEXT: vmov.f32 s15, s10
; CHECK-NEXT: vmov.f32 s16, s0
; CHECK-NEXT: vmov.f32 s17, s3
; CHECK-NEXT: vmov.f32 s19, s9 ; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vadd.i32 q3, q4, q3 ; CHECK-NEXT: vadd.i32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vmov.f32 s7, s11 ; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vadd.i32 q0, q3, q1 ; CHECK-NEXT: vadd.i32 q0, q3, q1
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a = add <4 x i32> %s1, %s2 %a = add <4 x i32> %s1, %s2
%r = add <4 x i32> %a, %s3 %r = add <4 x i32> %a, %s3
ret <4 x i32> %r ret <4 x i32> %r
} }
define arm_aapcs_vfpcc <4 x i32> @shuffle4step_i32(<16 x i32> %src) { define arm_aapcs_vfpcc <4 x i32> @shuffle4step_i32(<16 x i32> %src) {
; CHECK-LABEL: shuffle4step_i32: ; CHECK-LABEL: shuffle4step_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov.f32 s16, s3 ; CHECK-NEXT: vmov.f32 s16, s3
; CHECK-NEXT: vmov.f32 s20, s2 ; CHECK-NEXT: vmov.f32 s20, s2
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov.f32 s21, s6
; CHECK-NEXT: vmov.f32 s18, s11 ; CHECK-NEXT: vmov.f32 s18, s11
; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vmov.f32 s19, s15 ; CHECK-NEXT: vmov.f32 s19, s15
; CHECK-NEXT: vmov.f32 s21, s6
; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vmov.f32 s23, s14 ; CHECK-NEXT: vmov.f32 s23, s14
; CHECK-NEXT: vadd.i32 q4, q5, q4 ; CHECK-NEXT: vadd.i32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s20, s1 ; CHECK-NEXT: vmov.f32 s20, s1
; CHECK-NEXT: vmov.f32 s21, s5 ; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.f32 s22, s9 ; CHECK-NEXT: vmov.f32 s22, s9
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s23, s13 ; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s12 ; CHECK-NEXT: vmov.f32 s3, s12
; CHECK-NEXT: vadd.i32 q0, q0, q5 ; CHECK-NEXT: vadd.i32 q0, q0, q5
; CHECK-NEXT: vadd.i32 q0, q0, q4 ; CHECK-NEXT: vadd.i32 q0, q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %s2 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %s3 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%s4 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %s4 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
%a1 = add <4 x i32> %s1, %s2 %a1 = add <4 x i32> %s1, %s2
%a2 = add <4 x i32> %s3, %s4 %a2 = add <4 x i32> %s3, %s4
%r = add <4 x i32> %a1, %a2 %r = add <4 x i32> %a1, %a2
ret <4 x i32> %r ret <4 x i32> %r
} }
; i16 ; i16
define arm_aapcs_vfpcc <8 x i16> @shuffle1_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle1_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle1_i16: ; CHECK-LABEL: shuffle1_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s0, s7 ; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vmovx.f16 s1, s6 ; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vmovx.f16 s3, s4 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle2_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle2_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle2_i16: ; CHECK-LABEL: shuffle2_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle3_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle3_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle3_i16: ; CHECK-LABEL: shuffle3_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s1, s7
; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vins.f16 s1, s7
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vins.f16 s5, s4 ; CHECK-NEXT: vins.f16 s5, s4
; CHECK-NEXT: vins.f16 s2, s8 ; CHECK-NEXT: vins.f16 s2, s0
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmovx.f16 s1, s7
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vins.f16 s1, s7
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0> %out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle5_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle5_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle5_i16: ; CHECK-LABEL: shuffle5_i16:
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 undef, i32 undef, i32 12, i32 3, i32 14, i32 15> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 undef, i32 undef, i32 12, i32 3, i32 14, i32 15>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle2step_i16(<16 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle2step_i16(<16 x i16> %src) {
; CHECK-LABEL: shuffle2step_i16: ; CHECK-LABEL: shuffle2step_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmovx.f16 s9, s2 ; CHECK-NEXT: vmovx.f16 s9, s2
; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vins.f16 s2, s3 ; CHECK-NEXT: vins.f16 s2, s3
; CHECK-NEXT: vmovx.f16 s10, s4
; CHECK-NEXT: vmovx.f16 s16, s1
; CHECK-NEXT: vmov q3, q0 ; CHECK-NEXT: vmov q3, q0
; CHECK-NEXT: vins.f16 s8, s16 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vins.f16 s8, s0
; CHECK-NEXT: vmovx.f16 s0, s3 ; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vins.f16 s4, s5 ; CHECK-NEXT: vmovx.f16 s10, s4
; CHECK-NEXT: vins.f16 s9, s0 ; CHECK-NEXT: vins.f16 s9, s0
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vins.f16 s4, s5
; CHECK-NEXT: vins.f16 s10, s0 ; CHECK-NEXT: vins.f16 s10, s0
; CHECK-NEXT: vmov.f32 s13, s2
; CHECK-NEXT: vmov.f32 s14, s4
; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vmovx.f16 s11, s6 ; CHECK-NEXT: vmovx.f16 s11, s6
; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vins.f16 s6, s7 ; CHECK-NEXT: vins.f16 s6, s7
; CHECK-NEXT: vmov.f32 s13, s2
; CHECK-NEXT: vins.f16 s11, s0 ; CHECK-NEXT: vins.f16 s11, s0
; CHECK-NEXT: vmov.f32 s14, s4
; CHECK-NEXT: vmov.f32 s15, s6 ; CHECK-NEXT: vmov.f32 s15, s6
; CHECK-NEXT: vadd.i16 q0, q3, q2 ; CHECK-NEXT: vadd.i16 q0, q3, q2
; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %s1 = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%s2 = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %s2 = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%r = add <8 x i16> %s1, %s2 %r = add <8 x i16> %s1, %s2
ret <8 x i16> %r ret <8 x i16> %r
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle3step_i16(<32 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle3step_i16(<32 x i16> %src) {
; CHECK-LABEL: shuffle3step_i16: ; CHECK-LABEL: shuffle3step_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d11, d12, d13}
; CHECK-NEXT: vmovx.f16 s16, s1 ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s12, s0 ; CHECK-NEXT: vmov.f32 s12, s0
; CHECK-NEXT: vins.f16 s12, s16 ; CHECK-NEXT: vmovx.f16 s14, s1
; CHECK-NEXT: vmovx.f16 s16, s4 ; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vmovx.f16 s14, s4
; CHECK-NEXT: vmov.f32 s13, s3 ; CHECK-NEXT: vmov.f32 s13, s3
; CHECK-NEXT: vmovx.f16 s20, s5 ; CHECK-NEXT: vmovx.f16 s15, s7
; CHECK-NEXT: vins.f16 s13, s16 ; CHECK-NEXT: vins.f16 s13, s14
; CHECK-NEXT: vmovx.f16 s16, s7
; CHECK-NEXT: vmov.f32 s14, s6 ; CHECK-NEXT: vmov.f32 s14, s6
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vins.f16 s14, s15
; CHECK-NEXT: vins.f16 s14, s16 ; CHECK-NEXT: vmovx.f16 s15, s2
; CHECK-NEXT: vmovx.f16 s16, s2 ; CHECK-NEXT: vins.f16 s1, s15
; CHECK-NEXT: vins.f16 s1, s16 ; CHECK-NEXT: vmovx.f16 s15, s5
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vins.f16 s17, s20 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmovx.f16 s20, s10 ; CHECK-NEXT: vins.f16 s17, s15
; CHECK-NEXT: vmov.f32 s15, s9
; CHECK-NEXT: vins.f16 s15, s20
; CHECK-NEXT: vmovx.f16 s20, s11
; CHECK-NEXT: vins.f16 s10, s20
; CHECK-NEXT: vmov.f32 s16, s1 ; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vmovx.f16 s1, s10
; CHECK-NEXT: vmov.f32 s15, s9
; CHECK-NEXT: vins.f16 s15, s1
; CHECK-NEXT: vmovx.f16 s1, s11
; CHECK-NEXT: vins.f16 s10, s1
; CHECK-NEXT: vmovx.f16 s1, s3
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmovx.f16 s7, s9
; CHECK-NEXT: vmov.f32 s23, s10 ; CHECK-NEXT: vmov.f32 s23, s10
; CHECK-NEXT: vmov.f32 s22, s8 ; CHECK-NEXT: vmov.f32 s22, s8
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vins.f16 s1, s5
; CHECK-NEXT: vmov q6, q5 ; CHECK-NEXT: vmov q6, q5
; CHECK-NEXT: vins.f16 s6, s8
; CHECK-NEXT: vins.f16 s7, s11
; CHECK-NEXT: vmovnb.i32 q6, q4 ; CHECK-NEXT: vmovnb.i32 q6, q4
; CHECK-NEXT: vmov.f32 s19, s10
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmovnb.i32 q2, q0
; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vmov.f32 s18, s26 ; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vadd.i16 q0, q3, q0
; CHECK-NEXT: vmovx.f16 s20, s0
; CHECK-NEXT: vins.f16 s20, s2
; CHECK-NEXT: vmovx.f16 s21, s3
; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vmovx.f16 s3, s9
; CHECK-NEXT: vins.f16 s21, s5
; CHECK-NEXT: vins.f16 s3, s11
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovnb.i32 q1, q5
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s23, s3
; CHECK-NEXT: vadd.i16 q0, q3, q5
; CHECK-NEXT: vadd.i16 q0, q0, q4 ; CHECK-NEXT: vadd.i16 q0, q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: vpop {d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a = add <8 x i16> %s1, %s2 %a = add <8 x i16> %s1, %s2
%r = add <8 x i16> %a, %s3 %r = add <8 x i16> %a, %s3
ret <8 x i16> %r ret <8 x i16> %r
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle4step_i16(<32 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @shuffle4step_i16(<32 x i16> %src) {
; CHECK-LABEL: shuffle4step_i16: ; CHECK-LABEL: shuffle4step_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmovx.f16 s20, s11
; CHECK-NEXT: vmovx.f16 s18, s9 ; CHECK-NEXT: vmovx.f16 s18, s9
; CHECK-NEXT: vins.f16 s18, s20 ; CHECK-NEXT: vmovx.f16 s16, s11
; CHECK-NEXT: vmovx.f16 s20, s15 ; CHECK-NEXT: vins.f16 s18, s16
; CHECK-NEXT: vmovx.f16 s19, s13 ; CHECK-NEXT: vmovx.f16 s19, s13
; CHECK-NEXT: vins.f16 s9, s11 ; CHECK-NEXT: vmovx.f16 s16, s15
; CHECK-NEXT: vins.f16 s19, s20
; CHECK-NEXT: vmovx.f16 s20, s3 ; CHECK-NEXT: vmovx.f16 s20, s3
; CHECK-NEXT: vins.f16 s19, s16
; CHECK-NEXT: vmovx.f16 s16, s1 ; CHECK-NEXT: vmovx.f16 s16, s1
; CHECK-NEXT: vins.f16 s13, s15
; CHECK-NEXT: vins.f16 s16, s20 ; CHECK-NEXT: vins.f16 s16, s20
; CHECK-NEXT: vmovx.f16 s20, s7
; CHECK-NEXT: vmovx.f16 s17, s5 ; CHECK-NEXT: vmovx.f16 s17, s5
; CHECK-NEXT: vmovx.f16 s20, s7
; CHECK-NEXT: vins.f16 s9, s11
; CHECK-NEXT: vins.f16 s13, s15
; CHECK-NEXT: vins.f16 s5, s7
; CHECK-NEXT: vins.f16 s1, s3 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vins.f16 s17, s20 ; CHECK-NEXT: vins.f16 s17, s20
; CHECK-NEXT: vmov.f32 s20, s1
; CHECK-NEXT: vmovx.f16 s1, s10
; CHECK-NEXT: vmov.f32 s22, s9 ; CHECK-NEXT: vmov.f32 s22, s9
; CHECK-NEXT: vmov.f32 s23, s13 ; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vins.f16 s5, s7
; CHECK-NEXT: vmov.f32 s20, s1
; CHECK-NEXT: vmovx.f16 s24, s10
; CHECK-NEXT: vmov.f32 s21, s5 ; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vadd.i16 q4, q5, q4 ; CHECK-NEXT: vadd.i16 q4, q5, q4
; CHECK-NEXT: vmovx.f16 s22, s8 ; CHECK-NEXT: vmovx.f16 s22, s8
; CHECK-NEXT: vins.f16 s22, s24 ; CHECK-NEXT: vins.f16 s22, s1
; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vmovx.f16 s24, s14
; CHECK-NEXT: vmovx.f16 s23, s12 ; CHECK-NEXT: vmovx.f16 s23, s12
; CHECK-NEXT: vins.f16 s12, s14 ; CHECK-NEXT: vmovx.f16 s1, s14
; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vmov.f32 s11, s12
; CHECK-NEXT: vins.f16 s23, s24
; CHECK-NEXT: vmovx.f16 s24, s2
; CHECK-NEXT: vmovx.f16 s20, s0 ; CHECK-NEXT: vmovx.f16 s20, s0
; CHECK-NEXT: vins.f16 s20, s24 ; CHECK-NEXT: vins.f16 s23, s1
; CHECK-NEXT: vmovx.f16 s24, s6 ; CHECK-NEXT: vmovx.f16 s1, s2
; CHECK-NEXT: vins.f16 s20, s1
; CHECK-NEXT: vmovx.f16 s21, s4 ; CHECK-NEXT: vmovx.f16 s21, s4
; CHECK-NEXT: vins.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vins.f16 s4, s6 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vins.f16 s21, s1
; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov.f32 s3, s12
; CHECK-NEXT: vmov.f32 s1, s4 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.f32 s2, s10 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vadd.i16 q0, q0, q5 ; CHECK-NEXT: vadd.i16 q0, q0, q5
; CHECK-NEXT: vadd.i16 q0, q0, q4 ; CHECK-NEXT: vadd.i16 q0, q0, q4
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x i16> %src, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = add <8 x i16> %s1, %s2 %a1 = add <8 x i16> %s1, %s2
%a2 = add <8 x i16> %s3, %s4 %a2 = add <8 x i16> %s3, %s4
▲ Show 20 Lines • Show All 290 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.u8 r0, q2[5] ; CHECK-NEXT: vmov.u8 r0, q2[5]
; CHECK-NEXT: vmov.8 q4[12], r0 ; CHECK-NEXT: vmov.8 q4[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[8] ; CHECK-NEXT: vmov.u8 r0, q2[8]
; CHECK-NEXT: vmov.8 q4[13], r0 ; CHECK-NEXT: vmov.8 q4[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[11] ; CHECK-NEXT: vmov.u8 r0, q2[11]
; CHECK-NEXT: vmov.8 q4[14], r0 ; CHECK-NEXT: vmov.8 q4[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[14] ; CHECK-NEXT: vmov.u8 r0, q2[14]
; CHECK-NEXT: vmov.8 q4[15], r0 ; CHECK-NEXT: vmov.8 q4[15], r0
; CHECK-NEXT: vmov.u8 r0, q2[2]
; CHECK-NEXT: vmov q5, q3 ; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vmov.u8 r0, q2[2]
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.8 q5[11], r0 ; CHECK-NEXT: vmov.8 q5[11], r0
; CHECK-NEXT: vmov.u8 r0, q0[0] ; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.8 q4[0], r0 ; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[3] ; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.8 q4[1], r0 ; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[6] ; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.8 q4[2], r0 ; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[9] ; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.8 q4[3], r0 ; CHECK-NEXT: vmov.8 q4[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12] ; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vmov.8 q4[4], r0 ; CHECK-NEXT: vmov.8 q4[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[15] ; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.8 q4[5], r0 ; CHECK-NEXT: vmov.8 q4[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[2] ; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.8 q4[6], r0 ; CHECK-NEXT: vmov.8 q4[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[5] ; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.8 q4[7], r0 ; CHECK-NEXT: vmov.8 q4[7], r0
; CHECK-NEXT: vmov.u8 r0, q1[8] ; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.8 q4[8], r0 ; CHECK-NEXT: vmov.8 q4[8], r0
; CHECK-NEXT: vmov.u8 r0, q1[11] ; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.8 q4[9], r0 ; CHECK-NEXT: vmov.8 q4[9], r0
; CHECK-NEXT: vmov.u8 r0, q1[14] ; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.8 q4[10], r0 ; CHECK-NEXT: vmov.8 q4[10], r0
; CHECK-NEXT: vmov.u8 r0, q2[4] ; CHECK-NEXT: vmov.u8 r0, q2[4]
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.8 q5[12], r0 ; CHECK-NEXT: vmov.8 q5[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[7] ; CHECK-NEXT: vmov.u8 r0, q2[7]
; CHECK-NEXT: vmov q6, q4
; CHECK-NEXT: vmov.8 q5[13], r0 ; CHECK-NEXT: vmov.8 q5[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[10] ; CHECK-NEXT: vmov.u8 r0, q2[10]
; CHECK-NEXT: vmov.8 q5[14], r0 ; CHECK-NEXT: vmov.8 q5[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[13] ; CHECK-NEXT: vmov.u8 r0, q2[13]
; CHECK-NEXT: vmov.8 q5[15], r0 ; CHECK-NEXT: vmov.8 q5[15], r0
; CHECK-NEXT: vmov.u8 r0, q2[1] ; CHECK-NEXT: vmov.u8 r0, q2[1]
; CHECK-NEXT: vmov q6, q4
; CHECK-NEXT: vmov.8 q6[11], r0 ; CHECK-NEXT: vmov.8 q6[11], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vadd.i8 q3, q4, q3 ; CHECK-NEXT: vadd.i8 q3, q4, q3
; CHECK-NEXT: vmov.8 q4[0], r0 ; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[5] ; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.8 q4[1], r0 ; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[8] ; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmov.8 q4[2], r0 ; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11] ; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.8 q4[3], r0 ; CHECK-NEXT: vmov.8 q4[3], r0
▲ Show 20 Lines • Show All 202 Lines • ▼ Show 20 Linesentry:
%out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 0, i32 1> %out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
ret <2 x i64> %out ret <2 x i64> %out
} }
define arm_aapcs_vfpcc <2 x i64> @shuffle2_i64(<2 x i64> %src) { define arm_aapcs_vfpcc <2 x i64> @shuffle2_i64(<2 x i64> %src) {
; CHECK-LABEL: shuffle2_i64: ; CHECK-LABEL: shuffle2_i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s6, s0 ; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s7, s1 ; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 1, i32 0> %out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i64> %out ret <2 x i64> %out
} }
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <4 x float> @shuffle2step_f32(<8 x float> %src) { define arm_aapcs_vfpcc <4 x float> @shuffle2step_f32(<8 x float> %src) {
; CHECKFP-LABEL: shuffle2step_f32: ; CHECKFP-LABEL: shuffle2step_f32:
; CHECKFP: @ %bb.0: @ %entry ; CHECKFP: @ %bb.0: @ %entry
; CHECKFP-NEXT: vmov.f32 s8, s1 ; CHECKFP-NEXT: vmov.f32 s8, s1
; CHECKFP-NEXT: vmov.f32 s9, s3 ; CHECKFP-NEXT: vmov.f32 s9, s3
; CHECKFP-NEXT: vmov.f32 s1, s2 ; CHECKFP-NEXT: vmov.f32 s1, s2
; CHECKFP-NEXT: vmov.f32 s10, s5 ; CHECKFP-NEXT: vmov.f32 s10, s5
; CHECKFP-NEXT: vmov.f32 s2, s4
; CHECKFP-NEXT: vmov.f32 s11, s7 ; CHECKFP-NEXT: vmov.f32 s11, s7
; CHECKFP-NEXT: vmov.f32 s2, s4
; CHECKFP-NEXT: vmov.f32 s3, s6 ; CHECKFP-NEXT: vmov.f32 s3, s6
; CHECKFP-NEXT: vadd.f32 q0, q0, q2 ; CHECKFP-NEXT: vadd.f32 q0, q0, q2
; CHECKFP-NEXT: bx lr ; CHECKFP-NEXT: bx lr
entry: entry:
%s1 = shufflevector <8 x float> %src, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %s1 = shufflevector <8 x float> %src, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s2 = shufflevector <8 x float> %src, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %s2 = shufflevector <8 x float> %src, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%r = fadd <4 x float> %s1, %s2 %r = fadd <4 x float> %s1, %s2
ret <4 x float> %r ret <4 x float> %r
} }
define arm_aapcs_vfpcc <4 x float> @shuffle3step_f32(<16 x float> %src) { define arm_aapcs_vfpcc <4 x float> @shuffle3step_f32(<16 x float> %src) {
; CHECKFP-LABEL: shuffle3step_f32: ; CHECKFP-LABEL: shuffle3step_f32:
; CHECKFP: @ %bb.0: @ %entry ; CHECKFP: @ %bb.0: @ %entry
; CHECKFP-NEXT: .vsave {d8, d9} ; CHECKFP-NEXT: .vsave {d8, d9}
; CHECKFP-NEXT: vpush {d8, d9} ; CHECKFP-NEXT: vpush {d8, d9}
; CHECKFP-NEXT: vmov.f32 s12, s1
; CHECKFP-NEXT: vmov.f32 s16, s0
; CHECKFP-NEXT: vmov.f32 s13, s4 ; CHECKFP-NEXT: vmov.f32 s13, s4
; CHECKFP-NEXT: vmov.f32 s17, s3
; CHECKFP-NEXT: vmov.f32 s14, s7 ; CHECKFP-NEXT: vmov.f32 s14, s7
; CHECKFP-NEXT: vmov.f32 s18, s6 ; CHECKFP-NEXT: vmov.f32 s18, s6
; CHECKFP-NEXT: vmov.f32 s4, s2 ; CHECKFP-NEXT: vmov.f32 s12, s1
; CHECKFP-NEXT: vmov.f32 s6, s8
; CHECKFP-NEXT: vmov.f32 s15, s10 ; CHECKFP-NEXT: vmov.f32 s15, s10
; CHECKFP-NEXT: vmov.f32 s16, s0
; CHECKFP-NEXT: vmov.f32 s17, s3
; CHECKFP-NEXT: vmov.f32 s19, s9 ; CHECKFP-NEXT: vmov.f32 s19, s9
; CHECKFP-NEXT: vadd.f32 q3, q4, q3 ; CHECKFP-NEXT: vadd.f32 q3, q4, q3
; CHECKFP-NEXT: vmov.f32 s4, s2
; CHECKFP-NEXT: vmov.f32 s6, s8
; CHECKFP-NEXT: vmov.f32 s7, s11 ; CHECKFP-NEXT: vmov.f32 s7, s11
; CHECKFP-NEXT: vadd.f32 q0, q3, q1 ; CHECKFP-NEXT: vadd.f32 q0, q3, q1
; CHECKFP-NEXT: vpop {d8, d9} ; CHECKFP-NEXT: vpop {d8, d9}
; CHECKFP-NEXT: bx lr ; CHECKFP-NEXT: bx lr
entry: entry:
%s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a = fadd <4 x float> %s1, %s2 %a = fadd <4 x float> %s1, %s2
%r = fadd <4 x float> %a, %s3 %r = fadd <4 x float> %a, %s3
ret <4 x float> %r ret <4 x float> %r
} }
define arm_aapcs_vfpcc <4 x float> @shuffle4step_f32(<16 x float> %src) { define arm_aapcs_vfpcc <4 x float> @shuffle4step_f32(<16 x float> %src) {
; CHECKFP-LABEL: shuffle4step_f32: ; CHECKFP-LABEL: shuffle4step_f32:
; CHECKFP: @ %bb.0: @ %entry ; CHECKFP: @ %bb.0: @ %entry
; CHECKFP-NEXT: .vsave {d8, d9, d10, d11} ; CHECKFP-NEXT: .vsave {d8, d9, d10, d11}
; CHECKFP-NEXT: vpush {d8, d9, d10, d11} ; CHECKFP-NEXT: vpush {d8, d9, d10, d11}
; CHECKFP-NEXT: vmov.f32 s16, s3 ; CHECKFP-NEXT: vmov.f32 s16, s3
; CHECKFP-NEXT: vmov.f32 s20, s2 ; CHECKFP-NEXT: vmov.f32 s20, s2
; CHECKFP-NEXT: vmov.f32 s17, s7 ; CHECKFP-NEXT: vmov.f32 s17, s7
; CHECKFP-NEXT: vmov.f32 s21, s6
; CHECKFP-NEXT: vmov.f32 s18, s11 ; CHECKFP-NEXT: vmov.f32 s18, s11
; CHECKFP-NEXT: vmov.f32 s22, s10
; CHECKFP-NEXT: vmov.f32 s19, s15 ; CHECKFP-NEXT: vmov.f32 s19, s15
; CHECKFP-NEXT: vmov.f32 s21, s6
; CHECKFP-NEXT: vmov.f32 s22, s10
; CHECKFP-NEXT: vmov.f32 s23, s14 ; CHECKFP-NEXT: vmov.f32 s23, s14
; CHECKFP-NEXT: vadd.f32 q4, q5, q4 ; CHECKFP-NEXT: vadd.f32 q4, q5, q4
; CHECKFP-NEXT: vmov.f32 s20, s1 ; CHECKFP-NEXT: vmov.f32 s20, s1
; CHECKFP-NEXT: vmov.f32 s21, s5 ; CHECKFP-NEXT: vmov.f32 s21, s5
; CHECKFP-NEXT: vmov.f32 s1, s4
; CHECKFP-NEXT: vmov.f32 s22, s9 ; CHECKFP-NEXT: vmov.f32 s22, s9
; CHECKFP-NEXT: vmov.f32 s2, s8
; CHECKFP-NEXT: vmov.f32 s23, s13 ; CHECKFP-NEXT: vmov.f32 s23, s13
; CHECKFP-NEXT: vmov.f32 s1, s4
; CHECKFP-NEXT: vmov.f32 s2, s8
; CHECKFP-NEXT: vmov.f32 s3, s12 ; CHECKFP-NEXT: vmov.f32 s3, s12
; CHECKFP-NEXT: vadd.f32 q0, q0, q5 ; CHECKFP-NEXT: vadd.f32 q0, q0, q5
; CHECKFP-NEXT: vadd.f32 q0, q0, q4 ; CHECKFP-NEXT: vadd.f32 q0, q0, q4
; CHECKFP-NEXT: vpop {d8, d9, d10, d11} ; CHECKFP-NEXT: vpop {d8, d9, d10, d11}
; CHECKFP-NEXT: bx lr ; CHECKFP-NEXT: bx lr
entry: entry:
%s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %s1 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %s2 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %s3 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%s4 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %s4 = shufflevector <16 x float> %src, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
%a1 = fadd <4 x float> %s1, %s2 %a1 = fadd <4 x float> %s1, %s2
%a2 = fadd <4 x float> %s3, %s4 %a2 = fadd <4 x float> %s3, %s4
%r = fadd <4 x float> %a1, %a2 %r = fadd <4 x float> %a1, %a2
ret <4 x float> %r ret <4 x float> %r
} }
; f16 ; f16
define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle1_f16: ; CHECK-LABEL: shuffle1_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s0, s7 ; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vmovx.f16 s1, s6 ; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vmovx.f16 s3, s4 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle2_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle2_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle2_f16: ; CHECK-LABEL: shuffle2_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle3_f16: ; CHECK-LABEL: shuffle3_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s1, s7
; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vins.f16 s1, s7
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vmovx.f16 s0, s4
; CHECK-NEXT: vins.f16 s5, s4 ; CHECK-NEXT: vins.f16 s5, s4
; CHECK-NEXT: vins.f16 s2, s8 ; CHECK-NEXT: vins.f16 s2, s0
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmovx.f16 s1, s7
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vins.f16 s1, s7
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0> %out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle5_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle5_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle5_f16: ; CHECK-LABEL: shuffle5_f16:
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entry: entry:
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle2step_f16(<16 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle2step_f16(<16 x half> %src) {
; CHECKFP-LABEL: shuffle2step_f16: ; CHECKFP-LABEL: shuffle2step_f16:
; CHECKFP: @ %bb.0: @ %entry ; CHECKFP: @ %bb.0: @ %entry
; CHECKFP-NEXT: vmovx.f16 s12, s1
; CHECKFP-NEXT: vmovx.f16 s8, s0 ; CHECKFP-NEXT: vmovx.f16 s8, s0
; CHECKFP-NEXT: vins.f16 s8, s12 ; CHECKFP-NEXT: vmovx.f16 s10, s1
; CHECKFP-NEXT: vmovx.f16 s12, s3 ; CHECKFP-NEXT: vins.f16 s8, s10
; CHECKFP-NEXT: vmovx.f16 s9, s2 ; CHECKFP-NEXT: vmovx.f16 s9, s2
; CHECKFP-NEXT: vins.f16 s0, s1 ; CHECKFP-NEXT: vmovx.f16 s10, s3
; CHECKFP-NEXT: vins.f16 s9, s12
; CHECKFP-NEXT: vins.f16 s2, s3
; CHECKFP-NEXT: vmovx.f16 s12, s5 ; CHECKFP-NEXT: vmovx.f16 s12, s5
; CHECKFP-NEXT: vins.f16 s9, s10
; CHECKFP-NEXT: vmovx.f16 s10, s4 ; CHECKFP-NEXT: vmovx.f16 s10, s4
; CHECKFP-NEXT: vins.f16 s10, s12 ; CHECKFP-NEXT: vins.f16 s10, s12
; CHECKFP-NEXT: vins.f16 s4, s5
; CHECKFP-NEXT: vmov.f32 s1, s2
; CHECKFP-NEXT: vmovx.f16 s12, s7
; CHECKFP-NEXT: vmovx.f16 s11, s6 ; CHECKFP-NEXT: vmovx.f16 s11, s6
; CHECKFP-NEXT: vmovx.f16 s12, s7
; CHECKFP-NEXT: vins.f16 s2, s3
; CHECKFP-NEXT: vins.f16 s6, s7 ; CHECKFP-NEXT: vins.f16 s6, s7
; CHECKFP-NEXT: vmov.f32 s2, s4 ; CHECKFP-NEXT: vins.f16 s4, s5
; CHECKFP-NEXT: vins.f16 s0, s1
; CHECKFP-NEXT: vmov.f32 s1, s2
; CHECKFP-NEXT: vins.f16 s11, s12 ; CHECKFP-NEXT: vins.f16 s11, s12
; CHECKFP-NEXT: vmov.f32 s2, s4
; CHECKFP-NEXT: vmov.f32 s3, s6 ; CHECKFP-NEXT: vmov.f32 s3, s6
; CHECKFP-NEXT: vadd.f16 q0, q0, q2 ; CHECKFP-NEXT: vadd.f16 q0, q0, q2
; CHECKFP-NEXT: bx lr ; CHECKFP-NEXT: bx lr
entry: entry:
%s1 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %s1 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%s2 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %s2 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%r = fadd <8 x half> %s1, %s2 %r = fadd <8 x half> %s1, %s2
ret <8 x half> %r ret <8 x half> %r
} }
define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
; CHECKFP-LABEL: shuffle3step_f16: ; CHECKFP-LABEL: shuffle3step_f16:
; CHECKFP: @ %bb.0: @ %entry ; CHECKFP: @ %bb.0: @ %entry
; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECKFP-NEXT: .vsave {d8, d9, d10}
; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECKFP-NEXT: vpush {d8, d9, d10}
; CHECKFP-NEXT: vmovx.f16 s16, s2
; CHECKFP-NEXT: vmov.f32 s12, s1 ; CHECKFP-NEXT: vmov.f32 s12, s1
; CHECKFP-NEXT: vins.f16 s12, s16 ; CHECKFP-NEXT: vmovx.f16 s14, s2
; CHECKFP-NEXT: vmovx.f16 s16, s5 ; CHECKFP-NEXT: vins.f16 s12, s14
; CHECKFP-NEXT: vmov.f32 s13, s4 ; CHECKFP-NEXT: vmov.f32 s13, s4
; CHECKFP-NEXT: vmovx.f16 s20, s11 ; CHECKFP-NEXT: vmovx.f16 s14, s5
; CHECKFP-NEXT: vins.f16 s13, s16 ; CHECKFP-NEXT: vmov.f32 s15, s10
; CHECKFP-NEXT: vmov.f32 s19, s10 ; CHECKFP-NEXT: vins.f16 s13, s14
; CHECKFP-NEXT: vins.f16 s19, s20 ; CHECKFP-NEXT: vmovx.f16 s14, s11
; CHECKFP-NEXT: vins.f16 s15, s14
; CHECKFP-NEXT: vmov.f32 s14, s7 ; CHECKFP-NEXT: vmov.f32 s14, s7
; CHECKFP-NEXT: vmovx.f16 s20, s8 ; CHECKFP-NEXT: vmovx.f16 s16, s8
; CHECKFP-NEXT: vmov.f32 s28, s6 ; CHECKFP-NEXT: vmovx.f16 s4, s4
; CHECKFP-NEXT: vins.f16 s14, s20 ; CHECKFP-NEXT: vmovx.f16 s7, s7
; CHECKFP-NEXT: vmovx.f16 s20, s7 ; CHECKFP-NEXT: vmov.f32 s20, s6
; CHECKFP-NEXT: vins.f16 s28, s20 ; CHECKFP-NEXT: vmovx.f16 s10, s10
; CHECKFP-NEXT: vmovx.f16 s24, s1 ; CHECKFP-NEXT: vmovx.f16 s17, s3
; CHECKFP-NEXT: vmovx.f16 s20, s0 ; CHECKFP-NEXT: vmovx.f16 s19, s9
; CHECKFP-NEXT: vins.f16 s0, s24 ; CHECKFP-NEXT: vmovx.f16 s18, s6
; CHECKFP-NEXT: vins.f16 s20, s2 ; CHECKFP-NEXT: vins.f16 s14, s16
; CHECKFP-NEXT: vmovx.f16 s26, s4 ; CHECKFP-NEXT: vmovx.f16 s16, s0
; CHECKFP-NEXT: vmovx.f16 s21, s3 ; CHECKFP-NEXT: vmovx.f16 s1, s1
; CHECKFP-NEXT: vins.f16 s3, s26 ; CHECKFP-NEXT: vins.f16 s20, s7
; CHECKFP-NEXT: vins.f16 s21, s5 ; CHECKFP-NEXT: vins.f16 s3, s4
; CHECKFP-NEXT: vmovx.f16 s30, s10 ; CHECKFP-NEXT: vins.f16 s9, s10
; CHECKFP-NEXT: vmovx.f16 s23, s9 ; CHECKFP-NEXT: vins.f16 s0, s1
; CHECKFP-NEXT: vmov.f32 s18, s8 ; CHECKFP-NEXT: vins.f16 s16, s2
; CHECKFP-NEXT: vmov.f32 s1, s3 ; CHECKFP-NEXT: vmov.f32 s1, s3
; CHECKFP-NEXT: vins.f16 s9, s30 ; CHECKFP-NEXT: vins.f16 s17, s5
; CHECKFP-NEXT: vins.f16 s23, s11 ; CHECKFP-NEXT: vins.f16 s19, s11
; CHECKFP-NEXT: vmov.f32 s2, s28 ; CHECKFP-NEXT: vins.f16 s18, s8
; CHECKFP-NEXT: vmovx.f16 s22, s6 ; CHECKFP-NEXT: vmov.f32 s2, s20
; CHECKFP-NEXT: vmov.f32 s3, s9 ; CHECKFP-NEXT: vmov.f32 s3, s9
; CHECKFP-NEXT: vins.f16 s22, s8 ; CHECKFP-NEXT: vadd.f16 q0, q0, q4
; CHECKFP-NEXT: vmov.f32 s15, s19
; CHECKFP-NEXT: vadd.f16 q0, q0, q5
; CHECKFP-NEXT: vadd.f16 q0, q0, q3 ; CHECKFP-NEXT: vadd.f16 q0, q0, q3
; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECKFP-NEXT: vpop {d8, d9, d10}
; CHECKFP-NEXT: bx lr ; CHECKFP-NEXT: bx lr
entry: entry:
%s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a = fadd <8 x half> %s1, %s2 %a = fadd <8 x half> %s1, %s2
%r = fadd <8 x half> %a, %s3 %r = fadd <8 x half> %a, %s3
ret <8 x half> %r ret <8 x half> %r
} }
define arm_aapcs_vfpcc <8 x half> @shuffle4step_f16(<32 x half> %src) { define arm_aapcs_vfpcc <8 x half> @shuffle4step_f16(<32 x half> %src) {
; CHECKFP-LABEL: shuffle4step_f16: ; CHECKFP-LABEL: shuffle4step_f16:
; CHECKFP: @ %bb.0: @ %entry ; CHECKFP: @ %bb.0: @ %entry
; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECKFP-NEXT: vmovx.f16 s20, s11
; CHECKFP-NEXT: vmovx.f16 s18, s9 ; CHECKFP-NEXT: vmovx.f16 s18, s9
; CHECKFP-NEXT: vins.f16 s18, s20 ; CHECKFP-NEXT: vmovx.f16 s16, s11
; CHECKFP-NEXT: vmovx.f16 s20, s15 ; CHECKFP-NEXT: vins.f16 s18, s16
; CHECKFP-NEXT: vmovx.f16 s19, s13 ; CHECKFP-NEXT: vmovx.f16 s19, s13
; CHECKFP-NEXT: vins.f16 s9, s11 ; CHECKFP-NEXT: vmovx.f16 s16, s15
; CHECKFP-NEXT: vins.f16 s19, s20 ; CHECKFP-NEXT: vmovx.f16 s22, s8
; CHECKFP-NEXT: vmovx.f16 s20, s3 ; CHECKFP-NEXT: vins.f16 s19, s16
; CHECKFP-NEXT: vmovx.f16 s16, s1 ; CHECKFP-NEXT: vmovx.f16 s16, s1
; CHECKFP-NEXT: vmovx.f16 s24, s10 ; CHECKFP-NEXT: vmovx.f16 s20, s3
; CHECKFP-NEXT: vins.f16 s1, s3
; CHECKFP-NEXT: vmovx.f16 s3, s10
; CHECKFP-NEXT: vins.f16 s16, s20 ; CHECKFP-NEXT: vins.f16 s16, s20
; CHECKFP-NEXT: vmovx.f16 s20, s7
; CHECKFP-NEXT: vmovx.f16 s17, s5 ; CHECKFP-NEXT: vmovx.f16 s17, s5
; CHECKFP-NEXT: vins.f16 s13, s15 ; CHECKFP-NEXT: vmovx.f16 s20, s7
; CHECKFP-NEXT: vins.f16 s17, s20 ; CHECKFP-NEXT: vins.f16 s22, s3
; CHECKFP-NEXT: vmovx.f16 s22, s8
; CHECKFP-NEXT: vins.f16 s22, s24
; CHECKFP-NEXT: vmovx.f16 s24, s14
; CHECKFP-NEXT: vmovx.f16 s23, s12 ; CHECKFP-NEXT: vmovx.f16 s23, s12
; CHECKFP-NEXT: vins.f16 s1, s3 ; CHECKFP-NEXT: vmovx.f16 s3, s14
; CHECKFP-NEXT: vins.f16 s23, s24 ; CHECKFP-NEXT: vins.f16 s17, s20
; CHECKFP-NEXT: vmovx.f16 s24, s2 ; CHECKFP-NEXT: vins.f16 s23, s3
; CHECKFP-NEXT: vmovx.f16 s20, s0 ; CHECKFP-NEXT: vmovx.f16 s20, s0
; CHECKFP-NEXT: vmovx.f16 s3, s2
; CHECKFP-NEXT: vins.f16 s9, s11
; CHECKFP-NEXT: vins.f16 s13, s15
; CHECKFP-NEXT: vins.f16 s5, s7 ; CHECKFP-NEXT: vins.f16 s5, s7
; CHECKFP-NEXT: vins.f16 s20, s24 ; CHECKFP-NEXT: vins.f16 s20, s3
; CHECKFP-NEXT: vmovx.f16 s24, s6
; CHECKFP-NEXT: vmovx.f16 s21, s4 ; CHECKFP-NEXT: vmovx.f16 s21, s4
; CHECKFP-NEXT: vmovx.f16 s3, s6
; CHECKFP-NEXT: vins.f16 s8, s10 ; CHECKFP-NEXT: vins.f16 s8, s10
; CHECKFP-NEXT: vins.f16 s21, s24
; CHECKFP-NEXT: vmov.f32 s26, s9
; CHECKFP-NEXT: vins.f16 s12, s14 ; CHECKFP-NEXT: vins.f16 s12, s14
; CHECKFP-NEXT: vins.f16 s0, s2
; CHECKFP-NEXT: vmov.f32 s27, s13
; CHECKFP-NEXT: vins.f16 s4, s6 ; CHECKFP-NEXT: vins.f16 s4, s6
; CHECKFP-NEXT: vins.f16 s21, s3
; CHECKFP-NEXT: vins.f16 s0, s2
; CHECKFP-NEXT: vmov.f32 s24, s1 ; CHECKFP-NEXT: vmov.f32 s24, s1
; CHECKFP-NEXT: vmov.f32 s26, s9
; CHECKFP-NEXT: vmov.f32 s27, s13
; CHECKFP-NEXT: vmov.f32 s25, s5
; CHECKFP-NEXT: vmov.f32 s2, s8 ; CHECKFP-NEXT: vmov.f32 s2, s8
; CHECKFP-NEXT: vadd.f16 q4, q6, q4
; CHECKFP-NEXT: vmov.f32 s3, s12 ; CHECKFP-NEXT: vmov.f32 s3, s12
; CHECKFP-NEXT: vmov.f32 s1, s4 ; CHECKFP-NEXT: vmov.f32 s1, s4
; CHECKFP-NEXT: vmov.f32 s25, s5
; CHECKFP-NEXT: vadd.f16 q0, q0, q5 ; CHECKFP-NEXT: vadd.f16 q0, q0, q5
; CHECKFP-NEXT: vadd.f16 q4, q6, q4
; CHECKFP-NEXT: vadd.f16 q0, q0, q4 ; CHECKFP-NEXT: vadd.f16 q0, q0, q4
; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECKFP-NEXT: bx lr ; CHECKFP-NEXT: bx lr
entry: entry:
%s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
Show All 13 Linesentry:
%out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 0, i32 1> %out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %out ret <2 x double> %out
} }
define arm_aapcs_vfpcc <2 x double> @shuffle2_f64(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @shuffle2_f64(<2 x double> %src) {
; CHECK-LABEL: shuffle2_f64: ; CHECK-LABEL: shuffle2_f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s6, s0 ; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s7, s1 ; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 1, i32 0> %out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 1, i32 0>
ret <2 x double> %out ret <2 x double> %out
} }
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entry: entry:
%res = insertelement <2 x i64> undef, i64 %a, i32 0 %res = insertelement <2 x i64> undef, i64 %a, i32 0
ret <2 x i64> %res ret <2 x i64> %res
} }
define arm_aapcs_vfpcc <4 x float> @insert_f32(float %a) { define arm_aapcs_vfpcc <4 x float> @insert_f32(float %a) {
; CHECK-LABEL: insert_f32: ; CHECK-LABEL: insert_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%res = insertelement <4 x float> undef, float %a, i32 0 %res = insertelement <4 x float> undef, float %a, i32 0
ret <4 x float> %res ret <4 x float> %res
} }
define arm_aapcs_vfpcc <8 x half> @insert_f16(half %a) { define arm_aapcs_vfpcc <8 x half> @insert_f16(half %a) {
; CHECK-LABEL: insert_f16: ; CHECK-LABEL: insert_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%res = insertelement <8 x half> undef, half %a, i32 0 %res = insertelement <8 x half> undef, half %a, i32 0
ret <8 x half> %res ret <8 x half> %res
} }
define arm_aapcs_vfpcc <2 x double> @insert_f64(double %a) { define arm_aapcs_vfpcc <2 x double> @insert_f64(double %a) {
; CHECK-LABEL: insert_f64: ; CHECK-LABEL: insert_f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%res = insertelement <2 x double> undef, double %a, i32 0 %res = insertelement <2 x double> undef, double %a, i32 0
ret <2 x double> %res ret <2 x double> %res
} }
define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) { define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) {
; CHECK-LABEL: scalar_to_vector_i32: ; CHECK-LABEL: scalar_to_vector_i32:
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entry: entry:
%res = extractelement <2 x i64> %a, i32 1 %res = extractelement <2 x i64> %a, i32 1
ret i64 %res ret i64 %res
} }
define arm_aapcs_vfpcc float @extract_f32_0(<4 x float> %a) { define arm_aapcs_vfpcc float @extract_f32_0(<4 x float> %a) {
; CHECK-LABEL: extract_f32_0: ; CHECK-LABEL: extract_f32_0:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%res = extractelement <4 x float> %a, i32 0 %res = extractelement <4 x float> %a, i32 0
ret float %res ret float %res
} }
define arm_aapcs_vfpcc float @extract_f32_3(<4 x float> %a) { define arm_aapcs_vfpcc float @extract_f32_3(<4 x float> %a) {
; CHECK-LABEL: extract_f32_3: ; CHECK-LABEL: extract_f32_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s0, s3 ; CHECK-NEXT: vmov.f32 s0, s3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%res = extractelement <4 x float> %a, i32 3 %res = extractelement <4 x float> %a, i32 3
ret float %res ret float %res
} }
define arm_aapcs_vfpcc half @extract_f16_0(<8 x half> %a) { define arm_aapcs_vfpcc half @extract_f16_0(<8 x half> %a) {
; CHECK-LABEL: extract_f16_0: ; CHECK-LABEL: extract_f16_0:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%res = extractelement <8 x half> %a, i32 0 %res = extractelement <8 x half> %a, i32 0
ret half %res ret half %res
} }
define arm_aapcs_vfpcc half @extract_f16_3(<8 x half> %a) { define arm_aapcs_vfpcc half @extract_f16_3(<8 x half> %a) {
; CHECK-LABEL: extract_f16_3: ; CHECK-LABEL: extract_f16_3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%res = extractelement <8 x half> %a, i32 3 %res = extractelement <8 x half> %a, i32 3
ret half %res ret half %res
} }
define arm_aapcs_vfpcc double @extract_f64_0(<2 x double> %a) { define arm_aapcs_vfpcc double @extract_f64_0(<2 x double> %a) {
; CHECK-LABEL: extract_f64_0: ; CHECK-LABEL: extract_f64_0:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%res = extractelement <2 x double> %a, i32 0 %res = extractelement <2 x double> %a, i32 0
ret double %res ret double %res
} }
define arm_aapcs_vfpcc double @extract_f64_1(<2 x double> %a) { define arm_aapcs_vfpcc double @extract_f64_1(<2 x double> %a) {
; CHECK-LABEL: extract_f64_1: ; CHECK-LABEL: extract_f64_1:
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llvm/test/CodeGen/Thumb2/mve-shuffleext.ll

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define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357_swapped(<8 x i16> %src) { define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357_swapped(<8 x i16> %src) {
; CHECK-LABEL: sext_i32_1357_swapped: ; CHECK-LABEL: sext_i32_1357_swapped:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: mov r0, sp ; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: vldrh.s32 q2, [r0] ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vldrh.s32 q1, [r0, #8] ; CHECK-NEXT: vldrh.s32 q1, [r0, #8]
; CHECK-NEXT: vmov.f32 s0, s9 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s1, s11 ; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmov.f32 s2, s5 ; CHECK-NEXT: vmov.f32 s2, s5
; CHECK-NEXT: vmov.f32 s3, s7 ; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = sext <8 x i16> %src to <8 x i32> %out = sext <8 x i16> %src to <8 x i32>
%strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret <4 x i32> %strided.vec ret <4 x i32> %strided.vec
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; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vldrh.s32 q0, [r0] ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vldrh.s32 q1, [r0, #8] ; CHECK-NEXT: vldrh.s32 q1, [r0, #8]
; CHECK-NEXT: vldrh.s32 q2, [r1, #8] ; CHECK-NEXT: vldrh.s32 q2, [r1, #8]
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vldrh.s32 q1, [r1] ; CHECK-NEXT: vldrh.s32 q1, [r1]
; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: vmov.f32 s5, s6 ; CHECK-NEXT: vmov.f32 s5, s6
; CHECK-NEXT: vmov.f32 s6, s8 ; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = sext <16 x i16> %src to <16 x i32> %out = sext <16 x i16> %src to <16 x i32>
%strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
ret <8 x i32> %strided.vec ret <8 x i32> %strided.vec
} }
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; CHECK-LABEL: sext_i32_13579111315_swapped: ; CHECK-LABEL: sext_i32_13579111315_swapped:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #32
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: mov r0, sp ; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: add r1, sp, #16 ; CHECK-NEXT: add r1, sp, #16
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vldrh.s32 q2, [r0] ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vldrh.s32 q1, [r0, #8] ; CHECK-NEXT: vldrh.s32 q1, [r0, #8]
; CHECK-NEXT: vldrh.s32 q3, [r1]
; CHECK-NEXT: vmov.f32 s0, s9
; CHECK-NEXT: vmov.f32 s1, s11
; CHECK-NEXT: vldrh.s32 q2, [r1, #8] ; CHECK-NEXT: vldrh.s32 q2, [r1, #8]
; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmov.f32 s2, s5 ; CHECK-NEXT: vmov.f32 s2, s5
; CHECK-NEXT: vmov.f32 s3, s7 ; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vmov.f32 s4, s13 ; CHECK-NEXT: vldrh.s32 q1, [r1]
; CHECK-NEXT: vmov.f32 s5, s15
; CHECK-NEXT: vmov.f32 s6, s9 ; CHECK-NEXT: vmov.f32 s6, s9
; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vmov.f32 s7, s11 ; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = sext <16 x i16> %src to <16 x i32> %out = sext <16 x i16> %src to <16 x i32>
%strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret <8 x i32> %strided.vec ret <8 x i32> %strided.vec
} }
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define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357_swapped(<8 x i16> %src) { define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357_swapped(<8 x i16> %src) {
; CHECK-LABEL: zext_i32_1357_swapped: ; CHECK-LABEL: zext_i32_1357_swapped:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: mov r0, sp ; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: vldrh.u32 q2, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vldrh.u32 q1, [r0, #8] ; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
; CHECK-NEXT: vmov.f32 s0, s9 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s1, s11 ; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmov.f32 s2, s5 ; CHECK-NEXT: vmov.f32 s2, s5
; CHECK-NEXT: vmov.f32 s3, s7 ; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = zext <8 x i16> %src to <8 x i32> %out = zext <8 x i16> %src to <8 x i32>
%strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret <4 x i32> %strided.vec ret <4 x i32> %strided.vec
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; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vldrh.u32 q0, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vldrh.u32 q1, [r0, #8] ; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
; CHECK-NEXT: vldrh.u32 q2, [r1, #8] ; CHECK-NEXT: vldrh.u32 q2, [r1, #8]
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vldrh.u32 q1, [r1] ; CHECK-NEXT: vldrh.u32 q1, [r1]
; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: vmov.f32 s5, s6 ; CHECK-NEXT: vmov.f32 s5, s6
; CHECK-NEXT: vmov.f32 s6, s8 ; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = zext <16 x i16> %src to <16 x i32> %out = zext <16 x i16> %src to <16 x i32>
%strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
ret <8 x i32> %strided.vec ret <8 x i32> %strided.vec
} }
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; CHECK-LABEL: zext_i32_13579111315_swapped: ; CHECK-LABEL: zext_i32_13579111315_swapped:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #32
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: mov r0, sp ; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: add r1, sp, #16 ; CHECK-NEXT: add r1, sp, #16
; CHECK-NEXT: vstrw.32 q0, [r0] ; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vldrh.u32 q2, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: vldrh.u32 q1, [r0, #8] ; CHECK-NEXT: vldrh.u32 q1, [r0, #8]
; CHECK-NEXT: vldrh.u32 q3, [r1]
; CHECK-NEXT: vmov.f32 s0, s9
; CHECK-NEXT: vmov.f32 s1, s11
; CHECK-NEXT: vldrh.u32 q2, [r1, #8] ; CHECK-NEXT: vldrh.u32 q2, [r1, #8]
; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmov.f32 s2, s5 ; CHECK-NEXT: vmov.f32 s2, s5
; CHECK-NEXT: vmov.f32 s3, s7 ; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vmov.f32 s4, s13 ; CHECK-NEXT: vldrh.u32 q1, [r1]
; CHECK-NEXT: vmov.f32 s5, s15
; CHECK-NEXT: vmov.f32 s6, s9 ; CHECK-NEXT: vmov.f32 s6, s9
; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vmov.f32 s7, s11 ; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = zext <16 x i16> %src to <16 x i32> %out = zext <16 x i16> %src to <16 x i32>
%strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret <8 x i32> %strided.vec ret <8 x i32> %strided.vec
} }
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llvm/test/CodeGen/Thumb2/mve-shufflemov.ll

Show All 31 Linesentry:
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_76543210(<8 x i16> %s1, <8 x i16> %s2) { define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_76543210(<8 x i16> %s1, <8 x i16> %s2) {
; CHECK-LABEL: shuffle_i16_76543210: ; CHECK-LABEL: shuffle_i16_76543210:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s0, s7 ; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vmovx.f16 s1, s6 ; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vmovx.f16 s3, s4 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_01234567(<8 x i16> %s1, <8 x i16> %s2) { define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_01234567(<8 x i16> %s1, <8 x i16> %s2) {
▲ Show 20 Lines • Show All 281 Lines • ▼ Show 20 Linesentry:
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_76543210(<8 x half> %s1, <8 x half> %s2) { define arm_aapcs_vfpcc <8 x half> @shuffle_f16_76543210(<8 x half> %s1, <8 x half> %s2) {
; CHECK-LABEL: shuffle_f16_76543210: ; CHECK-LABEL: shuffle_f16_76543210:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmovx.f16 s0, s7 ; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vmovx.f16 s1, s6 ; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vmovx.f16 s3, s4 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vins.f16 s0, s7
; CHECK-NEXT: vins.f16 s1, s6
; CHECK-NEXT: vins.f16 s2, s5
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_01234567(<8 x half> %s1, <8 x half> %s2) { define arm_aapcs_vfpcc <8 x half> @shuffle_f16_01234567(<8 x half> %s1, <8 x half> %s2) {
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llvm/test/CodeGen/Thumb2/mve-simple-arith.ll

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entry: entry:
%0 = add nsw <2 x i64> %src1, %src2 %0 = add nsw <2 x i64> %src1, %src2
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <4 x float> @add_float32_t(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <4 x float> @add_float32_t(<4 x float> %src1, <4 x float> %src2) {
; CHECK-MVE-LABEL: add_float32_t: ; CHECK-MVE-LABEL: add_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vadd.f32 s11, s7, s3 ; CHECK-MVE-NEXT: vadd.f32 s3, s7, s3
; CHECK-MVE-NEXT: vadd.f32 s10, s6, s2 ; CHECK-MVE-NEXT: vadd.f32 s2, s6, s2
; CHECK-MVE-NEXT: vadd.f32 s9, s5, s1 ; CHECK-MVE-NEXT: vadd.f32 s1, s5, s1
; CHECK-MVE-NEXT: vadd.f32 s8, s4, s0 ; CHECK-MVE-NEXT: vadd.f32 s0, s4, s0
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: add_float32_t: ; CHECK-MVEFP-LABEL: add_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vadd.f32 q0, q1, q0 ; CHECK-MVEFP-NEXT: vadd.f32 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fadd nnan ninf nsz <4 x float> %src2, %src1 %0 = fadd nnan ninf nsz <4 x float> %src2, %src1
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @add_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @add_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: add_float16_t: ; CHECK-MVE-LABEL: add_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q2, q0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s0
; CHECK-MVE-NEXT: vmovx.f16 s2, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmovx.f16 s0, s8 ; CHECK-MVE-NEXT: vadd.f16 s0, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vadd.f16 s8, s10, s8
; CHECK-MVE-NEXT: vadd.f16 s12, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vadd.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s12, s9 ; CHECK-MVE-NEXT: vadd.f16 s1, s5, s1
; CHECK-MVE-NEXT: vadd.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vadd.f16 s4, s8, s4
; CHECK-MVE-NEXT: vadd.f16 s1, s5, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vins.f16 s1, s12 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s12, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vadd.f16 s2, s6, s2
; CHECK-MVE-NEXT: vadd.f16 s2, s6, s10 ; CHECK-MVE-NEXT: vadd.f16 s4, s8, s4
; CHECK-MVE-NEXT: vadd.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s14, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vins.f16 s2, s12 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vmovx.f16 s12, s11 ; CHECK-MVE-NEXT: vadd.f16 s3, s7, s3
; CHECK-MVE-NEXT: vadd.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vadd.f16 s4, s6, s4
; CHECK-MVE-NEXT: vadd.f16 s3, s7, s11 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s12
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: add_float16_t: ; CHECK-MVEFP-LABEL: add_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vadd.f16 q0, q1, q0 ; CHECK-MVEFP-NEXT: vadd.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fadd nnan ninf nsz <8 x half> %src2, %src1 %0 = fadd nnan ninf nsz <8 x half> %src2, %src1
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entry: entry:
%0 = sub nsw <2 x i64> %src2, %src1 %0 = sub nsw <2 x i64> %src2, %src1
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <4 x float> @sub_float32_t(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <4 x float> @sub_float32_t(<4 x float> %src1, <4 x float> %src2) {
; CHECK-MVE-LABEL: sub_float32_t: ; CHECK-MVE-LABEL: sub_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vsub.f32 s11, s7, s3 ; CHECK-MVE-NEXT: vsub.f32 s3, s7, s3
; CHECK-MVE-NEXT: vsub.f32 s10, s6, s2 ; CHECK-MVE-NEXT: vsub.f32 s2, s6, s2
; CHECK-MVE-NEXT: vsub.f32 s9, s5, s1 ; CHECK-MVE-NEXT: vsub.f32 s1, s5, s1
; CHECK-MVE-NEXT: vsub.f32 s8, s4, s0 ; CHECK-MVE-NEXT: vsub.f32 s0, s4, s0
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: sub_float32_t: ; CHECK-MVEFP-LABEL: sub_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vsub.f32 q0, q1, q0 ; CHECK-MVEFP-NEXT: vsub.f32 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fsub nnan ninf nsz <4 x float> %src2, %src1 %0 = fsub nnan ninf nsz <4 x float> %src2, %src1
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @sub_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @sub_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: sub_float16_t: ; CHECK-MVE-LABEL: sub_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q2, q0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s0
; CHECK-MVE-NEXT: vmovx.f16 s2, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmovx.f16 s0, s8 ; CHECK-MVE-NEXT: vsub.f16 s0, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vsub.f16 s8, s10, s8
; CHECK-MVE-NEXT: vsub.f16 s12, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vsub.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s12, s9 ; CHECK-MVE-NEXT: vsub.f16 s1, s5, s1
; CHECK-MVE-NEXT: vsub.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vsub.f16 s4, s8, s4
; CHECK-MVE-NEXT: vsub.f16 s1, s5, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vins.f16 s1, s12 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s12, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vsub.f16 s2, s6, s2
; CHECK-MVE-NEXT: vsub.f16 s2, s6, s10 ; CHECK-MVE-NEXT: vsub.f16 s4, s8, s4
; CHECK-MVE-NEXT: vsub.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s14, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vins.f16 s2, s12 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vmovx.f16 s12, s11 ; CHECK-MVE-NEXT: vsub.f16 s3, s7, s3
; CHECK-MVE-NEXT: vsub.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vsub.f16 s4, s6, s4
; CHECK-MVE-NEXT: vsub.f16 s3, s7, s11 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s12
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: sub_float16_t: ; CHECK-MVEFP-LABEL: sub_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vsub.f16 q0, q1, q0 ; CHECK-MVEFP-NEXT: vsub.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fsub nnan ninf nsz <8 x half> %src2, %src1 %0 = fsub nnan ninf nsz <8 x half> %src2, %src1
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entry: entry:
%0 = mul nsw <2 x i64> %src1, %src2 %0 = mul nsw <2 x i64> %src1, %src2
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <8 x half> @mul_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @mul_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-MVE-LABEL: mul_float16_t: ; CHECK-MVE-LABEL: mul_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q2, q0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s0
; CHECK-MVE-NEXT: vmovx.f16 s2, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmovx.f16 s0, s8 ; CHECK-MVE-NEXT: vmul.f16 s0, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s14, s5 ; CHECK-MVE-NEXT: vmul.f16 s8, s10, s8
; CHECK-MVE-NEXT: vmul.f16 s12, s2, s0 ; CHECK-MVE-NEXT: vins.f16 s0, s8
; CHECK-MVE-NEXT: vmul.f16 s0, s4, s8 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s12, s9 ; CHECK-MVE-NEXT: vmul.f16 s1, s5, s1
; CHECK-MVE-NEXT: vmul.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmul.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmul.f16 s1, s5, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vins.f16 s1, s12 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s12, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s14, s6 ; CHECK-MVE-NEXT: vmul.f16 s2, s6, s2
; CHECK-MVE-NEXT: vmul.f16 s2, s6, s10 ; CHECK-MVE-NEXT: vmul.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmul.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s14, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vins.f16 s2, s12 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vmovx.f16 s12, s11 ; CHECK-MVE-NEXT: vmul.f16 s3, s7, s3
; CHECK-MVE-NEXT: vmul.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmul.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmul.f16 s3, s7, s11 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s12
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: mul_float16_t: ; CHECK-MVEFP-LABEL: mul_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmul.f16 q0, q1, q0 ; CHECK-MVEFP-NEXT: vmul.f16 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fmul nnan ninf nsz <8 x half> %src2, %src1 %0 = fmul nnan ninf nsz <8 x half> %src2, %src1
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <4 x float> @mul_float32_t(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <4 x float> @mul_float32_t(<4 x float> %src1, <4 x float> %src2) {
; CHECK-MVE-LABEL: mul_float32_t: ; CHECK-MVE-LABEL: mul_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmul.f32 s11, s7, s3 ; CHECK-MVE-NEXT: vmul.f32 s3, s7, s3
; CHECK-MVE-NEXT: vmul.f32 s10, s6, s2 ; CHECK-MVE-NEXT: vmul.f32 s2, s6, s2
; CHECK-MVE-NEXT: vmul.f32 s9, s5, s1 ; CHECK-MVE-NEXT: vmul.f32 s1, s5, s1
; CHECK-MVE-NEXT: vmul.f32 s8, s4, s0 ; CHECK-MVE-NEXT: vmul.f32 s0, s4, s0
; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: mul_float32_t: ; CHECK-MVEFP-LABEL: mul_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmul.f32 q0, q1, q0 ; CHECK-MVEFP-NEXT: vmul.f32 q0, q1, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%0 = fmul nnan ninf nsz <4 x float> %src2, %src1 %0 = fmul nnan ninf nsz <4 x float> %src2, %src1
Show All 30 Lines

llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -o - %s | FileCheck %s --check-prefixes=CHECK-LE,CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve -o - %s | FileCheck %s --check-prefixes=CHECK-LE,CHECK-MVE
; RUN: llc -mtriple=thumbebv8.1m.main-none-eabi -mattr=+mve -o - %s | FileCheck %s --check-prefix=CHECK-BE ; RUN: llc -mtriple=thumbebv8.1m.main-none-eabi -mattr=+mve -o - %s | FileCheck %s --check-prefix=CHECK-BE
; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -o - %s | FileCheck %s --check-prefixes=CHECK-LE,CHECK-FP ; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -o - %s | FileCheck %s --check-prefixes=CHECK-LE,CHECK-FP
define <16 x i8> @vector_add_i8(<16 x i8> %lhs, <16 x i8> %rhs) { define <16 x i8> @vector_add_i8(<16 x i8> %lhs, <16 x i8> %rhs) {
; CHECK-LE-LABEL: vector_add_i8: ; CHECK-LE-LABEL: vector_add_i8:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vmov d1, r2, r3
; CHECK-LE-NEXT: vmov d0, r0, r1 ; CHECK-LE-NEXT: vmov d0, r0, r1
; CHECK-LE-NEXT: mov r0, sp ; CHECK-LE-NEXT: mov r0, sp
; CHECK-LE-NEXT: vldrw.u32 q1, [r0] ; CHECK-LE-NEXT: vldrw.u32 q1, [r0]
; CHECK-LE-NEXT: vmov d1, r2, r3
; CHECK-LE-NEXT: vadd.i8 q0, q0, q1 ; CHECK-LE-NEXT: vadd.i8 q0, q0, q1
; CHECK-LE-NEXT: vmov r0, r1, d0 ; CHECK-LE-NEXT: vmov r0, r1, d0
; CHECK-LE-NEXT: vmov r2, r3, d1 ; CHECK-LE-NEXT: vmov r2, r3, d1
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: vector_add_i8: ; CHECK-BE-LABEL: vector_add_i8:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vmov d0, r1, r0 ; CHECK-BE-NEXT: vmov d0, r1, r0
; CHECK-BE-NEXT: mov r0, sp ; CHECK-BE-NEXT: mov r0, sp
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vrev64.8 q1, q0 ; CHECK-BE-NEXT: vrev64.8 q1, q0
; CHECK-BE-NEXT: vldrb.u8 q0, [r0] ; CHECK-BE-NEXT: vldrb.u8 q0, [r0]
; CHECK-BE-NEXT: vadd.i8 q0, q1, q0 ; CHECK-BE-NEXT: vadd.i8 q0, q1, q0
; CHECK-BE-NEXT: vrev64.8 q1, q0 ; CHECK-BE-NEXT: vrev64.8 q1, q0
; CHECK-BE-NEXT: vmov r1, r0, d2 ; CHECK-BE-NEXT: vmov r1, r0, d2
; CHECK-BE-NEXT: vmov r3, r2, d3 ; CHECK-BE-NEXT: vmov r3, r2, d3
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%sum = add <16 x i8> %lhs, %rhs %sum = add <16 x i8> %lhs, %rhs
ret <16 x i8> %sum ret <16 x i8> %sum
} }
define <8 x i16> @vector_add_i16(<8 x i16> %lhs, <8 x i16> %rhs) { define <8 x i16> @vector_add_i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; CHECK-LE-LABEL: vector_add_i16: ; CHECK-LE-LABEL: vector_add_i16:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vmov d1, r2, r3
; CHECK-LE-NEXT: vmov d0, r0, r1 ; CHECK-LE-NEXT: vmov d0, r0, r1
; CHECK-LE-NEXT: mov r0, sp ; CHECK-LE-NEXT: mov r0, sp
; CHECK-LE-NEXT: vldrw.u32 q1, [r0] ; CHECK-LE-NEXT: vldrw.u32 q1, [r0]
; CHECK-LE-NEXT: vmov d1, r2, r3
; CHECK-LE-NEXT: vadd.i16 q0, q0, q1 ; CHECK-LE-NEXT: vadd.i16 q0, q0, q1
; CHECK-LE-NEXT: vmov r0, r1, d0 ; CHECK-LE-NEXT: vmov r0, r1, d0
; CHECK-LE-NEXT: vmov r2, r3, d1 ; CHECK-LE-NEXT: vmov r2, r3, d1
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: vector_add_i16: ; CHECK-BE-LABEL: vector_add_i16:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vmov d0, r1, r0 ; CHECK-BE-NEXT: vmov d0, r1, r0
; CHECK-BE-NEXT: mov r0, sp ; CHECK-BE-NEXT: mov r0, sp
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vrev64.16 q1, q0 ; CHECK-BE-NEXT: vrev64.16 q1, q0
; CHECK-BE-NEXT: vldrh.u16 q0, [r0] ; CHECK-BE-NEXT: vldrh.u16 q0, [r0]
; CHECK-BE-NEXT: vadd.i16 q0, q1, q0 ; CHECK-BE-NEXT: vadd.i16 q0, q1, q0
; CHECK-BE-NEXT: vrev64.16 q1, q0 ; CHECK-BE-NEXT: vrev64.16 q1, q0
; CHECK-BE-NEXT: vmov r1, r0, d2 ; CHECK-BE-NEXT: vmov r1, r0, d2
; CHECK-BE-NEXT: vmov r3, r2, d3 ; CHECK-BE-NEXT: vmov r3, r2, d3
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%sum = add <8 x i16> %lhs, %rhs %sum = add <8 x i16> %lhs, %rhs
ret <8 x i16> %sum ret <8 x i16> %sum
} }
define <4 x i32> @vector_add_i32(<4 x i32> %lhs, <4 x i32> %rhs) { define <4 x i32> @vector_add_i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; CHECK-LE-LABEL: vector_add_i32: ; CHECK-LE-LABEL: vector_add_i32:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vmov d1, r2, r3
; CHECK-LE-NEXT: vmov d0, r0, r1 ; CHECK-LE-NEXT: vmov d0, r0, r1
; CHECK-LE-NEXT: mov r0, sp ; CHECK-LE-NEXT: mov r0, sp
; CHECK-LE-NEXT: vldrw.u32 q1, [r0] ; CHECK-LE-NEXT: vldrw.u32 q1, [r0]
; CHECK-LE-NEXT: vmov d1, r2, r3
; CHECK-LE-NEXT: vadd.i32 q0, q0, q1 ; CHECK-LE-NEXT: vadd.i32 q0, q0, q1
; CHECK-LE-NEXT: vmov r0, r1, d0 ; CHECK-LE-NEXT: vmov r0, r1, d0
; CHECK-LE-NEXT: vmov r2, r3, d1 ; CHECK-LE-NEXT: vmov r2, r3, d1
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: vector_add_i32: ; CHECK-BE-LABEL: vector_add_i32:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vmov d0, r1, r0 ; CHECK-BE-NEXT: vmov d0, r1, r0
; CHECK-BE-NEXT: mov r0, sp ; CHECK-BE-NEXT: mov r0, sp
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: vldrw.u32 q0, [r0] ; CHECK-BE-NEXT: vldrw.u32 q0, [r0]
; CHECK-BE-NEXT: vadd.i32 q0, q1, q0 ; CHECK-BE-NEXT: vadd.i32 q0, q1, q0
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: vmov r1, r0, d2 ; CHECK-BE-NEXT: vmov r1, r0, d2
; CHECK-BE-NEXT: vmov r3, r2, d3 ; CHECK-BE-NEXT: vmov r3, r2, d3
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
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define <8 x half> @vector_add_f16(<8 x half> %lhs, <8 x half> %rhs) { define <8 x half> @vector_add_f16(<8 x half> %lhs, <8 x half> %rhs) {
; CHECK-MVE-LABEL: vector_add_f16: ; CHECK-MVE-LABEL: vector_add_f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .save {r4, r5, r7, lr} ; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
; CHECK-MVE-NEXT: push {r4, r5, r7, lr} ; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-MVE-NEXT: vmov d9, r2, r3
; CHECK-MVE-NEXT: vmov d8, r0, r1 ; CHECK-MVE-NEXT: vmov d8, r0, r1
; CHECK-MVE-NEXT: add r0, sp, #64 ; CHECK-MVE-NEXT: add r0, sp, #64
; CHECK-MVE-NEXT: vldrw.u32 q6, [r0] ; CHECK-MVE-NEXT: vldrw.u32 q6, [r0]
; CHECK-MVE-NEXT: vmov d9, r2, r3
; CHECK-MVE-NEXT: vmov.u16 r4, q4[0] ; CHECK-MVE-NEXT: vmov.u16 r4, q4[0]
; CHECK-MVE-NEXT: vmov.u16 r0, q6[0] ; CHECK-MVE-NEXT: vmov.u16 r0, q6[0]
; CHECK-MVE-NEXT: bl __aeabi_h2f ; CHECK-MVE-NEXT: bl __aeabi_h2f
; CHECK-MVE-NEXT: mov r5, r0 ; CHECK-MVE-NEXT: mov r5, r0
; CHECK-MVE-NEXT: mov r0, r4 ; CHECK-MVE-NEXT: mov r0, r4
; CHECK-MVE-NEXT: bl __aeabi_h2f ; CHECK-MVE-NEXT: bl __aeabi_h2f
; CHECK-MVE-NEXT: mov r1, r5 ; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fadd ; CHECK-MVE-NEXT: bl __aeabi_fadd
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; CHECK-MVE-NEXT: pop {r4, r5, r7, pc} ; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
; ;
; CHECK-BE-LABEL: vector_add_f16: ; CHECK-BE-LABEL: vector_add_f16:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r4, r5, r7, lr} ; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
; CHECK-BE-NEXT: push {r4, r5, r7, lr} ; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-BE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-BE-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-BE-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vmov d0, r1, r0 ; CHECK-BE-NEXT: vmov d0, r1, r0
; CHECK-BE-NEXT: add r0, sp, #64 ; CHECK-BE-NEXT: add r0, sp, #64
; CHECK-BE-NEXT: vldrh.u16 q6, [r0] ; CHECK-BE-NEXT: vldrh.u16 q6, [r0]
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vrev64.16 q4, q0 ; CHECK-BE-NEXT: vrev64.16 q4, q0
; CHECK-BE-NEXT: vmov.u16 r4, q4[0]
; CHECK-BE-NEXT: vmov.u16 r0, q6[0] ; CHECK-BE-NEXT: vmov.u16 r0, q6[0]
; CHECK-BE-NEXT: vmov.u16 r4, q4[0]
; CHECK-BE-NEXT: bl __aeabi_h2f ; CHECK-BE-NEXT: bl __aeabi_h2f
; CHECK-BE-NEXT: mov r5, r0 ; CHECK-BE-NEXT: mov r5, r0
; CHECK-BE-NEXT: mov r0, r4 ; CHECK-BE-NEXT: mov r0, r4
; CHECK-BE-NEXT: bl __aeabi_h2f ; CHECK-BE-NEXT: bl __aeabi_h2f
; CHECK-BE-NEXT: mov r1, r5 ; CHECK-BE-NEXT: mov r1, r5
; CHECK-BE-NEXT: bl __aeabi_fadd ; CHECK-BE-NEXT: bl __aeabi_fadd
; CHECK-BE-NEXT: bl __aeabi_f2h ; CHECK-BE-NEXT: bl __aeabi_f2h
; CHECK-BE-NEXT: vmov.16 q5[0], r0 ; CHECK-BE-NEXT: vmov.16 q5[0], r0
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; CHECK-BE-NEXT: vrev64.16 q0, q5 ; CHECK-BE-NEXT: vrev64.16 q0, q5
; CHECK-BE-NEXT: vmov r1, r0, d0 ; CHECK-BE-NEXT: vmov r1, r0, d0
; CHECK-BE-NEXT: vmov r3, r2, d1 ; CHECK-BE-NEXT: vmov r3, r2, d1
; CHECK-BE-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-BE-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-BE-NEXT: pop {r4, r5, r7, pc} ; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
; ;
; CHECK-FP-LABEL: vector_add_f16: ; CHECK-FP-LABEL: vector_add_f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov d1, r2, r3
; CHECK-FP-NEXT: vmov d0, r0, r1 ; CHECK-FP-NEXT: vmov d0, r0, r1
; CHECK-FP-NEXT: mov r0, sp ; CHECK-FP-NEXT: mov r0, sp
; CHECK-FP-NEXT: vldrw.u32 q1, [r0] ; CHECK-FP-NEXT: vldrw.u32 q1, [r0]
; CHECK-FP-NEXT: vmov d1, r2, r3
; CHECK-FP-NEXT: vadd.f16 q0, q0, q1 ; CHECK-FP-NEXT: vadd.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov r0, r1, d0 ; CHECK-FP-NEXT: vmov r0, r1, d0
; CHECK-FP-NEXT: vmov r2, r3, d1 ; CHECK-FP-NEXT: vmov r2, r3, d1
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
entry: entry:
%sum = fadd <8 x half> %lhs, %rhs %sum = fadd <8 x half> %lhs, %rhs
ret <8 x half> %sum ret <8 x half> %sum
} }
define <4 x float> @vector_add_f32(<4 x float> %lhs, <4 x float> %rhs) { define <4 x float> @vector_add_f32(<4 x float> %lhs, <4 x float> %rhs) {
; CHECK-MVE-LABEL: vector_add_f32: ; CHECK-MVE-LABEL: vector_add_f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-MVE-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-MVE-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-MVE-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-MVE-NEXT: .pad #4 ; CHECK-MVE-NEXT: .pad #4
; CHECK-MVE-NEXT: sub sp, #4 ; CHECK-MVE-NEXT: sub sp, #4
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: mov r4, r0 ; CHECK-MVE-NEXT: mov r4, r0
; CHECK-MVE-NEXT: add r0, sp, #56 ; CHECK-MVE-NEXT: add r0, sp, #40
; CHECK-MVE-NEXT: vldrw.u32 q5, [r0] ; CHECK-MVE-NEXT: vldrw.u32 q4, [r0]
; CHECK-MVE-NEXT: mov r6, r1 ; CHECK-MVE-NEXT: mov r6, r1
; CHECK-MVE-NEXT: mov r0, r3 ; CHECK-MVE-NEXT: mov r0, r3
; CHECK-MVE-NEXT: mov r5, r2 ; CHECK-MVE-NEXT: mov r5, r2
; CHECK-MVE-NEXT: vmov r7, r1, d11 ; CHECK-MVE-NEXT: vmov r7, r1, d9
; CHECK-MVE-NEXT: bl __aeabi_fadd ; CHECK-MVE-NEXT: bl __aeabi_fadd
; CHECK-MVE-NEXT: vmov s19, r0 ; CHECK-MVE-NEXT: vmov s19, r0
; CHECK-MVE-NEXT: mov r0, r5 ; CHECK-MVE-NEXT: mov r0, r5
; CHECK-MVE-NEXT: mov r1, r7 ; CHECK-MVE-NEXT: mov r1, r7
; CHECK-MVE-NEXT: bl __aeabi_fadd ; CHECK-MVE-NEXT: bl __aeabi_fadd
; CHECK-MVE-NEXT: vmov r5, r1, d10 ; CHECK-MVE-NEXT: vmov r5, r1, d8
; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: vmov s18, r0
; CHECK-MVE-NEXT: mov r0, r6 ; CHECK-MVE-NEXT: mov r0, r6
; CHECK-MVE-NEXT: bl __aeabi_fadd ; CHECK-MVE-NEXT: bl __aeabi_fadd
; CHECK-MVE-NEXT: vmov s17, r0 ; CHECK-MVE-NEXT: vmov s17, r0
; CHECK-MVE-NEXT: mov r0, r4 ; CHECK-MVE-NEXT: mov r0, r4
; CHECK-MVE-NEXT: mov r1, r5 ; CHECK-MVE-NEXT: mov r1, r5
; CHECK-MVE-NEXT: bl __aeabi_fadd ; CHECK-MVE-NEXT: bl __aeabi_fadd
; CHECK-MVE-NEXT: vmov s16, r0 ; CHECK-MVE-NEXT: vmov s16, r0
; CHECK-MVE-NEXT: vmov r2, r3, d9 ; CHECK-MVE-NEXT: vmov r2, r3, d9
; CHECK-MVE-NEXT: vmov r0, r1, d8 ; CHECK-MVE-NEXT: vmov r0, r1, d8
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: add sp, #4 ; CHECK-MVE-NEXT: add sp, #4
; CHECK-MVE-NEXT: pop {r4, r5, r6, r7, pc} ; CHECK-MVE-NEXT: pop {r4, r5, r6, r7, pc}
; ;
; CHECK-BE-LABEL: vector_add_f32: ; CHECK-BE-LABEL: vector_add_f32:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r4, r5, r7, lr} ; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
; CHECK-BE-NEXT: push {r4, r5, r7, lr} ; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-BE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-BE-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-BE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vmov d0, r1, r0 ; CHECK-BE-NEXT: vmov d0, r1, r0
; CHECK-BE-NEXT: add r1, sp, #64 ; CHECK-BE-NEXT: add r1, sp, #48
; CHECK-BE-NEXT: vldrw.u32 q6, [r1] ; CHECK-BE-NEXT: vldrw.u32 q5, [r1]
; CHECK-BE-NEXT: vrev64.32 q5, q0 ; CHECK-BE-NEXT: vmov d1, r3, r2
; CHECK-BE-NEXT: vmov r4, r0, d11 ; CHECK-BE-NEXT: vrev64.32 q4, q0
; CHECK-BE-NEXT: vmov r5, r1, d13 ; CHECK-BE-NEXT: vmov r4, r0, d9
; CHECK-BE-NEXT: vmov r5, r1, d11
; CHECK-BE-NEXT: bl __aeabi_fadd ; CHECK-BE-NEXT: bl __aeabi_fadd
; CHECK-BE-NEXT: vmov s19, r0 ; CHECK-BE-NEXT: vmov s19, r0
; CHECK-BE-NEXT: mov r0, r4 ; CHECK-BE-NEXT: mov r0, r4
; CHECK-BE-NEXT: mov r1, r5 ; CHECK-BE-NEXT: mov r1, r5
; CHECK-BE-NEXT: bl __aeabi_fadd ; CHECK-BE-NEXT: bl __aeabi_fadd
; CHECK-BE-NEXT: vmov s18, r0 ; CHECK-BE-NEXT: vmov s18, r0
; CHECK-BE-NEXT: vmov r4, r0, d10 ; CHECK-BE-NEXT: vmov r4, r0, d8
; CHECK-BE-NEXT: vmov r5, r1, d12 ; CHECK-BE-NEXT: vmov r5, r1, d10
; CHECK-BE-NEXT: bl __aeabi_fadd ; CHECK-BE-NEXT: bl __aeabi_fadd
; CHECK-BE-NEXT: vmov s17, r0 ; CHECK-BE-NEXT: vmov s17, r0
; CHECK-BE-NEXT: mov r0, r4 ; CHECK-BE-NEXT: mov r0, r4
; CHECK-BE-NEXT: mov r1, r5 ; CHECK-BE-NEXT: mov r1, r5
; CHECK-BE-NEXT: bl __aeabi_fadd ; CHECK-BE-NEXT: bl __aeabi_fadd
; CHECK-BE-NEXT: vmov s16, r0 ; CHECK-BE-NEXT: vmov s16, r0
; CHECK-BE-NEXT: vrev64.32 q0, q4 ; CHECK-BE-NEXT: vrev64.32 q0, q4
; CHECK-BE-NEXT: vmov r1, r0, d0 ; CHECK-BE-NEXT: vmov r1, r0, d0
; CHECK-BE-NEXT: vmov r3, r2, d1 ; CHECK-BE-NEXT: vmov r3, r2, d1
; CHECK-BE-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-BE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-BE-NEXT: pop {r4, r5, r7, pc} ; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
; ;
; CHECK-FP-LABEL: vector_add_f32: ; CHECK-FP-LABEL: vector_add_f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov d1, r2, r3
; CHECK-FP-NEXT: vmov d0, r0, r1 ; CHECK-FP-NEXT: vmov d0, r0, r1
; CHECK-FP-NEXT: mov r0, sp ; CHECK-FP-NEXT: mov r0, sp
; CHECK-FP-NEXT: vldrw.u32 q1, [r0] ; CHECK-FP-NEXT: vldrw.u32 q1, [r0]
; CHECK-FP-NEXT: vmov d1, r2, r3
; CHECK-FP-NEXT: vadd.f32 q0, q0, q1 ; CHECK-FP-NEXT: vadd.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov r0, r1, d0 ; CHECK-FP-NEXT: vmov r0, r1, d0
; CHECK-FP-NEXT: vmov r2, r3, d1 ; CHECK-FP-NEXT: vmov r2, r3, d1
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
entry: entry:
%sum = fadd <4 x float> %lhs, %rhs %sum = fadd <4 x float> %lhs, %rhs
ret <4 x float> %sum ret <4 x float> %sum
} }
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llvm/test/CodeGen/Thumb2/mve-vabdus.ll

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define void @vabd_loop_s32(i32* nocapture readonly %x, i32* nocapture readonly %y, i32* noalias nocapture %z, i32 %n) { define void @vabd_loop_s32(i32* nocapture readonly %x, i32* nocapture readonly %y, i32* noalias nocapture %z, i32 %n) {
; CHECK-LABEL: vabd_loop_s32: ; CHECK-LABEL: vabd_loop_s32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d9}
; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: mov.w lr, #256
; CHECK-NEXT: mov.w r12, #1 ; CHECK-NEXT: mov.w r12, #1
; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: .LBB8_1: @ %vector.body ; CHECK-NEXT: .LBB8_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vldrw.u32 q2, [r1], #16
; CHECK-NEXT: vmov.f32 s12, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.f32 s16, s8 ; CHECK-NEXT: vmov r5, s8
; CHECK-NEXT: vmov.f32 s14, s5 ; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: vmov.f32 s18, s9 ; CHECK-NEXT: vmov.f32 s18, s9
; CHECK-NEXT: vmov r5, s16 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov.f32 s8, s10
; CHECK-NEXT: vmov r7, s18 ; CHECK-NEXT: vmov r7, s18
; CHECK-NEXT: asrs r4, r3, #31 ; CHECK-NEXT: asrs r4, r3, #31
; CHECK-NEXT: subs.w r8, r3, r5 ; CHECK-NEXT: subs.w r8, r3, r5
; CHECK-NEXT: sbc.w r4, r4, r5, asr #31 ; CHECK-NEXT: sbc.w r4, r4, r5, asr #31
; CHECK-NEXT: asrs r5, r4, #31 ; CHECK-NEXT: asrs r5, r4, #31
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: bfi r4, r5, #0, #4 ; CHECK-NEXT: bfi r4, r5, #0, #4
; CHECK-NEXT: vmov r5, s14 ; CHECK-NEXT: vmov r5, s14
; CHECK-NEXT: vmov.f32 s12, s6
; CHECK-NEXT: vmov.f32 s14, s7
; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s6, s11
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: subs.w r9, r5, r7 ; CHECK-NEXT: subs.w r9, r5, r7
; CHECK-NEXT: asr.w r6, r5, #31 ; CHECK-NEXT: asr.w r6, r5, #31
; CHECK-NEXT: vmov r5, s12 ; CHECK-NEXT: vmov r5, s4
; CHECK-NEXT: sbc.w r6, r6, r7, asr #31 ; CHECK-NEXT: sbc.w r6, r6, r7, asr #31
; CHECK-NEXT: and.w r6, r12, r6, asr #31 ; CHECK-NEXT: and.w r6, r12, r6, asr #31
; CHECK-NEXT: rsbs r6, r6, #0 ; CHECK-NEXT: rsbs r6, r6, #0
; CHECK-NEXT: bfi r4, r6, #4, #4 ; CHECK-NEXT: bfi r4, r6, #4, #4
; CHECK-NEXT: vmov r6, s14 ; CHECK-NEXT: vmov r6, s6
; CHECK-NEXT: vmov.f32 s6, s11
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: asrs r7, r6, #31
; CHECK-NEXT: subs.w r10, r6, r3 ; CHECK-NEXT: subs.w r10, r6, r3
; CHECK-NEXT: asr.w r7, r6, #31 ; CHECK-NEXT: asr.w r6, r5, #31
; CHECK-NEXT: sbc.w r3, r7, r3, asr #31 ; CHECK-NEXT: sbc.w r3, r7, r3, asr #31
; CHECK-NEXT: vmov r7, s4 ; CHECK-NEXT: vmov r7, s8
; CHECK-NEXT: asrs r6, r5, #31
; CHECK-NEXT: asr.w r11, r3, #31 ; CHECK-NEXT: asr.w r11, r3, #31
; CHECK-NEXT: and.w r3, r12, r3, asr #31 ; CHECK-NEXT: and.w r3, r12, r3, asr #31
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: subs r5, r5, r7 ; CHECK-NEXT: subs r5, r5, r7
; CHECK-NEXT: sbc.w r6, r6, r7, asr #31 ; CHECK-NEXT: sbc.w r6, r6, r7, asr #31
; CHECK-NEXT: asrs r6, r6, #31 ; CHECK-NEXT: asrs r6, r6, #31
; CHECK-NEXT: vmov q1[2], q1[0], r6, r11 ; CHECK-NEXT: vmov q1[2], q1[0], r6, r11
; CHECK-NEXT: vmov r6, s4 ; CHECK-NEXT: vmov r6, s4
; CHECK-NEXT: vmov q1[2], q1[0], r8, r5 ; CHECK-NEXT: vmov q1[2], q1[0], r8, r5
; CHECK-NEXT: vmov q1[3], q1[1], r9, r10 ; CHECK-NEXT: vmov q1[3], q1[1], r9, r10
; CHECK-NEXT: and r6, r6, #1 ; CHECK-NEXT: and r6, r6, #1
; CHECK-NEXT: rsbs r6, r6, #0 ; CHECK-NEXT: rsbs r6, r6, #0
; CHECK-NEXT: bfi r4, r6, #8, #4 ; CHECK-NEXT: bfi r4, r6, #8, #4
; CHECK-NEXT: bfi r4, r3, #12, #4 ; CHECK-NEXT: bfi r4, r3, #12, #4
; CHECK-NEXT: vmsr p0, r4 ; CHECK-NEXT: vmsr p0, r4
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vsubt.i32 q1, q0, q1 ; CHECK-NEXT: vsubt.i32 q1, q0, q1
; CHECK-NEXT: vstrb.8 q1, [r2], #16 ; CHECK-NEXT: vstrb.8 q1, [r2], #16
; CHECK-NEXT: le lr, .LBB8_1 ; CHECK-NEXT: le lr, .LBB8_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i32, i32* %x, i32 %index %0 = getelementptr inbounds i32, i32* %x, i32 %index
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; CHECK-NEXT: vmov.f32 s12, s8 ; CHECK-NEXT: vmov.f32 s12, s8
; CHECK-NEXT: vmov.f32 s14, s9 ; CHECK-NEXT: vmov.f32 s14, s9
; CHECK-NEXT: vand q4, q3, q0 ; CHECK-NEXT: vand q4, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0], #16 ; CHECK-NEXT: vldrw.u32 q3, [r0], #16
; CHECK-NEXT: vmov r3, r4, d8 ; CHECK-NEXT: vmov r3, r4, d8
; CHECK-NEXT: vmov.f32 s20, s12 ; CHECK-NEXT: vmov.f32 s20, s12
; CHECK-NEXT: vmov.f32 s22, s13 ; CHECK-NEXT: vmov.f32 s22, s13
; CHECK-NEXT: vand q5, q5, q0 ; CHECK-NEXT: vand q5, q5, q0
; CHECK-NEXT: vmov.f32 s8, s10
; CHECK-NEXT: vmov r5, r6, d10 ; CHECK-NEXT: vmov r5, r6, d10
; CHECK-NEXT: vmov.f32 s10, s11
; CHECK-NEXT: vmov.f32 s12, s14
; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vmov.f32 s14, s15
; CHECK-NEXT: vand q3, q3, q0
; CHECK-NEXT: subs.w r8, r5, r3 ; CHECK-NEXT: subs.w r8, r5, r3
; CHECK-NEXT: vmov r7, r3, d11 ; CHECK-NEXT: vmov r7, r3, d11
; CHECK-NEXT: sbc.w r4, r6, r4 ; CHECK-NEXT: sbc.w r4, r6, r4
; CHECK-NEXT: asrs r5, r4, #31 ; CHECK-NEXT: asrs r5, r4, #31
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: bfi r4, r5, #0, #4 ; CHECK-NEXT: bfi r4, r5, #0, #4
; CHECK-NEXT: vmov r5, r6, d9 ; CHECK-NEXT: vmov r5, r6, d9
; CHECK-NEXT: vmov.f32 s16, s10
; CHECK-NEXT: vmov.f32 s18, s11
; CHECK-NEXT: vand q2, q4, q0
; CHECK-NEXT: vmov.f32 s16, s14
; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vand q3, q4, q0
; CHECK-NEXT: subs.w r9, r7, r5 ; CHECK-NEXT: subs.w r9, r7, r5
; CHECK-NEXT: mov.w r7, #1 ; CHECK-NEXT: mov.w r7, #1
; CHECK-NEXT: sbcs r3, r6 ; CHECK-NEXT: sbcs r3, r6
; CHECK-NEXT: and.w r3, r7, r3, asr #31 ; CHECK-NEXT: and.w r3, r7, r3, asr #31
; CHECK-NEXT: vmov r7, r5, d7 ; CHECK-NEXT: vmov r7, r5, d7
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: bfi r4, r3, #4, #4 ; CHECK-NEXT: bfi r4, r3, #4, #4
; CHECK-NEXT: vmov r3, r6, d5 ; CHECK-NEXT: vmov r3, r6, d5
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vcmpf.ll

Show First 20 Lines • Show All 753 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <8 x half> %src, %src2 %c = fcmp oeq <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_one_v8f16: ; CHECK-MVE-LABEL: vcmp_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <8 x half> %src, %src2 %c = fcmp one <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <8 x half> %src, %src2 %c = fcmp ogt <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <8 x half> %src, %src2 %c = fcmp oge <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <8 x half> %src, %src2 %c = fcmp olt <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <8 x half> %src, %src2 %c = fcmp ole <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <8 x half> %src, %src2 %c = fcmp ueq <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_une_v8f16: ; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <8 x half> %src, %src2 %c = fcmp une <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <8 x half> %src, %src2 %c = fcmp ugt <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <8 x half> %src, %src2 %c = fcmp uge <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <8 x half> %src, %src2 %c = fcmp ult <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <8 x half> %src, %src2 %c = fcmp ule <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <8 x half> %src, %src2 %c = fcmp ord <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vseleq.f16 s20, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vins.f16 s16, s20 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s20 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s20 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s20, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s22, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s20 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> %src, %src2 %c = fcmp uno <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }

llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll

Show First 20 Lines • Show All 795 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp oeq <8 x half> %src, %sp %c = fcmp oeq <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_one_v8f16: ; CHECK-MVE-LABEL: vcmp_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp one <8 x half> %src, %sp %c = fcmp one <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ogt <8 x half> %src, %sp %c = fcmp ogt <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp oge <8 x half> %src, %sp %c = fcmp oge <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp olt <8 x half> %src, %sp %c = fcmp olt <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ole <8 x half> %src, %sp %c = fcmp ole <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ueq <8 x half> %src, %sp %c = fcmp ueq <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_une_v8f16: ; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp une <8 x half> %src, %sp %c = fcmp une <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ugt <8 x half> %src, %sp %c = fcmp ugt <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp uge <8 x half> %src, %sp %c = fcmp uge <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ult <8 x half> %src, %sp %c = fcmp ult <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ule <8 x half> %src, %sp %c = fcmp ule <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ord <8 x half> %src, %sp %c = fcmp ord <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
▲ Show 20 Lines • Show All 803 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp oeq <8 x half> %sp, %src %c = fcmp oeq <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v8f16: ; CHECK-MVE-LABEL: vcmp_r_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp one <8 x half> %sp, %src %c = fcmp one <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ogt <8 x half> %sp, %src %c = fcmp ogt <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp oge <8 x half> %sp, %src %c = fcmp oge <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp olt <8 x half> %sp, %src %c = fcmp olt <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ole <8 x half> %sp, %src %c = fcmp ole <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ueq <8 x half> %sp, %src %c = fcmp ueq <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v8f16: ; CHECK-MVE-LABEL: vcmp_r_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp une <8 x half> %sp, %src %c = fcmp une <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ugt <8 x half> %sp, %src %c = fcmp ugt <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp uge <8 x half> %sp, %src %c = fcmp uge <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ult <8 x half> %sp, %src %c = fcmp ult <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ule <8 x half> %sp, %src %c = fcmp ule <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ord <8 x half> %sp, %src %c = fcmp ord <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp uno <8 x half> %sp, %src %c = fcmp uno <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v8f16_bc: ; CHECK-MVE-LABEL: vcmp_oeq_v8f16_bc:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s13 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s16, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s14 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s17, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s17, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s5, s15 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s18, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s18, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s19, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s19, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16_bc: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16_bc:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
Show All 9 Lines

llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

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ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <8 x half> %src, zeroinitializer %c = fcmp oeq <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_one_v8f16: ; CHECK-MVE-LABEL: vcmp_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <8 x half> %src, zeroinitializer %c = fcmp one <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <8 x half> %src, zeroinitializer %c = fcmp ogt <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <8 x half> %src, zeroinitializer %c = fcmp oge <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <8 x half> %src, zeroinitializer %c = fcmp olt <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <8 x half> %src, zeroinitializer %c = fcmp ole <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <8 x half> %src, zeroinitializer %c = fcmp ueq <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_une_v8f16: ; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <8 x half> %src, zeroinitializer %c = fcmp une <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <8 x half> %src, zeroinitializer %c = fcmp ugt <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <8 x half> %src, zeroinitializer %c = fcmp uge <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <8 x half> %src, zeroinitializer %c = fcmp ult <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <8 x half> %src, zeroinitializer %c = fcmp ule <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <8 x half> %src, zeroinitializer %c = fcmp ord <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
▲ Show 20 Lines • Show All 758 Lines • ▼ Show 20 Linesentry:
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <8 x half> zeroinitializer, %src %c = fcmp oeq <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v8f16: ; CHECK-MVE-LABEL: vcmp_r_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <8 x half> zeroinitializer, %src %c = fcmp one <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <8 x half> zeroinitializer, %src %c = fcmp ogt <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <8 x half> zeroinitializer, %src %c = fcmp oge <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <8 x half> zeroinitializer, %src %c = fcmp olt <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <8 x half> zeroinitializer, %src %c = fcmp ole <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <8 x half> zeroinitializer, %src %c = fcmp ueq <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v8f16: ; CHECK-MVE-LABEL: vcmp_r_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <8 x half> zeroinitializer, %src %c = fcmp une <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <8 x half> zeroinitializer, %src %c = fcmp ugt <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <8 x half> zeroinitializer, %src %c = fcmp uge <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <8 x half> zeroinitializer, %src %c = fcmp ult <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <8 x half> zeroinitializer, %src %c = fcmp ule <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <8 x half> zeroinitializer, %src %c = fcmp ord <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vins.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s16, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s1, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s13, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s13, s16 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s11
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s14, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: vins.f16 s14, s16 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s16, s3 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vcmp.f16 s16, s16 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s16, s7 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r1, ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cset r0, ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s15, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s15, s16 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> zeroinitializer, %src %c = fcmp uno <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }

llvm/test/CodeGen/Thumb2/mve-vcvt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <4 x float> @foo_float_int32(<4 x i32> %src) { define arm_aapcs_vfpcc <4 x float> @foo_float_int32(<4 x i32> %src) {
; CHECK-MVE-LABEL: foo_float_int32: ; CHECK-MVE-LABEL: foo_float_int32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvt.f32.s32 s7, s3 ; CHECK-MVE-NEXT: vcvt.f32.s32 s3, s3
; CHECK-MVE-NEXT: vcvt.f32.s32 s6, s2 ; CHECK-MVE-NEXT: vcvt.f32.s32 s2, s2
; CHECK-MVE-NEXT: vcvt.f32.s32 s5, s1 ; CHECK-MVE-NEXT: vcvt.f32.s32 s1, s1
; CHECK-MVE-NEXT: vcvt.f32.s32 s4, s0 ; CHECK-MVE-NEXT: vcvt.f32.s32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: foo_float_int32: ; CHECK-MVEFP-LABEL: foo_float_int32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvt.f32.s32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.f32.s32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%out = sitofp <4 x i32> %src to <4 x float> %out = sitofp <4 x i32> %src to <4 x float>
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <4 x float> @foo_float_uint32(<4 x i32> %src) { define arm_aapcs_vfpcc <4 x float> @foo_float_uint32(<4 x i32> %src) {
; CHECK-MVE-LABEL: foo_float_uint32: ; CHECK-MVE-LABEL: foo_float_uint32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvt.f32.u32 s7, s3 ; CHECK-MVE-NEXT: vcvt.f32.u32 s3, s3
; CHECK-MVE-NEXT: vcvt.f32.u32 s6, s2 ; CHECK-MVE-NEXT: vcvt.f32.u32 s2, s2
; CHECK-MVE-NEXT: vcvt.f32.u32 s5, s1 ; CHECK-MVE-NEXT: vcvt.f32.u32 s1, s1
; CHECK-MVE-NEXT: vcvt.f32.u32 s4, s0 ; CHECK-MVE-NEXT: vcvt.f32.u32 s0, s0
; CHECK-MVE-NEXT: vmov q0, q1
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: foo_float_uint32: ; CHECK-MVEFP-LABEL: foo_float_uint32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvt.f32.u32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.f32.u32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%out = uitofp <4 x i32> %src to <4 x float> %out = uitofp <4 x i32> %src to <4 x float>
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <4 x i32> @foo_int32_float(<4 x float> %src) { define arm_aapcs_vfpcc <4 x i32> @foo_int32_float(<4 x float> %src) {
; CHECK-MVE-LABEL: foo_int32_float: ; CHECK-MVE-LABEL: foo_int32_float:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s2 ; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s0 ; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s3
; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s1 ; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s1
; CHECK-MVE-NEXT: vmov r0, s2
; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vmov r0, s4
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: foo_int32_float: ; CHECK-MVEFP-LABEL: foo_int32_float:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%out = fptosi <4 x float> %src to <4 x i32> %out = fptosi <4 x float> %src to <4 x i32>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <4 x i32> @foo_uint32_float(<4 x float> %src) { define arm_aapcs_vfpcc <4 x i32> @foo_uint32_float(<4 x float> %src) {
; CHECK-MVE-LABEL: foo_uint32_float: ; CHECK-MVE-LABEL: foo_uint32_float:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s2 ; CHECK-MVE-NEXT: vcvt.u32.f32 s2, s2
; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s0 ; CHECK-MVE-NEXT: vcvt.u32.f32 s0, s0
; CHECK-MVE-NEXT: vcvt.u32.f32 s8, s3 ; CHECK-MVE-NEXT: vcvt.u32.f32 s4, s3
; CHECK-MVE-NEXT: vcvt.u32.f32 s10, s1 ; CHECK-MVE-NEXT: vcvt.u32.f32 s6, s1
; CHECK-MVE-NEXT: vmov r0, s2
; CHECK-MVE-NEXT: vmov r1, s0
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-MVE-NEXT: vmov r0, s4 ; CHECK-MVE-NEXT: vmov r0, s4
; CHECK-MVE-NEXT: vmov r1, s6 ; CHECK-MVE-NEXT: vmov r1, s6
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-MVE-NEXT: vmov r0, s8
; CHECK-MVE-NEXT: vmov r1, s10
; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: foo_uint32_float: ; CHECK-MVEFP-LABEL: foo_uint32_float:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%out = fptoui <4 x float> %src to <4 x i32> %out = fptoui <4 x float> %src to <4 x i32>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <8 x half> @foo_half_int16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x half> @foo_half_int16(<8 x i16> %src) {
; CHECK-MVE-LABEL: foo_half_int16: ; CHECK-MVE-LABEL: foo_half_int16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vmov.s16 r0, q0[0] ; CHECK-MVE-NEXT: vmov.s16 r0, q0[0]
; CHECK-MVE-NEXT: vmov s0, r0 ; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[1] ; CHECK-MVE-NEXT: vmov.s16 r0, q1[1]
; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: vmov s2, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[3]
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s2
; CHECK-MVE-NEXT: vcvt.f16.s32 s0, s0 ; CHECK-MVE-NEXT: vcvt.f16.s32 s0, s0
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s2
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov.s16 r0, q1[3]
; CHECK-MVE-NEXT: vins.f16 s0, s2
; CHECK-MVE-NEXT: vmov s2, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[2] ; CHECK-MVE-NEXT: vmov.s16 r0, q1[2]
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s2
; CHECK-MVE-NEXT: vmov s10, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[4]
; CHECK-MVE-NEXT: vcvt.f16.s32 s1, s10
; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[4]
; CHECK-MVE-NEXT: vcvt.f16.s32 s1, s8
; CHECK-MVE-NEXT: vins.f16 s1, s2
; CHECK-MVE-NEXT: vmov s2, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[5] ; CHECK-MVE-NEXT: vmov.s16 r0, q1[5]
; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s8 ; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s2
; CHECK-MVE-NEXT: vmov s10, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[7] ; CHECK-MVE-NEXT: vmov.s16 r0, q1[7]
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8
; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.s16 r0, q1[6] ; CHECK-MVE-NEXT: vmov.s16 r0, q1[6]
; CHECK-MVE-NEXT: vcvt.f16.s32 s10, s10
; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vins.f16 s2, s10
; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.s32 s8, s8
; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vcvt.f16.s32 s3, s4 ; CHECK-MVE-NEXT: vcvt.f16.s32 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: foo_half_int16: ; CHECK-MVEFP-LABEL: foo_half_int16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvt.f16.s16 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.f16.s16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%out = sitofp <8 x i16> %src to <8 x half> %out = sitofp <8 x i16> %src to <8 x half>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @foo_half_uint16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x half> @foo_half_uint16(<8 x i16> %src) {
; CHECK-MVE-LABEL: foo_half_uint16: ; CHECK-MVE-LABEL: foo_half_uint16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q1, q0 ; CHECK-MVE-NEXT: vmov q1, q0
; CHECK-MVE-NEXT: vmov.u16 r0, q0[0] ; CHECK-MVE-NEXT: vmov.u16 r0, q0[0]
; CHECK-MVE-NEXT: vmov s0, r0 ; CHECK-MVE-NEXT: vmov s0, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[1] ; CHECK-MVE-NEXT: vmov.u16 r0, q1[1]
; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: vmov s2, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[3]
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s2
; CHECK-MVE-NEXT: vcvt.f16.u32 s0, s0 ; CHECK-MVE-NEXT: vcvt.f16.u32 s0, s0
; CHECK-MVE-NEXT: vins.f16 s0, s8 ; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s2
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q1[3]
; CHECK-MVE-NEXT: vins.f16 s0, s2
; CHECK-MVE-NEXT: vmov s2, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[2] ; CHECK-MVE-NEXT: vmov.u16 r0, q1[2]
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s2
; CHECK-MVE-NEXT: vmov s10, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[4]
; CHECK-MVE-NEXT: vcvt.f16.u32 s1, s10
; CHECK-MVE-NEXT: vins.f16 s1, s8
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[4]
; CHECK-MVE-NEXT: vcvt.f16.u32 s1, s8
; CHECK-MVE-NEXT: vins.f16 s1, s2
; CHECK-MVE-NEXT: vmov s2, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[5] ; CHECK-MVE-NEXT: vmov.u16 r0, q1[5]
; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s8 ; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s2
; CHECK-MVE-NEXT: vmov s10, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[7] ; CHECK-MVE-NEXT: vmov.u16 r0, q1[7]
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8
; CHECK-MVE-NEXT: vins.f16 s2, s8
; CHECK-MVE-NEXT: vmov s8, r0 ; CHECK-MVE-NEXT: vmov s8, r0
; CHECK-MVE-NEXT: vmov.u16 r0, q1[6] ; CHECK-MVE-NEXT: vmov.u16 r0, q1[6]
; CHECK-MVE-NEXT: vcvt.f16.u32 s10, s10
; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vins.f16 s2, s10
; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8 ; CHECK-MVE-NEXT: vcvt.f16.u32 s8, s8
; CHECK-MVE-NEXT: vmov s4, r0
; CHECK-MVE-NEXT: vcvt.f16.u32 s3, s4 ; CHECK-MVE-NEXT: vcvt.f16.u32 s3, s4
; CHECK-MVE-NEXT: vins.f16 s3, s8 ; CHECK-MVE-NEXT: vins.f16 s3, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: foo_half_uint16: ; CHECK-MVEFP-LABEL: foo_half_uint16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvt.f16.u16 q0, q0 ; CHECK-MVEFP-NEXT: vcvt.f16.u16 q0, q0
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%out = uitofp <8 x i16> %src to <8 x half> %out = uitofp <8 x i16> %src to <8 x half>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x i16> @foo_int16_half(<8 x half> %src) { define arm_aapcs_vfpcc <8 x i16> @foo_int16_half(<8 x half> %src) {
; CHECK-MVE-LABEL: foo_int16_half: ; CHECK-MVE-LABEL: foo_int16_half:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s14, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcvt.s32.f16 s12, s2
; CHECK-MVE-NEXT: vmovx.f16 s2, s0
; CHECK-MVE-NEXT: vcvt.s32.f16 s0, s0 ; CHECK-MVE-NEXT: vcvt.s32.f16 s0, s0
; CHECK-MVE-NEXT: vcvt.s32.f16 s14, s14 ; CHECK-MVE-NEXT: vcvt.s32.f16 s14, s2
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vmovx.f16 s10, s1 ; CHECK-MVE-NEXT: vmovx.f16 s10, s1
; CHECK-MVE-NEXT: vcvt.s32.f16 s8, s3 ; CHECK-MVE-NEXT: vcvt.s32.f16 s8, s3
; CHECK-MVE-NEXT: vcvt.s32.f16 s12, s2
; CHECK-MVE-NEXT: vcvt.s32.f16 s5, s1 ; CHECK-MVE-NEXT: vcvt.s32.f16 s5, s1
; CHECK-MVE-NEXT: vmov.16 q0[0], r0 ; CHECK-MVE-NEXT: vmov.16 q0[0], r0
; CHECK-MVE-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-MVE-NEXT: vmov.16 q0[1], r0 ; CHECK-MVE-NEXT: vmov.16 q0[1], r0
; CHECK-MVE-NEXT: vmov r0, s5 ; CHECK-MVE-NEXT: vmov r0, s5
; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10
; CHECK-MVE-NEXT: vmov.16 q0[2], r0 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
; CHECK-MVE-NEXT: vmov r0, s10 ; CHECK-MVE-NEXT: vmov r0, s10
Show All 17 Lines
entry: entry:
%out = fptosi <8 x half> %src to <8 x i16> %out = fptosi <8 x half> %src to <8 x i16>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @foo_uint16_half(<8 x half> %src) { define arm_aapcs_vfpcc <8 x i16> @foo_uint16_half(<8 x half> %src) {
; CHECK-MVE-LABEL: foo_uint16_half: ; CHECK-MVE-LABEL: foo_uint16_half:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s14, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcvt.s32.f16 s12, s2
; CHECK-MVE-NEXT: vmovx.f16 s2, s0
; CHECK-MVE-NEXT: vcvt.s32.f16 s0, s0 ; CHECK-MVE-NEXT: vcvt.s32.f16 s0, s0
; CHECK-MVE-NEXT: vcvt.s32.f16 s14, s14 ; CHECK-MVE-NEXT: vcvt.s32.f16 s14, s2
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vmovx.f16 s10, s1 ; CHECK-MVE-NEXT: vmovx.f16 s10, s1
; CHECK-MVE-NEXT: vcvt.s32.f16 s8, s3 ; CHECK-MVE-NEXT: vcvt.s32.f16 s8, s3
; CHECK-MVE-NEXT: vcvt.s32.f16 s12, s2
; CHECK-MVE-NEXT: vcvt.s32.f16 s5, s1 ; CHECK-MVE-NEXT: vcvt.s32.f16 s5, s1
; CHECK-MVE-NEXT: vmov.16 q0[0], r0 ; CHECK-MVE-NEXT: vmov.16 q0[0], r0
; CHECK-MVE-NEXT: vmov r0, s14 ; CHECK-MVE-NEXT: vmov r0, s14
; CHECK-MVE-NEXT: vmov.16 q0[1], r0 ; CHECK-MVE-NEXT: vmov.16 q0[1], r0
; CHECK-MVE-NEXT: vmov r0, s5 ; CHECK-MVE-NEXT: vmov r0, s5
; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10 ; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10
; CHECK-MVE-NEXT: vmov.16 q0[2], r0 ; CHECK-MVE-NEXT: vmov.16 q0[2], r0
; CHECK-MVE-NEXT: vmov r0, s10 ; CHECK-MVE-NEXT: vmov r0, s10
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entry: entry:
%out = fptoui <2 x double> %src to <2 x i64> %out = fptoui <2 x double> %src to <2 x i64>
ret <2 x i64> %out ret <2 x i64> %out
} }
define arm_aapcs_vfpcc <8 x half> @vmovn32_trunc1(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <8 x half> @vmovn32_trunc1(<4 x float> %src1, <4 x float> %src2) {
; CHECK-MVE-LABEL: vmovn32_trunc1: ; CHECK-MVE-LABEL: vmovn32_trunc1:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q2, q0 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s2
; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s4 ; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s4
; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s9 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s4, s1
; CHECK-MVE-NEXT: vcvtb.f16.f32 s4, s3
; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s5 ; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s5
; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s10
; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s6 ; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s6
; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s11
; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s7 ; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s7
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vmovn32_trunc1: ; CHECK-MVEFP-LABEL: vmovn32_trunc1:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0 ; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0
; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q1 ; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
%out = fptrunc <8 x float> %strided.vec to <8 x half> %out = fptrunc <8 x float> %strided.vec to <8 x half>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @vmovn32_trunc2(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <8 x half> @vmovn32_trunc2(<4 x float> %src1, <4 x float> %src2) {
; CHECK-MVE-LABEL: vmovn32_trunc2: ; CHECK-MVE-LABEL: vmovn32_trunc2:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov q2, q0 ; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s0
; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s4 ; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s1
; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s8 ; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s2
; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s5 ; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s3
; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s9 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s4, s4
; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s6 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s4, s5
; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s10 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s4, s6
; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s7 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s4, s7
; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s11
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vmovn32_trunc2: ; CHECK-MVEFP-LABEL: vmovn32_trunc2:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1 ; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q1, q0 ; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q1, q0
; CHECK-MVEFP-NEXT: vmov q0, q1 ; CHECK-MVEFP-NEXT: vmov q0, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3> %strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>
%out = fptrunc <8 x float> %strided.vec to <8 x half> %out = fptrunc <8 x float> %strided.vec to <8 x half>
ret <8 x half> %out ret <8 x half> %out
} }

llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
define arm_aapcs_vfpcc <4 x float> @fpext_4(<4 x half> %src1) { define arm_aapcs_vfpcc <4 x float> @fpext_4(<4 x half> %src1) {
; CHECK-LABEL: fpext_4: ; CHECK-LABEL: fpext_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvtt.f32.f16 s7, s1 ; CHECK-NEXT: vcvtt.f32.f16 s3, s1
; CHECK-NEXT: vcvtb.f32.f16 s6, s1 ; CHECK-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-NEXT: vcvtt.f32.f16 s5, s0 ; CHECK-NEXT: vcvtt.f32.f16 s1, s0
; CHECK-NEXT: vcvtb.f32.f16 s4, s0 ; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fpext <4 x half> %src1 to <4 x float> %out = fpext <4 x half> %src1 to <4 x float>
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <8 x float> @fpext_8(<8 x half> %src1) { define arm_aapcs_vfpcc <8 x float> @fpext_8(<8 x half> %src1) {
; CHECK-LABEL: fpext_8: ; CHECK-LABEL: fpext_8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvtt.f32.f16 s11, s1 ; CHECK-NEXT: vcvtt.f32.f16 s11, s1
; CHECK-NEXT: vcvtt.f32.f16 s7, s3
; CHECK-NEXT: vcvtb.f32.f16 s10, s1 ; CHECK-NEXT: vcvtb.f32.f16 s10, s1
; CHECK-NEXT: vcvtb.f32.f16 s6, s3
; CHECK-NEXT: vcvtt.f32.f16 s9, s0 ; CHECK-NEXT: vcvtt.f32.f16 s9, s0
; CHECK-NEXT: vcvtt.f32.f16 s5, s2
; CHECK-NEXT: vcvtb.f32.f16 s8, s0 ; CHECK-NEXT: vcvtb.f32.f16 s8, s0
; CHECK-NEXT: vcvtt.f32.f16 s7, s3
; CHECK-NEXT: vcvtb.f32.f16 s6, s3
; CHECK-NEXT: vcvtt.f32.f16 s5, s2
; CHECK-NEXT: vcvtb.f32.f16 s4, s2 ; CHECK-NEXT: vcvtb.f32.f16 s4, s2
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fpext <8 x half> %src1 to <8 x float> %out = fpext <8 x half> %src1 to <8 x float>
ret <8 x float> %out ret <8 x float> %out
} }
define arm_aapcs_vfpcc <4 x half> @fptrunc_4(<4 x float> %src1) { define arm_aapcs_vfpcc <4 x half> @fptrunc_4(<4 x float> %src1) {
; CHECK-LABEL: fptrunc_4: ; CHECK-LABEL: fptrunc_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvtb.f16.f32 s4, s0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtt.f16.f32 s4, s1 ; CHECK-NEXT: vcvtb.f16.f32 s2, s2
; CHECK-NEXT: vcvtb.f16.f32 s5, s2 ; CHECK-NEXT: vcvtt.f16.f32 s0, s1
; CHECK-NEXT: vcvtt.f16.f32 s5, s3 ; CHECK-NEXT: vcvtt.f16.f32 s1, s3
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fptrunc <4 x float> %src1 to <4 x half> %out = fptrunc <4 x float> %src1 to <4 x half>
ret <4 x half> %out ret <4 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @fptrunc_8(<8 x float> %src1) { define arm_aapcs_vfpcc <8 x half> @fptrunc_8(<8 x float> %src1) {
; CHECK-LABEL: fptrunc_8: ; CHECK-LABEL: fptrunc_8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vcvtb.f16.f32 s0, s8 ; CHECK-NEXT: vcvtb.f16.f32 s2, s2
; CHECK-NEXT: vcvtt.f16.f32 s0, s9
; CHECK-NEXT: vcvtb.f16.f32 s1, s10
; CHECK-NEXT: vcvtt.f16.f32 s1, s11
; CHECK-NEXT: vcvtb.f16.f32 s2, s4 ; CHECK-NEXT: vcvtb.f16.f32 s2, s4
; CHECK-NEXT: vcvtt.f16.f32 s0, s1
; CHECK-NEXT: vcvtt.f16.f32 s1, s3
; CHECK-NEXT: vcvtt.f16.f32 s2, s5 ; CHECK-NEXT: vcvtt.f16.f32 s2, s5
; CHECK-NEXT: vcvtb.f16.f32 s3, s6
; CHECK-NEXT: vcvtt.f16.f32 s3, s7 ; CHECK-NEXT: vcvtt.f16.f32 s3, s7
; CHECK-NEXT: vcvtb.f16.f32 s4, s6
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fptrunc <8 x float> %src1 to <8 x half> %out = fptrunc <8 x float> %src1 to <8 x half>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle_trunc1(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <8 x half> @shuffle_trunc1(<4 x float> %src1, <4 x float> %src2) {
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} }
define arm_aapcs_vfpcc <8 x float> @load_shuffleext_16(<16 x half>* %src) { define arm_aapcs_vfpcc <8 x float> @load_shuffleext_16(<16 x half>* %src) {
; CHECK-LABEL: load_shuffleext_16: ; CHECK-LABEL: load_shuffleext_16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vld20.16 {q2, q3}, [r0] ; CHECK-NEXT: vld20.16 {q2, q3}, [r0]
; CHECK-NEXT: vld21.16 {q2, q3}, [r0] ; CHECK-NEXT: vld21.16 {q2, q3}, [r0]
; CHECK-NEXT: vcvtt.f32.f16 s3, s9 ; CHECK-NEXT: vcvtt.f32.f16 s3, s9
; CHECK-NEXT: vcvtt.f32.f16 s7, s11
; CHECK-NEXT: vcvtb.f32.f16 s2, s9 ; CHECK-NEXT: vcvtb.f32.f16 s2, s9
; CHECK-NEXT: vcvtb.f32.f16 s6, s11
; CHECK-NEXT: vcvtt.f32.f16 s1, s8 ; CHECK-NEXT: vcvtt.f32.f16 s1, s8
; CHECK-NEXT: vcvtt.f32.f16 s5, s10
; CHECK-NEXT: vcvtb.f32.f16 s0, s8 ; CHECK-NEXT: vcvtb.f32.f16 s0, s8
; CHECK-NEXT: vcvtt.f32.f16 s7, s11
; CHECK-NEXT: vcvtb.f32.f16 s6, s11
; CHECK-NEXT: vcvtt.f32.f16 s5, s10
; CHECK-NEXT: vcvtb.f32.f16 s4, s10 ; CHECK-NEXT: vcvtb.f32.f16 s4, s10
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%wide.load = load <16 x half>, <16 x half>* %src, align 4 %wide.load = load <16 x half>, <16 x half>* %src, align 4
%sh = shufflevector <16 x half> %wide.load, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %sh = shufflevector <16 x half> %wide.load, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%e = fpext <8 x half> %sh to <8 x float> %e = fpext <8 x half> %sh to <8 x float>
ret <8 x float> %e ret <8 x float> %e
} }
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llvm/test/CodeGen/Thumb2/mve-vdup.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Linesentry:
%out = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> zeroinitializer %out = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> zeroinitializer
%outbc = bitcast <8 x i16> %out to <8 x half> %outbc = bitcast <8 x i16> %out to <8 x half>
ret <8 x half> %outbc ret <8 x half> %outbc
} }
define arm_aapcs_vfpcc <2 x double> @vdup_f64(double %src) { define arm_aapcs_vfpcc <2 x double> @vdup_f64(double %src) {
; CHECK-LABEL: vdup_f64: ; CHECK-LABEL: vdup_f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: vmov.f32 s2, s0 ; CHECK-NEXT: vmov.f32 s2, s0
; CHECK-NEXT: vmov.f32 s3, s1 ; CHECK-NEXT: vmov.f32 s3, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = insertelement <2 x double> undef, double %src, i32 0 %0 = insertelement <2 x double> undef, double %src, i32 0
%out = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer %out = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
ret <2 x double> %out ret <2 x double> %out
} }
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llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll

Show All 10 Lines
entry: entry:
%z = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float %y, <2 x float> %x) %z = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float %y, <2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fadd_v4f32(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fadd_v4f32(<4 x float> %x, float %y) {
; CHECK-FP-LABEL: fadd_v4f32: ; CHECK-FP-LABEL: fadd_v4f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vadd.f32 s6, s2, s3 ; CHECK-FP-NEXT: vadd.f32 s2, s2, s3
; CHECK-FP-NEXT: vadd.f32 s0, s0, s1 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s1
; CHECK-FP-NEXT: vadd.f32 s0, s0, s6 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s2
; CHECK-FP-NEXT: vadd.f32 s0, s4, s0 ; CHECK-FP-NEXT: vadd.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fadd_v4f32: ; CHECK-NOFP-LABEL: fadd_v4f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vadd.f32 s6, s0, s1 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vadd.f32 s6, s6, s2 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vadd.f32 s0, s6, s3 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s3
; CHECK-NOFP-NEXT: vadd.f32 s0, s4, s0 ; CHECK-NOFP-NEXT: vadd.f32 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %y, <4 x float> %x) %z = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %y, <4 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fadd_v8f32(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fadd_v8f32(<8 x float> %x, float %y) {
; CHECK-FP-LABEL: fadd_v8f32: ; CHECK-FP-LABEL: fadd_v8f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vadd.f32 q0, q0, q1 ; CHECK-FP-NEXT: vadd.f32 q0, q0, q1
; CHECK-FP-NEXT: vadd.f32 s4, s2, s3 ; CHECK-FP-NEXT: vadd.f32 s2, s2, s3
; CHECK-FP-NEXT: vadd.f32 s0, s0, s1 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s1
; CHECK-FP-NEXT: vadd.f32 s0, s0, s4 ; CHECK-FP-NEXT: vadd.f32 s0, s0, s2
; CHECK-FP-NEXT: vadd.f32 s0, s8, s0 ; CHECK-FP-NEXT: vadd.f32 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fadd_v8f32: ; CHECK-NOFP-LABEL: fadd_v8f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vadd.f32 s12, s0, s4 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vadd.f32 s10, s1, s5 ; CHECK-NOFP-NEXT: vadd.f32 s10, s1, s5
; CHECK-NOFP-NEXT: vadd.f32 s14, s2, s6 ; CHECK-NOFP-NEXT: vadd.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vadd.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vadd.f32 s4, s3, s7
; CHECK-NOFP-NEXT: vadd.f32 s10, s12, s10 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s10
; CHECK-NOFP-NEXT: vadd.f32 s2, s10, s14 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vadd.f32 s0, s2, s0 ; CHECK-NOFP-NEXT: vadd.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vadd.f32 s0, s8, s0 ; CHECK-NOFP-NEXT: vadd.f32 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float %y, <8 x float> %x) %z = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float %y, <8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fadd_v2f16(<2 x half> %x, half %y) { define arm_aapcs_vfpcc half @fadd_v2f16(<2 x half> %x, half %y) {
; CHECK-LABEL: fadd_v2f16: ; CHECK-LABEL: fadd_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s6, s0 ; CHECK-NEXT: vmovx.f16 s2, s0
; CHECK-NEXT: vadd.f16 s0, s0, s6 ; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: vadd.f16 s0, s4, s0 ; CHECK-NEXT: vadd.f16 s0, s4, s0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fadd.f16.v2f16(half %y, <2 x half> %x) %z = call fast half @llvm.vector.reduce.fadd.f16.v2f16(half %y, <2 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fadd_v4f16(<4 x half> %x, half %y) { define arm_aapcs_vfpcc half @fadd_v4f16(<4 x half> %x, half %y) {
; CHECK-FP-LABEL: fadd_v4f16: ; CHECK-FP-LABEL: fadd_v4f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s6, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s8, s0 ; CHECK-FP-NEXT: vmovx.f16 s6, s0
; CHECK-FP-NEXT: vadd.f16 s6, s1, s6 ; CHECK-FP-NEXT: vadd.f16 s2, s1, s2
; CHECK-FP-NEXT: vadd.f16 s0, s0, s8
; CHECK-FP-NEXT: vadd.f16 s0, s0, s6 ; CHECK-FP-NEXT: vadd.f16 s0, s0, s6
; CHECK-FP-NEXT: vadd.f16 s0, s0, s2
; CHECK-FP-NEXT: vadd.f16 s0, s4, s0 ; CHECK-FP-NEXT: vadd.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fadd_v4f16: ; CHECK-NOFP-LABEL: fadd_v4f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vadd.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vadd.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vadd.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vadd.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vadd.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fadd.f16.v4f16(half %y, <4 x half> %x) %z = call fast half @llvm.vector.reduce.fadd.f16.v4f16(half %y, <4 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fadd_v8f16(<8 x half> %x, half %y) { define arm_aapcs_vfpcc half @fadd_v8f16(<8 x half> %x, half %y) {
; CHECK-FP-LABEL: fadd_v8f16: ; CHECK-FP-LABEL: fadd_v8f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q2, q0 ; CHECK-FP-NEXT: vrev32.16 q2, q0
; CHECK-FP-NEXT: vadd.f16 q0, q0, q2 ; CHECK-FP-NEXT: vadd.f16 q0, q0, q2
; CHECK-FP-NEXT: vadd.f16 s6, s2, s3 ; CHECK-FP-NEXT: vadd.f16 s2, s2, s3
; CHECK-FP-NEXT: vadd.f16 s0, s0, s1 ; CHECK-FP-NEXT: vadd.f16 s0, s0, s1
; CHECK-FP-NEXT: vadd.f16 s0, s0, s6 ; CHECK-FP-NEXT: vadd.f16 s0, s0, s2
; CHECK-FP-NEXT: vadd.f16 s0, s4, s0 ; CHECK-FP-NEXT: vadd.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fadd_v8f16: ; CHECK-NOFP-LABEL: fadd_v8f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s0
; CHECK-NOFP-NEXT: vmovx.f16 s8, s1 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vadd.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vadd.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vadd.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s8, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vadd.f16 s6, s6, s2 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vadd.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vadd.f16 s6, s6, s3 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vadd.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vadd.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vadd.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fadd.f16.v8f16(half %y, <8 x half> %x) %z = call fast half @llvm.vector.reduce.fadd.f16.v8f16(half %y, <8 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fadd_v16f16(<16 x half> %x, half %y) { define arm_aapcs_vfpcc half @fadd_v16f16(<16 x half> %x, half %y) {
; CHECK-FP-LABEL: fadd_v16f16: ; CHECK-FP-LABEL: fadd_v16f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vadd.f16 q0, q0, q1 ; CHECK-FP-NEXT: vadd.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vadd.f16 q0, q0, q1 ; CHECK-FP-NEXT: vadd.f16 q0, q0, q1
; CHECK-FP-NEXT: vadd.f16 s4, s2, s3 ; CHECK-FP-NEXT: vadd.f16 s2, s2, s3
; CHECK-FP-NEXT: vadd.f16 s0, s0, s1 ; CHECK-FP-NEXT: vadd.f16 s0, s0, s1
; CHECK-FP-NEXT: vadd.f16 s0, s0, s4 ; CHECK-FP-NEXT: vadd.f16 s0, s0, s2
; CHECK-FP-NEXT: vadd.f16 s0, s8, s0 ; CHECK-FP-NEXT: vadd.f16 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fadd_v16f16: ; CHECK-NOFP-LABEL: fadd_v16f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s12, s0
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vadd.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vadd.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vadd.f16 s12, s0, s4 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s10
; CHECK-NOFP-NEXT: vadd.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vadd.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vadd.f16 s12, s1, s5
; CHECK-NOFP-NEXT: vadd.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmovx.f16 s12, s5
; CHECK-NOFP-NEXT: vmovx.f16 s14, s1
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7
; CHECK-NOFP-NEXT: vadd.f16 s12, s14, s12
; CHECK-NOFP-NEXT: vmovx.f16 s14, s2
; CHECK-NOFP-NEXT: vadd.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vadd.f16 s12, s2, s6
; CHECK-NOFP-NEXT: vadd.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmovx.f16 s12, s6
; CHECK-NOFP-NEXT: vadd.f16 s12, s14, s12
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3
; CHECK-NOFP-NEXT: vadd.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vadd.f16 s12, s3, s7
; CHECK-NOFP-NEXT: vadd.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vadd.f16 s0, s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s10, s1
; CHECK-NOFP-NEXT: vadd.f16 s4, s10, s4
; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vadd.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vadd.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vadd.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vadd.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vadd.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vadd.f16 s0, s8, s0 ; CHECK-NOFP-NEXT: vadd.f16 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fadd.f16.v16f16(half %y, <16 x half> %x) %z = call fast half @llvm.vector.reduce.fadd.f16.v16f16(half %y, <16 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc double @fadd_v1f64(<1 x double> %x, double %y) { define arm_aapcs_vfpcc double @fadd_v1f64(<1 x double> %x, double %y) {
Show All 15 Lines
entry: entry:
%z = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double %y, <2 x double> %x) %z = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double %y, <2 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc double @fadd_v4f64(<4 x double> %x, double %y) { define arm_aapcs_vfpcc double @fadd_v4f64(<4 x double> %x, double %y) {
; CHECK-LABEL: fadd_v4f64: ; CHECK-LABEL: fadd_v4f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f64 d5, d1, d3 ; CHECK-NEXT: vadd.f64 d1, d1, d3
; CHECK-NEXT: vadd.f64 d0, d0, d2 ; CHECK-NEXT: vadd.f64 d0, d0, d2
; CHECK-NEXT: vadd.f64 d0, d0, d5 ; CHECK-NEXT: vadd.f64 d0, d0, d1
; CHECK-NEXT: vadd.f64 d0, d4, d0 ; CHECK-NEXT: vadd.f64 d0, d4, d0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast double @llvm.vector.reduce.fadd.f64.v4f64(double %y, <4 x double> %x) %z = call fast double @llvm.vector.reduce.fadd.f64.v4f64(double %y, <4 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc float @fadd_v2f32_nofast(<2 x float> %x, float %y) { define arm_aapcs_vfpcc float @fadd_v2f32_nofast(<2 x float> %x, float %y) {
; CHECK-LABEL: fadd_v2f32_nofast: ; CHECK-LABEL: fadd_v2f32_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f32 s4, s4, s0 ; CHECK-NEXT: vadd.f32 s0, s4, s0
; CHECK-NEXT: vadd.f32 s0, s4, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fadd.f32.v2f32(float %y, <2 x float> %x) %z = call float @llvm.vector.reduce.fadd.f32.v2f32(float %y, <2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fadd_v4f32_nofast(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fadd_v4f32_nofast(<4 x float> %x, float %y) {
; CHECK-LABEL: fadd_v4f32_nofast: ; CHECK-LABEL: fadd_v4f32_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f32 s4, s4, s0 ; CHECK-NEXT: vadd.f32 s0, s4, s0
; CHECK-NEXT: vadd.f32 s4, s4, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: vadd.f32 s4, s4, s2 ; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: vadd.f32 s0, s4, s3 ; CHECK-NEXT: vadd.f32 s0, s0, s3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fadd.f32.v4f32(float %y, <4 x float> %x) %z = call float @llvm.vector.reduce.fadd.f32.v4f32(float %y, <4 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fadd_v8f32_nofast(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fadd_v8f32_nofast(<8 x float> %x, float %y) {
; CHECK-LABEL: fadd_v8f32_nofast: ; CHECK-LABEL: fadd_v8f32_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f32 s8, s8, s0 ; CHECK-NEXT: vadd.f32 s0, s8, s0
; CHECK-NEXT: vadd.f32 s8, s8, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: vadd.f32 s8, s8, s2 ; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: vadd.f32 s0, s8, s3 ; CHECK-NEXT: vadd.f32 s0, s0, s3
; CHECK-NEXT: vadd.f32 s0, s0, s4 ; CHECK-NEXT: vadd.f32 s0, s0, s4
; CHECK-NEXT: vadd.f32 s0, s0, s5 ; CHECK-NEXT: vadd.f32 s0, s0, s5
; CHECK-NEXT: vadd.f32 s0, s0, s6 ; CHECK-NEXT: vadd.f32 s0, s0, s6
; CHECK-NEXT: vadd.f32 s0, s0, s7 ; CHECK-NEXT: vadd.f32 s0, s0, s7
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fadd.f32.v8f32(float %y, <8 x float> %x) %z = call float @llvm.vector.reduce.fadd.f32.v8f32(float %y, <8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fadd_v4f16_nofast(<4 x half> %x, half %y) { define arm_aapcs_vfpcc half @fadd_v4f16_nofast(<4 x half> %x, half %y) {
; CHECK-LABEL: fadd_v4f16_nofast: ; CHECK-LABEL: fadd_v4f16_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f16 s4, s4, s0 ; CHECK-NEXT: vadd.f16 s2, s4, s0
; CHECK-NEXT: vmovx.f16 s6, s0 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vadd.f16 s4, s4, s6 ; CHECK-NEXT: vadd.f16 s0, s2, s0
; CHECK-NEXT: vmovx.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s2, s1
; CHECK-NEXT: vadd.f16 s4, s4, s1 ; CHECK-NEXT: vadd.f16 s0, s0, s1
; CHECK-NEXT: vadd.f16 s0, s4, s0 ; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fadd.f16.v4f16(half %y, <4 x half> %x) %z = call half @llvm.vector.reduce.fadd.f16.v4f16(half %y, <4 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fadd_v8f16_nofast(<8 x half> %x, half %y) { define arm_aapcs_vfpcc half @fadd_v8f16_nofast(<8 x half> %x, half %y) {
; CHECK-LABEL: fadd_v8f16_nofast: ; CHECK-LABEL: fadd_v8f16_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f16 s4, s4, s0 ; CHECK-NEXT: vadd.f16 s4, s4, s0
; CHECK-NEXT: vmovx.f16 s6, s0 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vadd.f16 s4, s4, s6
; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vadd.f16 s4, s4, s1
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vadd.f16 s4, s4, s6
; CHECK-NEXT: vmovx.f16 s6, s2
; CHECK-NEXT: vadd.f16 s4, s4, s2
; CHECK-NEXT: vadd.f16 s4, s4, s6
; CHECK-NEXT: vadd.f16 s4, s4, s3
; CHECK-NEXT: vadd.f16 s0, s4, s0 ; CHECK-NEXT: vadd.f16 s0, s4, s0
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vadd.f16 s0, s0, s1
; CHECK-NEXT: vadd.f16 s0, s0, s4
; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s2
; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s3
; CHECK-NEXT: vadd.f16 s0, s0, s3
; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fadd.f16.v8f16(half %y, <8 x half> %x) %z = call half @llvm.vector.reduce.fadd.f16.v8f16(half %y, <8 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fadd_v16f16_nofast(<16 x half> %x, half %y) { define arm_aapcs_vfpcc half @fadd_v16f16_nofast(<16 x half> %x, half %y) {
; CHECK-LABEL: fadd_v16f16_nofast: ; CHECK-LABEL: fadd_v16f16_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f16 s8, s8, s0 ; CHECK-NEXT: vadd.f16 s8, s8, s0
; CHECK-NEXT: vmovx.f16 s10, s0 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vadd.f16 s8, s8, s10
; CHECK-NEXT: vmovx.f16 s10, s1
; CHECK-NEXT: vadd.f16 s8, s8, s1
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vadd.f16 s8, s8, s10
; CHECK-NEXT: vmovx.f16 s10, s2
; CHECK-NEXT: vadd.f16 s8, s8, s2
; CHECK-NEXT: vmovx.f16 s2, s4
; CHECK-NEXT: vadd.f16 s8, s8, s10
; CHECK-NEXT: vadd.f16 s8, s8, s3
; CHECK-NEXT: vadd.f16 s0, s8, s0 ; CHECK-NEXT: vadd.f16 s0, s8, s0
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vadd.f16 s0, s0, s1
; CHECK-NEXT: vadd.f16 s0, s0, s8
; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s2
; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s3
; CHECK-NEXT: vadd.f16 s0, s0, s3
; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s4
; CHECK-NEXT: vadd.f16 s0, s0, s4 ; CHECK-NEXT: vadd.f16 s0, s0, s4
; CHECK-NEXT: vadd.f16 s0, s0, s2 ; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vadd.f16 s0, s0, s5 ; CHECK-NEXT: vadd.f16 s0, s0, s5
; CHECK-NEXT: vadd.f16 s0, s0, s2 ; CHECK-NEXT: vadd.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s6 ; CHECK-NEXT: vmovx.f16 s2, s6
; CHECK-NEXT: vadd.f16 s0, s0, s6 ; CHECK-NEXT: vadd.f16 s0, s0, s6
; CHECK-NEXT: vadd.f16 s0, s0, s2 ; CHECK-NEXT: vadd.f16 s0, s0, s2
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entry: entry:
%z = call double @llvm.vector.reduce.fadd.f64.v1f64(double %y, <1 x double> %x) %z = call double @llvm.vector.reduce.fadd.f64.v1f64(double %y, <1 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc double @fadd_v2f64_nofast(<2 x double> %x, double %y) { define arm_aapcs_vfpcc double @fadd_v2f64_nofast(<2 x double> %x, double %y) {
; CHECK-LABEL: fadd_v2f64_nofast: ; CHECK-LABEL: fadd_v2f64_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f64 d2, d2, d0 ; CHECK-NEXT: vadd.f64 d0, d2, d0
; CHECK-NEXT: vadd.f64 d0, d2, d1 ; CHECK-NEXT: vadd.f64 d0, d0, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call double @llvm.vector.reduce.fadd.f64.v2f64(double %y, <2 x double> %x) %z = call double @llvm.vector.reduce.fadd.f64.v2f64(double %y, <2 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc double @fadd_v4f64_nofast(<4 x double> %x, double %y) { define arm_aapcs_vfpcc double @fadd_v4f64_nofast(<4 x double> %x, double %y) {
; CHECK-LABEL: fadd_v4f64_nofast: ; CHECK-LABEL: fadd_v4f64_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f64 d4, d4, d0 ; CHECK-NEXT: vadd.f64 d0, d4, d0
; CHECK-NEXT: vadd.f64 d0, d4, d1 ; CHECK-NEXT: vadd.f64 d0, d0, d1
; CHECK-NEXT: vadd.f64 d0, d0, d2 ; CHECK-NEXT: vadd.f64 d0, d0, d2
; CHECK-NEXT: vadd.f64 d0, d0, d3 ; CHECK-NEXT: vadd.f64 d0, d0, d3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call double @llvm.vector.reduce.fadd.f64.v4f64(double %y, <4 x double> %x) %z = call double @llvm.vector.reduce.fadd.f64.v4f64(double %y, <4 x double> %x)
ret double %z ret double %z
} }
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llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

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entry: entry:
%z = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x) %z = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmin_v4f32(<4 x float> %x) { define arm_aapcs_vfpcc float @fmin_v4f32(<4 x float> %x) {
; CHECK-FP-LABEL: fmin_v4f32: ; CHECK-FP-LABEL: fmin_v4f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f32: ; CHECK-NOFP-LABEL: fmin_v4f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vminnm.f32 s4, s0, s1 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f32 s4, s4, s2 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f32 s0, s4, s3 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s3
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x) %z = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)
ret float %z ret float %z
} }
; FIXME fminnum (vector) -> fminnum (scalar) ? ; FIXME fminnum (vector) -> fminnum (scalar) ?
define arm_aapcs_vfpcc float @fmin_v8f32(<8 x float> %x) { define arm_aapcs_vfpcc float @fmin_v8f32(<8 x float> %x) {
; CHECK-FP-LABEL: fmin_v8f32: ; CHECK-FP-LABEL: fmin_v8f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f32: ; CHECK-NOFP-LABEL: fmin_v8f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vcmp.f32 s5, s1 ; CHECK-NOFP-NEXT: vcmp.f32 s5, s1
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f32 s4, s0
; CHECK-NOFP-NEXT: vselgt.f32 s8, s1, s5 ; CHECK-NOFP-NEXT: vselgt.f32 s8, s1, s5
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s6, s2 ; CHECK-NOFP-NEXT: vcmp.f32 s6, s2
; CHECK-NOFP-NEXT: vselgt.f32 s10, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s7, s3 ; CHECK-NOFP-NEXT: vcmp.f32 s7, s3
; CHECK-NOFP-NEXT: vselgt.f32 s12, s2, s6 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s8
; CHECK-NOFP-NEXT: vselgt.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f32 s2, s10, s8 ; CHECK-NOFP-NEXT: vselgt.f32 s4, s3, s7
; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s12 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f32 s0, s2, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x) %z = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fmin_v4f16(<4 x half> %x) { define arm_aapcs_vfpcc half @fmin_v4f16(<4 x half> %x) {
; CHECK-FP-LABEL: fmin_v4f16: ; CHECK-FP-LABEL: fmin_v4f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s4, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s6, s0 ; CHECK-FP-NEXT: vmovx.f16 s4, s0
; CHECK-FP-NEXT: vminnm.f16 s4, s1, s4 ; CHECK-FP-NEXT: vminnm.f16 s2, s1, s2
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f16: ; CHECK-NOFP-LABEL: fmin_v4f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s4, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vminnm.f16 s4, s0, s4 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x) %z = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmin_v8f16(<8 x half> %x) { define arm_aapcs_vfpcc half @fmin_v8f16(<8 x half> %x) {
; CHECK-FP-LABEL: fmin_v8f16: ; CHECK-FP-LABEL: fmin_v8f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f16: ; CHECK-NOFP-LABEL: fmin_v8f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s4, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s0
; CHECK-NOFP-NEXT: vmovx.f16 s6, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s4, s0, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s6 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s6, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s2 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s3 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x) %z = call fast half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmin_v16f16(<16 x half> %x) { define arm_aapcs_vfpcc half @fmin_v16f16(<16 x half> %x) {
; CHECK-FP-LABEL: fmin_v16f16: ; CHECK-FP-LABEL: fmin_v16f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v16f16: ; CHECK-NOFP-LABEL: fmin_v16f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vmovx.f16 s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s0
; CHECK-NOFP-NEXT: vcmp.f16 s8, s10 ; CHECK-NOFP-NEXT: vcmp.f16 s8, s10
; CHECK-NOFP-NEXT: vmovx.f16 s12, s1
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s0
; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s5, s1 ; CHECK-NOFP-NEXT: vcmp.f16 s5, s1
; CHECK-NOFP-NEXT: vselgt.f16 s10, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vminnm.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s8
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vselgt.f16 s10, s1, s5 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s10, s5 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s8
; CHECK-NOFP-NEXT: vcmp.f16 s10, s12
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s6, s2 ; CHECK-NOFP-NEXT: vcmp.f16 s6, s2
; CHECK-NOFP-NEXT: vselgt.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s8, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s2 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vselgt.f16 s10, s2, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s10, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vcmp.f16 s10, s12 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s2
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s7, s3 ; CHECK-NOFP-NEXT: vcmp.f16 s7, s3
; CHECK-NOFP-NEXT: vselgt.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s4, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vselgt.f16 s10, s3, s7 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vcmp.f16 s2, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vselgt.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x) %z = call fast half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc double @fmin_v1f64(<1 x double> %x) { define arm_aapcs_vfpcc double @fmin_v1f64(<1 x double> %x) {
; CHECK-LABEL: fmin_v1f64: ; CHECK-LABEL: fmin_v1f64:
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} }
define arm_aapcs_vfpcc double @fmin_v4f64(<4 x double> %x) { define arm_aapcs_vfpcc double @fmin_v4f64(<4 x double> %x) {
; CHECK-LABEL: fmin_v4f64: ; CHECK-LABEL: fmin_v4f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.f64 d3, d1 ; CHECK-NEXT: vcmp.f64 d3, d1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f64 d2, d0 ; CHECK-NEXT: vcmp.f64 d2, d0
; CHECK-NEXT: vselgt.f64 d4, d1, d3 ; CHECK-NEXT: vselgt.f64 d1, d1, d3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vselgt.f64 d0, d0, d2 ; CHECK-NEXT: vselgt.f64 d0, d0, d2
; CHECK-NEXT: vminnm.f64 d0, d0, d4 ; CHECK-NEXT: vminnm.f64 d0, d0, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x) %z = call fast double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc float @fmin_v2f32_nofast(<2 x float> %x) { define arm_aapcs_vfpcc float @fmin_v2f32_nofast(<2 x float> %x) {
; CHECK-LABEL: fmin_v2f32_nofast: ; CHECK-LABEL: fmin_v2f32_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-NEXT: vminnm.f32 s0, s0, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x) %z = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmin_v4f32_nofast(<4 x float> %x) { define arm_aapcs_vfpcc float @fmin_v4f32_nofast(<4 x float> %x) {
; CHECK-FP-LABEL: fmin_v4f32_nofast: ; CHECK-FP-LABEL: fmin_v4f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f32_nofast: ; CHECK-NOFP-LABEL: fmin_v4f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vminnm.f32 s4, s0, s1 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f32 s4, s4, s2 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f32 s0, s4, s3 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s3
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x) %z = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmin_v8f32_nofast(<8 x float> %x) { define arm_aapcs_vfpcc float @fmin_v8f32_nofast(<8 x float> %x) {
; CHECK-FP-LABEL: fmin_v8f32_nofast: ; CHECK-FP-LABEL: fmin_v8f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f32_nofast: ; CHECK-NOFP-LABEL: fmin_v8f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vminnm.f32 s10, s0, s4
; CHECK-NOFP-NEXT: vminnm.f32 s8, s1, s5 ; CHECK-NOFP-NEXT: vminnm.f32 s8, s1, s5
; CHECK-NOFP-NEXT: vminnm.f32 s8, s10, s8 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f32 s10, s2, s6 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s8
; CHECK-NOFP-NEXT: vminnm.f32 s8, s8, s10 ; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vminnm.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f32 s0, s8, s0 ; CHECK-NOFP-NEXT: vminnm.f32 s2, s3, s7
; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x) %z = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) { define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {
; CHECK-FP-LABEL: fmin_v4f16_nofast: ; CHECK-FP-LABEL: fmin_v4f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s4, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s6, s0 ; CHECK-FP-NEXT: vmovx.f16 s4, s0
; CHECK-FP-NEXT: vminnm.f16 s4, s1, s4 ; CHECK-FP-NEXT: vminnm.f16 s2, s1, s2
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f16_nofast: ; CHECK-NOFP-LABEL: fmin_v4f16_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s4, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vminnm.f16 s4, s0, s4 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x) %z = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmin_v8f16_nofast(<8 x half> %x) { define arm_aapcs_vfpcc half @fmin_v8f16_nofast(<8 x half> %x) {
; CHECK-FP-LABEL: fmin_v8f16_nofast: ; CHECK-FP-LABEL: fmin_v8f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f16_nofast: ; CHECK-NOFP-LABEL: fmin_v8f16_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s4, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s0
; CHECK-NOFP-NEXT: vmovx.f16 s6, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s4, s0, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s6 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s6, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s2 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vminnm.f16 s4, s4, s3 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x) %z = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmin_v16f16_nofast(<16 x half> %x) { define arm_aapcs_vfpcc half @fmin_v16f16_nofast(<16 x half> %x) {
; CHECK-FP-LABEL: fmin_v16f16_nofast: ; CHECK-FP-LABEL: fmin_v16f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v16f16_nofast: ; CHECK-NOFP-LABEL: fmin_v16f16_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vmovx.f16 s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s0
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vminnm.f16 s8, s10, s8
; CHECK-NOFP-NEXT: vminnm.f16 s10, s0, s4 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s8
; CHECK-NOFP-NEXT: vminnm.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vminnm.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vminnm.f16 s10, s1, s5
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vmovx.f16 s10, s5
; CHECK-NOFP-NEXT: vmovx.f16 s12, s1
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7
; CHECK-NOFP-NEXT: vminnm.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vmovx.f16 s12, s2
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vminnm.f16 s10, s2, s6
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vmovx.f16 s10, s6
; CHECK-NOFP-NEXT: vminnm.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vminnm.f16 s10, s3, s7
; CHECK-NOFP-NEXT: vminnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s0, s8, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s8, s1
; CHECK-NOFP-NEXT: vminnm.f16 s4, s8, s4
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vminnm.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vminnm.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x) %z = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc double @fmin_v1f64_nofast(<1 x double> %x) { define arm_aapcs_vfpcc double @fmin_v1f64_nofast(<1 x double> %x) {
; CHECK-LABEL: fmin_v1f64_nofast: ; CHECK-LABEL: fmin_v1f64_nofast:
Show All 12 Lines
entry: entry:
%z = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x) %z = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc double @fmin_v4f64_nofast(<4 x double> %x) { define arm_aapcs_vfpcc double @fmin_v4f64_nofast(<4 x double> %x) {
; CHECK-LABEL: fmin_v4f64_nofast: ; CHECK-LABEL: fmin_v4f64_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vminnm.f64 d4, d1, d3 ; CHECK-NEXT: vminnm.f64 d1, d1, d3
; CHECK-NEXT: vminnm.f64 d0, d0, d2 ; CHECK-NEXT: vminnm.f64 d0, d0, d2
; CHECK-NEXT: vminnm.f64 d0, d0, d4 ; CHECK-NEXT: vminnm.f64 d0, d0, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x) %z = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc float @fmin_v2f32_acc(<2 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmin_v2f32_acc(<2 x float> %x, float %y) {
; CHECK-LABEL: fmin_v2f32_acc: ; CHECK-LABEL: fmin_v2f32_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-NEXT: vminnm.f32 s0, s0, s1
; CHECK-NEXT: vminnm.f32 s0, s4, s0 ; CHECK-NEXT: vminnm.f32 s0, s4, s0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x) %z = call fast float @llvm.vector.reduce.fmin.v2f32(<2 x float> %x)
%c = fcmp fast olt float %y, %z %c = fcmp fast olt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmin_v4f32_acc(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmin_v4f32_acc(<4 x float> %x, float %y) {
; CHECK-FP-LABEL: fmin_v4f32_acc: ; CHECK-FP-LABEL: fmin_v4f32_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 s6, s2, s3 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s6 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-FP-NEXT: vminnm.f32 s0, s4, s0 ; CHECK-FP-NEXT: vminnm.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f32_acc: ; CHECK-NOFP-LABEL: fmin_v4f32_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vminnm.f32 s6, s0, s1 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f32 s6, s6, s2 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f32 s0, s6, s3 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s3
; CHECK-NOFP-NEXT: vminnm.f32 s0, s4, s0 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x) %z = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)
%c = fcmp fast olt float %y, %z %c = fcmp fast olt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmin_v8f32_acc(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmin_v8f32_acc(<8 x float> %x, float %y) {
; CHECK-FP-LABEL: fmin_v8f32_acc: ; CHECK-FP-LABEL: fmin_v8f32_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-FP-NEXT: vminnm.f32 s0, s8, s0 ; CHECK-FP-NEXT: vminnm.f32 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f32_acc: ; CHECK-NOFP-LABEL: fmin_v8f32_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vcmp.f32 s5, s1 ; CHECK-NOFP-NEXT: vcmp.f32 s5, s1
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f32 s4, s0
; CHECK-NOFP-NEXT: vselgt.f32 s10, s1, s5 ; CHECK-NOFP-NEXT: vselgt.f32 s10, s1, s5
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s6, s2 ; CHECK-NOFP-NEXT: vcmp.f32 s6, s2
; CHECK-NOFP-NEXT: vselgt.f32 s12, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s7, s3 ; CHECK-NOFP-NEXT: vcmp.f32 s7, s3
; CHECK-NOFP-NEXT: vselgt.f32 s14, s2, s6 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s10
; CHECK-NOFP-NEXT: vselgt.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f32 s2, s12, s10 ; CHECK-NOFP-NEXT: vselgt.f32 s4, s3, s7
; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s14 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f32 s0, s2, s0
; CHECK-NOFP-NEXT: vminnm.f32 s0, s8, s0 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x) %z = call fast float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)
%c = fcmp fast olt float %y, %z %c = fcmp fast olt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc half @fmin_v4f16_acc(<4 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmin_v4f16_acc(<4 x half> %x, half %y) {
; CHECK-FP-LABEL: fmin_v4f16_acc: ; CHECK-FP-LABEL: fmin_v4f16_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s6, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s8, s0 ; CHECK-FP-NEXT: vmovx.f16 s6, s0
; CHECK-FP-NEXT: vminnm.f16 s6, s1, s6 ; CHECK-FP-NEXT: vminnm.f16 s2, s1, s2
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s8
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-FP-NEXT: vminnm.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f16_acc: ; CHECK-NOFP-LABEL: fmin_v4f16_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vminnm.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x) %z = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)
%c = fcmp fast olt half %y, %z %c = fcmp fast olt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmin_v2f16_acc(<2 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmin_v2f16_acc(<2 x half> %x, half %y) {
; CHECK-LABEL: fmin_v2f16_acc: ; CHECK-LABEL: fmin_v2f16_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s6, s0 ; CHECK-NEXT: vmovx.f16 s2, s0
; CHECK-NEXT: vminnm.f16 s0, s0, s6 ; CHECK-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-NEXT: vminnm.f16 s0, s4, s0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmin.v2f16(<2 x half> %x) %z = call fast half @llvm.vector.reduce.fmin.v2f16(<2 x half> %x)
%c = fcmp fast olt half %y, %z %c = fcmp fast olt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmin_v8f16_acc(<8 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmin_v8f16_acc(<8 x half> %x, half %y) {
; CHECK-FP-LABEL: fmin_v8f16_acc: ; CHECK-FP-LABEL: fmin_v8f16_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q2, q0 ; CHECK-FP-NEXT: vrev32.16 q2, q0
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q2 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q2
; CHECK-FP-NEXT: vminnm.f16 s6, s2, s3 ; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-FP-NEXT: vminnm.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f16_acc: ; CHECK-NOFP-LABEL: fmin_v8f16_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s0
; CHECK-NOFP-NEXT: vmovx.f16 s8, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vminnm.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s8, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s2 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s3 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vminnm.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x) %z = call fast half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)
%c = fcmp fast olt half %y, %z %c = fcmp fast olt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmin_v16f16_acc(<16 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmin_v16f16_acc(<16 x half> %x, half %y) {
; CHECK-FP-LABEL: fmin_v16f16_acc: ; CHECK-FP-LABEL: fmin_v16f16_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vminnm.f16 s0, s8, s0 ; CHECK-FP-NEXT: vminnm.f16 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v16f16_acc: ; CHECK-NOFP-LABEL: fmin_v16f16_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s12, s0
; CHECK-NOFP-NEXT: vcmp.f16 s10, s12 ; CHECK-NOFP-NEXT: vcmp.f16 s10, s12
; CHECK-NOFP-NEXT: vmovx.f16 s14, s1
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s0
; CHECK-NOFP-NEXT: vselgt.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vselgt.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s5, s1 ; CHECK-NOFP-NEXT: vcmp.f16 s5, s1
; CHECK-NOFP-NEXT: vselgt.f16 s12, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vminnm.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s10
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vselgt.f16 s12, s1, s5 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s12, s5 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s10
; CHECK-NOFP-NEXT: vcmp.f16 s12, s14
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s6, s2 ; CHECK-NOFP-NEXT: vcmp.f16 s6, s2
; CHECK-NOFP-NEXT: vselgt.f16 s12, s14, s12 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s10, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s14, s2 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vselgt.f16 s12, s2, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vcmp.f16 s12, s14 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s2
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s7, s3 ; CHECK-NOFP-NEXT: vcmp.f16 s7, s3
; CHECK-NOFP-NEXT: vselgt.f16 s12, s14, s12 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s4, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vselgt.f16 s12, s3, s7 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vcmp.f16 s2, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vselgt.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s0, s10, s0
; CHECK-NOFP-NEXT: vminnm.f16 s0, s8, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x) %z = call fast half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)
%c = fcmp fast olt half %y, %z %c = fcmp fast olt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
Show All 24 Lines
} }
define arm_aapcs_vfpcc double @fmin_v4f64_acc(<4 x double> %x, double %y) { define arm_aapcs_vfpcc double @fmin_v4f64_acc(<4 x double> %x, double %y) {
; CHECK-LABEL: fmin_v4f64_acc: ; CHECK-LABEL: fmin_v4f64_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.f64 d3, d1 ; CHECK-NEXT: vcmp.f64 d3, d1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f64 d2, d0 ; CHECK-NEXT: vcmp.f64 d2, d0
; CHECK-NEXT: vselgt.f64 d5, d1, d3 ; CHECK-NEXT: vselgt.f64 d1, d1, d3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vselgt.f64 d0, d0, d2 ; CHECK-NEXT: vselgt.f64 d0, d0, d2
; CHECK-NEXT: vminnm.f64 d0, d0, d5 ; CHECK-NEXT: vminnm.f64 d0, d0, d1
; CHECK-NEXT: vminnm.f64 d0, d4, d0 ; CHECK-NEXT: vminnm.f64 d0, d4, d0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x) %z = call fast double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)
%c = fcmp fast olt double %y, %z %c = fcmp fast olt double %y, %z
%r = select i1 %c, double %y, double %z %r = select i1 %c, double %y, double %z
ret double %r ret double %r
} }
Show All 11 Linesentry:
%c = fcmp olt float %y, %z %c = fcmp olt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmin_v4f32_acc_nofast(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmin_v4f32_acc_nofast(<4 x float> %x, float %y) {
; CHECK-FP-LABEL: fmin_v4f32_acc_nofast: ; CHECK-FP-LABEL: fmin_v4f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 s6, s2, s3 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s6 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f32 s0, s4 ; CHECK-FP-NEXT: vcmp.f32 s0, s4
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f32_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v4f32_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vminnm.f32 s6, s0, s1 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f32 s6, s6, s2 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f32 s0, s6, s3 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s3
; CHECK-NOFP-NEXT: vcmp.f32 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f32 s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x) %z = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %x)
%c = fcmp olt float %y, %z %c = fcmp olt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmin_v8f32_acc_nofast(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmin_v8f32_acc_nofast(<8 x float> %x, float %y) {
; CHECK-FP-LABEL: fmin_v8f32_acc_nofast: ; CHECK-FP-LABEL: fmin_v8f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f32 s0, s8 ; CHECK-FP-NEXT: vcmp.f32 s0, s8
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f32_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v8f32_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vminnm.f32 s12, s0, s4
; CHECK-NOFP-NEXT: vminnm.f32 s10, s1, s5 ; CHECK-NOFP-NEXT: vminnm.f32 s10, s1, s5
; CHECK-NOFP-NEXT: vminnm.f32 s10, s12, s10 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f32 s12, s2, s6 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s10
; CHECK-NOFP-NEXT: vminnm.f32 s10, s10, s12 ; CHECK-NOFP-NEXT: vminnm.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vminnm.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f32 s0, s10, s0 ; CHECK-NOFP-NEXT: vminnm.f32 s2, s3, s7
; CHECK-NOFP-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vcmp.f32 s0, s8 ; CHECK-NOFP-NEXT: vcmp.f32 s0, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s8, s0 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x) %z = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %x)
%c = fcmp olt float %y, %z %c = fcmp olt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc half @fmin_v4f16_acc_nofast(<4 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmin_v4f16_acc_nofast(<4 x half> %x, half %y) {
; CHECK-FP-LABEL: fmin_v4f16_acc_nofast: ; CHECK-FP-LABEL: fmin_v4f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s6, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s8, s0 ; CHECK-FP-NEXT: vmovx.f16 s6, s0
; CHECK-FP-NEXT: vminnm.f16 s6, s1, s6 ; CHECK-FP-NEXT: vminnm.f16 s2, s1, s2
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s8
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f16 s0, s4 ; CHECK-FP-NEXT: vcmp.f16 s0, s4
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f16_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v4f16_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vminnm.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vcmp.f16 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f16 s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x) %z = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %x)
%c = fcmp olt half %y, %z %c = fcmp olt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmin_v8f16_acc_nofast(<8 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmin_v8f16_acc_nofast(<8 x half> %x, half %y) {
; CHECK-FP-LABEL: fmin_v8f16_acc_nofast: ; CHECK-FP-LABEL: fmin_v8f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q2, q0 ; CHECK-FP-NEXT: vrev32.16 q2, q0
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q2 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q2
; CHECK-FP-NEXT: vminnm.f16 s6, s2, s3 ; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s6 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f16 s0, s4 ; CHECK-FP-NEXT: vcmp.f16 s0, s4
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f16_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v8f16_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s0
; CHECK-NOFP-NEXT: vmovx.f16 s8, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vminnm.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s8, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s2 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vminnm.f16 s6, s6, s3 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vminnm.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vcmp.f16 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f16 s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x) %z = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %x)
%c = fcmp olt half %y, %z %c = fcmp olt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmin_v16f16_acc_nofast(<16 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmin_v16f16_acc_nofast(<16 x half> %x, half %y) {
; CHECK-FP-LABEL: fmin_v16f16_acc_nofast: ; CHECK-FP-LABEL: fmin_v16f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vminnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vminnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f16 s0, s8 ; CHECK-FP-NEXT: vcmp.f16 s0, s8
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f16 s0, s8, s0 ; CHECK-FP-NEXT: vselgt.f16 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v16f16_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v16f16_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s12, s0
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vminnm.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vminnm.f16 s12, s0, s4 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s10
; CHECK-NOFP-NEXT: vminnm.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vminnm.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vminnm.f16 s12, s1, s5 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s12, s5 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s1
; CHECK-NOFP-NEXT: vmovx.f16 s14, s1 ; CHECK-NOFP-NEXT: vminnm.f16 s4, s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7
; CHECK-NOFP-NEXT: vminnm.f16 s12, s14, s12
; CHECK-NOFP-NEXT: vmovx.f16 s14, s2
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vminnm.f16 s12, s2, s6
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmovx.f16 s12, s6
; CHECK-NOFP-NEXT: vminnm.f16 s12, s14, s12
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vminnm.f16 s12, s3, s7
; CHECK-NOFP-NEXT: vminnm.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vminnm.f16 s0, s10, s0 ; CHECK-NOFP-NEXT: vminnm.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vminnm.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vminnm.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vminnm.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vcmp.f16 s0, s8 ; CHECK-NOFP-NEXT: vcmp.f16 s0, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f16 s0, s8, s0 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x) %z = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %x)
%c = fcmp olt half %y, %z %c = fcmp olt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
Show All 27 Linesentry:
%c = fcmp olt double %y, %z %c = fcmp olt double %y, %z
%r = select i1 %c, double %y, double %z %r = select i1 %c, double %y, double %z
ret double %r ret double %r
} }
define arm_aapcs_vfpcc double @fmin_v4f64_acc_nofast(<4 x double> %x, double %y) { define arm_aapcs_vfpcc double @fmin_v4f64_acc_nofast(<4 x double> %x, double %y) {
; CHECK-LABEL: fmin_v4f64_acc_nofast: ; CHECK-LABEL: fmin_v4f64_acc_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vminnm.f64 d5, d1, d3 ; CHECK-NEXT: vminnm.f64 d1, d1, d3
; CHECK-NEXT: vminnm.f64 d0, d0, d2 ; CHECK-NEXT: vminnm.f64 d0, d0, d2
; CHECK-NEXT: vminnm.f64 d0, d0, d5 ; CHECK-NEXT: vminnm.f64 d0, d0, d1
; CHECK-NEXT: vcmp.f64 d0, d4 ; CHECK-NEXT: vcmp.f64 d0, d4
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vselgt.f64 d0, d4, d0 ; CHECK-NEXT: vselgt.f64 d0, d4, d0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x) %z = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x)
%c = fcmp olt double %y, %z %c = fcmp olt double %y, %z
%r = select i1 %c, double %y, double %z %r = select i1 %c, double %y, double %z
ret double %r ret double %r
} }
define arm_aapcs_vfpcc float @fmax_v2f32(<2 x float> %x) { define arm_aapcs_vfpcc float @fmax_v2f32(<2 x float> %x) {
; CHECK-LABEL: fmax_v2f32: ; CHECK-LABEL: fmax_v2f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x) %z = call fast float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmax_v4f32(<4 x float> %x) { define arm_aapcs_vfpcc float @fmax_v4f32(<4 x float> %x) {
; CHECK-FP-LABEL: fmax_v4f32: ; CHECK-FP-LABEL: fmax_v4f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f32: ; CHECK-NOFP-LABEL: fmax_v4f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmaxnm.f32 s4, s0, s1 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f32 s4, s4, s2 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s4, s3 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s3
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x) %z = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmax_v8f32(<8 x float> %x) { define arm_aapcs_vfpcc float @fmax_v8f32(<8 x float> %x) {
; CHECK-FP-LABEL: fmax_v8f32: ; CHECK-FP-LABEL: fmax_v8f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f32: ; CHECK-NOFP-LABEL: fmax_v8f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vcmp.f32 s1, s5 ; CHECK-NOFP-NEXT: vcmp.f32 s1, s5
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f32 s0, s4
; CHECK-NOFP-NEXT: vselgt.f32 s8, s1, s5 ; CHECK-NOFP-NEXT: vselgt.f32 s8, s1, s5
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s2, s6 ; CHECK-NOFP-NEXT: vcmp.f32 s2, s6
; CHECK-NOFP-NEXT: vselgt.f32 s10, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s3, s7 ; CHECK-NOFP-NEXT: vcmp.f32 s3, s7
; CHECK-NOFP-NEXT: vselgt.f32 s12, s2, s6 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s8
; CHECK-NOFP-NEXT: vselgt.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s10, s8 ; CHECK-NOFP-NEXT: vselgt.f32 s4, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s2, s12 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s2, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x) %z = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fmax_v4f16(<4 x half> %x) { define arm_aapcs_vfpcc half @fmax_v4f16(<4 x half> %x) {
; CHECK-FP-LABEL: fmax_v4f16: ; CHECK-FP-LABEL: fmax_v4f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s4, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s6, s0 ; CHECK-FP-NEXT: vmovx.f16 s4, s0
; CHECK-FP-NEXT: vmaxnm.f16 s4, s1, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s1, s2
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s6
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f16: ; CHECK-NOFP-LABEL: fmax_v4f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s4, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x) %z = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmax_v8f16(<8 x half> %x) { define arm_aapcs_vfpcc half @fmax_v8f16(<8 x half> %x) {
; CHECK-FP-LABEL: fmax_v8f16: ; CHECK-FP-LABEL: fmax_v8f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f16: ; CHECK-NOFP-LABEL: fmax_v8f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s4, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s0
; CHECK-NOFP-NEXT: vmovx.f16 s6, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s0, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s6 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s6, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s2 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s3 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x) %z = call fast half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmax_v16f16(<16 x half> %x) { define arm_aapcs_vfpcc half @fmax_v16f16(<16 x half> %x) {
; CHECK-FP-LABEL: fmax_v16f16: ; CHECK-FP-LABEL: fmax_v16f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v16f16: ; CHECK-NOFP-LABEL: fmax_v16f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vmovx.f16 s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s0
; CHECK-NOFP-NEXT: vcmp.f16 s10, s8 ; CHECK-NOFP-NEXT: vcmp.f16 s10, s8
; CHECK-NOFP-NEXT: vmovx.f16 s12, s1
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f16 s0, s4
; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s1, s5 ; CHECK-NOFP-NEXT: vcmp.f16 s1, s5
; CHECK-NOFP-NEXT: vselgt.f16 s10, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s8
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vselgt.f16 s10, s1, s5 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s10, s5 ; CHECK-NOFP-NEXT: vcmp.f16 s8, s4
; CHECK-NOFP-NEXT: vcmp.f16 s12, s10
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s2, s6 ; CHECK-NOFP-NEXT: vcmp.f16 s2, s6
; CHECK-NOFP-NEXT: vselgt.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s8, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s2 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vselgt.f16 s10, s2, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s10, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vcmp.f16 s12, s10 ; CHECK-NOFP-NEXT: vcmp.f16 s2, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s3, s7 ; CHECK-NOFP-NEXT: vcmp.f16 s3, s7
; CHECK-NOFP-NEXT: vselgt.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vselgt.f16 s10, s3, s7 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vcmp.f16 s4, s2
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vselgt.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x) %z = call fast half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc double @fmax_v1f64(<1 x double> %x) { define arm_aapcs_vfpcc double @fmax_v1f64(<1 x double> %x) {
; CHECK-LABEL: fmax_v1f64: ; CHECK-LABEL: fmax_v1f64:
Show All 15 Lines
} }
define arm_aapcs_vfpcc double @fmax_v4f64(<4 x double> %x) { define arm_aapcs_vfpcc double @fmax_v4f64(<4 x double> %x) {
; CHECK-LABEL: fmax_v4f64: ; CHECK-LABEL: fmax_v4f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.f64 d1, d3 ; CHECK-NEXT: vcmp.f64 d1, d3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f64 d0, d2 ; CHECK-NEXT: vcmp.f64 d0, d2
; CHECK-NEXT: vselgt.f64 d4, d1, d3 ; CHECK-NEXT: vselgt.f64 d1, d1, d3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vselgt.f64 d0, d0, d2 ; CHECK-NEXT: vselgt.f64 d0, d0, d2
; CHECK-NEXT: vmaxnm.f64 d0, d0, d4 ; CHECK-NEXT: vmaxnm.f64 d0, d0, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x) %z = call fast double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc float @fmax_v2f32_nofast(<2 x float> %x) { define arm_aapcs_vfpcc float @fmax_v2f32_nofast(<2 x float> %x) {
; CHECK-LABEL: fmax_v2f32_nofast: ; CHECK-LABEL: fmax_v2f32_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x) %z = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmax_v4f32_nofast(<4 x float> %x) { define arm_aapcs_vfpcc float @fmax_v4f32_nofast(<4 x float> %x) {
; CHECK-FP-LABEL: fmax_v4f32_nofast: ; CHECK-FP-LABEL: fmax_v4f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f32_nofast: ; CHECK-NOFP-LABEL: fmax_v4f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmaxnm.f32 s4, s0, s1 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f32 s4, s4, s2 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s4, s3 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s3
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x) %z = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmax_v8f32_nofast(<8 x float> %x) { define arm_aapcs_vfpcc float @fmax_v8f32_nofast(<8 x float> %x) {
; CHECK-FP-LABEL: fmax_v8f32_nofast: ; CHECK-FP-LABEL: fmax_v8f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f32_nofast: ; CHECK-NOFP-LABEL: fmax_v8f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f32 s8, s1, s5 ; CHECK-NOFP-NEXT: vmaxnm.f32 s8, s1, s5
; CHECK-NOFP-NEXT: vmaxnm.f32 s8, s10, s8 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f32 s10, s2, s6 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s8
; CHECK-NOFP-NEXT: vmaxnm.f32 s8, s8, s10 ; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s8, s0 ; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x) %z = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fmax_v4f16_nofast(<4 x half> %x) { define arm_aapcs_vfpcc half @fmax_v4f16_nofast(<4 x half> %x) {
; CHECK-FP-LABEL: fmax_v4f16_nofast: ; CHECK-FP-LABEL: fmax_v4f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s4, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s6, s0 ; CHECK-FP-NEXT: vmovx.f16 s4, s0
; CHECK-FP-NEXT: vmaxnm.f16 s4, s1, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s1, s2
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s6
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f16_nofast: ; CHECK-NOFP-LABEL: fmax_v4f16_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s4, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x) %z = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmax_v8f16_nofast(<8 x half> %x) { define arm_aapcs_vfpcc half @fmax_v8f16_nofast(<8 x half> %x) {
; CHECK-FP-LABEL: fmax_v8f16_nofast: ; CHECK-FP-LABEL: fmax_v8f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f16_nofast: ; CHECK-NOFP-LABEL: fmax_v8f16_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s4, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s0
; CHECK-NOFP-NEXT: vmovx.f16 s6, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s0, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s6 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s6, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s2 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s4, s3 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x) %z = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmax_v16f16_nofast(<16 x half> %x) { define arm_aapcs_vfpcc half @fmax_v16f16_nofast(<16 x half> %x) {
; CHECK-FP-LABEL: fmax_v16f16_nofast: ; CHECK-FP-LABEL: fmax_v16f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v16f16_nofast: ; CHECK-NOFP-LABEL: fmax_v16f16_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vmovx.f16 s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s0
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s10, s8
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s8
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s1, s5
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vmovx.f16 s10, s5
; CHECK-NOFP-NEXT: vmovx.f16 s12, s1
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vmovx.f16 s12, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s2, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vmovx.f16 s10, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s8, s8, s10
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s8, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s8, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s8, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x) %z = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc double @fmax_v1f64_nofast(<1 x double> %x) { define arm_aapcs_vfpcc double @fmax_v1f64_nofast(<1 x double> %x) {
; CHECK-LABEL: fmax_v1f64_nofast: ; CHECK-LABEL: fmax_v1f64_nofast:
Show All 12 Lines
entry: entry:
%z = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x) %z = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc double @fmax_v4f64_nofast(<4 x double> %x) { define arm_aapcs_vfpcc double @fmax_v4f64_nofast(<4 x double> %x) {
; CHECK-LABEL: fmax_v4f64_nofast: ; CHECK-LABEL: fmax_v4f64_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmaxnm.f64 d4, d1, d3 ; CHECK-NEXT: vmaxnm.f64 d1, d1, d3
; CHECK-NEXT: vmaxnm.f64 d0, d0, d2 ; CHECK-NEXT: vmaxnm.f64 d0, d0, d2
; CHECK-NEXT: vmaxnm.f64 d0, d0, d4 ; CHECK-NEXT: vmaxnm.f64 d0, d0, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x) %z = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc float @fmax_v2f32_acc(<2 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmax_v2f32_acc(<2 x float> %x, float %y) {
; CHECK-LABEL: fmax_v2f32_acc: ; CHECK-LABEL: fmax_v2f32_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-NEXT: vmaxnm.f32 s0, s4, s0 ; CHECK-NEXT: vmaxnm.f32 s0, s4, s0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x) %z = call fast float @llvm.vector.reduce.fmax.v2f32(<2 x float> %x)
%c = fcmp fast ogt float %y, %z %c = fcmp fast ogt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmax_v4f32_acc(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmax_v4f32_acc(<4 x float> %x, float %y) {
; CHECK-FP-LABEL: fmax_v4f32_acc: ; CHECK-FP-LABEL: fmax_v4f32_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 s6, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s6 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-FP-NEXT: vmaxnm.f32 s0, s4, s0 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f32_acc: ; CHECK-NOFP-LABEL: fmax_v4f32_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmaxnm.f32 s6, s0, s1 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f32 s6, s6, s2 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s6, s3 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s3
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s4, s0 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x) %z = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)
%c = fcmp fast ogt float %y, %z %c = fcmp fast ogt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmax_v8f32_acc(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmax_v8f32_acc(<8 x float> %x, float %y) {
; CHECK-FP-LABEL: fmax_v8f32_acc: ; CHECK-FP-LABEL: fmax_v8f32_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-FP-NEXT: vmaxnm.f32 s0, s8, s0 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f32_acc: ; CHECK-NOFP-LABEL: fmax_v8f32_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vcmp.f32 s1, s5 ; CHECK-NOFP-NEXT: vcmp.f32 s1, s5
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f32 s0, s4
; CHECK-NOFP-NEXT: vselgt.f32 s10, s1, s5 ; CHECK-NOFP-NEXT: vselgt.f32 s10, s1, s5
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s2, s6 ; CHECK-NOFP-NEXT: vcmp.f32 s2, s6
; CHECK-NOFP-NEXT: vselgt.f32 s12, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f32 s3, s7 ; CHECK-NOFP-NEXT: vcmp.f32 s3, s7
; CHECK-NOFP-NEXT: vselgt.f32 s14, s2, s6 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s10
; CHECK-NOFP-NEXT: vselgt.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s12, s10 ; CHECK-NOFP-NEXT: vselgt.f32 s4, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s2, s14 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s2, s0
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s8, s0 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x) %z = call fast float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)
%c = fcmp fast ogt float %y, %z %c = fcmp fast ogt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc half @fmax_v2f16_acc(<2 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmax_v2f16_acc(<2 x half> %x, half %y) {
; CHECK-LABEL: fmax_v2f16_acc: ; CHECK-LABEL: fmax_v2f16_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s6, s0 ; CHECK-NEXT: vmovx.f16 s2, s0
; CHECK-NEXT: vmaxnm.f16 s0, s0, s6 ; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-NEXT: vmaxnm.f16 s0, s4, s0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmax.v2f16(<2 x half> %x) %z = call fast half @llvm.vector.reduce.fmax.v2f16(<2 x half> %x)
%c = fcmp fast ogt half %y, %z %c = fcmp fast ogt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmax_v4f16_acc(<4 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmax_v4f16_acc(<4 x half> %x, half %y) {
; CHECK-FP-LABEL: fmax_v4f16_acc: ; CHECK-FP-LABEL: fmax_v4f16_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s6, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s8, s0 ; CHECK-FP-NEXT: vmovx.f16 s6, s0
; CHECK-FP-NEXT: vmaxnm.f16 s6, s1, s6 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s1, s2
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s8
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s6 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s6
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f16_acc: ; CHECK-NOFP-LABEL: fmax_v4f16_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x) %z = call fast half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)
%c = fcmp fast ogt half %y, %z %c = fcmp fast ogt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmax_v8f16_acc(<8 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmax_v8f16_acc(<8 x half> %x, half %y) {
; CHECK-FP-LABEL: fmax_v8f16_acc: ; CHECK-FP-LABEL: fmax_v8f16_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q2, q0 ; CHECK-FP-NEXT: vrev32.16 q2, q0
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q2 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q2
; CHECK-FP-NEXT: vmaxnm.f16 s6, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s6 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f16_acc: ; CHECK-NOFP-LABEL: fmax_v8f16_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s0
; CHECK-NOFP-NEXT: vmovx.f16 s8, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s8, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s2 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s3 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x) %z = call fast half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)
%c = fcmp fast ogt half %y, %z %c = fcmp fast ogt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmax_v16f16_acc(<16 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmax_v16f16_acc(<16 x half> %x, half %y) {
; CHECK-FP-LABEL: fmax_v16f16_acc: ; CHECK-FP-LABEL: fmax_v16f16_acc:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vmaxnm.f16 s0, s8, s0 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v16f16_acc: ; CHECK-NOFP-LABEL: fmax_v16f16_acc:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s12, s0
; CHECK-NOFP-NEXT: vcmp.f16 s12, s10 ; CHECK-NOFP-NEXT: vcmp.f16 s12, s10
; CHECK-NOFP-NEXT: vmovx.f16 s14, s1
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f16 s0, s4
; CHECK-NOFP-NEXT: vselgt.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vselgt.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s1, s5 ; CHECK-NOFP-NEXT: vcmp.f16 s1, s5
; CHECK-NOFP-NEXT: vselgt.f16 s12, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s10
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vselgt.f16 s12, s1, s5 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s12, s5 ; CHECK-NOFP-NEXT: vcmp.f16 s10, s4
; CHECK-NOFP-NEXT: vcmp.f16 s14, s12
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s2, s6 ; CHECK-NOFP-NEXT: vcmp.f16 s2, s6
; CHECK-NOFP-NEXT: vselgt.f16 s12, s14, s12 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s10, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s14, s2 ; CHECK-NOFP-NEXT: vselgt.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vselgt.f16 s12, s2, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vcmp.f16 s14, s12 ; CHECK-NOFP-NEXT: vcmp.f16 s2, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s3, s7 ; CHECK-NOFP-NEXT: vcmp.f16 s3, s7
; CHECK-NOFP-NEXT: vselgt.f16 s12, s14, s12 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vselgt.f16 s12, s3, s7 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vcmp.f16 s4, s2
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vselgt.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vselgt.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s10, s0
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s8, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x) %z = call fast half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)
%c = fcmp fast ogt half %y, %z %c = fcmp fast ogt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
Show All 24 Lines
} }
define arm_aapcs_vfpcc double @fmax_v4f64_acc(<4 x double> %x, double %y) { define arm_aapcs_vfpcc double @fmax_v4f64_acc(<4 x double> %x, double %y) {
; CHECK-LABEL: fmax_v4f64_acc: ; CHECK-LABEL: fmax_v4f64_acc:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcmp.f64 d1, d3 ; CHECK-NEXT: vcmp.f64 d1, d3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f64 d0, d2 ; CHECK-NEXT: vcmp.f64 d0, d2
; CHECK-NEXT: vselgt.f64 d5, d1, d3 ; CHECK-NEXT: vselgt.f64 d1, d1, d3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vselgt.f64 d0, d0, d2 ; CHECK-NEXT: vselgt.f64 d0, d0, d2
; CHECK-NEXT: vmaxnm.f64 d0, d0, d5 ; CHECK-NEXT: vmaxnm.f64 d0, d0, d1
; CHECK-NEXT: vmaxnm.f64 d0, d4, d0 ; CHECK-NEXT: vmaxnm.f64 d0, d4, d0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x) %z = call fast double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)
%c = fcmp fast ogt double %y, %z %c = fcmp fast ogt double %y, %z
%r = select i1 %c, double %y, double %z %r = select i1 %c, double %y, double %z
ret double %r ret double %r
} }
Show All 11 Linesentry:
%c = fcmp ogt float %y, %z %c = fcmp ogt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmax_v4f32_acc_nofast(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmax_v4f32_acc_nofast(<4 x float> %x, float %y) {
; CHECK-FP-LABEL: fmax_v4f32_acc_nofast: ; CHECK-FP-LABEL: fmax_v4f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 s6, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s6 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f32 s4, s0 ; CHECK-FP-NEXT: vcmp.f32 s4, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f32_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v4f32_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmaxnm.f32 s6, s0, s1 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f32 s6, s6, s2 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s6, s3 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s3
; CHECK-NOFP-NEXT: vcmp.f32 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f32 s4, s0
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x) %z = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %x)
%c = fcmp ogt float %y, %z %c = fcmp ogt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmax_v8f32_acc_nofast(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmax_v8f32_acc_nofast(<8 x float> %x, float %y) {
; CHECK-FP-LABEL: fmax_v8f32_acc_nofast: ; CHECK-FP-LABEL: fmax_v8f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f32 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f32 s8, s0 ; CHECK-FP-NEXT: vcmp.f32 s8, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f32_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v8f32_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmaxnm.f32 s12, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f32 s10, s1, s5 ; CHECK-NOFP-NEXT: vmaxnm.f32 s10, s1, s5
; CHECK-NOFP-NEXT: vmaxnm.f32 s10, s12, s10 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f32 s12, s2, s6 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s10
; CHECK-NOFP-NEXT: vmaxnm.f32 s10, s10, s12 ; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s10, s0 ; CHECK-NOFP-NEXT: vmaxnm.f32 s2, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vcmp.f32 s8, s0 ; CHECK-NOFP-NEXT: vcmp.f32 s8, s0
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s8, s0 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x) %z = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %x)
%c = fcmp ogt float %y, %z %c = fcmp ogt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc half @fmax_v4f16_acc_nofast(<4 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmax_v4f16_acc_nofast(<4 x half> %x, half %y) {
; CHECK-FP-LABEL: fmax_v4f16_acc_nofast: ; CHECK-FP-LABEL: fmax_v4f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s6, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s8, s0 ; CHECK-FP-NEXT: vmovx.f16 s6, s0
; CHECK-FP-NEXT: vmaxnm.f16 s6, s1, s6 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s1, s2
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s8
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s6 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s6
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f16 s4, s0 ; CHECK-FP-NEXT: vcmp.f16 s4, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f16_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v4f16_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vcmp.f16 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s0
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x) %z = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %x)
%c = fcmp ogt half %y, %z %c = fcmp ogt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmax_v8f16_acc_nofast(<8 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmax_v8f16_acc_nofast(<8 x half> %x, half %y) {
; CHECK-FP-LABEL: fmax_v8f16_acc_nofast: ; CHECK-FP-LABEL: fmax_v8f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q2, q0 ; CHECK-FP-NEXT: vrev32.16 q2, q0
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q2 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q2
; CHECK-FP-NEXT: vmaxnm.f16 s6, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s6 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f16 s4, s0 ; CHECK-FP-NEXT: vcmp.f16 s4, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f16_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v8f16_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s0
; CHECK-NOFP-NEXT: vmovx.f16 s8, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s8, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s2 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s6, s6, s3 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vcmp.f16 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s0
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x) %z = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %x)
%c = fcmp ogt half %y, %z %c = fcmp ogt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
ret half %r ret half %r
} }
define arm_aapcs_vfpcc half @fmax_v16f16_acc_nofast(<16 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmax_v16f16_acc_nofast(<16 x half> %x, half %y) {
; CHECK-FP-LABEL: fmax_v16f16_acc_nofast: ; CHECK-FP-LABEL: fmax_v16f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmaxnm.f16 s4, s2, s3 ; CHECK-FP-NEXT: vmaxnm.f16 s2, s2, s3
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s1
; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-FP-NEXT: vcmp.f16 s8, s0 ; CHECK-FP-NEXT: vcmp.f16 s8, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f16 s0, s8, s0 ; CHECK-FP-NEXT: vselgt.f16 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v16f16_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v16f16_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s12, s0
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vmaxnm.f16 s12, s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s10
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vmaxnm.f16 s12, s1, s5 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s12, s5 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s1
; CHECK-NOFP-NEXT: vmovx.f16 s14, s1 ; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s12, s14, s12
; CHECK-NOFP-NEXT: vmovx.f16 s14, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmaxnm.f16 s12, s2, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmovx.f16 s12, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s12, s14, s12
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmaxnm.f16 s12, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s10, s0 ; CHECK-NOFP-NEXT: vmaxnm.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vmaxnm.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vcmp.f16 s8, s0 ; CHECK-NOFP-NEXT: vcmp.f16 s8, s0
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f16 s0, s8, s0 ; CHECK-NOFP-NEXT: vselgt.f16 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x) %z = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %x)
%c = fcmp ogt half %y, %z %c = fcmp ogt half %y, %z
%r = select i1 %c, half %y, half %z %r = select i1 %c, half %y, half %z
Show All 27 Linesentry:
%c = fcmp ogt double %y, %z %c = fcmp ogt double %y, %z
%r = select i1 %c, double %y, double %z %r = select i1 %c, double %y, double %z
ret double %r ret double %r
} }
define arm_aapcs_vfpcc double @fmax_v4f64_acc_nofast(<4 x double> %x, double %y) { define arm_aapcs_vfpcc double @fmax_v4f64_acc_nofast(<4 x double> %x, double %y) {
; CHECK-LABEL: fmax_v4f64_acc_nofast: ; CHECK-LABEL: fmax_v4f64_acc_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmaxnm.f64 d5, d1, d3 ; CHECK-NEXT: vmaxnm.f64 d1, d1, d3
; CHECK-NEXT: vmaxnm.f64 d0, d0, d2 ; CHECK-NEXT: vmaxnm.f64 d0, d0, d2
; CHECK-NEXT: vmaxnm.f64 d0, d0, d5 ; CHECK-NEXT: vmaxnm.f64 d0, d0, d1
; CHECK-NEXT: vcmp.f64 d4, d0 ; CHECK-NEXT: vcmp.f64 d4, d0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vselgt.f64 d0, d4, d0 ; CHECK-NEXT: vselgt.f64 d0, d4, d0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x) %z = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x)
%c = fcmp ogt double %y, %z %c = fcmp ogt double %y, %z
%r = select i1 %c, double %y, double %z %r = select i1 %c, double %y, double %z
Show All 23 Lines

llvm/test/CodeGen/Thumb2/mve-vecreduce-fmul.ll

Show All 10 Lines
entry: entry:
%z = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float %y, <2 x float> %x) %z = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float %y, <2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmul_v4f32(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmul_v4f32(<4 x float> %x, float %y) {
; CHECK-FP-LABEL: fmul_v4f32: ; CHECK-FP-LABEL: fmul_v4f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmul.f32 s6, s2, s3 ; CHECK-FP-NEXT: vmul.f32 s2, s2, s3
; CHECK-FP-NEXT: vmul.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s1
; CHECK-FP-NEXT: vmul.f32 s0, s0, s6 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s2
; CHECK-FP-NEXT: vmul.f32 s0, s4, s0 ; CHECK-FP-NEXT: vmul.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmul_v4f32: ; CHECK-NOFP-LABEL: fmul_v4f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmul.f32 s6, s0, s1 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vmul.f32 s6, s6, s2 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmul.f32 s0, s6, s3 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s3
; CHECK-NOFP-NEXT: vmul.f32 s0, s4, s0 ; CHECK-NOFP-NEXT: vmul.f32 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %y, <4 x float> %x) %z = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %y, <4 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmul_v8f32(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmul_v8f32(<8 x float> %x, float %y) {
; CHECK-FP-LABEL: fmul_v8f32: ; CHECK-FP-LABEL: fmul_v8f32:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmul.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmul.f32 q0, q0, q1
; CHECK-FP-NEXT: vmul.f32 s4, s2, s3 ; CHECK-FP-NEXT: vmul.f32 s2, s2, s3
; CHECK-FP-NEXT: vmul.f32 s0, s0, s1 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s1
; CHECK-FP-NEXT: vmul.f32 s0, s0, s4 ; CHECK-FP-NEXT: vmul.f32 s0, s0, s2
; CHECK-FP-NEXT: vmul.f32 s0, s8, s0 ; CHECK-FP-NEXT: vmul.f32 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmul_v8f32: ; CHECK-NOFP-LABEL: fmul_v8f32:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmul.f32 s12, s0, s4 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmul.f32 s10, s1, s5 ; CHECK-NOFP-NEXT: vmul.f32 s10, s1, s5
; CHECK-NOFP-NEXT: vmul.f32 s14, s2, s6 ; CHECK-NOFP-NEXT: vmul.f32 s2, s2, s6
; CHECK-NOFP-NEXT: vmul.f32 s0, s3, s7 ; CHECK-NOFP-NEXT: vmul.f32 s4, s3, s7
; CHECK-NOFP-NEXT: vmul.f32 s10, s12, s10 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s10
; CHECK-NOFP-NEXT: vmul.f32 s2, s10, s14 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s2
; CHECK-NOFP-NEXT: vmul.f32 s0, s2, s0 ; CHECK-NOFP-NEXT: vmul.f32 s0, s0, s4
; CHECK-NOFP-NEXT: vmul.f32 s0, s8, s0 ; CHECK-NOFP-NEXT: vmul.f32 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float %y, <8 x float> %x) %z = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float %y, <8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fmul_v2f16(<2 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmul_v2f16(<2 x half> %x, half %y) {
; CHECK-LABEL: fmul_v2f16: ; CHECK-LABEL: fmul_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s6, s0 ; CHECK-NEXT: vmovx.f16 s2, s0
; CHECK-NEXT: vmul.f16 s0, s0, s6 ; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: vmul.f16 s0, s4, s0 ; CHECK-NEXT: vmul.f16 s0, s4, s0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmul.f16.v2f16(half %y, <2 x half> %x) %z = call fast half @llvm.vector.reduce.fmul.f16.v2f16(half %y, <2 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmul_v4f16(<4 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmul_v4f16(<4 x half> %x, half %y) {
; CHECK-FP-LABEL: fmul_v4f16: ; CHECK-FP-LABEL: fmul_v4f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmovx.f16 s6, s1 ; CHECK-FP-NEXT: vmovx.f16 s2, s1
; CHECK-FP-NEXT: vmovx.f16 s8, s0 ; CHECK-FP-NEXT: vmovx.f16 s6, s0
; CHECK-FP-NEXT: vmul.f16 s6, s1, s6 ; CHECK-FP-NEXT: vmul.f16 s2, s1, s2
; CHECK-FP-NEXT: vmul.f16 s0, s0, s8
; CHECK-FP-NEXT: vmul.f16 s0, s0, s6 ; CHECK-FP-NEXT: vmul.f16 s0, s0, s6
; CHECK-FP-NEXT: vmul.f16 s0, s0, s2
; CHECK-FP-NEXT: vmul.f16 s0, s4, s0 ; CHECK-FP-NEXT: vmul.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmul_v4f16: ; CHECK-NOFP-LABEL: fmul_v4f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s0
; CHECK-NOFP-NEXT: vmul.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s0, s1 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s1
; CHECK-NOFP-NEXT: vmul.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmul.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmul.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vmul.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmul.f16.v4f16(half %y, <4 x half> %x) %z = call fast half @llvm.vector.reduce.fmul.f16.v4f16(half %y, <4 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmul_v8f16(<8 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmul_v8f16(<8 x half> %x, half %y) {
; CHECK-FP-LABEL: fmul_v8f16: ; CHECK-FP-LABEL: fmul_v8f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vrev32.16 q2, q0 ; CHECK-FP-NEXT: vrev32.16 q2, q0
; CHECK-FP-NEXT: vmul.f16 q0, q0, q2 ; CHECK-FP-NEXT: vmul.f16 q0, q0, q2
; CHECK-FP-NEXT: vmul.f16 s6, s2, s3 ; CHECK-FP-NEXT: vmul.f16 s2, s2, s3
; CHECK-FP-NEXT: vmul.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmul.f16 s0, s0, s1
; CHECK-FP-NEXT: vmul.f16 s0, s0, s6 ; CHECK-FP-NEXT: vmul.f16 s0, s0, s2
; CHECK-FP-NEXT: vmul.f16 s0, s4, s0 ; CHECK-FP-NEXT: vmul.f16 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmul_v8f16: ; CHECK-NOFP-LABEL: fmul_v8f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s6, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s0
; CHECK-NOFP-NEXT: vmovx.f16 s8, s1 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vmul.f16 s6, s0, s6 ; CHECK-NOFP-NEXT: vmovx.f16 s6, s1
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s1
; CHECK-NOFP-NEXT: vmul.f16 s6, s6, s1 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s6
; CHECK-NOFP-NEXT: vmul.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s8, s2 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmul.f16 s6, s6, s2 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmul.f16 s6, s6, s8 ; CHECK-NOFP-NEXT: vmovx.f16 s2, s3
; CHECK-NOFP-NEXT: vmul.f16 s6, s6, s3 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s3
; CHECK-NOFP-NEXT: vmul.f16 s0, s6, s0 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmul.f16 s0, s4, s0 ; CHECK-NOFP-NEXT: vmul.f16 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmul.f16.v8f16(half %y, <8 x half> %x) %z = call fast half @llvm.vector.reduce.fmul.f16.v8f16(half %y, <8 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmul_v16f16(<16 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmul_v16f16(<16 x half> %x, half %y) {
; CHECK-FP-LABEL: fmul_v16f16: ; CHECK-FP-LABEL: fmul_v16f16:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmul.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmul.f16 q0, q0, q1
; CHECK-FP-NEXT: vrev32.16 q1, q0 ; CHECK-FP-NEXT: vrev32.16 q1, q0
; CHECK-FP-NEXT: vmul.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmul.f16 q0, q0, q1
; CHECK-FP-NEXT: vmul.f16 s4, s2, s3 ; CHECK-FP-NEXT: vmul.f16 s2, s2, s3
; CHECK-FP-NEXT: vmul.f16 s0, s0, s1 ; CHECK-FP-NEXT: vmul.f16 s0, s0, s1
; CHECK-FP-NEXT: vmul.f16 s0, s0, s4 ; CHECK-FP-NEXT: vmul.f16 s0, s0, s2
; CHECK-FP-NEXT: vmul.f16 s0, s8, s0 ; CHECK-FP-NEXT: vmul.f16 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmul_v16f16: ; CHECK-NOFP-LABEL: fmul_v16f16:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s12, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s12, s0
; CHECK-NOFP-NEXT: vmovx.f16 s10, s4
; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmul.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vmul.f16 s10, s12, s10
; CHECK-NOFP-NEXT: vmul.f16 s12, s0, s4 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s10
; CHECK-NOFP-NEXT: vmul.f16 s10, s12, s10 ; CHECK-NOFP-NEXT: vmul.f16 s4, s1, s5
; CHECK-NOFP-NEXT: vmul.f16 s12, s1, s5 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmul.f16 s10, s10, s12 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s5
; CHECK-NOFP-NEXT: vmovx.f16 s12, s5 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s1
; CHECK-NOFP-NEXT: vmovx.f16 s14, s1 ; CHECK-NOFP-NEXT: vmul.f16 s4, s10, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s7 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmul.f16 s12, s14, s12 ; CHECK-NOFP-NEXT: vmul.f16 s4, s2, s6
; CHECK-NOFP-NEXT: vmovx.f16 s14, s2
; CHECK-NOFP-NEXT: vmul.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmul.f16 s12, s2, s6
; CHECK-NOFP-NEXT: vmul.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmovx.f16 s12, s6
; CHECK-NOFP-NEXT: vmul.f16 s12, s14, s12
; CHECK-NOFP-NEXT: vmovx.f16 s0, s3
; CHECK-NOFP-NEXT: vmul.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmul.f16 s12, s3, s7
; CHECK-NOFP-NEXT: vmul.f16 s10, s10, s12
; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4 ; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s4
; CHECK-NOFP-NEXT: vmul.f16 s0, s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s4, s6
; CHECK-NOFP-NEXT: vmovx.f16 s2, s2
; CHECK-NOFP-NEXT: vmul.f16 s2, s2, s4
; CHECK-NOFP-NEXT: vmovx.f16 s4, s3
; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmul.f16 s2, s3, s7
; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmovx.f16 s2, s7
; CHECK-NOFP-NEXT: vmul.f16 s2, s4, s2
; CHECK-NOFP-NEXT: vmul.f16 s0, s0, s2
; CHECK-NOFP-NEXT: vmul.f16 s0, s8, s0 ; CHECK-NOFP-NEXT: vmul.f16 s0, s8, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call fast half @llvm.vector.reduce.fmul.f16.v16f16(half %y, <16 x half> %x) %z = call fast half @llvm.vector.reduce.fmul.f16.v16f16(half %y, <16 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc double @fmul_v1f64(<1 x double> %x, double %y) { define arm_aapcs_vfpcc double @fmul_v1f64(<1 x double> %x, double %y) {
Show All 15 Lines
entry: entry:
%z = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double %y, <2 x double> %x) %z = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double %y, <2 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc double @fmul_v4f64(<4 x double> %x, double %y) { define arm_aapcs_vfpcc double @fmul_v4f64(<4 x double> %x, double %y) {
; CHECK-LABEL: fmul_v4f64: ; CHECK-LABEL: fmul_v4f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f64 d5, d1, d3 ; CHECK-NEXT: vmul.f64 d1, d1, d3
; CHECK-NEXT: vmul.f64 d0, d0, d2 ; CHECK-NEXT: vmul.f64 d0, d0, d2
; CHECK-NEXT: vmul.f64 d0, d0, d5 ; CHECK-NEXT: vmul.f64 d0, d0, d1
; CHECK-NEXT: vmul.f64 d0, d4, d0 ; CHECK-NEXT: vmul.f64 d0, d4, d0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call fast double @llvm.vector.reduce.fmul.f64.v4f64(double %y, <4 x double> %x) %z = call fast double @llvm.vector.reduce.fmul.f64.v4f64(double %y, <4 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc float @fmul_v2f32_nofast(<2 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmul_v2f32_nofast(<2 x float> %x, float %y) {
; CHECK-LABEL: fmul_v2f32_nofast: ; CHECK-LABEL: fmul_v2f32_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f32 s4, s4, s0 ; CHECK-NEXT: vmul.f32 s0, s4, s0
; CHECK-NEXT: vmul.f32 s0, s4, s1 ; CHECK-NEXT: vmul.f32 s0, s0, s1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmul.f32.v2f32(float %y, <2 x float> %x) %z = call float @llvm.vector.reduce.fmul.f32.v2f32(float %y, <2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmul_v4f32_nofast(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmul_v4f32_nofast(<4 x float> %x, float %y) {
; CHECK-LABEL: fmul_v4f32_nofast: ; CHECK-LABEL: fmul_v4f32_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f32 s4, s4, s0 ; CHECK-NEXT: vmul.f32 s0, s4, s0
; CHECK-NEXT: vmul.f32 s4, s4, s1 ; CHECK-NEXT: vmul.f32 s0, s0, s1
; CHECK-NEXT: vmul.f32 s4, s4, s2 ; CHECK-NEXT: vmul.f32 s0, s0, s2
; CHECK-NEXT: vmul.f32 s0, s4, s3 ; CHECK-NEXT: vmul.f32 s0, s0, s3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmul.f32.v4f32(float %y, <4 x float> %x) %z = call float @llvm.vector.reduce.fmul.f32.v4f32(float %y, <4 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmul_v8f32_nofast(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmul_v8f32_nofast(<8 x float> %x, float %y) {
; CHECK-LABEL: fmul_v8f32_nofast: ; CHECK-LABEL: fmul_v8f32_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f32 s8, s8, s0 ; CHECK-NEXT: vmul.f32 s0, s8, s0
; CHECK-NEXT: vmul.f32 s8, s8, s1 ; CHECK-NEXT: vmul.f32 s0, s0, s1
; CHECK-NEXT: vmul.f32 s8, s8, s2 ; CHECK-NEXT: vmul.f32 s0, s0, s2
; CHECK-NEXT: vmul.f32 s0, s8, s3 ; CHECK-NEXT: vmul.f32 s0, s0, s3
; CHECK-NEXT: vmul.f32 s0, s0, s4 ; CHECK-NEXT: vmul.f32 s0, s0, s4
; CHECK-NEXT: vmul.f32 s0, s0, s5 ; CHECK-NEXT: vmul.f32 s0, s0, s5
; CHECK-NEXT: vmul.f32 s0, s0, s6 ; CHECK-NEXT: vmul.f32 s0, s0, s6
; CHECK-NEXT: vmul.f32 s0, s0, s7 ; CHECK-NEXT: vmul.f32 s0, s0, s7
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call float @llvm.vector.reduce.fmul.f32.v8f32(float %y, <8 x float> %x) %z = call float @llvm.vector.reduce.fmul.f32.v8f32(float %y, <8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fmul_v2f16_nofast(<2 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmul_v2f16_nofast(<2 x half> %x, half %y) {
; CHECK-LABEL: fmul_v2f16_nofast: ; CHECK-LABEL: fmul_v2f16_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f16 s4, s4, s0 ; CHECK-NEXT: vmul.f16 s2, s4, s0
; CHECK-NEXT: vmovx.f16 s0, s0 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmul.f16 s0, s4, s0 ; CHECK-NEXT: vmul.f16 s0, s2, s0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmul.f16.v2f16(half %y, <2 x half> %x) %z = call half @llvm.vector.reduce.fmul.f16.v2f16(half %y, <2 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmul_v4f16_nofast(<4 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmul_v4f16_nofast(<4 x half> %x, half %y) {
; CHECK-LABEL: fmul_v4f16_nofast: ; CHECK-LABEL: fmul_v4f16_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f16 s4, s4, s0 ; CHECK-NEXT: vmul.f16 s2, s4, s0
; CHECK-NEXT: vmovx.f16 s6, s0 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmul.f16 s4, s4, s6 ; CHECK-NEXT: vmul.f16 s0, s2, s0
; CHECK-NEXT: vmovx.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s2, s1
; CHECK-NEXT: vmul.f16 s4, s4, s1 ; CHECK-NEXT: vmul.f16 s0, s0, s1
; CHECK-NEXT: vmul.f16 s0, s4, s0 ; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmul.f16.v4f16(half %y, <4 x half> %x) %z = call half @llvm.vector.reduce.fmul.f16.v4f16(half %y, <4 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmul_v8f16_nofast(<8 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmul_v8f16_nofast(<8 x half> %x, half %y) {
; CHECK-LABEL: fmul_v8f16_nofast: ; CHECK-LABEL: fmul_v8f16_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f16 s4, s4, s0 ; CHECK-NEXT: vmul.f16 s4, s4, s0
; CHECK-NEXT: vmovx.f16 s6, s0 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmul.f16 s4, s4, s6
; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vmul.f16 s4, s4, s1
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vmul.f16 s4, s4, s6
; CHECK-NEXT: vmovx.f16 s6, s2
; CHECK-NEXT: vmul.f16 s4, s4, s2
; CHECK-NEXT: vmul.f16 s4, s4, s6
; CHECK-NEXT: vmul.f16 s4, s4, s3
; CHECK-NEXT: vmul.f16 s0, s4, s0 ; CHECK-NEXT: vmul.f16 s0, s4, s0
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vmul.f16 s0, s0, s1
; CHECK-NEXT: vmul.f16 s0, s0, s4
; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s2
; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s3
; CHECK-NEXT: vmul.f16 s0, s0, s3
; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call half @llvm.vector.reduce.fmul.f16.v8f16(half %y, <8 x half> %x) %z = call half @llvm.vector.reduce.fmul.f16.v8f16(half %y, <8 x half> %x)
ret half %z ret half %z
} }
define arm_aapcs_vfpcc half @fmul_v16f16_nofast(<16 x half> %x, half %y) { define arm_aapcs_vfpcc half @fmul_v16f16_nofast(<16 x half> %x, half %y) {
; CHECK-LABEL: fmul_v16f16_nofast: ; CHECK-LABEL: fmul_v16f16_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f16 s8, s8, s0 ; CHECK-NEXT: vmul.f16 s8, s8, s0
; CHECK-NEXT: vmovx.f16 s10, s0 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmul.f16 s8, s8, s10
; CHECK-NEXT: vmovx.f16 s10, s1
; CHECK-NEXT: vmul.f16 s8, s8, s1
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vmul.f16 s8, s8, s10
; CHECK-NEXT: vmovx.f16 s10, s2
; CHECK-NEXT: vmul.f16 s8, s8, s2
; CHECK-NEXT: vmovx.f16 s2, s4
; CHECK-NEXT: vmul.f16 s8, s8, s10
; CHECK-NEXT: vmul.f16 s8, s8, s3
; CHECK-NEXT: vmul.f16 s0, s8, s0 ; CHECK-NEXT: vmul.f16 s0, s8, s0
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmul.f16 s0, s0, s1
; CHECK-NEXT: vmul.f16 s0, s0, s8
; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s2
; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s3
; CHECK-NEXT: vmul.f16 s0, s0, s3
; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s4
; CHECK-NEXT: vmul.f16 s0, s0, s4 ; CHECK-NEXT: vmul.f16 s0, s0, s4
; CHECK-NEXT: vmul.f16 s0, s0, s2 ; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vmul.f16 s0, s0, s5 ; CHECK-NEXT: vmul.f16 s0, s0, s5
; CHECK-NEXT: vmul.f16 s0, s0, s2 ; CHECK-NEXT: vmul.f16 s0, s0, s2
; CHECK-NEXT: vmovx.f16 s2, s6 ; CHECK-NEXT: vmovx.f16 s2, s6
; CHECK-NEXT: vmul.f16 s0, s0, s6 ; CHECK-NEXT: vmul.f16 s0, s0, s6
; CHECK-NEXT: vmul.f16 s0, s0, s2 ; CHECK-NEXT: vmul.f16 s0, s0, s2
Show All 14 Lines
entry: entry:
%z = call double @llvm.vector.reduce.fmul.f64.v1f64(double %y, <1 x double> %x) %z = call double @llvm.vector.reduce.fmul.f64.v1f64(double %y, <1 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc double @fmul_v2f64_nofast(<2 x double> %x, double %y) { define arm_aapcs_vfpcc double @fmul_v2f64_nofast(<2 x double> %x, double %y) {
; CHECK-LABEL: fmul_v2f64_nofast: ; CHECK-LABEL: fmul_v2f64_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f64 d2, d2, d0 ; CHECK-NEXT: vmul.f64 d0, d2, d0
; CHECK-NEXT: vmul.f64 d0, d2, d1 ; CHECK-NEXT: vmul.f64 d0, d0, d1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call double @llvm.vector.reduce.fmul.f64.v2f64(double %y, <2 x double> %x) %z = call double @llvm.vector.reduce.fmul.f64.v2f64(double %y, <2 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc double @fmul_v4f64_nofast(<4 x double> %x, double %y) { define arm_aapcs_vfpcc double @fmul_v4f64_nofast(<4 x double> %x, double %y) {
; CHECK-LABEL: fmul_v4f64_nofast: ; CHECK-LABEL: fmul_v4f64_nofast:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f64 d4, d4, d0 ; CHECK-NEXT: vmul.f64 d0, d4, d0
; CHECK-NEXT: vmul.f64 d0, d4, d1 ; CHECK-NEXT: vmul.f64 d0, d0, d1
; CHECK-NEXT: vmul.f64 d0, d0, d2 ; CHECK-NEXT: vmul.f64 d0, d0, d2
; CHECK-NEXT: vmul.f64 d0, d0, d3 ; CHECK-NEXT: vmul.f64 d0, d0, d3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%z = call double @llvm.vector.reduce.fmul.f64.v4f64(double %y, <4 x double> %x) %z = call double @llvm.vector.reduce.fmul.f64.v4f64(double %y, <4 x double> %x)
ret double %z ret double %z
} }
Show All 10 Lines

llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll

Show First 20 Lines • Show All 497 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2
; CHECK-NEXT: mov r3, r0 ; CHECK-NEXT: mov r3, r0
; CHECK-NEXT: .LBB5_5: @ %vector.body ; CHECK-NEXT: .LBB5_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r3], #16 ; CHECK-NEXT: vldrw.u32 q1, [r3], #16
; CHECK-NEXT: vadd.f32 q0, q1, q0 ; CHECK-NEXT: vadd.f32 q0, q1, q0
; CHECK-NEXT: le lr, .LBB5_5 ; CHECK-NEXT: le lr, .LBB5_5
; CHECK-NEXT: @ %bb.6: @ %middle.block ; CHECK-NEXT: @ %bb.6: @ %middle.block
; CHECK-NEXT: vadd.f32 s4, s2, s3 ; CHECK-NEXT: vadd.f32 s2, s2, s3
; CHECK-NEXT: cmp r2, r1 ; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: vadd.f32 s0, s0, s1 ; CHECK-NEXT: vadd.f32 s0, s0, s1
; CHECK-NEXT: vadd.f32 s0, s0, s4 ; CHECK-NEXT: vadd.f32 s0, s0, s2
; CHECK-NEXT: beq .LBB5_9 ; CHECK-NEXT: beq .LBB5_9
; CHECK-NEXT: .LBB5_7: @ %for.body.preheader1 ; CHECK-NEXT: .LBB5_7: @ %for.body.preheader1
; CHECK-NEXT: sub.w lr, r1, r2 ; CHECK-NEXT: sub.w lr, r1, r2
; CHECK-NEXT: add.w r0, r0, r2, lsl #2 ; CHECK-NEXT: add.w r0, r0, r2, lsl #2
; CHECK-NEXT: .LBB5_8: @ %for.body ; CHECK-NEXT: .LBB5_8: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldmia r0!, {s2} ; CHECK-NEXT: vldmia r0!, {s2}
; CHECK-NEXT: vadd.f32 s0, s2, s0 ; CHECK-NEXT: vadd.f32 s0, s2, s0
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add.w lr, r3, r12, lsr #2 ; CHECK-NEXT: add.w lr, r3, r12, lsr #2
; CHECK-NEXT: mov r3, r0 ; CHECK-NEXT: mov r3, r0
; CHECK-NEXT: .LBB6_5: @ %vector.body ; CHECK-NEXT: .LBB6_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r3], #16 ; CHECK-NEXT: vldrw.u32 q1, [r3], #16
; CHECK-NEXT: vmul.f32 q0, q1, q0 ; CHECK-NEXT: vmul.f32 q0, q1, q0
; CHECK-NEXT: le lr, .LBB6_5 ; CHECK-NEXT: le lr, .LBB6_5
; CHECK-NEXT: @ %bb.6: @ %middle.block ; CHECK-NEXT: @ %bb.6: @ %middle.block
; CHECK-NEXT: vmul.f32 s4, s2, s3 ; CHECK-NEXT: vmul.f32 s2, s2, s3
; CHECK-NEXT: cmp r2, r1 ; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: vmul.f32 s0, s0, s1 ; CHECK-NEXT: vmul.f32 s0, s0, s1
; CHECK-NEXT: vmul.f32 s0, s0, s4 ; CHECK-NEXT: vmul.f32 s0, s0, s2
; CHECK-NEXT: beq .LBB6_9 ; CHECK-NEXT: beq .LBB6_9
; CHECK-NEXT: .LBB6_7: @ %for.body.preheader1 ; CHECK-NEXT: .LBB6_7: @ %for.body.preheader1
; CHECK-NEXT: sub.w lr, r1, r2 ; CHECK-NEXT: sub.w lr, r1, r2
; CHECK-NEXT: add.w r0, r0, r2, lsl #2 ; CHECK-NEXT: add.w r0, r0, r2, lsl #2
; CHECK-NEXT: .LBB6_8: @ %for.body ; CHECK-NEXT: .LBB6_8: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldmia r0!, {s2} ; CHECK-NEXT: vldmia r0!, {s2}
; CHECK-NEXT: vmul.f32 s0, s2, s0 ; CHECK-NEXT: vmul.f32 s0, s2, s0
▲ Show 20 Lines • Show All 843 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mov r3, r0 ; CHECK-NEXT: mov r3, r0
; CHECK-NEXT: .LBB15_5: @ %vector.body ; CHECK-NEXT: .LBB15_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r3], #16 ; CHECK-NEXT: vldrw.u32 q1, [r3], #16
; CHECK-NEXT: vcmp.f32 lt, q0, q1 ; CHECK-NEXT: vcmp.f32 lt, q0, q1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: le lr, .LBB15_5 ; CHECK-NEXT: le lr, .LBB15_5
; CHECK-NEXT: @ %bb.6: @ %middle.block ; CHECK-NEXT: @ %bb.6: @ %middle.block
; CHECK-NEXT: vminnm.f32 s4, s2, s3 ; CHECK-NEXT: vminnm.f32 s2, s2, s3
; CHECK-NEXT: vminnm.f32 s0, s0, s1 ; CHECK-NEXT: vminnm.f32 s0, s0, s1
; CHECK-NEXT: vminnm.f32 s0, s0, s4 ; CHECK-NEXT: vminnm.f32 s0, s0, s2
; CHECK-NEXT: cmp r2, r1 ; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: beq .LBB15_9 ; CHECK-NEXT: beq .LBB15_9
; CHECK-NEXT: .LBB15_7: @ %for.body.preheader1 ; CHECK-NEXT: .LBB15_7: @ %for.body.preheader1
; CHECK-NEXT: sub.w lr, r1, r2 ; CHECK-NEXT: sub.w lr, r1, r2
; CHECK-NEXT: add.w r0, r0, r2, lsl #2 ; CHECK-NEXT: add.w r0, r0, r2, lsl #2
; CHECK-NEXT: .LBB15_8: @ %for.body ; CHECK-NEXT: .LBB15_8: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldmia r0!, {s2} ; CHECK-NEXT: vldmia r0!, {s2}
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mov r3, r0 ; CHECK-NEXT: mov r3, r0
; CHECK-NEXT: .LBB16_5: @ %vector.body ; CHECK-NEXT: .LBB16_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r3], #16 ; CHECK-NEXT: vldrw.u32 q1, [r3], #16
; CHECK-NEXT: vcmp.f32 lt, q1, q0 ; CHECK-NEXT: vcmp.f32 lt, q1, q0
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: le lr, .LBB16_5 ; CHECK-NEXT: le lr, .LBB16_5
; CHECK-NEXT: @ %bb.6: @ %middle.block ; CHECK-NEXT: @ %bb.6: @ %middle.block
; CHECK-NEXT: vmaxnm.f32 s4, s2, s3 ; CHECK-NEXT: vmaxnm.f32 s2, s2, s3
; CHECK-NEXT: vmaxnm.f32 s0, s0, s1 ; CHECK-NEXT: vmaxnm.f32 s0, s0, s1
; CHECK-NEXT: vmaxnm.f32 s0, s0, s4 ; CHECK-NEXT: vmaxnm.f32 s0, s0, s2
; CHECK-NEXT: cmp r2, r1 ; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: beq .LBB16_9 ; CHECK-NEXT: beq .LBB16_9
; CHECK-NEXT: .LBB16_7: @ %for.body.preheader1 ; CHECK-NEXT: .LBB16_7: @ %for.body.preheader1
; CHECK-NEXT: sub.w lr, r1, r2 ; CHECK-NEXT: sub.w lr, r1, r2
; CHECK-NEXT: add.w r0, r0, r2, lsl #2 ; CHECK-NEXT: add.w r0, r0, r2, lsl #2
; CHECK-NEXT: .LBB16_8: @ %for.body ; CHECK-NEXT: .LBB16_8: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldmia r0!, {s2} ; CHECK-NEXT: vldmia r0!, {s2}
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llvm/test/CodeGen/Thumb2/mve-vhadd.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines; CHECK-NEXT: bx lr
%resulti16 = lshr <8 x i32> %add2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %resulti16 = lshr <8 x i32> %add2, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%result = trunc <8 x i32> %resulti16 to <8 x i16> %result = trunc <8 x i32> %resulti16 to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
} }
define arm_aapcs_vfpcc <4 x i32> @vrhadd_s32(<4 x i32> %src1, <4 x i32> %src2) { define arm_aapcs_vfpcc <4 x i32> @vrhadd_s32(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: vrhadd_s32: ; CHECK-LABEL: vrhadd_s32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d9}
; CHECK-NEXT: vmov.f32 s12, s2 ; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s16, s6
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.f32 s10, s3
; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov.f32 s18, s5
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: asrs r1, r0, #31 ; CHECK-NEXT: asrs r1, r0, #31
; CHECK-NEXT: adds r0, r0, r2 ; CHECK-NEXT: adds r0, r0, r2
; CHECK-NEXT: adc.w r1, r1, r2, asr #31 ; CHECK-NEXT: adc.w r1, r1, r2, asr #31
; CHECK-NEXT: adds r0, #1 ; CHECK-NEXT: adds r0, #1
; CHECK-NEXT: adc r1, r1, #0 ; CHECK-NEXT: adc r1, r1, #0
; CHECK-NEXT: lsrl r0, r1, #1 ; CHECK-NEXT: lsrl r0, r1, #1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: asrs r2, r1, #31 ; CHECK-NEXT: asrs r2, r1, #31
; CHECK-NEXT: adds r1, r1, r3 ; CHECK-NEXT: adds r1, r1, r3
; CHECK-NEXT: adc.w r3, r2, r3, asr #31 ; CHECK-NEXT: adc.w r3, r2, r3, asr #31
; CHECK-NEXT: adds r2, r1, #1 ; CHECK-NEXT: adds r2, r1, #1
; CHECK-NEXT: adc r1, r3, #0 ; CHECK-NEXT: adc r1, r3, #0
; CHECK-NEXT: vmov r3, s6 ; CHECK-NEXT: vmov r3, s18
; CHECK-NEXT: lsrl r2, r1, #1 ; CHECK-NEXT: lsrl r2, r1, #1
; CHECK-NEXT: vmov q2[2], q2[0], r2, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: vmov r0, s14 ; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: vmov r2, s18 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: asrs r1, r0, #31 ; CHECK-NEXT: asrs r1, r0, #31
; CHECK-NEXT: adds r0, r0, r2 ; CHECK-NEXT: adds r0, r0, r2
; CHECK-NEXT: adc.w r1, r1, r2, asr #31 ; CHECK-NEXT: adc.w r1, r1, r2, asr #31
; CHECK-NEXT: adds r0, #1 ; CHECK-NEXT: adds r0, #1
; CHECK-NEXT: adc r1, r1, #0 ; CHECK-NEXT: adc r1, r1, #0
; CHECK-NEXT: lsrl r0, r1, #1 ; CHECK-NEXT: lsrl r0, r1, #1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s14
; CHECK-NEXT: asrs r2, r1, #31 ; CHECK-NEXT: asrs r2, r1, #31
; CHECK-NEXT: adds r1, r1, r3 ; CHECK-NEXT: adds r1, r1, r3
; CHECK-NEXT: adc.w r3, r2, r3, asr #31 ; CHECK-NEXT: adc.w r3, r2, r3, asr #31
; CHECK-NEXT: adds r2, r1, #1 ; CHECK-NEXT: adds r2, r1, #1
; CHECK-NEXT: adc r1, r3, #0 ; CHECK-NEXT: adc r1, r3, #0
; CHECK-NEXT: lsrl r2, r1, #1 ; CHECK-NEXT: lsrl r2, r1, #1
; CHECK-NEXT: vmov q2[3], q2[1], r2, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r2, r0
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vpop {d9}
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%sextsrc1 = sext <4 x i32> %src1 to <4 x i64> %sextsrc1 = sext <4 x i32> %src1 to <4 x i64>
%sextsrc2 = sext <4 x i32> %src2 to <4 x i64> %sextsrc2 = sext <4 x i32> %src2 to <4 x i64>
%add1 = add <4 x i64> %sextsrc1, %sextsrc2 %add1 = add <4 x i64> %sextsrc1, %sextsrc2
%add2 = add <4 x i64> %add1, <i64 1, i64 1, i64 1, i64 1> %add2 = add <4 x i64> %add1, <i64 1, i64 1, i64 1, i64 1>
%resulti16 = lshr <4 x i64> %add2, <i64 1, i64 1, i64 1, i64 1> %resulti16 = lshr <4 x i64> %add2, <i64 1, i64 1, i64 1, i64 1>
%result = trunc <4 x i64> %resulti16 to <4 x i32> %result = trunc <4 x i64> %resulti16 to <4 x i32>
ret <4 x i32> %result ret <4 x i32> %result
Show All 39 Lines; CHECK-NEXT: bx lr
%resulti16 = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %resulti16 = lshr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%result = trunc <8 x i32> %resulti16 to <8 x i16> %result = trunc <8 x i32> %resulti16 to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
} }
define arm_aapcs_vfpcc <4 x i32> @vhadd_s32(<4 x i32> %src1, <4 x i32> %src2) { define arm_aapcs_vfpcc <4 x i32> @vhadd_s32(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: vhadd_s32: ; CHECK-LABEL: vhadd_s32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d9}
; CHECK-NEXT: vmov.f32 s12, s2 ; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s16, s6
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.f32 s10, s3
; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov.f32 s18, s5
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: asrs r1, r0, #31 ; CHECK-NEXT: asrs r1, r0, #31
; CHECK-NEXT: adds r0, r0, r2 ; CHECK-NEXT: adds r0, r0, r2
; CHECK-NEXT: adc.w r1, r1, r2, asr #31 ; CHECK-NEXT: adc.w r1, r1, r2, asr #31
; CHECK-NEXT: lsrl r0, r1, #1 ; CHECK-NEXT: lsrl r0, r1, #1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: adds r2, r1, r3 ; CHECK-NEXT: adds r2, r1, r3
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: asr.w r12, r1, #31
; CHECK-NEXT: adc.w r1, r12, r3, asr #31 ; CHECK-NEXT: adc.w r1, r12, r3, asr #31
; CHECK-NEXT: lsrl r2, r1, #1 ; CHECK-NEXT: lsrl r2, r1, #1
; CHECK-NEXT: vmov r3, s6 ; CHECK-NEXT: vmov r3, s18
; CHECK-NEXT: vmov q2[2], q2[0], r2, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: vmov r0, s14 ; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: vmov r2, s18 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: asrs r1, r0, #31 ; CHECK-NEXT: asrs r1, r0, #31
; CHECK-NEXT: adds r0, r0, r2 ; CHECK-NEXT: adds r0, r0, r2
; CHECK-NEXT: adc.w r1, r1, r2, asr #31 ; CHECK-NEXT: adc.w r1, r1, r2, asr #31
; CHECK-NEXT: lsrl r0, r1, #1 ; CHECK-NEXT: lsrl r0, r1, #1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s14
; CHECK-NEXT: adds r2, r1, r3 ; CHECK-NEXT: adds r2, r1, r3
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: asr.w r12, r1, #31
; CHECK-NEXT: adc.w r1, r12, r3, asr #31 ; CHECK-NEXT: adc.w r1, r12, r3, asr #31
; CHECK-NEXT: lsrl r2, r1, #1 ; CHECK-NEXT: lsrl r2, r1, #1
; CHECK-NEXT: vmov q2[3], q2[1], r2, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r2, r0
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vpop {d9}
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%sextsrc1 = sext <4 x i32> %src1 to <4 x i64> %sextsrc1 = sext <4 x i32> %src1 to <4 x i64>
%sextsrc2 = sext <4 x i32> %src2 to <4 x i64> %sextsrc2 = sext <4 x i32> %src2 to <4 x i64>
%add = add <4 x i64> %sextsrc1, %sextsrc2 %add = add <4 x i64> %sextsrc1, %sextsrc2
%resulti16 = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1> %resulti16 = lshr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
%result = trunc <4 x i64> %resulti16 to <4 x i32> %result = trunc <4 x i64> %resulti16 to <4 x i32>
ret <4 x i32> %result ret <4 x i32> %result
} }
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <4 x i32> @vrhadd_u32(<4 x i32> %src1, <4 x i32> %src2) { define arm_aapcs_vfpcc <4 x i32> @vrhadd_u32(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: vrhadd_u32: ; CHECK-LABEL: vrhadd_u32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s8, s6 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.i64 q4, #0xffffffff ; CHECK-NEXT: vmov.i64 q4, #0xffffffff
; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vand q2, q2, q4 ; CHECK-NEXT: vand q2, q2, q4
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vand q3, q3, q4 ; CHECK-NEXT: vand q3, q3, q4
; CHECK-NEXT: vmov r0, r1, d4 ; CHECK-NEXT: vmov r0, r1, d4
; CHECK-NEXT: vmov r2, r3, d6 ; CHECK-NEXT: vmov r2, r3, d6
; CHECK-NEXT: vmov.f32 s6, s5 ; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov.f32 s2, s1 ; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vand q1, q1, q4 ; CHECK-NEXT: vand q1, q1, q4
; CHECK-NEXT: vand q4, q0, q4 ; CHECK-NEXT: vand q4, q0, q4
; CHECK-NEXT: adds r0, r0, r2 ; CHECK-NEXT: adds r0, r0, r2
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; CHECK-LABEL: vhadd_u32: ; CHECK-LABEL: vhadd_u32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s8, s6 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.i64 q4, #0xffffffff ; CHECK-NEXT: vmov.i64 q4, #0xffffffff
; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vand q2, q2, q4 ; CHECK-NEXT: vand q2, q2, q4
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vand q3, q3, q4 ; CHECK-NEXT: vand q3, q3, q4
; CHECK-NEXT: vmov r0, r1, d4 ; CHECK-NEXT: vmov r0, r1, d4
; CHECK-NEXT: vmov r2, r3, d6 ; CHECK-NEXT: vmov r2, r3, d6
; CHECK-NEXT: vmov.f32 s6, s5 ; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov.f32 s2, s1 ; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vand q1, q1, q4 ; CHECK-NEXT: vand q1, q1, q4
; CHECK-NEXT: vand q4, q0, q4 ; CHECK-NEXT: vand q4, q0, q4
; CHECK-NEXT: adds r0, r0, r2 ; CHECK-NEXT: adds r0, r0, r2
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Linesfor.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @vhadd_loop_s32(i32* nocapture readonly %x, i32* nocapture readonly %y, i32* noalias nocapture %z, i32 %n) { define void @vhadd_loop_s32(i32* nocapture readonly %x, i32* nocapture readonly %y, i32* noalias nocapture %z, i32 %n) {
; CHECK-LABEL: vhadd_loop_s32: ; CHECK-LABEL: vhadd_loop_s32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d9}
; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: mov.w lr, #256
; CHECK-NEXT: .LBB14_1: @ %vector.body ; CHECK-NEXT: .LBB14_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r1], #16 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16
; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov.f32 s10, s1
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vldrw.u32 q1, [r0], #16 ; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: vmov.f32 s8, s2 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s12, s6 ; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov.f32 s10, s3 ; CHECK-NEXT: vmov.f32 s18, s5
; CHECK-NEXT: vmov.f32 s14, s7 ; CHECK-NEXT: vmov r5, s8
; CHECK-NEXT: vmov r3, s8 ; CHECK-NEXT: asrs r4, r3, #31
; CHECK-NEXT: vmov r5, s12
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: adds.w r12, r3, r5 ; CHECK-NEXT: adds.w r12, r3, r5
; CHECK-NEXT: asr.w r4, r3, #31
; CHECK-NEXT: adc.w r3, r4, r5, asr #31 ; CHECK-NEXT: adc.w r3, r4, r5, asr #31
; CHECK-NEXT: vmov r5, s4 ; CHECK-NEXT: vmov r5, s4
; CHECK-NEXT: lsrl r12, r3, #1 ; CHECK-NEXT: lsrl r12, r3, #1
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: adds r6, r3, r5 ; CHECK-NEXT: adds r6, r3, r5
; CHECK-NEXT: asr.w r4, r3, #31 ; CHECK-NEXT: asr.w r4, r3, #31
; CHECK-NEXT: adc.w r3, r4, r5, asr #31 ; CHECK-NEXT: adc.w r3, r4, r5, asr #31
; CHECK-NEXT: lsrl r6, r3, #1 ; CHECK-NEXT: lsrl r6, r3, #1
; CHECK-NEXT: vmov r5, s14 ; CHECK-NEXT: vmov r5, s6
; CHECK-NEXT: vmov r3, s10 ; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov q4[2], q4[0], r6, r12 ; CHECK-NEXT: vmov q3[2], q3[0], r6, r12
; CHECK-NEXT: adds r4, r3, r5 ; CHECK-NEXT: adds r4, r3, r5
; CHECK-NEXT: asr.w r6, r3, #31 ; CHECK-NEXT: asr.w r6, r3, #31
; CHECK-NEXT: adc.w r3, r6, r5, asr #31 ; CHECK-NEXT: adc.w r3, r6, r5, asr #31
; CHECK-NEXT: lsrl r4, r3, #1 ; CHECK-NEXT: lsrl r4, r3, #1
; CHECK-NEXT: vmov r5, s6 ; CHECK-NEXT: vmov r5, s18
; CHECK-NEXT: vmov r3, s2 ; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: adds r6, r3, r5 ; CHECK-NEXT: adds r6, r3, r5
; CHECK-NEXT: asr.w r12, r3, #31 ; CHECK-NEXT: asr.w r12, r3, #31
; CHECK-NEXT: adc.w r3, r12, r5, asr #31 ; CHECK-NEXT: adc.w r3, r12, r5, asr #31
; CHECK-NEXT: lsrl r6, r3, #1 ; CHECK-NEXT: lsrl r6, r3, #1
; CHECK-NEXT: vmov q4[3], q4[1], r6, r4 ; CHECK-NEXT: vmov q3[3], q3[1], r6, r4
; CHECK-NEXT: vstrb.8 q4, [r2], #16 ; CHECK-NEXT: vstrb.8 q3, [r2], #16
; CHECK-NEXT: le lr, .LBB14_1 ; CHECK-NEXT: le lr, .LBB14_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d9}
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
br label %vector.body br label %vector.body
vector.body: ; preds = %vector.body, %entry vector.body: ; preds = %vector.body, %entry
%index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds i32, i32* %x, i32 %index %0 = getelementptr inbounds i32, i32* %x, i32 %index
%1 = bitcast i32* %0 to <4 x i32>* %1 = bitcast i32* %0 to <4 x i32>*
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; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: mov.w lr, #256
; CHECK-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: .LBB17_1: @ %vector.body ; CHECK-NEXT: .LBB17_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q3, [r0], #16 ; CHECK-NEXT: vldrw.u32 q3, [r0], #16
; CHECK-NEXT: vldrw.u32 q4, [r1], #16 ; CHECK-NEXT: vldrw.u32 q4, [r1], #16
; CHECK-NEXT: vmov.f32 s4, s14 ; CHECK-NEXT: vmov.f32 s4, s14
; CHECK-NEXT: vmov.f32 s8, s18
; CHECK-NEXT: vmov.f32 s6, s15 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vmov.f32 s10, s19 ; CHECK-NEXT: vmov.f32 s8, s18
; CHECK-NEXT: vand q1, q1, q0 ; CHECK-NEXT: vand q1, q1, q0
; CHECK-NEXT: vmov.f32 s10, s19
; CHECK-NEXT: vand q2, q2, q0 ; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vmov r3, r5, d2 ; CHECK-NEXT: vmov r3, r5, d2
; CHECK-NEXT: vmov r4, r6, d4 ; CHECK-NEXT: vmov r4, r6, d4
; CHECK-NEXT: vmov.f32 s14, s13 ; CHECK-NEXT: vmov.f32 s14, s13
; CHECK-NEXT: vmov.f32 s18, s17 ; CHECK-NEXT: vmov.f32 s18, s17
; CHECK-NEXT: vand q3, q3, q0 ; CHECK-NEXT: vand q3, q3, q0
; CHECK-NEXT: vand q5, q4, q0 ; CHECK-NEXT: vand q5, q4, q0
; CHECK-NEXT: adds.w r12, r4, r3 ; CHECK-NEXT: adds.w r12, r4, r3
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; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: mov.w lr, #256
; CHECK-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: .LBB20_1: @ %vector.body ; CHECK-NEXT: .LBB20_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q3, [r1], #16 ; CHECK-NEXT: vldrw.u32 q3, [r1], #16
; CHECK-NEXT: vldrw.u32 q4, [r0], #16 ; CHECK-NEXT: vldrw.u32 q4, [r0], #16
; CHECK-NEXT: vmov.f32 s4, s14 ; CHECK-NEXT: vmov.f32 s4, s14
; CHECK-NEXT: vmov.f32 s8, s18
; CHECK-NEXT: vmov.f32 s6, s15 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vmov.f32 s10, s19 ; CHECK-NEXT: vmov.f32 s8, s18
; CHECK-NEXT: vand q1, q1, q0 ; CHECK-NEXT: vand q1, q1, q0
; CHECK-NEXT: vmov.f32 s10, s19
; CHECK-NEXT: vand q2, q2, q0 ; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vmov r3, r12, d2 ; CHECK-NEXT: vmov r3, r12, d2
; CHECK-NEXT: vmov r4, r5, d4 ; CHECK-NEXT: vmov r4, r5, d4
; CHECK-NEXT: vmov.f32 s14, s13 ; CHECK-NEXT: vmov.f32 s14, s13
; CHECK-NEXT: vmov.f32 s18, s17 ; CHECK-NEXT: vmov.f32 s18, s17
; CHECK-NEXT: vand q3, q3, q0 ; CHECK-NEXT: vand q3, q3, q0
; CHECK-NEXT: vand q5, q4, q0 ; CHECK-NEXT: vand q5, q4, q0
; CHECK-NEXT: adds r3, r3, r4 ; CHECK-NEXT: adds r3, r3, r4
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; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: mov.w lr, #256 ; CHECK-NEXT: mov.w lr, #256
; CHECK-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: .LBB23_1: @ %vector.body ; CHECK-NEXT: .LBB23_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q3, [r1], #16 ; CHECK-NEXT: vldrw.u32 q3, [r1], #16
; CHECK-NEXT: vldrw.u32 q4, [r0], #16 ; CHECK-NEXT: vldrw.u32 q4, [r0], #16
; CHECK-NEXT: vmov.f32 s4, s14 ; CHECK-NEXT: vmov.f32 s4, s14
; CHECK-NEXT: vmov.f32 s8, s18
; CHECK-NEXT: vmov.f32 s6, s15 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vmov.f32 s10, s19 ; CHECK-NEXT: vmov.f32 s8, s18
; CHECK-NEXT: vand q1, q1, q0 ; CHECK-NEXT: vand q1, q1, q0
; CHECK-NEXT: vmov.f32 s10, s19
; CHECK-NEXT: vand q2, q2, q0 ; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vmov r3, r12, d2 ; CHECK-NEXT: vmov r3, r12, d2
; CHECK-NEXT: vmov r4, r5, d4 ; CHECK-NEXT: vmov r4, r5, d4
; CHECK-NEXT: vmov.f32 s14, s13 ; CHECK-NEXT: vmov.f32 s14, s13
; CHECK-NEXT: vmov.f32 s18, s17 ; CHECK-NEXT: vmov.f32 s18, s17
; CHECK-NEXT: vand q3, q3, q0 ; CHECK-NEXT: vand q3, q3, q0
; CHECK-NEXT: vand q5, q4, q0 ; CHECK-NEXT: vand q5, q4, q0
; CHECK-NEXT: adds r3, r3, r4 ; CHECK-NEXT: adds r3, r3, r4
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llvm/test/CodeGen/Thumb2/mve-vld2-post.ll

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define <4 x i64> *@vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) { define <4 x i64> *@vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) {
; CHECK-LABEL: vld2_v2i64: ; CHECK-LABEL: vld2_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, r7, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0], #32 ; CHECK-NEXT: vldrw.u32 q0, [r0], #32
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s9, s3 ; CHECK-NEXT: vmov.f32 s9, s3
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov r4, r7, d4 ; CHECK-NEXT: vmov lr, r12, d3
; CHECK-NEXT: vmov r2, r5, d0 ; CHECK-NEXT: vmov r2, r5, d0
; CHECK-NEXT: vmov lr, r12, d5 ; CHECK-NEXT: vmov r4, r7, d4
; CHECK-NEXT: vmov r3, r6, d1 ; CHECK-NEXT: vmov r3, r6, d1
; CHECK-NEXT: adds.w r3, r3, lr ; CHECK-NEXT: adds.w r3, r3, lr
; CHECK-NEXT: adc.w r6, r6, r12 ; CHECK-NEXT: adc.w r6, r6, r12
; CHECK-NEXT: adds r2, r2, r4 ; CHECK-NEXT: adds r2, r2, r4
; CHECK-NEXT: adcs r7, r5 ; CHECK-NEXT: adcs r7, r5
; CHECK-NEXT: vmov q0[2], q0[0], r2, r3 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r3
; CHECK-NEXT: vmov q0[3], q0[1], r7, r6 ; CHECK-NEXT: vmov q0[3], q0[1], r7, r6
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
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llvm/test/CodeGen/Thumb2/mve-vld2.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add.w r2, r0, #96 ; CHECK-NEXT: add.w r2, r0, #96
; CHECK-NEXT: add.w r3, r0, #64 ; CHECK-NEXT: add.w r3, r0, #64
; CHECK-NEXT: vld20.32 {q3, q4}, [r2] ; CHECK-NEXT: vld20.32 {q3, q4}, [r2]
; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! ; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!
; CHECK-NEXT: vld21.32 {q3, q4}, [r2] ; CHECK-NEXT: vld21.32 {q3, q4}, [r2]
; CHECK-NEXT: vld20.32 {q5, q6}, [r0] ; CHECK-NEXT: vld20.32 {q5, q6}, [r0]
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vld20.32 {q1, q2}, [r3] ; CHECK-NEXT: vld20.32 {q1, q2}, [r3]
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q3_q4
; CHECK-NEXT: vld21.32 {q5, q6}, [r0]
; CHECK-NEXT: vadd.i32 q3, q3, q4 ; CHECK-NEXT: vadd.i32 q3, q3, q4
; CHECK-NEXT: vld21.32 {q5, q6}, [r0]
; CHECK-NEXT: vld21.32 {q1, q2}, [r3] ; CHECK-NEXT: vld21.32 {q1, q2}, [r3]
; CHECK-NEXT: vstrw.32 q3, [r1, #48] ; CHECK-NEXT: vstrw.32 q3, [r1, #48]
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q1_q2
; CHECK-NEXT: vadd.i32 q5, q5, q6 ; CHECK-NEXT: vadd.i32 q5, q5, q6
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vadd.i32 q1, q1, q2 ; CHECK-NEXT: vadd.i32 q1, q1, q2
; CHECK-NEXT: vstrw.32 q5, [r1, #16] ; CHECK-NEXT: vstrw.32 q5, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x i32>, <32 x i32>* %src, align 4 %l1 = load <32 x i32>, <32 x i32>* %src, align 4
%s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%a = add <16 x i32> %s1, %s2 %a = add <16 x i32> %s1, %s2
store <16 x i32> %a, <16 x i32> *%dst store <16 x i32> %a, <16 x i32> *%dst
ret void ret void
} }
define void @vld2_v4i32_align1(<8 x i32> *%src, <4 x i32> *%dst) { define void @vld2_v4i32_align1(<8 x i32> *%src, <4 x i32> *%dst) {
; CHECK-LABEL: vld2_v4i32_align1: ; CHECK-LABEL: vld2_v4i32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q1, [r0]
; CHECK-NEXT: vldrb.u8 q0, [r0, #16] ; CHECK-NEXT: vldrb.u8 q0, [r0, #16]
; CHECK-NEXT: vldrb.u8 q1, [r0]
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s8, s5
; CHECK-NEXT: vmov.f32 s9, s7 ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s5, s6 ; CHECK-NEXT: vmov.f32 s5, s6
; CHECK-NEXT: vmov.f32 s10, s1 ; CHECK-NEXT: vmov.f32 s10, s1
; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s11, s3 ; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s7, s2 ; CHECK-NEXT: vmov.f32 s7, s2
; CHECK-NEXT: vadd.i32 q0, q1, q2 ; CHECK-NEXT: vadd.i32 q0, q1, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <8 x i32>, <8 x i32>* %src, align 1 %l1 = load <8 x i32>, <8 x i32>* %src, align 1
%s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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store <16 x i16> %a, <16 x i16> *%dst store <16 x i16> %a, <16 x i16> *%dst
ret void ret void
} }
define void @vld2_v8i16_align1(<16 x i16> *%src, <8 x i16> *%dst) { define void @vld2_v8i16_align1(<16 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld2_v8i16_align1: ; CHECK-LABEL: vld2_v8i16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0] ; CHECK-NEXT: vldrb.u8 q0, [r0]
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vldrb.u8 q2, [r0, #16]
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vmovx.f16 s8, s3 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s5, s2 ; CHECK-NEXT: vmovx.f16 s5, s2
; CHECK-NEXT: vins.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s6, s3
; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vldrb.u8 q2, [r0, #16]
; CHECK-NEXT: vins.f16 s2, s3
; CHECK-NEXT: vmovx.f16 s12, s9 ; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vmovx.f16 s6, s8 ; CHECK-NEXT: vmovx.f16 s6, s8
; CHECK-NEXT: vins.f16 s6, s12 ; CHECK-NEXT: vins.f16 s6, s12
; CHECK-NEXT: vmovx.f16 s12, s11
; CHECK-NEXT: vmovx.f16 s7, s10 ; CHECK-NEXT: vmovx.f16 s7, s10
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmovx.f16 s12, s11
; CHECK-NEXT: vins.f16 s2, s3
; CHECK-NEXT: vins.f16 s10, s11
; CHECK-NEXT: vins.f16 s8, s9 ; CHECK-NEXT: vins.f16 s8, s9
; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vins.f16 s7, s12 ; CHECK-NEXT: vins.f16 s7, s12
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vins.f16 s10, s11
; CHECK-NEXT: vmov.f32 s3, s10 ; CHECK-NEXT: vmov.f32 s3, s10
; CHECK-NEXT: vadd.i16 q0, q0, q1 ; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x i16>, <16 x i16>* %src, align 1 %l1 = load <16 x i16>, <16 x i16>* %src, align 1
%s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
define void @vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) { define void @vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) {
; CHECK-LABEL: vld2_v2i64: ; CHECK-LABEL: vld2_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s9, s3 ; CHECK-NEXT: vmov.f32 s9, s3
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov r0, r4, d4 ; CHECK-NEXT: vmov lr, r12, d3
; CHECK-NEXT: vmov r5, r6, d0 ; CHECK-NEXT: vmov r5, r6, d0
; CHECK-NEXT: vmov lr, r12, d5 ; CHECK-NEXT: vmov r0, r4, d4
; CHECK-NEXT: vmov r3, r2, d1 ; CHECK-NEXT: vmov r3, r2, d1
; CHECK-NEXT: adds.w r3, r3, lr ; CHECK-NEXT: adds.w r3, r3, lr
; CHECK-NEXT: adc.w r2, r2, r12 ; CHECK-NEXT: adc.w r2, r2, r12
; CHECK-NEXT: adds r0, r0, r5 ; CHECK-NEXT: adds r0, r0, r5
; CHECK-NEXT: adcs r6, r4 ; CHECK-NEXT: adcs r6, r4
; CHECK-NEXT: vmov q0[2], q0[0], r0, r3 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
; CHECK-NEXT: vmov q0[3], q0[1], r6, r2 ; CHECK-NEXT: vmov q0[3], q0[1], r6, r2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%l1 = load <4 x i64>, <4 x i64>* %src, align 8 %l1 = load <4 x i64>, <4 x i64>* %src, align 8
%s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2> %s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2>
%s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3> %s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3>
%a = add <2 x i64> %s1, %s2 %a = add <2 x i64> %s1, %s2
store <2 x i64> %a, <2 x i64> *%dst store <2 x i64> %a, <2 x i64> *%dst
ret void ret void
} }
define void @vld2_v4i64(<8 x i64> *%src, <4 x i64> *%dst) { define void @vld2_v4i64(<8 x i64> *%src, <4 x i64> *%dst) {
; CHECK-LABEL: vld2_v4i64: ; CHECK-LABEL: vld2_v4i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48] ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vmov.f64 d2, d1 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s6, s10 ; CHECK-NEXT: vmov lr, r12, d5
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vmov.f32 s3, s9 ; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vmov.f64 d8, d5 ; CHECK-NEXT: vmov.f32 s16, s10
; CHECK-NEXT: vmov.f32 s17, s11 ; CHECK-NEXT: vmov.f32 s17, s11
; CHECK-NEXT: vmov.f32 s18, s14 ; CHECK-NEXT: vmov r5, r6, d4
; CHECK-NEXT: vmov.f32 s10, s12
; CHECK-NEXT: vmov lr, r12, d3
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: vmov.f32 s19, s15 ; CHECK-NEXT: vmov.f32 s2, s12
; CHECK-NEXT: vmov.f32 s11, s13 ; CHECK-NEXT: vmov.f32 s3, s13
; CHECK-NEXT: vmov r0, r7, d8 ; CHECK-NEXT: vmov r0, r7, d8
; CHECK-NEXT: vmov r5, r6, d4
; CHECK-NEXT: adds.w lr, lr, r2 ; CHECK-NEXT: adds.w lr, lr, r2
; CHECK-NEXT: adc.w r12, r12, r3 ; CHECK-NEXT: adc.w r12, r12, r3
; CHECK-NEXT: vmov r3, r4, d9 ; CHECK-NEXT: vmov r3, r4, d7
; CHECK-NEXT: adds r0, r0, r5 ; CHECK-NEXT: adds r0, r0, r5
; CHECK-NEXT: adc.w r8, r6, r7 ; CHECK-NEXT: adc.w r8, r6, r7
; CHECK-NEXT: vmov r6, r5, d5 ; CHECK-NEXT: vmov r6, r5, d1
; CHECK-NEXT: vmov r2, r7, d0 ; CHECK-NEXT: vmov r2, r7, d0
; CHECK-NEXT: adds r3, r3, r6 ; CHECK-NEXT: adds r3, r3, r6
; CHECK-NEXT: adc.w r6, r5, r4 ; CHECK-NEXT: adc.w r6, r5, r4
; CHECK-NEXT: vmov r5, r4, d2 ; CHECK-NEXT: vmov r5, r4, d2
; CHECK-NEXT: vmov q1[2], q1[0], r0, r3 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r3
; CHECK-NEXT: vmov q1[3], q1[1], r8, r6 ; CHECK-NEXT: vmov q1[3], q1[1], r8, r6
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: adds r2, r2, r5 ; CHECK-NEXT: adds r2, r2, r5
; CHECK-NEXT: vmov q0[2], q0[0], r2, lr ; CHECK-NEXT: vmov q0[2], q0[0], r2, lr
; CHECK-NEXT: adc.w r0, r7, r4 ; CHECK-NEXT: adc.w r0, r7, r4
; CHECK-NEXT: vmov q0[3], q0[1], r0, r12 ; CHECK-NEXT: vmov q0[3], q0[1], r0, r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
entry: entry:
%l1 = load <8 x i64>, <8 x i64>* %src, align 8 %l1 = load <8 x i64>, <8 x i64>* %src, align 8
%s1 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %s1 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s2 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %s2 = shufflevector <8 x i64> %l1, <8 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%a = add <4 x i64> %s1, %s2 %a = add <4 x i64> %s1, %s2
store <4 x i64> %a, <4 x i64> *%dst store <4 x i64> %a, <4 x i64> *%dst
ret void ret void
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add.w r2, r0, #96 ; CHECK-NEXT: add.w r2, r0, #96
; CHECK-NEXT: add.w r3, r0, #64 ; CHECK-NEXT: add.w r3, r0, #64
; CHECK-NEXT: vld20.32 {q3, q4}, [r2] ; CHECK-NEXT: vld20.32 {q3, q4}, [r2]
; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! ; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!
; CHECK-NEXT: vld21.32 {q3, q4}, [r2] ; CHECK-NEXT: vld21.32 {q3, q4}, [r2]
; CHECK-NEXT: vld20.32 {q5, q6}, [r0] ; CHECK-NEXT: vld20.32 {q5, q6}, [r0]
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vld20.32 {q1, q2}, [r3] ; CHECK-NEXT: vld20.32 {q1, q2}, [r3]
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q3_q4
; CHECK-NEXT: vld21.32 {q5, q6}, [r0]
; CHECK-NEXT: vadd.f32 q3, q3, q4 ; CHECK-NEXT: vadd.f32 q3, q3, q4
; CHECK-NEXT: vld21.32 {q5, q6}, [r0]
; CHECK-NEXT: vld21.32 {q1, q2}, [r3] ; CHECK-NEXT: vld21.32 {q1, q2}, [r3]
; CHECK-NEXT: vstrw.32 q3, [r1, #48] ; CHECK-NEXT: vstrw.32 q3, [r1, #48]
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q1_q2
; CHECK-NEXT: vadd.f32 q5, q5, q6 ; CHECK-NEXT: vadd.f32 q5, q5, q6
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vadd.f32 q1, q1, q2 ; CHECK-NEXT: vadd.f32 q1, q1, q2
; CHECK-NEXT: vstrw.32 q5, [r1, #16] ; CHECK-NEXT: vstrw.32 q5, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x float>, <32 x float>* %src, align 4 %l1 = load <32 x float>, <32 x float>* %src, align 4
%s1 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %s1 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%s2 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %s2 = shufflevector <32 x float> %l1, <32 x float> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%a = fadd <16 x float> %s1, %s2 %a = fadd <16 x float> %s1, %s2
store <16 x float> %a, <16 x float> *%dst store <16 x float> %a, <16 x float> *%dst
ret void ret void
} }
define void @vld2_v4f32_align1(<8 x float> *%src, <4 x float> *%dst) { define void @vld2_v4f32_align1(<8 x float> *%src, <4 x float> *%dst) {
; CHECK-LABEL: vld2_v4f32_align1: ; CHECK-LABEL: vld2_v4f32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q1, [r0]
; CHECK-NEXT: vldrb.u8 q0, [r0, #16] ; CHECK-NEXT: vldrb.u8 q0, [r0, #16]
; CHECK-NEXT: vldrb.u8 q1, [r0]
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s8, s5
; CHECK-NEXT: vmov.f32 s9, s7 ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s5, s6 ; CHECK-NEXT: vmov.f32 s5, s6
; CHECK-NEXT: vmov.f32 s10, s1 ; CHECK-NEXT: vmov.f32 s10, s1
; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s11, s3 ; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s7, s2 ; CHECK-NEXT: vmov.f32 s7, s2
; CHECK-NEXT: vadd.f32 q0, q1, q2 ; CHECK-NEXT: vadd.f32 q0, q1, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <8 x float>, <8 x float>* %src, align 1 %l1 = load <8 x float>, <8 x float>* %src, align 1
%s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%a = fadd <4 x float> %s1, %s2 %a = fadd <4 x float> %s1, %s2
store <4 x float> %a, <4 x float> *%dst store <4 x float> %a, <4 x float> *%dst
ret void ret void
} }
; f16 ; f16
define void @vld2_v2f16(<4 x half> *%src, <2 x half> *%dst) { define void @vld2_v2f16(<4 x half> *%src, <2 x half> *%dst) {
; CHECK-LABEL: vld2_v2f16: ; CHECK-LABEL: vld2_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r2, [r0] ; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: ldr r0, [r0, #4] ; CHECK-NEXT: ldr r0, [r0, #4]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov.32 q0[1], r0 ; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmovx.f16 s4, s1 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s2, s1
; CHECK-NEXT: vins.f16 s8, s4 ; CHECK-NEXT: vins.f16 s4, s2
; CHECK-NEXT: vins.f16 s0, s1 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vadd.f16 q0, q0, q2 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: str r0, [r1] ; CHECK-NEXT: str r0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <4 x half>, <4 x half>* %src, align 2 %l1 = load <4 x half>, <4 x half>* %src, align 2
%s1 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 0, i32 2> %s1 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 0, i32 2>
%s2 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 1, i32 3> %s2 = shufflevector <4 x half> %l1, <4 x half> undef, <2 x i32> <i32 1, i32 3>
%a = fadd <2 x half> %s1, %s2 %a = fadd <2 x half> %s1, %s2
store <2 x half> %a, <2 x half> *%dst store <2 x half> %a, <2 x half> *%dst
ret void ret void
} }
define void @vld2_v4f16(<8 x half> *%src, <4 x half> *%dst) { define void @vld2_v4f16(<8 x half> *%src, <4 x half> *%dst) {
; CHECK-LABEL: vld2_v4f16: ; CHECK-LABEL: vld2_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vmovx.f16 s8, s3 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s5, s2 ; CHECK-NEXT: vmovx.f16 s5, s2
; CHECK-NEXT: vins.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s6, s3
; CHECK-NEXT: vins.f16 s2, s3 ; CHECK-NEXT: vins.f16 s2, s3
; CHECK-NEXT: vins.f16 s5, s8 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vmov r0, r2, d0 ; CHECK-NEXT: vmov r0, r2, d0
; CHECK-NEXT: strd r0, r2, [r1] ; CHECK-NEXT: strd r0, r2, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <8 x half>, <8 x half>* %src, align 2 %l1 = load <8 x half>, <8 x half>* %src, align 2
%s1 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %s1 = shufflevector <8 x half> %l1, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
Show All 40 Linesentry:
store <16 x half> %a, <16 x half> *%dst store <16 x half> %a, <16 x half> *%dst
ret void ret void
} }
define void @vld2_v8f16_align1(<16 x half> *%src, <8 x half> *%dst) { define void @vld2_v8f16_align1(<16 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld2_v8f16_align1: ; CHECK-LABEL: vld2_v8f16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0] ; CHECK-NEXT: vldrb.u8 q0, [r0]
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vldrb.u8 q2, [r0, #16]
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vmovx.f16 s8, s3 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s5, s2 ; CHECK-NEXT: vmovx.f16 s5, s2
; CHECK-NEXT: vins.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s6, s3
; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vldrb.u8 q2, [r0, #16]
; CHECK-NEXT: vins.f16 s2, s3
; CHECK-NEXT: vmovx.f16 s12, s9 ; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vmovx.f16 s6, s8 ; CHECK-NEXT: vmovx.f16 s6, s8
; CHECK-NEXT: vins.f16 s6, s12 ; CHECK-NEXT: vins.f16 s6, s12
; CHECK-NEXT: vmovx.f16 s12, s11
; CHECK-NEXT: vmovx.f16 s7, s10 ; CHECK-NEXT: vmovx.f16 s7, s10
; CHECK-NEXT: vmovx.f16 s12, s11
; CHECK-NEXT: vins.f16 s2, s3
; CHECK-NEXT: vins.f16 s10, s11
; CHECK-NEXT: vins.f16 s8, s9 ; CHECK-NEXT: vins.f16 s8, s9
; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vins.f16 s10, s11
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vins.f16 s7, s12 ; CHECK-NEXT: vins.f16 s7, s12
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s10 ; CHECK-NEXT: vmov.f32 s3, s10
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x half>, <16 x half>* %src, align 1 %l1 = load <16 x half>, <16 x half>* %src, align 1
%s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vld3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s
; i32 ; i32
define void @vld3_v2i32(<6 x i32> *%src, <2 x i32> *%dst) { define void @vld3_v2i32(<6 x i32> *%src, <2 x i32> *%dst) {
; CHECK-LABEL: vld3_v2i32: ; CHECK-LABEL: vld3_v2i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: ldrd r2, r0, [r0, #16] ; CHECK-NEXT: ldrd r2, r0, [r0, #16]
; CHECK-NEXT: vmov.f64 d2, d0
; CHECK-NEXT: vmov.f32 s6, s3 ; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: vmov r12, lr, d0 ; CHECK-NEXT: vmov r12, lr, d0
; CHECK-NEXT: vmov r3, s6 ; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
; CHECK-NEXT: add.w r3, r12, lr ; CHECK-NEXT: add.w r3, r12, lr
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
Show All 10 Linesentry:
ret void ret void
} }
define void @vld3_v4i32(<12 x i32> *%src, <4 x i32> *%dst) { define void @vld3_v4i32(<12 x i32> *%src, <4 x i32> *%dst) {
; CHECK-LABEL: vld3_v4i32: ; CHECK-LABEL: vld3_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f64 d4, d2
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s10, s2 ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vmov.f32 s2, s16 ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s15, s18 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vadd.i32 q2, q2, q3 ; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vmov.f32 s3, s19 ; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vadd.i32 q0, q2, q0 ; CHECK-NEXT: vadd.i32 q0, q2, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <12 x i32>, <12 x i32>* %src, align 4 %l1 = load <12 x i32>, <12 x i32>* %src, align 4
%s1 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x i32> %l1, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = add <4 x i32> %s1, %s2 %a1 = add <4 x i32> %s1, %s2
%a = add <4 x i32> %a1, %s3 %a = add <4 x i32> %a1, %s3
store <4 x i32> %a, <4 x i32> *%dst store <4 x i32> %a, <4 x i32> *%dst
ret void ret void
} }
define void @vld3_v8i32(<24 x i32> *%src, <8 x i32> *%dst) { define void @vld3_v8i32(<24 x i32> *%src, <8 x i32> *%dst) {
; CHECK-LABEL: vld3_v8i32: ; CHECK-LABEL: vld3_v8i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #80] ; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
; CHECK-NEXT: vmov.f64 d4, d2
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s10, s2 ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s2, s16 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s15, s18 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vadd.i32 q2, q2, q3 ; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s3, s19 ; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vadd.i32 q0, q2, q0 ; CHECK-NEXT: vadd.i32 q0, q2, q0
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s21, s11 ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s19, s14 ; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vmov.f32 s20, s8
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s23, s13 ; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vadd.i32 q4, q5, q4 ; CHECK-NEXT: vadd.i32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vadd.i32 q1, q4, q1 ; CHECK-NEXT: vadd.i32 q1, q4, q1
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x i32>, <24 x i32>* %src, align 4 %l1 = load <24 x i32>, <24 x i32>* %src, align 4
%s1 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x i32> %l1, <24 x i32> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = add <8 x i32> %s1, %s2 %a1 = add <8 x i32> %s1, %s2
%a = add <8 x i32> %a1, %s3 %a = add <8 x i32> %a1, %s3
store <8 x i32> %a, <8 x i32> *%dst store <8 x i32> %a, <8 x i32> *%dst
ret void ret void
} }
define void @vld3_v16i32(<48 x i32> *%src, <16 x i32> *%dst) { define void @vld3_v16i32(<48 x i32> *%src, <16 x i32> *%dst) {
; CHECK-LABEL: vld3_v16i32: ; CHECK-LABEL: vld3_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #80] ; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
; CHECK-NEXT: vldrw.u32 q6, [r0, #176] ; CHECK-NEXT: vldrw.u32 q6, [r0, #176]
; CHECK-NEXT: vmov.f64 d4, d2
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s10, s2 ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s2, s16 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s15, s18 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vadd.i32 q2, q2, q3 ; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s3, s19 ; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vadd.i32 q0, q2, q0 ; CHECK-NEXT: vadd.i32 q0, q2, q0
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vmov.f32 s20, s8
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s19, s14 ; CHECK-NEXT: vadd.i32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vldrw.u32 q3, [r0, #144] ; CHECK-NEXT: vldrw.u32 q3, [r0, #144]
; CHECK-NEXT: vadd.i32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vadd.i32 q1, q4, q1 ; CHECK-NEXT: vadd.i32 q1, q4, q1
; CHECK-NEXT: vmov.f64 d8, d6
; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s18, s10 ; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s22, s11 ; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s8, s14 ; CHECK-NEXT: vmov.f32 s16, s12
; CHECK-NEXT: vldrw.u32 q3, [r0, #112] ; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vmov.f32 s10, s24 ; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vmov.f32 s23, s26 ; CHECK-NEXT: vmov.f32 s23, s26
; CHECK-NEXT: vmov.f32 s19, s25 ; CHECK-NEXT: vmov.f32 s19, s25
; CHECK-NEXT: vadd.i32 q4, q4, q5 ; CHECK-NEXT: vadd.i32 q4, q4, q5
; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s10, s24
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vmov.f32 s11, s27 ; CHECK-NEXT: vmov.f32 s11, s27
; CHECK-NEXT: vldrw.u32 q5, [r0, #128]
; CHECK-NEXT: vadd.i32 q2, q4, q2 ; CHECK-NEXT: vadd.i32 q2, q4, q2
; CHECK-NEXT: vldrw.u32 q4, [r0, #96] ; CHECK-NEXT: vldrw.u32 q4, [r0, #96]
; CHECK-NEXT: vldrw.u32 q5, [r0, #128]
; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s24, s17
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f64 d14, d8
; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s25, s12 ; CHECK-NEXT: vmov.f32 s25, s12
; CHECK-NEXT: vmov.f32 s29, s19 ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s26, s15 ; CHECK-NEXT: vmov.f32 s26, s15
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s30, s14 ; CHECK-NEXT: vmov.f32 s30, s14
; CHECK-NEXT: vmov.f32 s12, s18 ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s14, s20 ; CHECK-NEXT: vmov.f32 s24, s17
; CHECK-NEXT: vmov.f32 s27, s22 ; CHECK-NEXT: vmov.f32 s27, s22
; CHECK-NEXT: vmov.f32 s28, s16
; CHECK-NEXT: vmov.f32 s29, s19
; CHECK-NEXT: vmov.f32 s31, s21 ; CHECK-NEXT: vmov.f32 s31, s21
; CHECK-NEXT: vadd.i32 q6, q7, q6 ; CHECK-NEXT: vadd.i32 q6, q7, q6
; CHECK-NEXT: vmov.f32 s12, s18
; CHECK-NEXT: vmov.f32 s14, s20
; CHECK-NEXT: vmov.f32 s15, s23 ; CHECK-NEXT: vmov.f32 s15, s23
; CHECK-NEXT: vadd.i32 q3, q6, q3 ; CHECK-NEXT: vadd.i32 q3, q6, q3
; CHECK-NEXT: vstrw.32 q3, [r1, #32] ; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x i32>, <48 x i32>* %src, align 4 %l1 = load <48 x i32>, <48 x i32>* %src, align 4
%s1 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x i32> %l1, <48 x i32> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
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; CHECK-LABEL: vld3_v2i16: ; CHECK-LABEL: vld3_v2i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #8 ; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, #8 ; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: vldrh.u32 q0, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: ldr r2, [r0, #8] ; CHECK-NEXT: ldr r2, [r0, #8]
; CHECK-NEXT: mov r3, sp ; CHECK-NEXT: mov r3, sp
; CHECK-NEXT: str r2, [sp] ; CHECK-NEXT: str r2, [sp]
; CHECK-NEXT: vmov.f64 d2, d0
; CHECK-NEXT: vmov.f32 s6, s3 ; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f64 d6, d1
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vldrh.u32 q1, [r3] ; CHECK-NEXT: vldrh.u32 q1, [r3]
; CHECK-NEXT: vmov.f32 s10, s4 ; CHECK-NEXT: vmov.f32 s6, s4
; CHECK-NEXT: vmov.f32 s14, s5 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: vmov.f32 s2, s5
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: vmov r2, s14 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: strh r0, [r1, #2] ; CHECK-NEXT: strh r0, [r1, #2]
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: strh r0, [r1] ; CHECK-NEXT: strh r0, [r1]
; CHECK-NEXT: add sp, #8 ; CHECK-NEXT: add sp, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <6 x i16>, <6 x i16>* %src, align 4 %l1 = load <6 x i16>, <6 x i16>* %src, align 4
%s1 = shufflevector <6 x i16> %l1, <6 x i16> undef, <2 x i32> <i32 0, i32 3> %s1 = shufflevector <6 x i16> %l1, <6 x i16> undef, <2 x i32> <i32 0, i32 3>
%s2 = shufflevector <6 x i16> %l1, <6 x i16> undef, <2 x i32> <i32 1, i32 4> %s2 = shufflevector <6 x i16> %l1, <6 x i16> undef, <2 x i32> <i32 1, i32 4>
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
} }
define void @vld3_v8i16(<24 x i16> *%src, <8 x i16> *%dst) { define void @vld3_v8i16(<24 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld3_v8i16: ; CHECK-LABEL: vld3_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vins.f16 s1, s12
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s2, s11 ; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vmov.u16 r0, q2[5] ; CHECK-NEXT: vmovx.f16 s2, s6
; CHECK-NEXT: vmovx.f16 s20, s15 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmovx.f16 s2, s9
; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmovx.f16 s5, s5
; CHECK-NEXT: vins.f16 s1, s2
; CHECK-NEXT: vmov.f32 s19, s14 ; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vins.f16 s19, s20 ; CHECK-NEXT: vmovx.f16 s2, s15
; CHECK-NEXT: vmov.f32 s18, s12 ; CHECK-NEXT: vmov.f32 s18, s12
; CHECK-NEXT: vins.f16 s19, s2
; CHECK-NEXT: vmov.f32 s2, s11
; CHECK-NEXT: vmov q5, q4 ; CHECK-NEXT: vmov q5, q4
; CHECK-NEXT: vmovnb.i32 q5, q0 ; CHECK-NEXT: vmov.f32 s16, s4
; CHECK-NEXT: vmov.f32 s2, s22 ; CHECK-NEXT: vins.f16 s16, s5
; CHECK-NEXT: vmovx.f16 s20, s5 ; CHECK-NEXT: vmovx.f16 s5, s8
; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vins.f16 s16, s20
; CHECK-NEXT: vmovx.f16 s20, s8
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vins.f16 s17, s20 ; CHECK-NEXT: vmovx.f16 s4, s4
; CHECK-NEXT: vmovx.f16 s20, s11 ; CHECK-NEXT: vins.f16 s17, s5
; CHECK-NEXT: vmovx.f16 s5, s11
; CHECK-NEXT: vmov.f32 s18, s10 ; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vins.f16 s18, s20 ; CHECK-NEXT: vmov.u16 r0, q2[5]
; CHECK-NEXT: vmovx.f16 s20, s14 ; CHECK-NEXT: vmovx.f16 s11, s13
; CHECK-NEXT: vins.f16 s18, s5
; CHECK-NEXT: vmovx.f16 s5, s7
; CHECK-NEXT: vmovnb.i32 q5, q0
; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vmovx.f16 s14, s14
; CHECK-NEXT: vmov.f32 s19, s13 ; CHECK-NEXT: vmov.f32 s19, s13
; CHECK-NEXT: vins.f16 s19, s20 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s20, s4 ; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vins.f16 s20, s6 ; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmovx.f16 s21, s7 ; CHECK-NEXT: vins.f16 s11, s15
; CHECK-NEXT: vins.f16 s6, s12 ; CHECK-NEXT: vins.f16 s19, s14
; CHECK-NEXT: vmovx.f16 s7, s13 ; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vins.f16 s21, s9 ; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vins.f16 s7, s15 ; CHECK-NEXT: vmovnb.i32 q3, q1
; CHECK-NEXT: vmov.16 q5[4], r0 ; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vmov q2, q1 ; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vmovnb.i32 q2, q5 ; CHECK-NEXT: vmov.f32 s2, s22
; CHECK-NEXT: vmov.f32 s22, s10 ; CHECK-NEXT: vadd.i16 q1, q4, q1
; CHECK-NEXT: vmov.f32 s23, s7
; CHECK-NEXT: vadd.i16 q1, q4, q5
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: vadd.i16 q0, q1, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x i16>, <24 x i16>* %src, align 4 %l1 = load <24 x i16>, <24 x i16>* %src, align 4
%s1 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x i16> %l1, <24 x i16> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = add <8 x i16> %s1, %s2 %a1 = add <8 x i16> %s1, %s2
%a = add <8 x i16> %a1, %s3 %a = add <8 x i16> %a1, %s3
store <8 x i16> %a, <8 x i16> *%dst store <8 x i16> %a, <8 x i16> *%dst
ret void ret void
} }
define void @vld3_v16i16(<48 x i16> *%src, <16 x i16> *%dst) { define void @vld3_v16i16(<48 x i16> *%src, <16 x i16> *%dst) {
; CHECK-LABEL: vld3_v16i16: ; CHECK-LABEL: vld3_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vmov.f64 d0, d2
; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vldrw.u32 q2, [r0, #64] ; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
; CHECK-NEXT: vmov.f32 s0, s4
; CHECK-NEXT: vmovx.f16 s2, s5
; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmovx.f16 s2, s8
; CHECK-NEXT: vmov.f32 s1, s7 ; CHECK-NEXT: vmov.f32 s1, s7
; CHECK-NEXT: vmovx.f16 s12, s8
; CHECK-NEXT: vmovx.f16 s16, s9
; CHECK-NEXT: vins.f16 s1, s12
; CHECK-NEXT: vmovx.f16 s12, s11 ; CHECK-NEXT: vmovx.f16 s12, s11
; CHECK-NEXT: vins.f16 s1, s2
; CHECK-NEXT: vmov.f32 s2, s10 ; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vmov.u16 r2, q2[5] ; CHECK-NEXT: vmovx.f16 s14, s18
; CHECK-NEXT: vmov.f32 s3, s17
; CHECK-NEXT: vins.f16 s2, s12 ; CHECK-NEXT: vins.f16 s2, s12
; CHECK-NEXT: vmovx.f16 s12, s6 ; CHECK-NEXT: vmovx.f16 s12, s6
; CHECK-NEXT: vins.f16 s3, s14
; CHECK-NEXT: vmovx.f16 s14, s19
; CHECK-NEXT: vins.f16 s18, s14
; CHECK-NEXT: vins.f16 s5, s12 ; CHECK-NEXT: vins.f16 s5, s12
; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vmov.f32 s13, s8 ; CHECK-NEXT: vmov.f32 s13, s8
; CHECK-NEXT: vins.f16 s13, s16 ; CHECK-NEXT: vmovx.f16 s4, s4
; CHECK-NEXT: vldrw.u32 q4, [r0, #80] ; CHECK-NEXT: vins.f16 s13, s12
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmovx.f16 s20, s18 ; CHECK-NEXT: vmovx.f16 s5, s7
; CHECK-NEXT: vmov.f32 s3, s17 ; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vins.f16 s3, s20
; CHECK-NEXT: vmovx.f16 s20, s19
; CHECK-NEXT: vins.f16 s18, s20
; CHECK-NEXT: vmov.f32 s14, s11 ; CHECK-NEXT: vmov.f32 s14, s11
; CHECK-NEXT: vmovx.f16 s11, s17
; CHECK-NEXT: vmov.f32 s23, s18 ; CHECK-NEXT: vmov.f32 s23, s18
; CHECK-NEXT: vmov.f32 s22, s16 ; CHECK-NEXT: vmov.f32 s22, s16
; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vmov q6, q5 ; CHECK-NEXT: vmov q6, q5
; CHECK-NEXT: vins.f16 s10, s16
; CHECK-NEXT: vins.f16 s11, s19
; CHECK-NEXT: vmovnb.i32 q6, q3 ; CHECK-NEXT: vmovnb.i32 q6, q3
; CHECK-NEXT: vmov.f32 s14, s26 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vmov.f32 s15, s23 ; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmovx.f16 s20, s4 ; CHECK-NEXT: vmov q4, q2
; CHECK-NEXT: vins.f16 s20, s6 ; CHECK-NEXT: vmovnb.i32 q4, q1
; CHECK-NEXT: vmovx.f16 s21, s7 ; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vins.f16 s6, s16 ; CHECK-NEXT: vmov.f32 s6, s18
; CHECK-NEXT: vmovx.f16 s7, s17
; CHECK-NEXT: vins.f16 s21, s9
; CHECK-NEXT: vins.f16 s7, s19
; CHECK-NEXT: vmov.16 q5[4], r2
; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmovnb.i32 q2, q5
; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmov.f32 s23, s7 ; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vadd.i16 q0, q0, q5 ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f32 s4, s9 ; CHECK-NEXT: vmov.f32 s14, s26
; CHECK-NEXT: vmovx.f16 s6, s10
; CHECK-NEXT: vadd.i16 q0, q0, q3 ; CHECK-NEXT: vadd.i16 q0, q0, q3
; CHECK-NEXT: vmovx.f16 s12, s10
; CHECK-NEXT: vins.f16 s4, s12
; CHECK-NEXT: vldrw.u32 q3, [r0, #16] ; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s4, s9
; CHECK-NEXT: vmovx.f16 s0, s9 ; CHECK-NEXT: vmovx.f16 s7, s19
; CHECK-NEXT: vmovx.f16 s16, s13
; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vins.f16 s5, s16
; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmovx.f16 s20, s19
; CHECK-NEXT: vmov.f32 s27, s18 ; CHECK-NEXT: vmov.f32 s27, s18
; CHECK-NEXT: vins.f16 s27, s20 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov.f64 d10, d4 ; CHECK-NEXT: vmovx.f16 s6, s13
; CHECK-NEXT: vins.f16 s20, s0 ; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vins.f16 s27, s7
; CHECK-NEXT: vmov.f32 s26, s16 ; CHECK-NEXT: vmov.f32 s26, s16
; CHECK-NEXT: vmovx.f16 s0, s12 ; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vmov.f32 s21, s11 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vins.f16 s21, s0
; CHECK-NEXT: vmov q7, q6 ; CHECK-NEXT: vmov q7, q6
; CHECK-NEXT: vmov.f32 s20, s8
; CHECK-NEXT: vmovnb.i32 q7, q1 ; CHECK-NEXT: vmovnb.i32 q7, q1
; CHECK-NEXT: vmovx.f16 s0, s15 ; CHECK-NEXT: vmovx.f16 s6, s9
; CHECK-NEXT: vins.f16 s20, s6
; CHECK-NEXT: vmovx.f16 s6, s12
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmovx.f16 s8, s8
; CHECK-NEXT: vmovx.f16 s9, s11
; CHECK-NEXT: vins.f16 s21, s6
; CHECK-NEXT: vmovx.f16 s6, s15
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmovx.f16 s15, s17
; CHECK-NEXT: vmov.f32 s22, s14 ; CHECK-NEXT: vmov.f32 s22, s14
; CHECK-NEXT: vins.f16 s22, s0 ; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vins.f16 s9, s13
; CHECK-NEXT: vins.f16 s14, s16
; CHECK-NEXT: vins.f16 s15, s19
; CHECK-NEXT: vins.f16 s22, s6
; CHECK-NEXT: vmovx.f16 s6, s18
; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov q4, q3
; CHECK-NEXT: vins.f16 s23, s6
; CHECK-NEXT: vmovnb.i32 q4, q2
; CHECK-NEXT: vmov.f32 s11, s15
; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s6, s30 ; CHECK-NEXT: vmov.f32 s6, s30
; CHECK-NEXT: vadd.i16 q2, q5, q2
; CHECK-NEXT: vmov.f32 s7, s27 ; CHECK-NEXT: vmov.f32 s7, s27
; CHECK-NEXT: vmovx.f16 s24, s8 ; CHECK-NEXT: vadd.i16 q1, q2, q1
; CHECK-NEXT: vmovx.f16 s0, s18 ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vins.f16 s24, s10
; CHECK-NEXT: vins.f16 s23, s0
; CHECK-NEXT: vins.f16 s2, s16
; CHECK-NEXT: vmovx.f16 s25, s11
; CHECK-NEXT: vmovx.f16 s3, s17
; CHECK-NEXT: vins.f16 s25, s13
; CHECK-NEXT: vins.f16 s3, s19
; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vmovnb.i32 q2, q6
; CHECK-NEXT: vmov.f32 s26, s10
; CHECK-NEXT: vmov.f32 s27, s3
; CHECK-NEXT: vadd.i16 q0, q5, q6
; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x i16>, <48 x i16>* %src, align 4 %l1 = load <48 x i16>, <48 x i16>* %src, align 4
%s1 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x i16> %l1, <48 x i16> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = add <16 x i16> %s1, %s2 %a1 = add <16 x i16> %s1, %s2
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrb.u16 q1, [r0, #16] ; CHECK-NEXT: vldrb.u16 q1, [r0, #16]
; CHECK-NEXT: vmov.u8 r2, q0[1] ; CHECK-NEXT: vmov.u8 r2, q0[1]
; CHECK-NEXT: vmov.u8 r0, q0[0] ; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vmov.16 q2[0], r2
; CHECK-NEXT: vmov.u8 r2, q0[4] ; CHECK-NEXT: vmov.u8 r2, q0[4]
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov.u8 r2, q0[7]
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[3] ; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov.u8 r2, q0[10] ; CHECK-NEXT: vmov.u8 r2, q0[7]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[6] ; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.16 q2[3], r2 ; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vmov.u8 r2, q0[13] ; CHECK-NEXT: vmov.u8 r2, q0[10]
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[9] ; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.16 q2[4], r2 ; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vmov.u8 r2, q0[13]
; CHECK-NEXT: vmov.16 q3[3], r0 ; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12] ; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vins.f16 s10, s4 ; CHECK-NEXT: vmov.16 q2[4], r2
; CHECK-NEXT: vmov.16 q3[4], r0 ; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[15] ; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmovx.f16 s16, s6 ; CHECK-NEXT: vmovx.f16 s16, s6
; CHECK-NEXT: vmov.f32 s18, s5 ; CHECK-NEXT: vmov.f32 s18, s5
; CHECK-NEXT: vmovx.f16 s11, s5 ; CHECK-NEXT: vmovx.f16 s11, s5
; CHECK-NEXT: vmov.16 q3[5], r0 ; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vins.f16 s18, s16 ; CHECK-NEXT: vins.f16 s18, s16
; CHECK-NEXT: vins.f16 s10, s4
; CHECK-NEXT: vins.f16 s11, s7 ; CHECK-NEXT: vins.f16 s11, s7
; CHECK-NEXT: vmov.f32 s15, s18 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vmov.u8 r0, q0[2] ; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vadd.i16 q2, q3, q2 ; CHECK-NEXT: vadd.i16 q2, q3, q2
; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[5] ; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[8] ; CHECK-NEXT: vmov.u8 r0, q0[8]
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.8 q3[9], r2 ; CHECK-NEXT: vmov.8 q3[9], r2
; CHECK-NEXT: vmov.u8 r2, q0[15] ; CHECK-NEXT: vmov.u8 r2, q0[15]
; CHECK-NEXT: vmov.8 q4[13], r0 ; CHECK-NEXT: vmov.8 q4[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[11] ; CHECK-NEXT: vmov.u8 r0, q2[11]
; CHECK-NEXT: vmov.8 q3[10], r2 ; CHECK-NEXT: vmov.8 q3[10], r2
; CHECK-NEXT: vmov.8 q4[14], r0 ; CHECK-NEXT: vmov.8 q4[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[14] ; CHECK-NEXT: vmov.u8 r0, q2[14]
; CHECK-NEXT: vmov.8 q4[15], r0 ; CHECK-NEXT: vmov.8 q4[15], r0
; CHECK-NEXT: vmov.u8 r0, q2[2]
; CHECK-NEXT: vmov q5, q3 ; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vmov.u8 r0, q2[2]
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.8 q5[11], r0 ; CHECK-NEXT: vmov.8 q5[11], r0
; CHECK-NEXT: vmov.u8 r0, q1[0] ; CHECK-NEXT: vmov.u8 r0, q1[0]
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.8 q4[0], r0 ; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[3] ; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.8 q4[1], r0 ; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[6] ; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.8 q4[2], r0 ; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[9] ; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.8 q4[3], r0 ; CHECK-NEXT: vmov.8 q4[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[12] ; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.8 q4[4], r0 ; CHECK-NEXT: vmov.8 q4[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[15] ; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.8 q4[5], r0 ; CHECK-NEXT: vmov.8 q4[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[2] ; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.8 q4[6], r0 ; CHECK-NEXT: vmov.8 q4[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[5] ; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.8 q4[7], r0 ; CHECK-NEXT: vmov.8 q4[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[8] ; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmov.8 q4[8], r0 ; CHECK-NEXT: vmov.8 q4[8], r0
; CHECK-NEXT: vmov.u8 r0, q0[11] ; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.8 q4[9], r0 ; CHECK-NEXT: vmov.8 q4[9], r0
; CHECK-NEXT: vmov.u8 r0, q0[14] ; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.8 q4[10], r0 ; CHECK-NEXT: vmov.8 q4[10], r0
; CHECK-NEXT: vmov.u8 r0, q2[4] ; CHECK-NEXT: vmov.u8 r0, q2[4]
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.8 q5[12], r0 ; CHECK-NEXT: vmov.8 q5[12], r0
; CHECK-NEXT: vmov.u8 r0, q2[7] ; CHECK-NEXT: vmov.u8 r0, q2[7]
; CHECK-NEXT: vmov q6, q4
; CHECK-NEXT: vmov.8 q5[13], r0 ; CHECK-NEXT: vmov.8 q5[13], r0
; CHECK-NEXT: vmov.u8 r0, q2[10] ; CHECK-NEXT: vmov.u8 r0, q2[10]
; CHECK-NEXT: vmov.8 q5[14], r0 ; CHECK-NEXT: vmov.8 q5[14], r0
; CHECK-NEXT: vmov.u8 r0, q2[13] ; CHECK-NEXT: vmov.u8 r0, q2[13]
; CHECK-NEXT: vmov.8 q5[15], r0 ; CHECK-NEXT: vmov.8 q5[15], r0
; CHECK-NEXT: vmov.u8 r0, q2[1] ; CHECK-NEXT: vmov.u8 r0, q2[1]
; CHECK-NEXT: vmov q6, q4
; CHECK-NEXT: vmov.8 q6[11], r0 ; CHECK-NEXT: vmov.8 q6[11], r0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vadd.i8 q3, q4, q3 ; CHECK-NEXT: vadd.i8 q3, q4, q3
; CHECK-NEXT: vmov.8 q4[0], r0 ; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[5] ; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.8 q4[1], r0 ; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[8] ; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.8 q4[2], r0 ; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[11] ; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.8 q4[3], r0 ; CHECK-NEXT: vmov.8 q4[3], r0
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
define void @vld3_v2i64(<6 x i64> *%src, <2 x i64> *%dst) { define void @vld3_v2i64(<6 x i64> *%src, <2 x i64> *%dst) {
; CHECK-LABEL: vld3_v2i64: ; CHECK-LABEL: vld3_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.f64 d6, d1 ; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov.f32 s13, s3 ; CHECK-NEXT: vmov.f32 s13, s3
; CHECK-NEXT: vmov.f32 s14, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s2, s10 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov r0, r3, d5
; CHECK-NEXT: vmov.f32 s15, s5 ; CHECK-NEXT: vmov r2, r4, d3
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov r5, r8, d6
; CHECK-NEXT: vmov r6, r7, d0 ; CHECK-NEXT: vmov r6, r7, d0
; CHECK-NEXT: vmov r0, r3, d1 ; CHECK-NEXT: vmov r5, r8, d6
; CHECK-NEXT: vmov lr, r12, d7 ; CHECK-NEXT: vmov lr, r12, d1
; CHECK-NEXT: vmov r2, r4, d5
; CHECK-NEXT: adds.w r0, r0, lr ; CHECK-NEXT: adds.w r0, r0, lr
; CHECK-NEXT: adc.w r3, r3, r12 ; CHECK-NEXT: adc.w r3, r3, r12
; CHECK-NEXT: adds r0, r0, r2 ; CHECK-NEXT: adds r0, r0, r2
; CHECK-NEXT: adc.w r2, r3, r4 ; CHECK-NEXT: adc.w r2, r3, r4
; CHECK-NEXT: vmov r3, r4, d4 ; CHECK-NEXT: vmov r3, r4, d4
; CHECK-NEXT: adds r6, r6, r5 ; CHECK-NEXT: adds r6, r6, r5
; CHECK-NEXT: adc.w r7, r7, r8 ; CHECK-NEXT: adc.w r7, r7, r8
; CHECK-NEXT: adds r3, r3, r6 ; CHECK-NEXT: adds r3, r3, r6
Show All 13 Linesentry:
ret void ret void
} }
define void @vld3_v4i64(<12 x i64> *%src, <4 x i64> *%dst) { define void @vld3_v4i64(<12 x i64> *%src, <4 x i64> *%dst) {
; CHECK-LABEL: vld3_v4i64: ; CHECK-LABEL: vld3_v4i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q6, [r0, #80] ; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vmov.f64 d2, d1 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vldrw.u32 q4, [r0, #64] ; CHECK-NEXT: vldrw.u32 q4, [r0, #64]
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s2, s12
; CHECK-NEXT: vmov.f32 s2, s10 ; CHECK-NEXT: vmov.f32 s3, s13
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov r5, r4, d5
; CHECK-NEXT: vmov.f32 s10, s14 ; CHECK-NEXT: vmov r3, r8, d7
; CHECK-NEXT: vmov.f32 s7, s13 ; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
; CHECK-NEXT: vmov.f32 s11, s15 ; CHECK-NEXT: vmov.f32 s24, s22
; CHECK-NEXT: vldrw.u32 q3, [r0, #48] ; CHECK-NEXT: vmov.f32 s25, s23
; CHECK-NEXT: vmov.f64 d10, d7 ; CHECK-NEXT: vmov lr, r12, d1
; CHECK-NEXT: vmov lr, r12, d3 ; CHECK-NEXT: vmov.f32 s2, s12
; CHECK-NEXT: vmov r5, r4, d1 ; CHECK-NEXT: vmov.f32 s3, s13
; CHECK-NEXT: vmov r3, r8, d5 ; CHECK-NEXT: vmov r6, r7, d12
; CHECK-NEXT: vmov.f32 s21, s15
; CHECK-NEXT: vmov.f32 s22, s24
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.f32 s23, s25
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vmov r6, r7, d10
; CHECK-NEXT: vmov.f32 s19, s27
; CHECK-NEXT: adds.w r0, r5, lr ; CHECK-NEXT: adds.w r0, r5, lr
; CHECK-NEXT: adc.w r5, r4, r12 ; CHECK-NEXT: adc.w r5, r4, r12
; CHECK-NEXT: adds.w lr, r0, r3 ; CHECK-NEXT: adds.w lr, r0, r3
; CHECK-NEXT: vmov r4, r2, d6 ; CHECK-NEXT: vmov r4, r2, d10
; CHECK-NEXT: adc.w r12, r5, r8 ; CHECK-NEXT: adc.w r12, r5, r8
; CHECK-NEXT: vmov r5, r0, d8 ; CHECK-NEXT: vmov r5, r0, d8
; CHECK-NEXT: adds r6, r6, r4 ; CHECK-NEXT: adds r6, r6, r4
; CHECK-NEXT: adcs r2, r7 ; CHECK-NEXT: adcs r2, r7
; CHECK-NEXT: adds r6, r6, r5 ; CHECK-NEXT: adds r6, r6, r5
; CHECK-NEXT: adc.w r8, r2, r0 ; CHECK-NEXT: adc.w r8, r2, r0
; CHECK-NEXT: vmov r7, r4, d11 ; CHECK-NEXT: vmov r7, r4, d1
; CHECK-NEXT: vmov r2, r5, d7 ; CHECK-NEXT: vmov r2, r5, d9
; CHECK-NEXT: vmov r3, r0, d0 ; CHECK-NEXT: vmov r3, r0, d0
; CHECK-NEXT: adds r2, r2, r7 ; CHECK-NEXT: adds r2, r2, r7
; CHECK-NEXT: adc.w r7, r5, r4 ; CHECK-NEXT: adc.w r7, r5, r4
; CHECK-NEXT: vmov r5, r4, d9 ; CHECK-NEXT: vmov r5, r4, d7
; CHECK-NEXT: adds r2, r2, r5 ; CHECK-NEXT: adds r2, r2, r5
; CHECK-NEXT: adcs r7, r4 ; CHECK-NEXT: adcs r7, r4
; CHECK-NEXT: vmov r5, r4, d2 ; CHECK-NEXT: vmov r5, r4, d2
; CHECK-NEXT: vmov q1[2], q1[0], r6, r2 ; CHECK-NEXT: vmov q1[2], q1[0], r6, r2
; CHECK-NEXT: vmov q1[3], q1[1], r8, r7 ; CHECK-NEXT: vmov q1[3], q1[1], r8, r7
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: adds r3, r3, r5 ; CHECK-NEXT: adds r3, r3, r5
; CHECK-NEXT: adcs r0, r4 ; CHECK-NEXT: adcs r0, r4
; CHECK-NEXT: vmov r4, r5, d4 ; CHECK-NEXT: vmov r4, r5, d4
; CHECK-NEXT: adds r3, r3, r4 ; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: vmov q0[2], q0[0], r3, lr ; CHECK-NEXT: vmov q0[2], q0[0], r3, lr
; CHECK-NEXT: adcs r0, r5 ; CHECK-NEXT: adcs r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r0, r12 ; CHECK-NEXT: vmov q0[3], q0[1], r0, r12
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
entry: entry:
%l1 = load <12 x i64>, <12 x i64>* %src, align 4 %l1 = load <12 x i64>, <12 x i64>* %src, align 4
%s1 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x i64> %l1, <12 x i64> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = add <4 x i64> %s1, %s2 %a1 = add <4 x i64> %s1, %s2
%a = add <4 x i64> %a1, %s3 %a = add <4 x i64> %a1, %s3
store <4 x i64> %a, <4 x i64> *%dst store <4 x i64> %a, <4 x i64> *%dst
ret void ret void
} }
; f32 ; f32
define void @vld3_v2f32(<6 x float> *%src, <2 x float> *%dst) { define void @vld3_v2f32(<6 x float> *%src, <2 x float> *%dst) {
; CHECK-LABEL: vld3_v2f32: ; CHECK-LABEL: vld3_v2f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldr s1, [r0, #16] ; CHECK-NEXT: vldr s1, [r0, #16]
; CHECK-NEXT: vldr s5, [r0, #20] ; CHECK-NEXT: vldr s5, [r0, #20]
; CHECK-NEXT: vmov.f64 d6, d4 ; CHECK-NEXT: vmov.f32 s12, s8
; CHECK-NEXT: vmov.f32 s13, s11 ; CHECK-NEXT: vmov.f32 s13, s11
; CHECK-NEXT: vmov.f32 s0, s9 ; CHECK-NEXT: vmov.f32 s0, s9
; CHECK-NEXT: vadd.f32 q0, q3, q0 ; CHECK-NEXT: vadd.f32 q0, q3, q0
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vstmia r1, {s0, s1} ; CHECK-NEXT: vstmia r1, {s0, s1}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <6 x float>, <6 x float>* %src, align 4 %l1 = load <6 x float>, <6 x float>* %src, align 4
%s1 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 0, i32 3> %s1 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 0, i32 3>
%s2 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 1, i32 4> %s2 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 1, i32 4>
%s3 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 2, i32 5> %s3 = shufflevector <6 x float> %l1, <6 x float> undef, <2 x i32> <i32 2, i32 5>
%a1 = fadd <2 x float> %s1, %s2 %a1 = fadd <2 x float> %s1, %s2
%a = fadd <2 x float> %a1, %s3 %a = fadd <2 x float> %a1, %s3
store <2 x float> %a, <2 x float> *%dst store <2 x float> %a, <2 x float> *%dst
ret void ret void
} }
define void @vld3_v4f32(<12 x float> *%src, <4 x float> *%dst) { define void @vld3_v4f32(<12 x float> *%src, <4 x float> *%dst) {
; CHECK-LABEL: vld3_v4f32: ; CHECK-LABEL: vld3_v4f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f64 d4, d2
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s10, s2 ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vmov.f32 s2, s16 ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s15, s18 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vadd.f32 q2, q2, q3 ; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vmov.f32 s3, s19 ; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vadd.f32 q0, q2, q0 ; CHECK-NEXT: vadd.f32 q0, q2, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <12 x float>, <12 x float>* %src, align 4 %l1 = load <12 x float>, <12 x float>* %src, align 4
%s1 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = fadd <4 x float> %s1, %s2 %a1 = fadd <4 x float> %s1, %s2
%a = fadd <4 x float> %a1, %s3 %a = fadd <4 x float> %a1, %s3
store <4 x float> %a, <4 x float> *%dst store <4 x float> %a, <4 x float> *%dst
ret void ret void
} }
define void @vld3_v8f32(<24 x float> *%src, <8 x float> *%dst) { define void @vld3_v8f32(<24 x float> *%src, <8 x float> *%dst) {
; CHECK-LABEL: vld3_v8f32: ; CHECK-LABEL: vld3_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #80] ; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
; CHECK-NEXT: vmov.f64 d4, d2
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s10, s2 ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s2, s16 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s15, s18 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vadd.f32 q2, q2, q3 ; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s3, s19 ; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vadd.f32 q0, q2, q0 ; CHECK-NEXT: vadd.f32 q0, q2, q0
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s21, s11 ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s19, s14 ; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vmov.f32 s20, s8
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s23, s13 ; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vadd.f32 q4, q5, q4 ; CHECK-NEXT: vadd.f32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vadd.f32 q1, q4, q1 ; CHECK-NEXT: vadd.f32 q1, q4, q1
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x float>, <24 x float>* %src, align 4 %l1 = load <24 x float>, <24 x float>* %src, align 4
%s1 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = fadd <8 x float> %s1, %s2 %a1 = fadd <8 x float> %s1, %s2
%a = fadd <8 x float> %a1, %s3 %a = fadd <8 x float> %a1, %s3
store <8 x float> %a, <8 x float> *%dst store <8 x float> %a, <8 x float> *%dst
ret void ret void
} }
define void @vld3_v16f32(<48 x float> *%src, <16 x float> *%dst) { define void @vld3_v16f32(<48 x float> *%src, <16 x float> *%dst) {
; CHECK-LABEL: vld3_v16f32: ; CHECK-LABEL: vld3_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #80] ; CHECK-NEXT: vldrw.u32 q4, [r0, #80]
; CHECK-NEXT: vldrw.u32 q6, [r0, #176] ; CHECK-NEXT: vldrw.u32 q6, [r0, #176]
; CHECK-NEXT: vmov.f64 d4, d2
; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s10, s2 ; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s2, s16 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s15, s18 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vadd.f32 q2, q2, q3 ; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s3, s19 ; CHECK-NEXT: vmov.f32 s3, s19
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vadd.f32 q0, q2, q0 ; CHECK-NEXT: vadd.f32 q0, q2, q0
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vmov.f32 s20, s8
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s19, s14 ; CHECK-NEXT: vadd.f32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vldrw.u32 q3, [r0, #144] ; CHECK-NEXT: vldrw.u32 q3, [r0, #144]
; CHECK-NEXT: vadd.f32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vadd.f32 q1, q4, q1 ; CHECK-NEXT: vadd.f32 q1, q4, q1
; CHECK-NEXT: vmov.f64 d8, d6
; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s18, s10 ; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s22, s11 ; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s8, s14 ; CHECK-NEXT: vmov.f32 s16, s12
; CHECK-NEXT: vldrw.u32 q3, [r0, #112] ; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vmov.f32 s10, s24 ; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vmov.f32 s23, s26 ; CHECK-NEXT: vmov.f32 s23, s26
; CHECK-NEXT: vmov.f32 s19, s25 ; CHECK-NEXT: vmov.f32 s19, s25
; CHECK-NEXT: vadd.f32 q4, q4, q5 ; CHECK-NEXT: vadd.f32 q4, q4, q5
; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s10, s24
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vmov.f32 s11, s27 ; CHECK-NEXT: vmov.f32 s11, s27
; CHECK-NEXT: vldrw.u32 q5, [r0, #128]
; CHECK-NEXT: vadd.f32 q2, q4, q2 ; CHECK-NEXT: vadd.f32 q2, q4, q2
; CHECK-NEXT: vldrw.u32 q4, [r0, #96] ; CHECK-NEXT: vldrw.u32 q4, [r0, #96]
; CHECK-NEXT: vldrw.u32 q5, [r0, #128]
; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s24, s17
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f64 d14, d8
; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s25, s12 ; CHECK-NEXT: vmov.f32 s25, s12
; CHECK-NEXT: vmov.f32 s29, s19 ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s26, s15 ; CHECK-NEXT: vmov.f32 s26, s15
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s30, s14 ; CHECK-NEXT: vmov.f32 s30, s14
; CHECK-NEXT: vmov.f32 s12, s18 ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s14, s20 ; CHECK-NEXT: vmov.f32 s24, s17
; CHECK-NEXT: vmov.f32 s27, s22 ; CHECK-NEXT: vmov.f32 s27, s22
; CHECK-NEXT: vmov.f32 s28, s16
; CHECK-NEXT: vmov.f32 s29, s19
; CHECK-NEXT: vmov.f32 s31, s21 ; CHECK-NEXT: vmov.f32 s31, s21
; CHECK-NEXT: vadd.f32 q6, q7, q6 ; CHECK-NEXT: vadd.f32 q6, q7, q6
; CHECK-NEXT: vmov.f32 s12, s18
; CHECK-NEXT: vmov.f32 s14, s20
; CHECK-NEXT: vmov.f32 s15, s23 ; CHECK-NEXT: vmov.f32 s15, s23
; CHECK-NEXT: vadd.f32 q3, q6, q3 ; CHECK-NEXT: vadd.f32 q3, q6, q3
; CHECK-NEXT: vstrw.32 q3, [r1, #32] ; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x float>, <48 x float>* %src, align 4 %l1 = load <48 x float>, <48 x float>* %src, align 4
%s1 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
Show All 13 Lines
; CHECK-NEXT: ldrd r2, r3, [r0] ; CHECK-NEXT: ldrd r2, r3, [r0]
; CHECK-NEXT: ldr r0, [r0, #8] ; CHECK-NEXT: ldr r0, [r0, #8]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov.32 q0[1], r3 ; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: vmov.32 q0[2], r0 ; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s8, s0
; CHECK-NEXT: vmovx.f16 s4, s2 ; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vins.f16 s8, s2 ; CHECK-NEXT: vins.f16 s8, s2
; CHECK-NEXT: vmovx.f16 s6, s1 ; CHECK-NEXT: vmovx.f16 s2, s1
; CHECK-NEXT: vins.f16 s1, s4 ; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vins.f16 s0, s6 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vadd.f16 q1, q0, q2 ; CHECK-NEXT: vadd.f16 q1, q0, q2
; CHECK-NEXT: vmov.f32 s0, s1 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vadd.f16 q0, q1, q0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: str r0, [r1] ; CHECK-NEXT: str r0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <6 x half>, <6 x half>* %src, align 4 %l1 = load <6 x half>, <6 x half>* %src, align 4
%s1 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 0, i32 3> %s1 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 0, i32 3>
%s2 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 1, i32 4> %s2 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 1, i32 4>
%s3 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 2, i32 5> %s3 = shufflevector <6 x half> %l1, <6 x half> undef, <2 x i32> <i32 2, i32 5>
%a1 = fadd <2 x half> %s1, %s2 %a1 = fadd <2 x half> %s1, %s2
%a = fadd <2 x half> %a1, %s3 %a = fadd <2 x half> %a1, %s3
store <2 x half> %a, <2 x half> *%dst store <2 x half> %a, <2 x half> *%dst
ret void ret void
} }
define void @vld3_v4f16(<12 x half> *%src, <4 x half> *%dst) { define void @vld3_v4f16(<12 x half> *%src, <4 x half> *%dst) {
; CHECK-LABEL: vld3_v4f16: ; CHECK-LABEL: vld3_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: ldrd r2, r3, [r0, #16] ; CHECK-NEXT: ldrd r2, r3, [r0, #16]
; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmovx.f16 s4, s9
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmovx.f16 s8, s8 ; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmovx.f16 s16, s5 ; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: vins.f16 s12, s6
; CHECK-NEXT: vins.f16 s4, s16
; CHECK-NEXT: vmovx.f16 s16, s6
; CHECK-NEXT: vins.f16 s5, s16
; CHECK-NEXT: vmovx.f16 s13, s7 ; CHECK-NEXT: vmovx.f16 s13, s7
; CHECK-NEXT: vins.f16 s7, s8 ; CHECK-NEXT: vmovx.f16 s0, s9
; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vins.f16 s1, s0
; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vmov.f32 s0, s5 ; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vins.f16 s12, s6
; CHECK-NEXT: vins.f16 s13, s9 ; CHECK-NEXT: vins.f16 s13, s9
; CHECK-NEXT: vmov.f32 s5, s7 ; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vadd.f16 q1, q1, q3 ; CHECK-NEXT: vadd.f16 q1, q1, q3
; CHECK-NEXT: vadd.f16 q0, q1, q0 ; CHECK-NEXT: vadd.f16 q0, q1, q0
; CHECK-NEXT: vmov r0, r2, d0 ; CHECK-NEXT: vmov r0, r2, d0
; CHECK-NEXT: strd r0, r2, [r1] ; CHECK-NEXT: strd r0, r2, [r1]
; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <12 x half>, <12 x half>* %src, align 4 %l1 = load <12 x half>, <12 x half>* %src, align 4
%s1 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x half> %l1, <12 x half> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = fadd <4 x half> %s1, %s2 %a1 = fadd <4 x half> %s1, %s2
%a = fadd <4 x half> %a1, %s3 %a = fadd <4 x half> %a1, %s3
store <4 x half> %a, <4 x half> *%dst store <4 x half> %a, <4 x half> *%dst
ret void ret void
} }
define void @vld3_v8f16(<24 x half> *%src, <8 x half> *%dst) { define void @vld3_v8f16(<24 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld3_v8f16: ; CHECK-LABEL: vld3_v8f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10}
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16] ; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmov.f32 s4, s1 ; CHECK-NEXT: vmov.f32 s4, s1
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vmovx.f16 s6, s2
; CHECK-NEXT: vmovx.f16 s8, s17 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov.f32 s5, s16 ; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vmovx.f16 s20, s15 ; CHECK-NEXT: vmovx.f16 s6, s13
; CHECK-NEXT: vins.f16 s5, s8 ; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: vmov.f32 s11, s14 ; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vins.f16 s11, s20 ; CHECK-NEXT: vmovx.f16 s6, s11
; CHECK-NEXT: vmov.f32 s6, s19 ; CHECK-NEXT: vins.f16 s7, s6
; CHECK-NEXT: vmovx.f16 s20, s12 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vmov.f32 s28, s18 ; CHECK-NEXT: vmovx.f16 s16, s8
; CHECK-NEXT: vins.f16 s6, s20 ; CHECK-NEXT: vmovx.f16 s12, s12
; CHECK-NEXT: vmovx.f16 s20, s19 ; CHECK-NEXT: vmovx.f16 s15, s15
; CHECK-NEXT: vins.f16 s28, s20 ; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vmovx.f16 s24, s1 ; CHECK-NEXT: vmovx.f16 s10, s10
; CHECK-NEXT: vmovx.f16 s20, s0 ; CHECK-NEXT: vmovx.f16 s17, s3
; CHECK-NEXT: vins.f16 s0, s24 ; CHECK-NEXT: vmovx.f16 s19, s9
; CHECK-NEXT: vins.f16 s20, s2 ; CHECK-NEXT: vmovx.f16 s18, s14
; CHECK-NEXT: vmovx.f16 s26, s16 ; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vmovx.f16 s21, s3 ; CHECK-NEXT: vmovx.f16 s16, s0
; CHECK-NEXT: vins.f16 s3, s26 ; CHECK-NEXT: vmovx.f16 s1, s1
; CHECK-NEXT: vins.f16 s21, s17 ; CHECK-NEXT: vins.f16 s20, s15
; CHECK-NEXT: vmovx.f16 s30, s14 ; CHECK-NEXT: vins.f16 s3, s12
; CHECK-NEXT: vmovx.f16 s23, s13 ; CHECK-NEXT: vins.f16 s9, s10
; CHECK-NEXT: vmov.f32 s10, s12 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vins.f16 s16, s2
; CHECK-NEXT: vmov.f32 s1, s3 ; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vins.f16 s13, s30 ; CHECK-NEXT: vins.f16 s17, s13
; CHECK-NEXT: vins.f16 s23, s15 ; CHECK-NEXT: vins.f16 s19, s11
; CHECK-NEXT: vmov.f32 s2, s28 ; CHECK-NEXT: vins.f16 s18, s8
; CHECK-NEXT: vmovx.f16 s22, s18 ; CHECK-NEXT: vmov.f32 s2, s20
; CHECK-NEXT: vmov.f32 s3, s13 ; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vins.f16 s22, s12 ; CHECK-NEXT: vadd.f16 q0, q0, q4
; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vadd.f16 q0, q0, q5
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x half>, <24 x half>* %src, align 4 %l1 = load <24 x half>, <24 x half>* %src, align 4
%s1 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x half> %l1, <24 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = fadd <8 x half> %s1, %s2 %a1 = fadd <8 x half> %s1, %s2
%a = fadd <8 x half> %a1, %s3 %a = fadd <8 x half> %a1, %s3
store <8 x half> %a, <8 x half> *%dst store <8 x half> %a, <8 x half> *%dst
ret void ret void
} }
define void @vld3_v16f16(<48 x half> *%src, <16 x half> *%dst) { define void @vld3_v16f16(<48 x half> *%src, <16 x half> *%dst) {
; CHECK-LABEL: vld3_v16f16: ; CHECK-LABEL: vld3_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10}
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q3, [r0, #64] ; CHECK-NEXT: vldrw.u32 q3, [r0, #64]
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vmov.f32 s4, s1 ; CHECK-NEXT: vmov.f32 s4, s1
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vmovx.f16 s6, s2
; CHECK-NEXT: vmovx.f16 s8, s13 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov.f32 s5, s12 ; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vmovx.f16 s24, s1 ; CHECK-NEXT: vmovx.f16 s6, s13
; CHECK-NEXT: vins.f16 s5, s8 ; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vmovx.f16 s6, s11
; CHECK-NEXT: vins.f16 s7, s6
; CHECK-NEXT: vmov.f32 s6, s15 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vmovx.f16 s26, s12 ; CHECK-NEXT: vmovx.f16 s16, s8
; CHECK-NEXT: vmovx.f16 s20, s11 ; CHECK-NEXT: vmovx.f16 s12, s12
; CHECK-NEXT: vmov.f32 s19, s10 ; CHECK-NEXT: vmovx.f16 s15, s15
; CHECK-NEXT: vins.f16 s19, s20 ; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vmovx.f16 s20, s8 ; CHECK-NEXT: vmovx.f16 s10, s10
; CHECK-NEXT: vins.f16 s6, s20 ; CHECK-NEXT: vmovx.f16 s17, s3
; CHECK-NEXT: vmovx.f16 s20, s15 ; CHECK-NEXT: vmovx.f16 s19, s9
; CHECK-NEXT: vmov.f32 s28, s14 ; CHECK-NEXT: vmovx.f16 s18, s14
; CHECK-NEXT: vmovx.f16 s30, s10 ; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vins.f16 s28, s20 ; CHECK-NEXT: vmovx.f16 s16, s0
; CHECK-NEXT: vmovx.f16 s20, s0 ; CHECK-NEXT: vmovx.f16 s1, s1
; CHECK-NEXT: vins.f16 s0, s24 ; CHECK-NEXT: vins.f16 s20, s15
; CHECK-NEXT: vins.f16 s20, s2 ; CHECK-NEXT: vins.f16 s3, s12
; CHECK-NEXT: vmovx.f16 s21, s3 ; CHECK-NEXT: vins.f16 s9, s10
; CHECK-NEXT: vins.f16 s3, s26 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vins.f16 s21, s13 ; CHECK-NEXT: vins.f16 s16, s2
; CHECK-NEXT: vmov.f32 s18, s8 ; CHECK-NEXT: vins.f16 s17, s13
; CHECK-NEXT: vmovx.f16 s23, s9
; CHECK-NEXT: vmov.f32 s1, s3 ; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vins.f16 s9, s30 ; CHECK-NEXT: vins.f16 s19, s11
; CHECK-NEXT: vins.f16 s23, s11 ; CHECK-NEXT: vins.f16 s18, s8
; CHECK-NEXT: vmovx.f16 s22, s14
; CHECK-NEXT: vmov.f32 s2, s28
; CHECK-NEXT: vins.f16 s22, s8
; CHECK-NEXT: vmov.f32 s3, s9 ; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov.f32 s7, s19 ; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vadd.f16 q0, q0, q5 ; CHECK-NEXT: vmov.f32 s2, s20
; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vadd.f16 q0, q0, q4
; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vadd.f16 q1, q0, q1 ; CHECK-NEXT: vadd.f16 q1, q0, q1
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vmov.f32 s4, s1
; CHECK-NEXT: vmovx.f16 s20, s11
; CHECK-NEXT: vins.f16 s4, s16
; CHECK-NEXT: vmovx.f16 s16, s13
; CHECK-NEXT: vmov.f32 s5, s12 ; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vmovx.f16 s24, s1 ; CHECK-NEXT: vmov.f32 s4, s1
; CHECK-NEXT: vins.f16 s5, s16 ; CHECK-NEXT: vmovx.f16 s6, s2
; CHECK-NEXT: vmov.f32 s19, s10 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vins.f16 s19, s20 ; CHECK-NEXT: vmovx.f16 s6, s13
; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: vmovx.f16 s6, s11
; CHECK-NEXT: vmovx.f16 s16, s8
; CHECK-NEXT: vins.f16 s7, s6
; CHECK-NEXT: vmov.f32 s6, s15 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vmovx.f16 s20, s8 ; CHECK-NEXT: vmovx.f16 s15, s15
; CHECK-NEXT: vmov.f32 s28, s14 ; CHECK-NEXT: vmovx.f16 s12, s12
; CHECK-NEXT: vins.f16 s6, s20 ; CHECK-NEXT: vmovx.f16 s10, s10
; CHECK-NEXT: vmovx.f16 s20, s15 ; CHECK-NEXT: vmovx.f16 s17, s3
; CHECK-NEXT: vins.f16 s28, s20 ; CHECK-NEXT: vmovx.f16 s19, s9
; CHECK-NEXT: vmovx.f16 s20, s0 ; CHECK-NEXT: vmovx.f16 s18, s14
; CHECK-NEXT: vins.f16 s0, s24 ; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vins.f16 s20, s2 ; CHECK-NEXT: vmovx.f16 s16, s0
; CHECK-NEXT: vmovx.f16 s21, s3 ; CHECK-NEXT: vmovx.f16 s1, s1
; CHECK-NEXT: vmovx.f16 s26, s12 ; CHECK-NEXT: vins.f16 s20, s15
; CHECK-NEXT: vins.f16 s21, s13 ; CHECK-NEXT: vins.f16 s3, s12
; CHECK-NEXT: vins.f16 s3, s26 ; CHECK-NEXT: vins.f16 s9, s10
; CHECK-NEXT: vmovx.f16 s30, s10 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmovx.f16 s23, s9 ; CHECK-NEXT: vins.f16 s16, s2
; CHECK-NEXT: vmov.f32 s18, s8
; CHECK-NEXT: vins.f16 s9, s30
; CHECK-NEXT: vins.f16 s23, s11
; CHECK-NEXT: vmov.f32 s1, s3 ; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmovx.f16 s22, s14 ; CHECK-NEXT: vins.f16 s17, s13
; CHECK-NEXT: vmov.f32 s2, s28 ; CHECK-NEXT: vins.f16 s19, s11
; CHECK-NEXT: vins.f16 s22, s8 ; CHECK-NEXT: vins.f16 s18, s8
; CHECK-NEXT: vmov.f32 s2, s20
; CHECK-NEXT: vmov.f32 s3, s9 ; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov.f32 s7, s19 ; CHECK-NEXT: vadd.f16 q0, q0, q4
; CHECK-NEXT: vadd.f16 q0, q0, q5
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x half>, <48 x half>* %src, align 4 %l1 = load <48 x half>, <48 x half>* %src, align 4
%s1 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x half> %l1, <48 x half> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = fadd <16 x half> %s1, %s2 %a1 = fadd <16 x half> %s1, %s2
%a = fadd <16 x half> %a1, %s3 %a = fadd <16 x half> %a1, %s3
store <16 x half> %a, <16 x half> *%dst store <16 x half> %a, <16 x half> *%dst
ret void ret void
} }
; f64 ; f64
define void @vld3_v2f64(<6 x double> *%src, <2 x double> *%dst) { define void @vld3_v2f64(<6 x double> *%src, <2 x double> *%dst) {
; CHECK-LABEL: vld3_v2f64: ; CHECK-LABEL: vld3_v2f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.f64 d4, d3, d0 ; CHECK-NEXT: vadd.f64 d0, d3, d0
; CHECK-NEXT: vadd.f64 d5, d6, d7 ; CHECK-NEXT: vadd.f64 d3, d4, d5
; CHECK-NEXT: vadd.f64 d1, d4, d1 ; CHECK-NEXT: vadd.f64 d1, d0, d1
; CHECK-NEXT: vadd.f64 d0, d5, d2 ; CHECK-NEXT: vadd.f64 d0, d3, d2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <6 x double>, <6 x double>* %src, align 4 %l1 = load <6 x double>, <6 x double>* %src, align 4
%s1 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 0, i32 3> %s1 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 0, i32 3>
%s2 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 1, i32 4> %s2 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 1, i32 4>
%s3 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 2, i32 5> %s3 = shufflevector <6 x double> %l1, <6 x double> undef, <2 x i32> <i32 2, i32 5>
%a1 = fadd <2 x double> %s1, %s2 %a1 = fadd <2 x double> %s1, %s2
%a = fadd <2 x double> %a1, %s3 %a = fadd <2 x double> %a1, %s3
store <2 x double> %a, <2 x double> *%dst store <2 x double> %a, <2 x double> *%dst
ret void ret void
} }
define void @vld3_v4f64(<12 x double> *%src, <4 x double> *%dst) { define void @vld3_v4f64(<12 x double> *%src, <4 x double> *%dst) {
; CHECK-LABEL: vld3_v4f64: ; CHECK-LABEL: vld3_v4f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q1, [r0, #80] ; CHECK-NEXT: vldrw.u32 q1, [r0, #80]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vadd.f64 d5, d6, d7 ; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vadd.f64 d1, d1, d2
; CHECK-NEXT: vldrw.u32 q6, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vadd.f64 d4, d1, d2 ; CHECK-NEXT: vadd.f64 d2, d4, d5
; CHECK-NEXT: vadd.f64 d10, d9, d6 ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vadd.f64 d11, d12, d13 ; CHECK-NEXT: vadd.f64 d4, d7, d4
; CHECK-NEXT: vadd.f64 d3, d4, d3 ; CHECK-NEXT: vadd.f64 d7, d8, d9
; CHECK-NEXT: vadd.f64 d2, d5, d0 ; CHECK-NEXT: vadd.f64 d1, d1, d3
; CHECK-NEXT: vadd.f64 d1, d10, d7 ; CHECK-NEXT: vadd.f64 d0, d2, d0
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vadd.f64 d3, d4, d5
; CHECK-NEXT: vadd.f64 d0, d11, d8 ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vadd.f64 d2, d7, d6
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <12 x double>, <12 x double>* %src, align 4 %l1 = load <12 x double>, <12 x double>* %src, align 4
%s1 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x double> %l1, <12 x double> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = fadd <4 x double> %s1, %s2 %a1 = fadd <4 x double> %s1, %s2
%a = fadd <4 x double> %a1, %s3 %a = fadd <4 x double> %a1, %s3
store <4 x double> %a, <4 x double> *%dst store <4 x double> %a, <4 x double> *%dst
ret void ret void
} }

llvm/test/CodeGen/Thumb2/mve-vld4-post.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s
; i32 ; i32
define <16 x i32> *@vld4_v4i32(<16 x i32> *%src, <4 x i32> *%dst) { define <16 x i32> *@vld4_v4i32(<16 x i32> *%src, <4 x i32> *%dst) {
; CHECK-LABEL: vld4_v4i32: ; CHECK-LABEL: vld4_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vadd.i32 q4, q2, q3
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vadd.i32 q0, q0, q4 ; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x i32>, <16 x i32>* %src, align 4 %l1 = load <16 x i32>, <16 x i32>* %src, align 4
%s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%s3 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %s3 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%s4 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %s4 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
%a1 = add <4 x i32> %s1, %s2 %a1 = add <4 x i32> %s1, %s2
%a2 = add <4 x i32> %s3, %s4 %a2 = add <4 x i32> %s3, %s4
%a3 = add <4 x i32> %a1, %a2 %a3 = add <4 x i32> %a1, %a2
store <4 x i32> %a3, <4 x i32> *%dst store <4 x i32> %a3, <4 x i32> *%dst
%ret = getelementptr inbounds <16 x i32>, <16 x i32>* %src, i32 1 %ret = getelementptr inbounds <16 x i32>, <16 x i32>* %src, i32 1
ret <16 x i32> *%ret ret <16 x i32> *%ret
} }
; i16 ; i16
define <32 x i16> *@vld4_v8i16(<32 x i16> *%src, <8 x i16> *%dst) { define <32 x i16> *@vld4_v8i16(<32 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld4_v8i16: ; CHECK-LABEL: vld4_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i16 q2, q2, q3
; CHECK-NEXT: vadd.i16 q4, q2, q3
; CHECK-NEXT: vadd.i16 q0, q0, q1 ; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vadd.i16 q0, q0, q4 ; CHECK-NEXT: vadd.i16 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x i16>, <32 x i16>* %src, align 4 %l1 = load <32 x i16>, <32 x i16>* %src, align 4
%s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = add <8 x i16> %s1, %s2 %a1 = add <8 x i16> %s1, %s2
%a2 = add <8 x i16> %s3, %s4 %a2 = add <8 x i16> %s3, %s4
%a3 = add <8 x i16> %a1, %a2 %a3 = add <8 x i16> %a1, %a2
store <8 x i16> %a3, <8 x i16> *%dst store <8 x i16> %a3, <8 x i16> *%dst
%ret = getelementptr inbounds <32 x i16>, <32 x i16>* %src, i32 1 %ret = getelementptr inbounds <32 x i16>, <32 x i16>* %src, i32 1
ret <32 x i16> *%ret ret <32 x i16> *%ret
} }
; i8 ; i8
define <64 x i8> *@vld4_v16i8(<64 x i8> *%src, <16 x i8> *%dst) { define <64 x i8> *@vld4_v16i8(<64 x i8> *%src, <16 x i8> *%dst) {
; CHECK-LABEL: vld4_v16i8: ; CHECK-LABEL: vld4_v16i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.8 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.8 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i8 q2, q2, q3
; CHECK-NEXT: vadd.i8 q4, q2, q3
; CHECK-NEXT: vadd.i8 q0, q0, q1 ; CHECK-NEXT: vadd.i8 q0, q0, q1
; CHECK-NEXT: vadd.i8 q0, q0, q4 ; CHECK-NEXT: vadd.i8 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <64 x i8>, <64 x i8>* %src, align 4 %l1 = load <64 x i8>, <64 x i8>* %src, align 4
%s1 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> %s1 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
%s2 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> %s2 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
%s3 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> %s3 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
%s4 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> %s4 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
%a1 = add <16 x i8> %s1, %s2 %a1 = add <16 x i8> %s1, %s2
Show All 11 Lines
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0, #48] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f64 d2, d1 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s6, s10
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vmov.f32 s3, s9 ; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov lr, r12, d5
; CHECK-NEXT: vldrw.u32 q2, [r0], #64 ; CHECK-NEXT: vldrw.u32 q2, [r0], #64
; CHECK-NEXT: vmov.f64 d6, d5 ; CHECK-NEXT: vmov r4, r8, d9
; CHECK-NEXT: vmov.f32 s12, s10
; CHECK-NEXT: vmov.f32 s13, s11 ; CHECK-NEXT: vmov.f32 s13, s11
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.f32 s10, s16
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vmov lr, r12, d3
; CHECK-NEXT: vmov r2, r7, d1 ; CHECK-NEXT: vmov r2, r7, d1
; CHECK-NEXT: vmov r4, r8, d7 ; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vmov r3, r6, d5 ; CHECK-NEXT: vmov.f32 s3, s17
; CHECK-NEXT: vmov r3, r6, d1
; CHECK-NEXT: adds.w r2, r2, lr ; CHECK-NEXT: adds.w r2, r2, lr
; CHECK-NEXT: adc.w r7, r7, r12 ; CHECK-NEXT: adc.w r7, r7, r12
; CHECK-NEXT: adds r3, r3, r4 ; CHECK-NEXT: adds r3, r3, r4
; CHECK-NEXT: vmov r4, r5, d2 ; CHECK-NEXT: vmov r4, r5, d2
; CHECK-NEXT: adc.w r6, r6, r8 ; CHECK-NEXT: adc.w r6, r6, r8
; CHECK-NEXT: adds.w r12, r3, r2 ; CHECK-NEXT: adds.w r12, r3, r2
; CHECK-NEXT: vmov r3, r2, d0 ; CHECK-NEXT: vmov r3, r2, d0
; CHECK-NEXT: adc.w lr, r6, r7 ; CHECK-NEXT: adc.w lr, r6, r7
Show All 24 Linesentry:
ret <8 x i64> *%ret ret <8 x i64> *%ret
} }
; f32 ; f32
define <16 x float> *@vld4_v4f32(<16 x float> *%src, <4 x float> *%dst) { define <16 x float> *@vld4_v4f32(<16 x float> *%src, <4 x float> *%dst) {
; CHECK-LABEL: vld4_v4f32: ; CHECK-LABEL: vld4_v4f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vadd.f32 q4, q2, q3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vadd.f32 q0, q0, q4 ; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x float>, <16 x float>* %src, align 4 %l1 = load <16 x float>, <16 x float>* %src, align 4
%s1 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %s1 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%s2 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %s2 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%s3 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %s3 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%s4 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %s4 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
%a1 = fadd <4 x float> %s1, %s2 %a1 = fadd <4 x float> %s1, %s2
%a2 = fadd <4 x float> %s3, %s4 %a2 = fadd <4 x float> %s3, %s4
%a3 = fadd <4 x float> %a1, %a2 %a3 = fadd <4 x float> %a1, %a2
store <4 x float> %a3, <4 x float> *%dst store <4 x float> %a3, <4 x float> *%dst
%ret = getelementptr inbounds <16 x float>, <16 x float>* %src, i32 1 %ret = getelementptr inbounds <16 x float>, <16 x float>* %src, i32 1
ret <16 x float> *%ret ret <16 x float> *%ret
} }
; f16 ; f16
define <32 x half> *@vld4_v8f16(<32 x half> *%src, <8 x half> *%dst) { define <32 x half> *@vld4_v8f16(<32 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld4_v8f16: ; CHECK-LABEL: vld4_v8f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.f16 q2, q2, q3
; CHECK-NEXT: vadd.f16 q4, q2, q3
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vadd.f16 q0, q0, q4 ; CHECK-NEXT: vadd.f16 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x half>, <32 x half>* %src, align 4 %l1 = load <32 x half>, <32 x half>* %src, align 4
%s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = fadd <8 x half> %s1, %s2 %a1 = fadd <8 x half> %s1, %s2
Show All 37 Lines

llvm/test/CodeGen/Thumb2/mve-vld4.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s
; i32 ; i32
define void @vld4_v2i32(<8 x i32> *%src, <2 x i32> *%dst) { define void @vld4_v2i32(<8 x i32> *%src, <2 x i32> *%dst) {
; CHECK-LABEL: vld4_v2i32: ; CHECK-LABEL: vld4_v2i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s8, s3 ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.f32 s12, s1 ; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.f32 s8, s3
; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vmov r0, s10 ; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: vmov r2, s14 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
; CHECK-NEXT: vmov r3, s2 ; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: add.w r12, r2, r0 ; CHECK-NEXT: add.w r12, r2, r0
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
; CHECK-NEXT: vmov r3, s12 ; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: add r0, r3 ; CHECK-NEXT: add r0, r3
Show All 11 Linesentry:
%a3 = add <2 x i32> %a1, %a2 %a3 = add <2 x i32> %a1, %a2
store <2 x i32> %a3, <2 x i32> *%dst store <2 x i32> %a3, <2 x i32> *%dst
ret void ret void
} }
define void @vld4_v4i32(<16 x i32> *%src, <4 x i32> *%dst) { define void @vld4_v4i32(<16 x i32> *%src, <4 x i32> *%dst) {
; CHECK-LABEL: vld4_v4i32: ; CHECK-LABEL: vld4_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vadd.i32 q4, q2, q3
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vadd.i32 q0, q0, q4 ; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x i32>, <16 x i32>* %src, align 4 %l1 = load <16 x i32>, <16 x i32>* %src, align 4
%s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %s1 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %s2 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%s3 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %s3 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%s4 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %s4 = shufflevector <16 x i32> %l1, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
%a1 = add <4 x i32> %s1, %s2 %a1 = add <4 x i32> %s1, %s2
%a2 = add <4 x i32> %s3, %s4 %a2 = add <4 x i32> %s3, %s4
%a3 = add <4 x i32> %a1, %a2 %a3 = add <4 x i32> %a1, %a2
store <4 x i32> %a3, <4 x i32> *%dst store <4 x i32> %a3, <4 x i32> *%dst
ret void ret void
} }
define void @vld4_v8i32(<32 x i32> *%src, <8 x i32> *%dst) { define void @vld4_v8i32(<32 x i32> *%src, <8 x i32> *%dst) {
; CHECK-LABEL: vld4_v8i32: ; CHECK-LABEL: vld4_v8i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
; CHECK-NEXT: vadd.i32 q4, q2, q3 ; CHECK-NEXT: vadd.i32 q4, q2, q3
; CHECK-NEXT: vadd.i32 q5, q0, q1 ; CHECK-NEXT: vadd.i32 q5, q0, q1
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vadd.i32 q4, q5, q4 ; CHECK-NEXT: vadd.i32 q4, q5, q4
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vstrw.32 q4, [r1] ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vadd.i32 q5, q2, q3
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vadd.i32 q0, q0, q5 ; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x i32>, <32 x i32>* %src, align 4 %l1 = load <32 x i32>, <32 x i32>* %src, align 4
%s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x i32> %l1, <32 x i32> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = add <8 x i32> %s1, %s2 %a1 = add <8 x i32> %s1, %s2
%a2 = add <8 x i32> %s3, %s4 %a2 = add <8 x i32> %s3, %s4
%a3 = add <8 x i32> %a1, %a2 %a3 = add <8 x i32> %a1, %a2
store <8 x i32> %a3, <8 x i32> *%dst store <8 x i32> %a3, <8 x i32> *%dst
ret void ret void
} }
define void @vld4_v16i32(<64 x i32> *%src, <16 x i32> *%dst) { define void @vld4_v16i32(<64 x i32> *%src, <16 x i32> *%dst) {
; CHECK-LABEL: vld4_v16i32: ; CHECK-LABEL: vld4_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: push {r4, r5} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .pad #32
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: .pad #112
; CHECK-NEXT: sub sp, #112
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: mov r2, r0 ; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: add.w r3, r0, #192 ; CHECK-NEXT: add.w r3, r0, #192
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]! ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vadd.i32 q4, q2, q3 ; CHECK-NEXT: vld40.32 {q3, q4, q5, q6}, [r3]
; CHECK-NEXT: vadd.i32 q6, q0, q1
; CHECK-NEXT: vstrw.32 q4, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vld41.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vld42.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vld43.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q1_q2_q3_q4
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vadd.i32 q2, q6, q2
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vadd.i32 q2, q3, q4
; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
; CHECK-NEXT: vld40.32 {q1, q2, q3, q4}, [r0]
; CHECK-NEXT: vld41.32 {q1, q2, q3, q4}, [r0]
; CHECK-NEXT: vld42.32 {q1, q2, q3, q4}, [r0]
; CHECK-NEXT: vld43.32 {q1, q2, q3, q4}, [r0]
; CHECK-NEXT: vstrw.32 q4, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vldrw.u32 q1, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vadd.i32 q1, q3, q1
; CHECK-NEXT: vldmia sp, {d6, d7, d8, d9, d10, d11, d12, d13} @ 64-byte Reload
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q3_q4_q5_q6 ; CHECK-NEXT: vld41.32 {q3, q4, q5, q6}, [r3]
; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vld42.32 {q3, q4, q5, q6}, [r3]
; CHECK-NEXT: vld43.32 {q3, q4, q5, q6}, [r3]
; CHECK-NEXT: vadd.i32 q1, q5, q6 ; CHECK-NEXT: vadd.i32 q1, q5, q6
; CHECK-NEXT: vadd.i32 q2, q3, q4 ; CHECK-NEXT: vadd.i32 q2, q3, q4
; CHECK-NEXT: vadd.i32 q0, q2, q1
; CHECK-NEXT: vld40.32 {q4, q5, q6, q7}, [r2]
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.32 {q4, q5, q6, q7}, [r2]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q4, q5, q6, q7}, [r2]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q4, q5, q6, q7}, [r2]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vadd.i32 q2, q2, q3
; CHECK-NEXT: vadd.i32 q0, q0, q2
; CHECK-NEXT: vadd.i32 q1, q6, q7
; CHECK-NEXT: vadd.i32 q2, q4, q5
; CHECK-NEXT: vstrw.32 q0, [r1, #32] ; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vldrw.u32 q2, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #112 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <64 x i32>, <64 x i32>* %src, align 4 %l1 = load <64 x i32>, <64 x i32>* %src, align 4
%s1 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> %s1 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
%s2 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> %s2 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
%s3 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> %s3 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
%s4 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> %s4 = shufflevector <64 x i32> %l1, <64 x i32> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
%a1 = add <16 x i32> %s1, %s2 %a1 = add <16 x i32> %s1, %s2
%a2 = add <16 x i32> %s3, %s4 %a2 = add <16 x i32> %s3, %s4
%a3 = add <16 x i32> %a1, %a2 %a3 = add <16 x i32> %a1, %a2
store <16 x i32> %a3, <16 x i32> *%dst store <16 x i32> %a3, <16 x i32> *%dst
ret void ret void
} }
define void @vld4_v4i32_align1(<16 x i32> *%src, <4 x i32> *%dst) { define void @vld4_v4i32_align1(<16 x i32> *%src, <4 x i32> *%dst) {
; CHECK-LABEL: vld4_v4i32_align1: ; CHECK-LABEL: vld4_v4i32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrb.u8 q2, [r0]
; CHECK-NEXT: vldrb.u8 q3, [r0, #16]
; CHECK-NEXT: vldrb.u8 q1, [r0, #32]
; CHECK-NEXT: vldrb.u8 q0, [r0, #48] ; CHECK-NEXT: vldrb.u8 q0, [r0, #48]
; CHECK-NEXT: vldrb.u8 q1, [r0, #32]
; CHECK-NEXT: vldrb.u8 q3, [r0, #16]
; CHECK-NEXT: vldrb.u8 q2, [r0]
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s16, s11 ; CHECK-NEXT: vmov.f32 s16, s11
; CHECK-NEXT: vmov.f64 d10, d5 ; CHECK-NEXT: vmov.f32 s20, s10
; CHECK-NEXT: vmov.f32 s17, s15 ; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmov.f32 s21, s14 ; CHECK-NEXT: vmov.f32 s21, s14
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmov.f32 s23, s2 ; CHECK-NEXT: vmov.f32 s23, s2
; CHECK-NEXT: vadd.i32 q4, q5, q4 ; CHECK-NEXT: vadd.i32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s20, s9 ; CHECK-NEXT: vmov.f32 s20, s9
; CHECK-NEXT: vmov.f32 s21, s13 ; CHECK-NEXT: vmov.f32 s21, s13
; CHECK-NEXT: vmov.f32 s9, s12
; CHECK-NEXT: vmov.f32 s22, s5 ; CHECK-NEXT: vmov.f32 s22, s5
; CHECK-NEXT: vmov.f32 s10, s4
; CHECK-NEXT: vmov.f32 s23, s1 ; CHECK-NEXT: vmov.f32 s23, s1
; CHECK-NEXT: vmov.f32 s9, s12
; CHECK-NEXT: vmov.f32 s10, s4
; CHECK-NEXT: vmov.f32 s11, s0 ; CHECK-NEXT: vmov.f32 s11, s0
; CHECK-NEXT: vadd.i32 q0, q2, q5 ; CHECK-NEXT: vadd.i32 q0, q2, q5
; CHECK-NEXT: vadd.i32 q0, q0, q4 ; CHECK-NEXT: vadd.i32 q0, q0, q4
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x i32>, <16 x i32>* %src, align 1 %l1 = load <16 x i32>, <16 x i32>* %src, align 1
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Linesentry:
%a3 = add <4 x i16> %a1, %a2 %a3 = add <4 x i16> %a1, %a2
store <4 x i16> %a3, <4 x i16> *%dst store <4 x i16> %a3, <4 x i16> *%dst
ret void ret void
} }
define void @vld4_v8i16(<32 x i16> *%src, <8 x i16> *%dst) { define void @vld4_v8i16(<32 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld4_v8i16: ; CHECK-LABEL: vld4_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i16 q2, q2, q3
; CHECK-NEXT: vadd.i16 q4, q2, q3
; CHECK-NEXT: vadd.i16 q0, q0, q1 ; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vadd.i16 q0, q0, q4 ; CHECK-NEXT: vadd.i16 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x i16>, <32 x i16>* %src, align 2 %l1 = load <32 x i16>, <32 x i16>* %src, align 2
%s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = add <8 x i16> %s1, %s2 %a1 = add <8 x i16> %s1, %s2
%a2 = add <8 x i16> %s3, %s4 %a2 = add <8 x i16> %s3, %s4
%a3 = add <8 x i16> %a1, %a2 %a3 = add <8 x i16> %a1, %a2
store <8 x i16> %a3, <8 x i16> *%dst store <8 x i16> %a3, <8 x i16> *%dst
ret void ret void
} }
define void @vld4_v16i16(<64 x i16> *%src, <16 x i16> *%dst) { define void @vld4_v16i16(<64 x i16> *%src, <16 x i16> *%dst) {
; CHECK-LABEL: vld4_v16i16: ; CHECK-LABEL: vld4_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
; CHECK-NEXT: vadd.i16 q4, q2, q3 ; CHECK-NEXT: vadd.i16 q4, q2, q3
; CHECK-NEXT: vadd.i16 q5, q0, q1 ; CHECK-NEXT: vadd.i16 q5, q0, q1
; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vadd.i16 q4, q5, q4 ; CHECK-NEXT: vadd.i16 q4, q5, q4
; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vstrw.32 q4, [r1] ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i16 q2, q2, q3
; CHECK-NEXT: vadd.i16 q5, q2, q3
; CHECK-NEXT: vadd.i16 q0, q0, q1 ; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vadd.i16 q0, q0, q5 ; CHECK-NEXT: vadd.i16 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <64 x i16>, <64 x i16>* %src, align 2 %l1 = load <64 x i16>, <64 x i16>* %src, align 2
%s1 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> %s1 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
%s2 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> %s2 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
%s3 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> %s3 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
%s4 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> %s4 = shufflevector <64 x i16> %l1, <64 x i16> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
%a1 = add <16 x i16> %s1, %s2 %a1 = add <16 x i16> %s1, %s2
%a2 = add <16 x i16> %s3, %s4 %a2 = add <16 x i16> %s3, %s4
%a3 = add <16 x i16> %a1, %a2 %a3 = add <16 x i16> %a1, %a2
store <16 x i16> %a3, <16 x i16> *%dst store <16 x i16> %a3, <16 x i16> *%dst
ret void ret void
} }
define void @vld4_v8i16_align1(<32 x i16> *%src, <8 x i16> *%dst) { define void @vld4_v8i16_align1(<32 x i16> *%src, <8 x i16> *%dst) {
; CHECK-LABEL: vld4_v8i16_align1: ; CHECK-LABEL: vld4_v8i16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrb.u8 q1, [r0, #32] ; CHECK-NEXT: vldrb.u8 q1, [r0, #32]
; CHECK-NEXT: vldrb.u8 q2, [r0, #48] ; CHECK-NEXT: vldrb.u8 q2, [r0, #48]
; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vmovx.f16 s18, s5 ; CHECK-NEXT: vmovx.f16 s18, s5
; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vins.f16 s18, s0 ; CHECK-NEXT: vins.f16 s18, s0
; CHECK-NEXT: vmovx.f16 s0, s11
; CHECK-NEXT: vmovx.f16 s19, s9 ; CHECK-NEXT: vmovx.f16 s19, s9
; CHECK-NEXT: vmovx.f16 s0, s11
; CHECK-NEXT: vins.f16 s5, s7 ; CHECK-NEXT: vins.f16 s5, s7
; CHECK-NEXT: vins.f16 s19, s0 ; CHECK-NEXT: vins.f16 s19, s0
; CHECK-NEXT: vldrb.u8 q0, [r0] ; CHECK-NEXT: vldrb.u8 q0, [r0]
; CHECK-NEXT: vins.f16 s9, s11 ; CHECK-NEXT: vins.f16 s9, s11
; CHECK-NEXT: vmovx.f16 s24, s6 ; CHECK-NEXT: vmov.f32 s22, s5
; CHECK-NEXT: vmovx.f16 s12, s3
; CHECK-NEXT: vmovx.f16 s16, s1 ; CHECK-NEXT: vmovx.f16 s16, s1
; CHECK-NEXT: vmovx.f16 s12, s3
; CHECK-NEXT: vins.f16 s16, s12 ; CHECK-NEXT: vins.f16 s16, s12
; CHECK-NEXT: vldrb.u8 q3, [r0, #16] ; CHECK-NEXT: vldrb.u8 q3, [r0, #16]
; CHECK-NEXT: vins.f16 s1, s3 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vmovx.f16 s20, s15
; CHECK-NEXT: vmovx.f16 s17, s13
; CHECK-NEXT: vins.f16 s17, s20
; CHECK-NEXT: vmov.f32 s22, s5
; CHECK-NEXT: vmov.f32 s23, s9 ; CHECK-NEXT: vmov.f32 s23, s9
; CHECK-NEXT: vmovx.f16 s17, s13
; CHECK-NEXT: vmovx.f16 s20, s15
; CHECK-NEXT: vins.f16 s13, s15 ; CHECK-NEXT: vins.f16 s13, s15
; CHECK-NEXT: vins.f16 s17, s20
; CHECK-NEXT: vmov.f32 s20, s1 ; CHECK-NEXT: vmov.f32 s20, s1
; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vmov.f32 s21, s13 ; CHECK-NEXT: vmov.f32 s21, s13
; CHECK-NEXT: vadd.i16 q4, q5, q4 ; CHECK-NEXT: vadd.i16 q4, q5, q4
; CHECK-NEXT: vmovx.f16 s22, s4 ; CHECK-NEXT: vmovx.f16 s22, s4
; CHECK-NEXT: vins.f16 s22, s24 ; CHECK-NEXT: vins.f16 s22, s1
; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s24, s10
; CHECK-NEXT: vmovx.f16 s23, s8 ; CHECK-NEXT: vmovx.f16 s23, s8
; CHECK-NEXT: vins.f16 s8, s10 ; CHECK-NEXT: vmovx.f16 s1, s10
; CHECK-NEXT: vmov.f32 s6, s4
; CHECK-NEXT: vmov.f32 s7, s8
; CHECK-NEXT: vins.f16 s23, s24
; CHECK-NEXT: vmovx.f16 s24, s2
; CHECK-NEXT: vmovx.f16 s20, s0 ; CHECK-NEXT: vmovx.f16 s20, s0
; CHECK-NEXT: vins.f16 s20, s24 ; CHECK-NEXT: vins.f16 s23, s1
; CHECK-NEXT: vmovx.f16 s24, s14 ; CHECK-NEXT: vmovx.f16 s1, s2
; CHECK-NEXT: vins.f16 s20, s1
; CHECK-NEXT: vmovx.f16 s21, s12 ; CHECK-NEXT: vmovx.f16 s21, s12
; CHECK-NEXT: vins.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s1, s14
; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vins.f16 s12, s14 ; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vins.f16 s21, s1
; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov.f32 s3, s8
; CHECK-NEXT: vmov.f32 s1, s12 ; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov.f32 s2, s6 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vadd.i16 q0, q0, q5 ; CHECK-NEXT: vadd.i16 q0, q0, q5
; CHECK-NEXT: vadd.i16 q0, q0, q4 ; CHECK-NEXT: vadd.i16 q0, q0, q4
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x i16>, <32 x i16>* %src, align 1 %l1 = load <32 x i16>, <32 x i16>* %src, align 1
%s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x i16> %l1, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = add <8 x i16> %s1, %s2 %a1 = add <8 x i16> %s1, %s2
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Linesentry:
%a3 = add <8 x i8> %a1, %a2 %a3 = add <8 x i8> %a1, %a2
store <8 x i8> %a3, <8 x i8> *%dst store <8 x i8> %a3, <8 x i8> *%dst
ret void ret void
} }
define void @vld4_v16i8(<64 x i8> *%src, <16 x i8> *%dst) { define void @vld4_v16i8(<64 x i8> *%src, <16 x i8> *%dst) {
; CHECK-LABEL: vld4_v16i8: ; CHECK-LABEL: vld4_v16i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.8 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld43.8 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.i8 q2, q2, q3
; CHECK-NEXT: vadd.i8 q4, q2, q3
; CHECK-NEXT: vadd.i8 q0, q0, q1 ; CHECK-NEXT: vadd.i8 q0, q0, q1
; CHECK-NEXT: vadd.i8 q0, q0, q4 ; CHECK-NEXT: vadd.i8 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <64 x i8>, <64 x i8>* %src, align 1 %l1 = load <64 x i8>, <64 x i8>* %src, align 1
%s1 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> %s1 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
%s2 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> %s2 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
%s3 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> %s3 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
%s4 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> %s4 = shufflevector <64 x i8> %l1, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
%a1 = add <16 x i8> %s1, %s2 %a1 = add <16 x i8> %s1, %s2
Show All 10 Lines
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0, #48] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f64 d2, d1 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s6, s10
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vmov.f32 s3, s9 ; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov lr, r12, d5
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmov.f64 d6, d5 ; CHECK-NEXT: vmov r0, r8, d9
; CHECK-NEXT: vmov.f32 s12, s10
; CHECK-NEXT: vmov.f32 s13, s11 ; CHECK-NEXT: vmov.f32 s13, s11
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.f32 s10, s16
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vmov lr, r12, d3
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: vmov r0, r8, d7 ; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vmov r5, r6, d5 ; CHECK-NEXT: vmov.f32 s3, s17
; CHECK-NEXT: vmov r5, r6, d1
; CHECK-NEXT: adds.w r2, r2, lr ; CHECK-NEXT: adds.w r2, r2, lr
; CHECK-NEXT: adc.w r3, r3, r12 ; CHECK-NEXT: adc.w r3, r3, r12
; CHECK-NEXT: vmov r4, r12, d2 ; CHECK-NEXT: vmov r4, r12, d2
; CHECK-NEXT: adds r0, r0, r5 ; CHECK-NEXT: adds r0, r0, r5
; CHECK-NEXT: vmov r5, r7, d0 ; CHECK-NEXT: vmov r5, r7, d0
; CHECK-NEXT: adc.w r6, r6, r8 ; CHECK-NEXT: adc.w r6, r6, r8
; CHECK-NEXT: adds r0, r0, r2 ; CHECK-NEXT: adds r0, r0, r2
; CHECK-NEXT: adc.w lr, r6, r3 ; CHECK-NEXT: adc.w lr, r6, r3
Show All 27 Lines
; CHECK-LABEL: vld4_v4i64: ; CHECK-LABEL: vld4_v4i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vldrw.u32 q5, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f64 d6, d3 ; CHECK-NEXT: vldrw.u32 q6, [r0, #80]
; CHECK-NEXT: vldrw.u32 q6, [r0, #112] ; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s9, s3
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s2, s20
; CHECK-NEXT: vldrw.u32 q7, [r0, #112]
; CHECK-NEXT: vmov.f32 s3, s21
; CHECK-NEXT: vmov r3, r2, d11
; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vmov.f32 s0, s26
; CHECK-NEXT: vmov.f32 s1, s27
; CHECK-NEXT: vmov lr, r12, d9
; CHECK-NEXT: vmov.f32 s12, s6
; CHECK-NEXT: vmov.f32 s13, s7 ; CHECK-NEXT: vmov.f32 s13, s7
; CHECK-NEXT: vmov.f32 s14, s2 ; CHECK-NEXT: vmov r4, r5, d1
; CHECK-NEXT: vmov.f32 s6, s0 ; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vmov.f32 s15, s3 ; CHECK-NEXT: vmov.f32 s3, s17
; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vldrw.u32 q0, [r0, #96]
; CHECK-NEXT: vmov.f64 d4, d11
; CHECK-NEXT: vmov.f32 s9, s23
; CHECK-NEXT: vmov r3, r2, d7
; CHECK-NEXT: vmov r4, r5, d3
; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vmov.f32 s11, s19
; CHECK-NEXT: vmov.f32 s22, s16
; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vldrw.u32 q4, [r0, #64] ; CHECK-NEXT: vldrw.u32 q4, [r0, #64]
; CHECK-NEXT: vmov q7, q5 ; CHECK-NEXT: vmov.f32 s6, s28
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s7, s29
; CHECK-NEXT: vldrw.u32 q5, [r0, #80] ; CHECK-NEXT: vmov.f32 s10, s20
; CHECK-NEXT: vmov r0, r6, d15 ; CHECK-NEXT: vmov.f32 s11, s21
; CHECK-NEXT: vmov.f64 d14, d11 ; CHECK-NEXT: vmov r0, r6, d1
; CHECK-NEXT: vmov.f32 s29, s23
; CHECK-NEXT: vmov lr, r12, d5
; CHECK-NEXT: vmov.f32 s30, s26
; CHECK-NEXT: vmov.f32 s22, s24
; CHECK-NEXT: vmov.f32 s31, s27
; CHECK-NEXT: vmov.f32 s23, s25
; CHECK-NEXT: vmov.f64 d12, d9
; CHECK-NEXT: adds r7, r4, r3 ; CHECK-NEXT: adds r7, r4, r3
; CHECK-NEXT: vmov r4, r8, d0
; CHECK-NEXT: adcs r5, r2 ; CHECK-NEXT: adcs r5, r2
; CHECK-NEXT: vmov r4, r8, d14 ; CHECK-NEXT: vmov r2, r3, d12
; CHECK-NEXT: vmov r2, r3, d10 ; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: vmov.f32 s25, s19 ; CHECK-NEXT: vmov.f32 s1, s19
; CHECK-NEXT: vmov.f32 s26, s2
; CHECK-NEXT: vmov.f32 s18, s0
; CHECK-NEXT: vmov.f32 s27, s3
; CHECK-NEXT: vmov.f32 s19, s1
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: adds.w r0, r0, lr ; CHECK-NEXT: adds.w r0, r0, lr
; CHECK-NEXT: adc.w r6, r6, r12 ; CHECK-NEXT: adc.w r6, r6, r12
; CHECK-NEXT: adds.w lr, r0, r7 ; CHECK-NEXT: adds.w lr, r0, r7
; CHECK-NEXT: adc.w r12, r6, r5 ; CHECK-NEXT: adc.w r12, r6, r5
; CHECK-NEXT: vmov r6, r5, d12 ; CHECK-NEXT: vmov r6, r5, d0
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: adds r2, r2, r4 ; CHECK-NEXT: adds r2, r2, r4
; CHECK-NEXT: vmov r4, r0, d8 ; CHECK-NEXT: vmov r4, r0, d8
; CHECK-NEXT: adc.w r3, r3, r8 ; CHECK-NEXT: adc.w r3, r3, r8
; CHECK-NEXT: adds r6, r6, r4 ; CHECK-NEXT: adds r6, r6, r4
; CHECK-NEXT: adcs r0, r5 ; CHECK-NEXT: adcs r0, r5
; CHECK-NEXT: adds.w r9, r6, r2 ; CHECK-NEXT: adds.w r9, r6, r2
; CHECK-NEXT: adc.w r8, r0, r3 ; CHECK-NEXT: adc.w r8, r0, r3
; CHECK-NEXT: vmov r5, r4, d15 ; CHECK-NEXT: vmov r5, r4, d15
; CHECK-NEXT: vmov r3, r6, d11 ; CHECK-NEXT: vmov r3, r6, d3
; CHECK-NEXT: vmov r7, r0, d9 ; CHECK-NEXT: vmov r7, r0, d5
; CHECK-NEXT: adds r3, r3, r5 ; CHECK-NEXT: adds r3, r3, r5
; CHECK-NEXT: adcs r6, r4 ; CHECK-NEXT: adcs r6, r4
; CHECK-NEXT: vmov r5, r4, d13 ; CHECK-NEXT: vmov r5, r4, d11
; CHECK-NEXT: adds r5, r5, r7 ; CHECK-NEXT: adds r5, r5, r7
; CHECK-NEXT: adcs r0, r4 ; CHECK-NEXT: adcs r0, r4
; CHECK-NEXT: adds r3, r3, r5 ; CHECK-NEXT: adds r3, r3, r5
; CHECK-NEXT: adc.w r10, r0, r6 ; CHECK-NEXT: adc.w r10, r0, r6
; CHECK-NEXT: vmov r4, r5, d4 ; CHECK-NEXT: vmov r4, r5, d4
; CHECK-NEXT: vmov r6, r7, d0 ; CHECK-NEXT: vmov r6, r7, d0
; CHECK-NEXT: vmov r2, r0, d2 ; CHECK-NEXT: vmov r2, r0, d2
; CHECK-NEXT: vmov q1[2], q1[0], r9, r3 ; CHECK-NEXT: vmov q1[2], q1[0], r9, r3
Show All 25 Linesentry:
ret void ret void
} }
; f32 ; f32
define void @vld4_v2f32(<8 x float> *%src, <2 x float> *%dst) { define void @vld4_v2f32(<8 x float> *%src, <2 x float> *%dst) {
; CHECK-LABEL: vld4_v2f32: ; CHECK-LABEL: vld4_v2f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f32 s8, s7 ; CHECK-NEXT: vmov.f32 s8, s7
; CHECK-NEXT: vmov.f64 d6, d3
; CHECK-NEXT: vmov.f32 s9, s3 ; CHECK-NEXT: vmov.f32 s9, s3
; CHECK-NEXT: vmov.f32 s12, s6
; CHECK-NEXT: vmov.f32 s13, s2 ; CHECK-NEXT: vmov.f32 s13, s2
; CHECK-NEXT: vadd.f32 q2, q3, q2 ; CHECK-NEXT: vadd.f32 q2, q3, q2
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s13, s1 ; CHECK-NEXT: vmov.f32 s13, s1
; CHECK-NEXT: vmov.f32 s5, s0 ; CHECK-NEXT: vmov.f32 s5, s0
; CHECK-NEXT: vadd.f32 q0, q1, q3 ; CHECK-NEXT: vadd.f32 q0, q1, q3
; CHECK-NEXT: vadd.f32 q0, q0, q2 ; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vstmia r1, {s0, s1} ; CHECK-NEXT: vstmia r1, {s0, s1}
Show All 9 Linesentry:
%a3 = fadd <2 x float> %a1, %a2 %a3 = fadd <2 x float> %a1, %a2
store <2 x float> %a3, <2 x float> *%dst store <2 x float> %a3, <2 x float> *%dst
ret void ret void
} }
define void @vld4_v4f32(<16 x float> *%src, <4 x float> *%dst) { define void @vld4_v4f32(<16 x float> *%src, <4 x float> *%dst) {
; CHECK-LABEL: vld4_v4f32: ; CHECK-LABEL: vld4_v4f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vadd.f32 q4, q2, q3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vadd.f32 q0, q0, q4 ; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x float>, <16 x float>* %src, align 4 %l1 = load <16 x float>, <16 x float>* %src, align 4
%s1 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %s1 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%s2 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %s2 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%s3 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %s3 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%s4 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %s4 = shufflevector <16 x float> %l1, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
%a1 = fadd <4 x float> %s1, %s2 %a1 = fadd <4 x float> %s1, %s2
%a2 = fadd <4 x float> %s3, %s4 %a2 = fadd <4 x float> %s3, %s4
%a3 = fadd <4 x float> %a1, %a2 %a3 = fadd <4 x float> %a1, %a2
store <4 x float> %a3, <4 x float> *%dst store <4 x float> %a3, <4 x float> *%dst
ret void ret void
} }
define void @vld4_v8f32(<32 x float> *%src, <8 x float> *%dst) { define void @vld4_v8f32(<32 x float> *%src, <8 x float> *%dst) {
; CHECK-LABEL: vld4_v8f32: ; CHECK-LABEL: vld4_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
; CHECK-NEXT: vadd.f32 q4, q2, q3 ; CHECK-NEXT: vadd.f32 q4, q2, q3
; CHECK-NEXT: vadd.f32 q5, q0, q1 ; CHECK-NEXT: vadd.f32 q5, q0, q1
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vadd.f32 q4, q5, q4 ; CHECK-NEXT: vadd.f32 q4, q5, q4
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vstrw.32 q4, [r1] ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vadd.f32 q5, q2, q3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vadd.f32 q0, q0, q5 ; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x float>, <32 x float>* %src, align 4 %l1 = load <32 x float>, <32 x float>* %src, align 4
%s1 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x float> %l1, <32 x float> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = fadd <8 x float> %s1, %s2 %a1 = fadd <8 x float> %s1, %s2
%a2 = fadd <8 x float> %s3, %s4 %a2 = fadd <8 x float> %s3, %s4
%a3 = fadd <8 x float> %a1, %a2 %a3 = fadd <8 x float> %a1, %a2
store <8 x float> %a3, <8 x float> *%dst store <8 x float> %a3, <8 x float> *%dst
ret void ret void
} }
define void @vld4_v16f32(<64 x float> *%src, <16 x float> *%dst) { define void @vld4_v16f32(<64 x float> *%src, <16 x float> *%dst) {
; CHECK-LABEL: vld4_v16f32: ; CHECK-LABEL: vld4_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: push {r4, r5} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .pad #32
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: .pad #112
; CHECK-NEXT: sub sp, #112
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: mov r2, r0 ; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: add.w r3, r0, #192 ; CHECK-NEXT: add.w r3, r0, #192
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: adds r0, #128 ; CHECK-NEXT: adds r0, #128
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]! ; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]!
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vadd.f32 q4, q2, q3 ; CHECK-NEXT: vld40.32 {q3, q4, q5, q6}, [r3]
; CHECK-NEXT: vadd.f32 q6, q0, q1
; CHECK-NEXT: vstrw.32 q4, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vld41.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vld42.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: vld43.32 {q1, q2, q3, q4}, [r3]
; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q1_q2_q3_q4
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vldrw.u32 q2, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vadd.f32 q0, q1, q0
; CHECK-NEXT: vadd.f32 q2, q6, q2
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vadd.f32 q2, q3, q4
; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r2]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
; CHECK-NEXT: vld40.32 {q1, q2, q3, q4}, [r0]
; CHECK-NEXT: vld41.32 {q1, q2, q3, q4}, [r0]
; CHECK-NEXT: vld42.32 {q1, q2, q3, q4}, [r0]
; CHECK-NEXT: vld43.32 {q1, q2, q3, q4}, [r0]
; CHECK-NEXT: vstrw.32 q4, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vldrw.u32 q1, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vadd.f32 q1, q3, q1
; CHECK-NEXT: vldmia sp, {d6, d7, d8, d9, d10, d11, d12, d13} @ 64-byte Reload
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q3_q4_q5_q6 ; CHECK-NEXT: vld41.32 {q3, q4, q5, q6}, [r3]
; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vld42.32 {q3, q4, q5, q6}, [r3]
; CHECK-NEXT: vld43.32 {q3, q4, q5, q6}, [r3]
; CHECK-NEXT: vadd.f32 q1, q5, q6 ; CHECK-NEXT: vadd.f32 q1, q5, q6
; CHECK-NEXT: vadd.f32 q2, q3, q4 ; CHECK-NEXT: vadd.f32 q2, q3, q4
; CHECK-NEXT: vadd.f32 q0, q2, q1
; CHECK-NEXT: vld40.32 {q4, q5, q6, q7}, [r2]
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vld40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.32 {q4, q5, q6, q7}, [r2]
; CHECK-NEXT: vld41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.32 {q4, q5, q6, q7}, [r2]
; CHECK-NEXT: vld42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.32 {q4, q5, q6, q7}, [r2]
; CHECK-NEXT: vld43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vadd.f32 q2, q2, q3
; CHECK-NEXT: vadd.f32 q0, q0, q2
; CHECK-NEXT: vadd.f32 q1, q6, q7
; CHECK-NEXT: vadd.f32 q2, q4, q5
; CHECK-NEXT: vstrw.32 q0, [r1, #32] ; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vadd.f32 q1, q2, q1 ; CHECK-NEXT: vadd.f32 q1, q2, q1
; CHECK-NEXT: vldrw.u32 q2, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #112 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <64 x float>, <64 x float>* %src, align 4 %l1 = load <64 x float>, <64 x float>* %src, align 4
%s1 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> %s1 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
%s2 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> %s2 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
%s3 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> %s3 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
%s4 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> %s4 = shufflevector <64 x float> %l1, <64 x float> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
%a1 = fadd <16 x float> %s1, %s2 %a1 = fadd <16 x float> %s1, %s2
%a2 = fadd <16 x float> %s3, %s4 %a2 = fadd <16 x float> %s3, %s4
%a3 = fadd <16 x float> %a1, %a2 %a3 = fadd <16 x float> %a1, %a2
store <16 x float> %a3, <16 x float> *%dst store <16 x float> %a3, <16 x float> *%dst
ret void ret void
} }
define void @vld4_v4f32_align1(<16 x float> *%src, <4 x float> *%dst) { define void @vld4_v4f32_align1(<16 x float> *%src, <4 x float> *%dst) {
; CHECK-LABEL: vld4_v4f32_align1: ; CHECK-LABEL: vld4_v4f32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrb.u8 q2, [r0]
; CHECK-NEXT: vldrb.u8 q3, [r0, #16]
; CHECK-NEXT: vldrb.u8 q1, [r0, #32]
; CHECK-NEXT: vldrb.u8 q0, [r0, #48] ; CHECK-NEXT: vldrb.u8 q0, [r0, #48]
; CHECK-NEXT: vldrb.u8 q1, [r0, #32]
; CHECK-NEXT: vldrb.u8 q3, [r0, #16]
; CHECK-NEXT: vldrb.u8 q2, [r0]
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s16, s11 ; CHECK-NEXT: vmov.f32 s16, s11
; CHECK-NEXT: vmov.f64 d10, d5 ; CHECK-NEXT: vmov.f32 s20, s10
; CHECK-NEXT: vmov.f32 s17, s15 ; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmov.f32 s21, s14 ; CHECK-NEXT: vmov.f32 s21, s14
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmov.f32 s23, s2 ; CHECK-NEXT: vmov.f32 s23, s2
; CHECK-NEXT: vadd.f32 q4, q5, q4 ; CHECK-NEXT: vadd.f32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s20, s9 ; CHECK-NEXT: vmov.f32 s20, s9
; CHECK-NEXT: vmov.f32 s21, s13 ; CHECK-NEXT: vmov.f32 s21, s13
; CHECK-NEXT: vmov.f32 s9, s12
; CHECK-NEXT: vmov.f32 s22, s5 ; CHECK-NEXT: vmov.f32 s22, s5
; CHECK-NEXT: vmov.f32 s10, s4
; CHECK-NEXT: vmov.f32 s23, s1 ; CHECK-NEXT: vmov.f32 s23, s1
; CHECK-NEXT: vmov.f32 s9, s12
; CHECK-NEXT: vmov.f32 s10, s4
; CHECK-NEXT: vmov.f32 s11, s0 ; CHECK-NEXT: vmov.f32 s11, s0
; CHECK-NEXT: vadd.f32 q0, q2, q5 ; CHECK-NEXT: vadd.f32 q0, q2, q5
; CHECK-NEXT: vadd.f32 q0, q0, q4 ; CHECK-NEXT: vadd.f32 q0, q0, q4
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x float>, <16 x float>* %src, align 1 %l1 = load <16 x float>, <16 x float>* %src, align 1
Show All 9 Lines
} }
; f16 ; f16
define void @vld4_v2f16(<8 x half> *%src, <2 x half> *%dst) { define void @vld4_v2f16(<8 x half> *%src, <2 x half> *%dst) {
; CHECK-LABEL: vld4_v2f16: ; CHECK-LABEL: vld4_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vins.f16 s1, s3 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vins.f16 s8, s4 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vmovx.f16 s12, s0 ; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vins.f16 s12, s4 ; CHECK-NEXT: vins.f16 s12, s4
; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov.f32 s4, s1 ; CHECK-NEXT: vmov.f32 s4, s1
; CHECK-NEXT: vadd.f16 q0, q0, q3 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vadd.f16 q1, q1, q2 ; CHECK-NEXT: vadd.f16 q1, q1, q2
; CHECK-NEXT: vadd.f16 q0, q0, q3
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: str r0, [r1] ; CHECK-NEXT: str r0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <8 x half>, <8 x half>* %src, align 2 %l1 = load <8 x half>, <8 x half>* %src, align 2
%s1 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 0, i32 4> %s1 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 0, i32 4>
%s2 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 1, i32 5> %s2 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 1, i32 5>
%s3 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 2, i32 6> %s3 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 2, i32 6>
%s4 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 3, i32 7> %s4 = shufflevector <8 x half> %l1, <8 x half> undef, <2 x i32> <i32 3, i32 7>
%a1 = fadd <2 x half> %s1, %s2 %a1 = fadd <2 x half> %s1, %s2
%a2 = fadd <2 x half> %s3, %s4 %a2 = fadd <2 x half> %s3, %s4
%a3 = fadd <2 x half> %a1, %a2 %a3 = fadd <2 x half> %a1, %a2
store <2 x half> %a3, <2 x half> *%dst store <2 x half> %a3, <2 x half> *%dst
ret void ret void
} }
define void @vld4_v4f16(<16 x half> *%src, <4 x half> *%dst) { define void @vld4_v4f16(<16 x half> *%src, <4 x half> *%dst) {
; CHECK-LABEL: vld4_v4f16: ; CHECK-LABEL: vld4_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vldrh.u16 q0, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vldrh.u16 q2, [r0, #16] ; CHECK-NEXT: vldrh.u16 q2, [r0, #16]
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s6, s2
; CHECK-NEXT: vins.f16 s0, s2 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmovx.f16 s16, s3
; CHECK-NEXT: vmovx.f16 s12, s10
; CHECK-NEXT: vmovx.f16 s5, s8
; CHECK-NEXT: vins.f16 s5, s12
; CHECK-NEXT: vmovx.f16 s12, s1 ; CHECK-NEXT: vmovx.f16 s12, s1
; CHECK-NEXT: vins.f16 s12, s16 ; CHECK-NEXT: vmovx.f16 s2, s3
; CHECK-NEXT: vins.f16 s8, s10 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s16, s11 ; CHECK-NEXT: vmovx.f16 s5, s8
; CHECK-NEXT: vmovx.f16 s6, s10
; CHECK-NEXT: vins.f16 s12, s2
; CHECK-NEXT: vmovx.f16 s13, s9 ; CHECK-NEXT: vmovx.f16 s13, s9
; CHECK-NEXT: vmovx.f16 s2, s11
; CHECK-NEXT: vins.f16 s1, s3 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vins.f16 s13, s16
; CHECK-NEXT: vins.f16 s9, s11 ; CHECK-NEXT: vins.f16 s9, s11
; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vmov.f32 s16, s1 ; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vins.f16 s13, s2
; CHECK-NEXT: vmov.f32 s1, s8 ; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.f32 s17, s9 ; CHECK-NEXT: vmov.f32 s17, s9
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vadd.f16 q3, q4, q3 ; CHECK-NEXT: vadd.f16 q3, q4, q3
; CHECK-NEXT: vadd.f16 q0, q0, q3 ; CHECK-NEXT: vadd.f16 q0, q0, q3
; CHECK-NEXT: vmov r0, r2, d0 ; CHECK-NEXT: vmov r0, r2, d0
; CHECK-NEXT: strd r0, r2, [r1] ; CHECK-NEXT: strd r0, r2, [r1]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <16 x half>, <16 x half>* %src, align 2 %l1 = load <16 x half>, <16 x half>* %src, align 2
%s1 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %s1 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
%s2 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> %s2 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
%s3 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> %s3 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
%s4 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> %s4 = shufflevector <16 x half> %l1, <16 x half> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
%a1 = fadd <4 x half> %s1, %s2 %a1 = fadd <4 x half> %s1, %s2
%a2 = fadd <4 x half> %s3, %s4 %a2 = fadd <4 x half> %s3, %s4
%a3 = fadd <4 x half> %a1, %a2 %a3 = fadd <4 x half> %a1, %a2
store <4 x half> %a3, <4 x half> *%dst store <4 x half> %a3, <4 x half> *%dst
ret void ret void
} }
define void @vld4_v8f16(<32 x half> *%src, <8 x half> *%dst) { define void @vld4_v8f16(<32 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld4_v8f16: ; CHECK-LABEL: vld4_v8f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 ; CHECK-NEXT: vadd.f16 q2, q2, q3
; CHECK-NEXT: vadd.f16 q4, q2, q3
; CHECK-NEXT: vadd.f16 q0, q0, q1 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vadd.f16 q0, q0, q4 ; CHECK-NEXT: vadd.f16 q0, q0, q2
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x half>, <32 x half>* %src, align 2 %l1 = load <32 x half>, <32 x half>* %src, align 2
%s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> %s2 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> %s3 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> %s4 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%a1 = fadd <8 x half> %s1, %s2 %a1 = fadd <8 x half> %s1, %s2
%a2 = fadd <8 x half> %s3, %s4 %a2 = fadd <8 x half> %s3, %s4
%a3 = fadd <8 x half> %a1, %a2 %a3 = fadd <8 x half> %a1, %a2
store <8 x half> %a3, <8 x half> *%dst store <8 x half> %a3, <8 x half> *%dst
ret void ret void
} }
define void @vld4_v16f16(<64 x half> *%src, <16 x half> *%dst) { define void @vld4_v16f16(<64 x half> *%src, <16 x half> *%dst) {
; CHECK-LABEL: vld4_v16f16: ; CHECK-LABEL: vld4_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5}
; CHECK-NEXT: push {r4, r5}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #80
; CHECK-NEXT: sub sp, #80
; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld40.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld41.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vld42.16 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vld43.16 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: vld40.16 {q4, q5, q6, q7}, [r0] ; CHECK-NEXT: vld40.16 {q4, q5, q6, q7}, [r0]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill ; CHECK-NEXT: vadd.f16 q2, q2, q3
; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vld41.16 {q4, q5, q6, q7}, [r0] ; CHECK-NEXT: vld41.16 {q4, q5, q6, q7}, [r0]
; CHECK-NEXT: vadd.f16 q0, q0, q2
; CHECK-NEXT: vld42.16 {q4, q5, q6, q7}, [r0] ; CHECK-NEXT: vld42.16 {q4, q5, q6, q7}, [r0]
; CHECK-NEXT: vld43.16 {q4, q5, q6, q7}, [r0] ; CHECK-NEXT: vld43.16 {q4, q5, q6, q7}, [r0]
; CHECK-NEXT: @ kill: def $q4 killed $q4 killed $q4_q5_q6_q7 ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vadd.f16 q0, q6, q7 ; CHECK-NEXT: vadd.f16 q6, q6, q7
; CHECK-NEXT: vadd.f16 q4, q4, q5 ; CHECK-NEXT: vadd.f16 q4, q4, q5
; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vadd.f16 q4, q4, q6
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vadd.f16 q4, q4, q0
; CHECK-NEXT: vldmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload
; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3
; CHECK-NEXT: vstrw.32 q4, [r1, #16] ; CHECK-NEXT: vstrw.32 q4, [r1, #16]
; CHECK-NEXT: vadd.f16 q4, q2, q3
; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: vadd.f16 q0, q0, q4
; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #80
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <64 x half>, <64 x half>* %src, align 2 %l1 = load <64 x half>, <64 x half>* %src, align 2
%s1 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> %s1 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60>
%s2 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> %s2 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61>
%s3 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> %s3 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62>
%s4 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> %s4 = shufflevector <64 x half> %l1, <64 x half> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63>
%a1 = fadd <16 x half> %s1, %s2 %a1 = fadd <16 x half> %s1, %s2
%a2 = fadd <16 x half> %s3, %s4 %a2 = fadd <16 x half> %s3, %s4
%a3 = fadd <16 x half> %a1, %a2 %a3 = fadd <16 x half> %a1, %a2
store <16 x half> %a3, <16 x half> *%dst store <16 x half> %a3, <16 x half> *%dst
ret void ret void
} }
define void @vld4_v8f16_align1(<32 x half> *%src, <8 x half> *%dst) { define void @vld4_v8f16_align1(<32 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vld4_v8f16_align1: ; CHECK-LABEL: vld4_v8f16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrb.u8 q0, [r0, #32] ; CHECK-NEXT: vldrb.u8 q0, [r0, #32]
; CHECK-NEXT: vldrb.u8 q2, [r0, #48] ; CHECK-NEXT: vldrb.u8 q2, [r0, #48]
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vmovx.f16 s18, s1 ; CHECK-NEXT: vmovx.f16 s18, s1
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vins.f16 s18, s4 ; CHECK-NEXT: vins.f16 s18, s4
; CHECK-NEXT: vmovx.f16 s4, s11
; CHECK-NEXT: vmovx.f16 s19, s9 ; CHECK-NEXT: vmovx.f16 s19, s9
; CHECK-NEXT: vmovx.f16 s4, s11
; CHECK-NEXT: vins.f16 s1, s3 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vins.f16 s19, s4 ; CHECK-NEXT: vins.f16 s19, s4
; CHECK-NEXT: vldrb.u8 q1, [r0] ; CHECK-NEXT: vldrb.u8 q1, [r0]
; CHECK-NEXT: vmovx.f16 s24, s2 ; CHECK-NEXT: vmovx.f16 s22, s0
; CHECK-NEXT: vins.f16 s9, s11 ; CHECK-NEXT: vmovx.f16 s3, s2
; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vmovx.f16 s16, s5 ; CHECK-NEXT: vmovx.f16 s16, s5
; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vins.f16 s16, s12 ; CHECK-NEXT: vins.f16 s16, s12
; CHECK-NEXT: vldrb.u8 q3, [r0, #16] ; CHECK-NEXT: vldrb.u8 q3, [r0, #16]
; CHECK-NEXT: vins.f16 s5, s7 ; CHECK-NEXT: vins.f16 s22, s3
; CHECK-NEXT: vmovx.f16 s20, s15 ; CHECK-NEXT: vmovx.f16 s23, s8
; CHECK-NEXT: vmovx.f16 s17, s13 ; CHECK-NEXT: vmovx.f16 s17, s13
; CHECK-NEXT: vmovx.f16 s20, s15
; CHECK-NEXT: vmovx.f16 s3, s10
; CHECK-NEXT: vins.f16 s17, s20 ; CHECK-NEXT: vins.f16 s17, s20
; CHECK-NEXT: vmovx.f16 s22, s0 ; CHECK-NEXT: vins.f16 s23, s3
; CHECK-NEXT: vins.f16 s22, s24
; CHECK-NEXT: vmovx.f16 s24, s10
; CHECK-NEXT: vmovx.f16 s23, s8
; CHECK-NEXT: vins.f16 s13, s15
; CHECK-NEXT: vins.f16 s23, s24
; CHECK-NEXT: vmovx.f16 s24, s6
; CHECK-NEXT: vmovx.f16 s20, s4 ; CHECK-NEXT: vmovx.f16 s20, s4
; CHECK-NEXT: vins.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s3, s6
; CHECK-NEXT: vins.f16 s20, s24 ; CHECK-NEXT: vins.f16 s9, s11
; CHECK-NEXT: vmovx.f16 s24, s14 ; CHECK-NEXT: vins.f16 s5, s7
; CHECK-NEXT: vins.f16 s13, s15
; CHECK-NEXT: vins.f16 s20, s3
; CHECK-NEXT: vmovx.f16 s21, s12 ; CHECK-NEXT: vmovx.f16 s21, s12
; CHECK-NEXT: vmovx.f16 s3, s14
; CHECK-NEXT: vins.f16 s8, s10 ; CHECK-NEXT: vins.f16 s8, s10
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmov.f32 s26, s1 ; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vins.f16 s4, s6 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov.f32 s27, s9
; CHECK-NEXT: vmov.f32 s24, s5 ; CHECK-NEXT: vmov.f32 s24, s5
; CHECK-NEXT: vins.f16 s12, s14 ; CHECK-NEXT: vins.f16 s21, s3
; CHECK-NEXT: vmov.f32 s26, s1
; CHECK-NEXT: vmov.f32 s27, s9
; CHECK-NEXT: vmov.f32 s25, s13
; CHECK-NEXT: vmov.f32 s6, s0 ; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vadd.f16 q4, q6, q4
; CHECK-NEXT: vmov.f32 s7, s8 ; CHECK-NEXT: vmov.f32 s7, s8
; CHECK-NEXT: vmov.f32 s25, s13
; CHECK-NEXT: vmov.f32 s5, s12 ; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vadd.f16 q4, q6, q4
; CHECK-NEXT: vadd.f16 q0, q1, q5 ; CHECK-NEXT: vadd.f16 q0, q1, q5
; CHECK-NEXT: vadd.f16 q0, q0, q4 ; CHECK-NEXT: vadd.f16 q0, q0, q4
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <32 x half>, <32 x half>* %src, align 1 %l1 = load <32 x half>, <32 x half>* %src, align 1
%s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> %s1 = shufflevector <32 x half> %l1, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll

Show All 24 Lines
; CHECK-NEXT: add.w r12, r1, r4, lsl #1 ; CHECK-NEXT: add.w r12, r1, r4, lsl #1
; CHECK-NEXT: add.w lr, r5, r3, lsr #3 ; CHECK-NEXT: add.w lr, r5, r3, lsr #3
; CHECK-NEXT: add.w r3, r0, r4, lsl #2 ; CHECK-NEXT: add.w r3, r0, r4, lsl #2
; CHECK-NEXT: and r5, r2, #7 ; CHECK-NEXT: and r5, r2, #7
; CHECK-NEXT: .LBB0_4: @ %vector.body ; CHECK-NEXT: .LBB0_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vld20.16 {q0, q1}, [r0] ; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
; CHECK-NEXT: vld21.16 {q0, q1}, [r0]! ; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!
; CHECK-NEXT: vmul.f16 q2, q0, q0 ; CHECK-NEXT: vmul.f16 q0, q0, q0
; CHECK-NEXT: vfma.f16 q2, q1, q1 ; CHECK-NEXT: vfma.f16 q0, q1, q1
; CHECK-NEXT: vstrb.8 q2, [r1], #16 ; CHECK-NEXT: vstrb.8 q0, [r1], #16
; CHECK-NEXT: le lr, .LBB0_4 ; CHECK-NEXT: le lr, .LBB0_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r4, r2 ; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r7, pc} ; CHECK-NEXT: popeq {r4, r5, r7, pc}
; CHECK-NEXT: .LBB0_6: @ %while.body.preheader26 ; CHECK-NEXT: .LBB0_6: @ %while.body.preheader26
; CHECK-NEXT: dls lr, r5 ; CHECK-NEXT: dls lr, r5
; CHECK-NEXT: .LBB0_7: @ %while.body ; CHECK-NEXT: .LBB0_7: @ %while.body
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add.w r12, r1, r4, lsl #2 ; CHECK-NEXT: add.w r12, r1, r4, lsl #2
; CHECK-NEXT: add.w lr, r5, r3, lsr #2 ; CHECK-NEXT: add.w lr, r5, r3, lsr #2
; CHECK-NEXT: add.w r3, r0, r4, lsl #3 ; CHECK-NEXT: add.w r3, r0, r4, lsl #3
; CHECK-NEXT: and r5, r2, #3 ; CHECK-NEXT: and r5, r2, #3
; CHECK-NEXT: .LBB1_4: @ %vector.body ; CHECK-NEXT: .LBB1_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vld20.32 {q0, q1}, [r0] ; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
; CHECK-NEXT: vld21.32 {q0, q1}, [r0]! ; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!
; CHECK-NEXT: vmul.f32 q2, q0, q0 ; CHECK-NEXT: vmul.f32 q0, q0, q0
; CHECK-NEXT: vfma.f32 q2, q1, q1 ; CHECK-NEXT: vfma.f32 q0, q1, q1
; CHECK-NEXT: vstrb.8 q2, [r1], #16 ; CHECK-NEXT: vstrb.8 q0, [r1], #16
; CHECK-NEXT: le lr, .LBB1_4 ; CHECK-NEXT: le lr, .LBB1_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r4, r2 ; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r7, pc} ; CHECK-NEXT: popeq {r4, r5, r7, pc}
; CHECK-NEXT: .LBB1_6: @ %while.body.preheader26 ; CHECK-NEXT: .LBB1_6: @ %while.body.preheader26
; CHECK-NEXT: dls lr, r5 ; CHECK-NEXT: dls lr, r5
; CHECK-NEXT: .LBB1_7: @ %while.body ; CHECK-NEXT: .LBB1_7: @ %while.body
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vldst4.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 { define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
; CHECK-LABEL: vldst4: ; CHECK-LABEL: vldst4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: mul r12, r3, r2 ; CHECK-NEXT: mul r12, r3, r2
; CHECK-NEXT: lsrs.w r2, r12, #2 ; CHECK-NEXT: lsrs.w r2, r12, #2
; CHECK-NEXT: beq.w .LBB0_3 ; CHECK-NEXT: beq.w .LBB0_3
; CHECK-NEXT: @ %bb.1: @ %vector.ph ; CHECK-NEXT: @ %bb.1: @ %vector.ph
; CHECK-NEXT: mvn r3, #7 ; CHECK-NEXT: mvn r3, #7
; CHECK-NEXT: ldr r2, [sp, #88] ; CHECK-NEXT: ldr r2, [sp, #56]
; CHECK-NEXT: and.w r3, r3, r12, lsr #2 ; CHECK-NEXT: and.w r3, r3, r12, lsr #2
; CHECK-NEXT: sub.w r12, r3, #8 ; CHECK-NEXT: sub.w r12, r3, #8
; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: movs r3, #1
; CHECK-NEXT: add.w lr, r3, r12, lsr #3 ; CHECK-NEXT: add.w lr, r3, r12, lsr #3
; CHECK-NEXT: .LBB0_2: @ %vector.body ; CHECK-NEXT: .LBB0_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q4, [r0, #32] ; CHECK-NEXT: vldrh.u16 q1, [r0, #32]
; CHECK-NEXT: vldrh.u16 q5, [r0, #48] ; CHECK-NEXT: vldrh.u16 q4, [r0, #48]
; CHECK-NEXT: vldrh.u16 q3, [r0], #64 ; CHECK-NEXT: vldrh.u16 q3, [r0], #64
; CHECK-NEXT: vmov.f32 s2, s17 ; CHECK-NEXT: vmovx.f16 s26, s4
; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s6, s6
; CHECK-NEXT: vldrh.u16 q5, [r0, #-48]
; CHECK-NEXT: vmovx.f16 s27, s16
; CHECK-NEXT: vins.f16 s26, s6
; CHECK-NEXT: vmovx.f16 s6, s18
; CHECK-NEXT: vmovx.f16 s8, s7
; CHECK-NEXT: vmovx.f16 s10, s5
; CHECK-NEXT: vmovx.f16 s24, s12
; CHECK-NEXT: vins.f16 s10, s8
; CHECK-NEXT: vins.f16 s27, s6
; CHECK-NEXT: vmovx.f16 s6, s14
; CHECK-NEXT: vmovx.f16 s8, s19 ; CHECK-NEXT: vmovx.f16 s8, s19
; CHECK-NEXT: vldrh.u16 q6, [r0, #-48] ; CHECK-NEXT: vmovx.f16 s11, s17
; CHECK-NEXT: vins.f16 s2, s19
; CHECK-NEXT: vmov.f32 s3, s21
; CHECK-NEXT: vmovx.f16 s5, s25
; CHECK-NEXT: vins.f16 s3, s23
; CHECK-NEXT: vmovx.f16 s6, s17
; CHECK-NEXT: vmov.f32 s0, s13 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vins.f16 s6, s8 ; CHECK-NEXT: vins.f16 s11, s8
; CHECK-NEXT: vmovx.f16 s8, s23 ; CHECK-NEXT: vmovx.f16 s25, s20
; CHECK-NEXT: vmovx.f16 s7, s21 ; CHECK-NEXT: vins.f16 s24, s6
; CHECK-NEXT: vins.f16 s0, s15 ; CHECK-NEXT: vmovx.f16 s6, s22
; CHECK-NEXT: vins.f16 s7, s8 ; CHECK-NEXT: vmovx.f16 s1, s15
; CHECK-NEXT: vmovx.f16 s8, s15 ; CHECK-NEXT: vmovx.f16 s8, s13
; CHECK-NEXT: vmovx.f16 s4, s13
; CHECK-NEXT: vins.f16 s25, s27
; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmovx.f16 s8, s27
; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vmov.f32 s1, s25
; CHECK-NEXT: vmul.f16 q2, q1, r2
; CHECK-NEXT: vmul.f16 q0, q0, r2
; CHECK-NEXT: vmovx.f16 s7, s0
; CHECK-NEXT: vmovx.f16 s28, s8
; CHECK-NEXT: vins.f16 s7, s28
; CHECK-NEXT: vmovx.f16 s30, s16
; CHECK-NEXT: vmovx.f16 s31, s20
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s28, s12
; CHECK-NEXT: vins.f16 s16, s18
; CHECK-NEXT: vmovx.f16 s29, s24
; CHECK-NEXT: vmovx.f16 s4, s18
; CHECK-NEXT: vins.f16 s20, s22 ; CHECK-NEXT: vins.f16 s20, s22
; CHECK-NEXT: vins.f16 s30, s4 ; CHECK-NEXT: vins.f16 s16, s18
; CHECK-NEXT: vmovx.f16 s4, s22 ; CHECK-NEXT: vins.f16 s25, s6
; CHECK-NEXT: vmov.f32 s2, s5
; CHECK-NEXT: vmov.f32 s3, s17
; CHECK-NEXT: vins.f16 s0, s15
; CHECK-NEXT: vmovx.f16 s9, s21
; CHECK-NEXT: vins.f16 s8, s1
; CHECK-NEXT: vmovx.f16 s1, s23
; CHECK-NEXT: vins.f16 s12, s14 ; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vins.f16 s31, s4 ; CHECK-NEXT: vins.f16 s21, s23
; CHECK-NEXT: vmovx.f16 s4, s14 ; CHECK-NEXT: vmov.f32 s14, s4
; CHECK-NEXT: vmov.f32 s14, s16 ; CHECK-NEXT: vmov.f32 s15, s16
; CHECK-NEXT: vins.f16 s24, s26 ; CHECK-NEXT: vins.f16 s9, s1
; CHECK-NEXT: vmov.f32 s15, s20 ; CHECK-NEXT: vmov.f32 s13, s20
; CHECK-NEXT: vins.f16 s28, s4 ; CHECK-NEXT: vmul.f16 q6, q6, r2
; CHECK-NEXT: vmovx.f16 s4, s26
; CHECK-NEXT: vmov.f32 s13, s24
; CHECK-NEXT: vins.f16 s29, s4
; CHECK-NEXT: vmul.f16 q3, q3, r2 ; CHECK-NEXT: vmul.f16 q3, q3, r2
; CHECK-NEXT: vmul.f16 q7, q7, r2 ; CHECK-NEXT: vins.f16 s2, s7
; CHECK-NEXT: vins.f16 s3, s19
; CHECK-NEXT: vmov.f32 s1, s21
; CHECK-NEXT: vmul.f16 q0, q0, r2
; CHECK-NEXT: vmovx.f16 s4, s12 ; CHECK-NEXT: vmovx.f16 s4, s12
; CHECK-NEXT: vmovx.f16 s6, s28 ; CHECK-NEXT: vmovx.f16 s6, s24
; CHECK-NEXT: vmul.f16 q2, q2, r2
; CHECK-NEXT: vmovx.f16 s7, s0
; CHECK-NEXT: vins.f16 s0, s8 ; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vmovx.f16 s8, s8
; CHECK-NEXT: vins.f16 s4, s6 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s6, s1 ; CHECK-NEXT: vmovx.f16 s5, s1
; CHECK-NEXT: vmovx.f16 s5, s9 ; CHECK-NEXT: vmovx.f16 s6, s9
; CHECK-NEXT: vins.f16 s12, s28 ; CHECK-NEXT: vins.f16 s7, s8
; CHECK-NEXT: vins.f16 s6, s5 ; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vmovx.f16 s18, s13 ; CHECK-NEXT: vmovx.f16 s6, s13
; CHECK-NEXT: vmovx.f16 s5, s29 ; CHECK-NEXT: vmovx.f16 s8, s25
; CHECK-NEXT: vins.f16 s1, s9 ; CHECK-NEXT: vins.f16 s6, s8
; CHECK-NEXT: vins.f16 s18, s5 ; CHECK-NEXT: vmovx.f16 s19, s2
; CHECK-NEXT: vmovx.f16 s23, s2 ; CHECK-NEXT: vmovx.f16 s8, s10
; CHECK-NEXT: vmovx.f16 s5, s10 ; CHECK-NEXT: vmovx.f16 s18, s14
; CHECK-NEXT: vins.f16 s2, s10 ; CHECK-NEXT: vins.f16 s19, s8
; CHECK-NEXT: vins.f16 s23, s5 ; CHECK-NEXT: vmovx.f16 s8, s26
; CHECK-NEXT: vins.f16 s13, s29 ; CHECK-NEXT: vins.f16 s18, s8
; CHECK-NEXT: vmovx.f16 s27, s3 ; CHECK-NEXT: vmovx.f16 s23, s3
; CHECK-NEXT: vmovx.f16 s8, s11 ; CHECK-NEXT: vmovx.f16 s8, s11
; CHECK-NEXT: vmovx.f16 s22, s14 ; CHECK-NEXT: vins.f16 s14, s26
; CHECK-NEXT: vins.f16 s27, s8 ; CHECK-NEXT: vins.f16 s23, s8
; CHECK-NEXT: vins.f16 s14, s30 ; CHECK-NEXT: vmovx.f16 s22, s15
; CHECK-NEXT: vmovx.f16 s26, s15 ; CHECK-NEXT: vins.f16 s15, s27
; CHECK-NEXT: vins.f16 s15, s31 ; CHECK-NEXT: vmovx.f16 s8, s27
; CHECK-NEXT: vmovx.f16 s8, s31 ; CHECK-NEXT: vins.f16 s12, s24
; CHECK-NEXT: vins.f16 s13, s25
; CHECK-NEXT: vins.f16 s3, s11 ; CHECK-NEXT: vins.f16 s3, s11
; CHECK-NEXT: vins.f16 s26, s8 ; CHECK-NEXT: vins.f16 s1, s9
; CHECK-NEXT: vins.f16 s2, s10
; CHECK-NEXT: vins.f16 s22, s8
; CHECK-NEXT: vmov q2, q3 ; CHECK-NEXT: vmov q2, q3
; CHECK-NEXT: vmovx.f16 s5, s30 ; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s4 ; CHECK-NEXT: vmov.f32 s10, s4
; CHECK-NEXT: vmov.f32 s29, s0 ; CHECK-NEXT: vmov q6, q0
; CHECK-NEXT: vins.f16 s22, s5 ; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vmov.f32 s9, s0 ; CHECK-NEXT: vmov.f32 s9, s0
; CHECK-NEXT: vmov.f32 s11, s31 ; CHECK-NEXT: vmov.f32 s17, s2
; CHECK-NEXT: vmov q7, q0 ; CHECK-NEXT: vmov.f32 s16, s14
; CHECK-NEXT: vmov.f32 s31, s6 ; CHECK-NEXT: vmov.f32 s21, s3
; CHECK-NEXT: vmov.f32 s16, s13 ; CHECK-NEXT: vstrh.16 q4, [r1, #32]
; CHECK-NEXT: vmov.f32 s21, s2 ; CHECK-NEXT: vmov.f32 s20, s15
; CHECK-NEXT: vmov.f32 s25, s3 ; CHECK-NEXT: vmov.f32 s7, s5
; CHECK-NEXT: vmov.f32 s17, s29 ; CHECK-NEXT: vstrh.16 q5, [r1, #48]
; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vmov.f32 s24, s15
; CHECK-NEXT: vstrh.16 q5, [r1, #32]
; CHECK-NEXT: vstrh.16 q6, [r1, #48]
; CHECK-NEXT: vstrh.16 q2, [r1], #64 ; CHECK-NEXT: vstrh.16 q2, [r1], #64
; CHECK-NEXT: vmov.f32 s19, s31 ; CHECK-NEXT: vmov.f32 s4, s13
; CHECK-NEXT: vstrh.16 q4, [r1, #-48] ; CHECK-NEXT: vmov.f32 s5, s25
; CHECK-NEXT: vstrh.16 q1, [r1, #-48]
; CHECK-NEXT: le lr, .LBB0_2 ; CHECK-NEXT: le lr, .LBB0_2
; CHECK-NEXT: .LBB0_3: @ %while.end ; CHECK-NEXT: .LBB0_3: @ %while.end
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%tmp.0.extract.trunc = trunc i32 %scale.coerce to i16 %tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
%l0 = bitcast i16 %tmp.0.extract.trunc to half %l0 = bitcast i16 %tmp.0.extract.trunc to half
%mul = mul i32 %numCols, %numRows %mul = mul i32 %numCols, %numRows
%shr = lshr i32 %mul, 2 %shr = lshr i32 %mul, 2
%cmp38 = icmp eq i32 %shr, 0 %cmp38 = icmp eq i32 %shr, 0
br i1 %cmp38, label %while.end, label %vector.ph br i1 %cmp38, label %while.end, label %vector.ph
Show All 40 Lines

llvm/test/CodeGen/Thumb2/mve-vmovn.ll

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Linesentry:
%out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3> %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3>
ret <2 x i64> %out ret <2 x i64> %out
} }
define arm_aapcs_vfpcc <2 x i64> @vmovn64_b2(<2 x i64> %src1, <2 x i64> %src2) { define arm_aapcs_vfpcc <2 x i64> @vmovn64_b2(<2 x i64> %src1, <2 x i64> %src2) {
; CHECK-LABEL: vmovn64_b2: ; CHECK-LABEL: vmovn64_b2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s4, s6 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vmov.f32 s6, s0 ; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vmov.f32 s7, s1 ; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECKBE-LABEL: vmovn64_b2: ; CHECKBE-LABEL: vmovn64_b2:
; CHECKBE: @ %bb.0: @ %entry ; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.f32 s4, s6 ; CHECKBE-NEXT: vmov.f32 s4, s6
; CHECKBE-NEXT: vmov.f32 s5, s7
; CHECKBE-NEXT: vmov.f32 s6, s0 ; CHECKBE-NEXT: vmov.f32 s6, s0
; CHECKBE-NEXT: vmov.f32 s5, s7
; CHECKBE-NEXT: vmov.f32 s7, s1 ; CHECKBE-NEXT: vmov.f32 s7, s1
; CHECKBE-NEXT: vmov q0, q1 ; CHECKBE-NEXT: vmov q0, q1
; CHECKBE-NEXT: bx lr ; CHECKBE-NEXT: bx lr
entry: entry:
%out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 0> %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %out ret <2 x i64> %out
} }
define arm_aapcs_vfpcc <2 x i64> @vmovn64_b3(<2 x i64> %src1, <2 x i64> %src2) { define arm_aapcs_vfpcc <2 x i64> @vmovn64_b3(<2 x i64> %src1, <2 x i64> %src2) {
; CHECK-LABEL: vmovn64_b3: ; CHECK-LABEL: vmovn64_b3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s0, s2 ; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECKBE-LABEL: vmovn64_b3: ; CHECKBE-LABEL: vmovn64_b3:
; CHECKBE: @ %bb.0: @ %entry ; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.f32 s0, s2 ; CHECKBE-NEXT: vmov.f32 s0, s2
; CHECKBE-NEXT: vmov.f32 s1, s3
; CHECKBE-NEXT: vmov.f32 s2, s4 ; CHECKBE-NEXT: vmov.f32 s2, s4
; CHECKBE-NEXT: vmov.f32 s1, s3
; CHECKBE-NEXT: vmov.f32 s3, s5 ; CHECKBE-NEXT: vmov.f32 s3, s5
; CHECKBE-NEXT: bx lr ; CHECKBE-NEXT: bx lr
entry: entry:
%out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 1, i32 2> %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 1, i32 2>
ret <2 x i64> %out ret <2 x i64> %out
} }
define arm_aapcs_vfpcc <2 x i64> @vmovn64_b4(<2 x i64> %src1, <2 x i64> %src2) { define arm_aapcs_vfpcc <2 x i64> @vmovn64_b4(<2 x i64> %src1, <2 x i64> %src2) {
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
entry: entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 5, i32 2, i32 7> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <4 x i32> @vmovn32_b2(<4 x i32> %src1, <4 x i32> %src2) { define arm_aapcs_vfpcc <4 x i32> @vmovn32_b2(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: vmovn32_b2: ; CHECK-LABEL: vmovn32_b2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vmov.f32 s9, s0 ; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s5, s0
; CHECK-NEXT: vmov.f32 s11, s2 ; CHECK-NEXT: vmov.f32 s7, s2
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECKBE-LABEL: vmovn32_b2: ; CHECKBE-LABEL: vmovn32_b2:
; CHECKBE: @ %bb.0: @ %entry ; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vrev64.32 q2, q0 ; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: vrev64.32 q0, q1 ; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: vmov.f32 s4, s1 ; CHECKBE-NEXT: vmov.f32 s4, s1
; CHECKBE-NEXT: vmov.f32 s5, s8 ; CHECKBE-NEXT: vmov.f32 s5, s8
; CHECKBE-NEXT: vmov.f32 s6, s3 ; CHECKBE-NEXT: vmov.f32 s6, s3
; CHECKBE-NEXT: vmov.f32 s7, s10 ; CHECKBE-NEXT: vmov.f32 s7, s10
; CHECKBE-NEXT: vrev64.32 q0, q1 ; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr ; CHECKBE-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 5, i32 0, i32 7, i32 2> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 5, i32 0, i32 7, i32 2>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <4 x i32> @vmovn32_b3(<4 x i32> %src1, <4 x i32> %src2) { define arm_aapcs_vfpcc <4 x i32> @vmovn32_b3(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: vmovn32_b3: ; CHECK-LABEL: vmovn32_b3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s9, s4 ; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov.f32 s10, s3 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.f32 s11, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECKBE-LABEL: vmovn32_b3: ; CHECKBE-LABEL: vmovn32_b3:
; CHECKBE: @ %bb.0: @ %entry ; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vrev64.32 q2, q1 ; CHECKBE-NEXT: vrev64.32 q2, q1
; CHECKBE-NEXT: vrev64.32 q1, q0 ; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: vmov.f32 s12, s5 ; CHECKBE-NEXT: vmov.f32 s4, s5
; CHECKBE-NEXT: vmov.f32 s13, s8 ; CHECKBE-NEXT: vmov.f32 s6, s7
; CHECKBE-NEXT: vmov.f32 s14, s7 ; CHECKBE-NEXT: vmov.f32 s5, s8
; CHECKBE-NEXT: vmov.f32 s15, s10 ; CHECKBE-NEXT: vmov.f32 s7, s10
; CHECKBE-NEXT: vrev64.32 q0, q3 ; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr ; CHECKBE-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 1, i32 4, i32 3, i32 6> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 1, i32 4, i32 3, i32 6>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <4 x i32> @vmovn32_b4(<4 x i32> %src1, <4 x i32> %src2) { define arm_aapcs_vfpcc <4 x i32> @vmovn32_b4(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: vmovn32_b4: ; CHECK-LABEL: vmovn32_b4:
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: vmovn16_b2: ; CHECK-LABEL: vmovn16_b2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s9, s5 ; CHECK-NEXT: vmovx.f16 s5, s5
; CHECK-NEXT: vins.f16 s9, s1 ; CHECK-NEXT: vmovx.f16 s4, s4
; CHECK-NEXT: vmovx.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s6, s6
; CHECK-NEXT: vins.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s7, s7
; CHECK-NEXT: vmovx.f16 s10, s6 ; CHECK-NEXT: vins.f16 s5, s1
; CHECK-NEXT: vins.f16 s10, s2 ; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s11, s7 ; CHECK-NEXT: vins.f16 s6, s2
; CHECK-NEXT: vins.f16 s11, s3 ; CHECK-NEXT: vins.f16 s7, s3
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECKBE-LABEL: vmovn16_b2: ; CHECKBE-LABEL: vmovn16_b2:
; CHECKBE: @ %bb.0: @ %entry ; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vrev64.16 q2, q0 ; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: vrev64.16 q0, q1 ; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: vmovx.f16 s5, s1 ; CHECKBE-NEXT: vmovx.f16 s5, s1
; CHECKBE-NEXT: vins.f16 s5, s9
; CHECKBE-NEXT: vmovx.f16 s4, s0 ; CHECKBE-NEXT: vmovx.f16 s4, s0
; CHECKBE-NEXT: vins.f16 s4, s8
; CHECKBE-NEXT: vmovx.f16 s6, s2 ; CHECKBE-NEXT: vmovx.f16 s6, s2
; CHECKBE-NEXT: vins.f16 s6, s10
; CHECKBE-NEXT: vmovx.f16 s7, s3 ; CHECKBE-NEXT: vmovx.f16 s7, s3
; CHECKBE-NEXT: vins.f16 s5, s9
; CHECKBE-NEXT: vins.f16 s4, s8
; CHECKBE-NEXT: vins.f16 s6, s10
; CHECKBE-NEXT: vins.f16 s7, s11 ; CHECKBE-NEXT: vins.f16 s7, s11
; CHECKBE-NEXT: vrev64.16 q0, q1 ; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr ; CHECKBE-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6>
ret <8 x i16> %out ret <8 x i16> %out
} }
define arm_aapcs_vfpcc <8 x i16> @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: vmovn16_b3: ; CHECK-LABEL: vmovn16_b3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmovx.f16 s1, s1
; CHECK-NEXT: vmovx.f16 s1, s9 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmovx.f16 s2, s2
; CHECK-NEXT: vmovx.f16 s3, s3
; CHECK-NEXT: vins.f16 s1, s5 ; CHECK-NEXT: vins.f16 s1, s5
; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vins.f16 s0, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s2, s10
; CHECK-NEXT: vins.f16 s2, s6 ; CHECK-NEXT: vins.f16 s2, s6
; CHECK-NEXT: vmovx.f16 s3, s11
; CHECK-NEXT: vins.f16 s3, s7 ; CHECK-NEXT: vins.f16 s3, s7
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECKBE-LABEL: vmovn16_b3: ; CHECKBE-LABEL: vmovn16_b3:
; CHECKBE: @ %bb.0: @ %entry ; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vrev64.16 q3, q0
; CHECKBE-NEXT: vrev64.16 q2, q1 ; CHECKBE-NEXT: vrev64.16 q2, q1
; CHECKBE-NEXT: vmovx.f16 s5, s13 ; CHECKBE-NEXT: vrev64.16 q1, q0
; CHECKBE-NEXT: vmovx.f16 s5, s5
; CHECKBE-NEXT: vmovx.f16 s4, s4
; CHECKBE-NEXT: vmovx.f16 s6, s6
; CHECKBE-NEXT: vmovx.f16 s7, s7
; CHECKBE-NEXT: vins.f16 s5, s9 ; CHECKBE-NEXT: vins.f16 s5, s9
; CHECKBE-NEXT: vmovx.f16 s4, s12
; CHECKBE-NEXT: vins.f16 s4, s8 ; CHECKBE-NEXT: vins.f16 s4, s8
; CHECKBE-NEXT: vmovx.f16 s6, s14
; CHECKBE-NEXT: vins.f16 s6, s10 ; CHECKBE-NEXT: vins.f16 s6, s10
; CHECKBE-NEXT: vmovx.f16 s7, s15
; CHECKBE-NEXT: vins.f16 s7, s11 ; CHECKBE-NEXT: vins.f16 s7, s11
; CHECKBE-NEXT: vrev64.16 q0, q1 ; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr ; CHECKBE-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
ret <8 x i16> %out ret <8 x i16> %out
} }
▲ Show 20 Lines • Show All 427 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Linesentry:
%out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3> %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 0, i32 3>
store <2 x i64> %out, <2 x i64> *%dest, align 8 store <2 x i64> %out, <2 x i64> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn64_b2(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { define arm_aapcs_vfpcc void @vmovn64_b2(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) {
; CHECK-LABEL: vmovn64_b2: ; CHECK-LABEL: vmovn64_b2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s6 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vmov.f32 s9, s7 ; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vmov.f32 s10, s0 ; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vmov.f32 s11, s1 ; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vstrw.32 q2, [r0] ; CHECK-NEXT: vstrw.32 q1, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 0> %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 3, i32 0>
store <2 x i64> %out, <2 x i64> *%dest, align 8 store <2 x i64> %out, <2 x i64> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn64_b3(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { define arm_aapcs_vfpcc void @vmovn64_b3(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) {
; CHECK-LABEL: vmovn64_b3: ; CHECK-LABEL: vmovn64_b3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s2 ; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vmov.f32 s9, s3 ; CHECK-NEXT: vmov.f32 s1, s3
; CHECK-NEXT: vmov.f32 s10, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s11, s5 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vstrw.32 q2, [r0] ; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 1, i32 2> %out = shufflevector <2 x i64> %src1, <2 x i64> %src2, <2 x i32> <i32 1, i32 2>
store <2 x i64> %out, <2 x i64> *%dest, align 8 store <2 x i64> %out, <2 x i64> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn64_b4(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) { define arm_aapcs_vfpcc void @vmovn64_b4(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) {
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Linesentry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 5, i32 2, i32 7> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
store <4 x i32> %out, <4 x i32> *%dest, align 8 store <4 x i32> %out, <4 x i32> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn32_b2(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { define arm_aapcs_vfpcc void @vmovn32_b2(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) {
; CHECK-LABEL: vmovn32_b2: ; CHECK-LABEL: vmovn32_b2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vmov.f32 s9, s0 ; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s5, s0
; CHECK-NEXT: vmov.f32 s11, s2 ; CHECK-NEXT: vmov.f32 s7, s2
; CHECK-NEXT: vstrw.32 q2, [r0] ; CHECK-NEXT: vstrw.32 q1, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 5, i32 0, i32 7, i32 2> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 5, i32 0, i32 7, i32 2>
store <4 x i32> %out, <4 x i32> *%dest, align 8 store <4 x i32> %out, <4 x i32> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn32_b3(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { define arm_aapcs_vfpcc void @vmovn32_b3(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) {
; CHECK-LABEL: vmovn32_b3: ; CHECK-LABEL: vmovn32_b3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s9, s4 ; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmov.f32 s10, s3 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.f32 s11, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vstrw.32 q2, [r0] ; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 1, i32 4, i32 3, i32 6> %out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 1, i32 4, i32 3, i32 6>
store <4 x i32> %out, <4 x i32> *%dest, align 8 store <4 x i32> %out, <4 x i32> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn32_b4(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) { define arm_aapcs_vfpcc void @vmovn32_b4(<4 x i32> %src1, <4 x i32> %src2, <4 x i32> *%dest) {
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesentry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
store <8 x i16> %out, <8 x i16> *%dest, align 8 store <8 x i16> %out, <8 x i16> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { define arm_aapcs_vfpcc void @vmovn16_b2(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) {
; CHECK-LABEL: vmovn16_b2: ; CHECK-LABEL: vmovn16_b2:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s9, s5 ; CHECK-NEXT: vmovx.f16 s5, s5
; CHECK-NEXT: vins.f16 s9, s1 ; CHECK-NEXT: vmovx.f16 s4, s4
; CHECK-NEXT: vmovx.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s6, s6
; CHECK-NEXT: vins.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s7, s7
; CHECK-NEXT: vmovx.f16 s10, s6 ; CHECK-NEXT: vins.f16 s5, s1
; CHECK-NEXT: vins.f16 s10, s2 ; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmovx.f16 s11, s7 ; CHECK-NEXT: vins.f16 s6, s2
; CHECK-NEXT: vins.f16 s11, s3 ; CHECK-NEXT: vins.f16 s7, s3
; CHECK-NEXT: vstrw.32 q2, [r0] ; CHECK-NEXT: vstrw.32 q1, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 9, i32 0, i32 11, i32 2, i32 13, i32 4, i32 15, i32 6>
store <8 x i16> %out, <8 x i16> *%dest, align 8 store <8 x i16> %out, <8 x i16> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { define arm_aapcs_vfpcc void @vmovn16_b3(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) {
; CHECK-LABEL: vmovn16_b3: ; CHECK-LABEL: vmovn16_b3:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s9, s1 ; CHECK-NEXT: vmovx.f16 s1, s1
; CHECK-NEXT: vins.f16 s9, s5 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s2, s2
; CHECK-NEXT: vins.f16 s8, s4 ; CHECK-NEXT: vmovx.f16 s3, s3
; CHECK-NEXT: vmovx.f16 s10, s2 ; CHECK-NEXT: vins.f16 s1, s5
; CHECK-NEXT: vins.f16 s10, s6 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s11, s3 ; CHECK-NEXT: vins.f16 s2, s6
; CHECK-NEXT: vins.f16 s11, s7 ; CHECK-NEXT: vins.f16 s3, s7
; CHECK-NEXT: vstrw.32 q2, [r0] ; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14> %out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
store <8 x i16> %out, <8 x i16> *%dest, align 8 store <8 x i16> %out, <8 x i16> *%dest, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) { define arm_aapcs_vfpcc void @vmovn16_b4(<8 x i16> %src1, <8 x i16> %src2, <8 x i16> *%dest) {
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Linesentry:
%shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer
%out = mul <2 x i64> %shuf2, %out1 %out = mul <2 x i64> %shuf2, %out1
ret <2 x i64> %out ret <2 x i64> %out
} }
define arm_aapcs_vfpcc <4 x i64> @sext32_0213_0ext(<8 x i32> %src1, i32 %src2) { define arm_aapcs_vfpcc <4 x i64> @sext32_0213_0ext(<8 x i32> %src1, i32 %src2) {
; CHECK-LABEL: sext32_0213_0ext: ; CHECK-LABEL: sext32_0213_0ext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vmov q3[2], q3[0], r0, r0 ; CHECK-NEXT: vmov q3[2], q3[0], r0, r0
; CHECK-NEXT: vmov.f32 s18, s3
; CHECK-NEXT: vmullb.s32 q2, q0, q3 ; CHECK-NEXT: vmullb.s32 q2, q0, q3
; CHECK-NEXT: vmullb.s32 q1, q4, q3 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmullb.s32 q1, q0, q3
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
%out1 = sext <4 x i32> %shuf1 to <4 x i64> %out1 = sext <4 x i32> %shuf1 to <4 x i64>
%ins = insertelement <8 x i32> poison, i32 %src2, i32 0 %ins = insertelement <8 x i32> poison, i32 %src2, i32 0
%shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer
%out2 = sext <4 x i32> %shuf2 to <4 x i64> %out2 = sext <4 x i32> %shuf2 to <4 x i64>
%out = mul <4 x i64> %out1, %out2 %out = mul <4 x i64> %out1, %out2
ret <4 x i64> %out ret <4 x i64> %out
} }
define arm_aapcs_vfpcc <4 x i64> @sext32_0ext_0213(<8 x i32> %src1, i32 %src2) { define arm_aapcs_vfpcc <4 x i64> @sext32_0ext_0213(<8 x i32> %src1, i32 %src2) {
; CHECK-LABEL: sext32_0ext_0213: ; CHECK-LABEL: sext32_0ext_0213:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vmov q3[2], q3[0], r0, r0 ; CHECK-NEXT: vmov q3[2], q3[0], r0, r0
; CHECK-NEXT: vmov.f32 s18, s3
; CHECK-NEXT: vmullb.s32 q2, q3, q0 ; CHECK-NEXT: vmullb.s32 q2, q3, q0
; CHECK-NEXT: vmullb.s32 q1, q3, q4 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmullb.s32 q1, q3, q0
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
%out1 = sext <4 x i32> %shuf1 to <4 x i64> %out1 = sext <4 x i32> %shuf1 to <4 x i64>
%ins = insertelement <8 x i32> poison, i32 %src2, i32 0 %ins = insertelement <8 x i32> poison, i32 %src2, i32 0
%shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer
%out2 = sext <4 x i32> %shuf2 to <4 x i64> %out2 = sext <4 x i32> %shuf2 to <4 x i64>
%out = mul <4 x i64> %out2, %out1 %out = mul <4 x i64> %out2, %out1
ret <4 x i64> %out ret <4 x i64> %out
} }
define arm_aapcs_vfpcc <4 x i64> @sext32_0213_ext0(<8 x i32> %src1, i32 %src2) { define arm_aapcs_vfpcc <4 x i64> @sext32_0213_ext0(<8 x i32> %src1, i32 %src2) {
; CHECK-LABEL: sext32_0213_ext0: ; CHECK-LABEL: sext32_0213_ext0:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: umull lr, r12, r1, r0 ; CHECK-NEXT: umull lr, r12, r1, r0
; CHECK-NEXT: umull r2, r5, r3, r0 ; CHECK-NEXT: umull r2, r5, r3, r0
; CHECK-NEXT: vmov q0[2], q0[0], r2, lr ; CHECK-NEXT: vmov q0[2], q0[0], r2, lr
; CHECK-NEXT: asrs r2, r0, #31 ; CHECK-NEXT: asrs r2, r0, #31
; CHECK-NEXT: mla r4, r1, r2, r12 ; CHECK-NEXT: mla r4, r1, r2, r12
; CHECK-NEXT: asrs r1, r1, #31 ; CHECK-NEXT: asrs r1, r1, #31
; CHECK-NEXT: mla r5, r3, r2, r5 ; CHECK-NEXT: mla r5, r3, r2, r5
; CHECK-NEXT: asrs r3, r3, #31 ; CHECK-NEXT: asrs r3, r3, #31
; CHECK-NEXT: mla r1, r1, r0, r4 ; CHECK-NEXT: mla r1, r1, r0, r4
; CHECK-NEXT: vmov r4, s8 ; CHECK-NEXT: vmov r4, s4
; CHECK-NEXT: mla r3, r3, r0, r5 ; CHECK-NEXT: mla r3, r3, r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r3, r1 ; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
; CHECK-NEXT: vmov r1, s10 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: umull r5, lr, r4, r0 ; CHECK-NEXT: umull r5, lr, r4, r0
; CHECK-NEXT: umull r3, r12, r1, r0 ; CHECK-NEXT: umull r3, r12, r1, r0
; CHECK-NEXT: vmov q1[2], q1[0], r5, r3 ; CHECK-NEXT: vmov q1[2], q1[0], r5, r3
; CHECK-NEXT: mla r3, r1, r2, r12 ; CHECK-NEXT: mla r3, r1, r2, r12
; CHECK-NEXT: asrs r1, r1, #31 ; CHECK-NEXT: asrs r1, r1, #31
; CHECK-NEXT: mla r2, r4, r2, lr ; CHECK-NEXT: mla r2, r4, r2, lr
; CHECK-NEXT: mla r1, r1, r0, r3 ; CHECK-NEXT: mla r1, r1, r0, r3
; CHECK-NEXT: asrs r3, r4, #31 ; CHECK-NEXT: asrs r3, r4, #31
Show All 14 Lines
; CHECK-LABEL: sext32_ext0_0213: ; CHECK-LABEL: sext32_ext0_0213:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: asrs r4, r0, #31 ; CHECK-NEXT: asrs r4, r0, #31
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s6, s7
; CHECK-NEXT: umull lr, r12, r0, r1 ; CHECK-NEXT: umull lr, r12, r0, r1
; CHECK-NEXT: umull r2, r5, r0, r3 ; CHECK-NEXT: umull r2, r5, r0, r3
; CHECK-NEXT: vmov q0[2], q0[0], r2, lr ; CHECK-NEXT: vmov q0[2], q0[0], r2, lr
; CHECK-NEXT: asrs r2, r1, #31 ; CHECK-NEXT: asrs r2, r1, #31
; CHECK-NEXT: mla r2, r0, r2, r12 ; CHECK-NEXT: mla r2, r0, r2, r12
; CHECK-NEXT: mla r1, r4, r1, r2 ; CHECK-NEXT: mla r1, r4, r1, r2
; CHECK-NEXT: asrs r2, r3, #31 ; CHECK-NEXT: asrs r2, r3, #31
; CHECK-NEXT: mla r2, r0, r2, r5 ; CHECK-NEXT: mla r2, r0, r2, r5
; CHECK-NEXT: vmov r5, s8 ; CHECK-NEXT: vmov r5, s4
; CHECK-NEXT: mla r2, r4, r3, r2 ; CHECK-NEXT: mla r2, r4, r3, r2
; CHECK-NEXT: vmov q0[3], q0[1], r2, r1 ; CHECK-NEXT: vmov q0[3], q0[1], r2, r1
; CHECK-NEXT: vmov r1, s10 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: umull r3, lr, r0, r5 ; CHECK-NEXT: umull r3, lr, r0, r5
; CHECK-NEXT: umull r2, r12, r0, r1 ; CHECK-NEXT: umull r2, r12, r0, r1
; CHECK-NEXT: vmov q1[2], q1[0], r3, r2 ; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
; CHECK-NEXT: asrs r2, r1, #31 ; CHECK-NEXT: asrs r2, r1, #31
; CHECK-NEXT: mla r2, r0, r2, r12 ; CHECK-NEXT: mla r2, r0, r2, r12
; CHECK-NEXT: mla r1, r4, r1, r2 ; CHECK-NEXT: mla r1, r4, r1, r2
; CHECK-NEXT: asrs r2, r5, #31 ; CHECK-NEXT: asrs r2, r5, #31
; CHECK-NEXT: mla r0, r0, r2, lr ; CHECK-NEXT: mla r0, r0, r2, lr
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Linesentry:
%shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer %shuf2 = shufflevector <2 x i64> %ins, <2 x i64> undef, <2 x i32> zeroinitializer
%out = mul <2 x i64> %shuf2, %out1 %out = mul <2 x i64> %shuf2, %out1
ret <2 x i64> %out ret <2 x i64> %out
} }
define arm_aapcs_vfpcc <4 x i64> @zext32_0213_0ext(<8 x i32> %src1, i32 %src2) { define arm_aapcs_vfpcc <4 x i64> @zext32_0213_0ext(<8 x i32> %src1, i32 %src2) {
; CHECK-LABEL: zext32_0213_0ext: ; CHECK-LABEL: zext32_0213_0ext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vmov q3[2], q3[0], r0, r0 ; CHECK-NEXT: vmov q3[2], q3[0], r0, r0
; CHECK-NEXT: vmov.f32 s18, s3
; CHECK-NEXT: vmullb.u32 q2, q0, q3 ; CHECK-NEXT: vmullb.u32 q2, q0, q3
; CHECK-NEXT: vmullb.u32 q1, q4, q3 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmullb.u32 q1, q0, q3
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
%out1 = zext <4 x i32> %shuf1 to <4 x i64> %out1 = zext <4 x i32> %shuf1 to <4 x i64>
%ins = insertelement <8 x i32> poison, i32 %src2, i32 0 %ins = insertelement <8 x i32> poison, i32 %src2, i32 0
%shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer
%out2 = zext <4 x i32> %shuf2 to <4 x i64> %out2 = zext <4 x i32> %shuf2 to <4 x i64>
%out = mul <4 x i64> %out1, %out2 %out = mul <4 x i64> %out1, %out2
ret <4 x i64> %out ret <4 x i64> %out
} }
define arm_aapcs_vfpcc <4 x i64> @zext32_0ext_0213(<8 x i32> %src1, i32 %src2) { define arm_aapcs_vfpcc <4 x i64> @zext32_0ext_0213(<8 x i32> %src1, i32 %src2) {
; CHECK-LABEL: zext32_0ext_0213: ; CHECK-LABEL: zext32_0ext_0213:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vmov q3[2], q3[0], r0, r0 ; CHECK-NEXT: vmov q3[2], q3[0], r0, r0
; CHECK-NEXT: vmov.f32 s18, s3
; CHECK-NEXT: vmullb.u32 q2, q3, q0 ; CHECK-NEXT: vmullb.u32 q2, q3, q0
; CHECK-NEXT: vmullb.u32 q1, q3, q4 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: vmullb.u32 q1, q3, q0
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
%out1 = zext <4 x i32> %shuf1 to <4 x i64> %out1 = zext <4 x i32> %shuf1 to <4 x i64>
%ins = insertelement <8 x i32> poison, i32 %src2, i32 0 %ins = insertelement <8 x i32> poison, i32 %src2, i32 0
%shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer %shuf2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <4 x i32> zeroinitializer
%out2 = zext <4 x i32> %shuf2 to <4 x i64> %out2 = zext <4 x i32> %shuf2 to <4 x i64>
%out = mul <4 x i64> %out2, %out1 %out = mul <4 x i64> %out2, %out1
ret <4 x i64> %out ret <4 x i64> %out
} }
define arm_aapcs_vfpcc <4 x i64> @zext32_0213_ext0(<8 x i32> %src1, i32 %src2) { define arm_aapcs_vfpcc <4 x i64> @zext32_0213_ext0(<8 x i32> %src1, i32 %src2) {
; CHECK-LABEL: zext32_0213_ext0: ; CHECK-LABEL: zext32_0213_ext0:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov.f32 s4, s1 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s6, s3 ; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: umull r1, r12, r1, r0 ; CHECK-NEXT: umull r1, r12, r1, r0
; CHECK-NEXT: umull r3, r2, r3, r0 ; CHECK-NEXT: umull r3, r2, r3, r0
; CHECK-NEXT: vmov q2[2], q2[0], r3, r1 ; CHECK-NEXT: vmov q2[2], q2[0], r3, r1
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov q2[3], q2[1], r2, r12 ; CHECK-NEXT: vmov q2[3], q2[1], r2, r12
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: umull r1, r2, r1, r0 ; CHECK-NEXT: umull r1, r2, r1, r0
; CHECK-NEXT: umull r0, r3, r3, r0 ; CHECK-NEXT: umull r0, r3, r3, r0
; CHECK-NEXT: vmov q1[2], q1[0], r0, r1 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r1
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2 ; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %shuf1 = shufflevector <8 x i32> %src1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
%out1 = zext <4 x i32> %shuf1 to <4 x i64> %out1 = zext <4 x i32> %shuf1 to <4 x i64>
%ext = zext i32 %src2 to i64 %ext = zext i32 %src2 to i64
%ins = insertelement <4 x i64> poison, i64 %ext, i32 0 %ins = insertelement <4 x i64> poison, i64 %ext, i32 0
%shuf2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %shuf2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer
%out = mul <4 x i64> %out1, %shuf2 %out = mul <4 x i64> %out1, %shuf2
ret <4 x i64> %out ret <4 x i64> %out
} }
define arm_aapcs_vfpcc <4 x i64> @zext32_ext0_0213(<8 x i32> %src1, i32 %src2) { define arm_aapcs_vfpcc <4 x i64> @zext32_ext0_0213(<8 x i32> %src1, i32 %src2) {
; CHECK-LABEL: zext32_ext0_0213: ; CHECK-LABEL: zext32_ext0_0213:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov.f32 s4, s1 ; CHECK-NEXT: vmov.f32 s0, s1
; CHECK-NEXT: vmov.f32 s6, s3 ; CHECK-NEXT: vmov.f32 s2, s3
; CHECK-NEXT: umull r1, r12, r0, r1 ; CHECK-NEXT: umull r1, r12, r0, r1
; CHECK-NEXT: umull r3, r2, r0, r3 ; CHECK-NEXT: umull r3, r2, r0, r3
; CHECK-NEXT: vmov q2[2], q2[0], r3, r1 ; CHECK-NEXT: vmov q2[2], q2[0], r3, r1
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov q2[3], q2[1], r2, r12 ; CHECK-NEXT: vmov q2[3], q2[1], r2, r12
; CHECK-NEXT: vmov q0, q2 ; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: umull r1, r2, r0, r1 ; CHECK-NEXT: umull r1, r2, r0, r1
; CHECK-NEXT: umull r0, r3, r0, r3 ; CHECK-NEXT: umull r0, r3, r0, r3
; CHECK-NEXT: vmov q1[2], q1[0], r0, r1 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r1
; CHECK-NEXT: vmov q1[3], q1[1], r3, r2 ; CHECK-NEXT: vmov q1[3], q1[1], r3, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
▲ Show 20 Lines • Show All 848 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vst2-post.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Linesentry:
ret <32 x i8> *%ret ret <32 x i8> *%ret
} }
; i64 ; i64
define <4 x i64> *@vst2_v2i64(<2 x i64> *%src, <4 x i64> *%dst) { define <4 x i64> *@vst2_v2i64(<2 x i64> *%src, <4 x i64> *%dst) {
; CHECK-LABEL: vst2_v2i64: ; CHECK-LABEL: vst2_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: add.w r0, r1, #32 ; CHECK-NEXT: add.w r0, r1, #32
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f32 s9, s3 ; CHECK-NEXT: vmov.f32 s9, s3
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.f32 s11, s7 ; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vstrb.8 q0, [r1], #16 ; CHECK-NEXT: vstrb.8 q0, [r1], #16
; CHECK-NEXT: vmov.f32 s11, s7
; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q2, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0 %s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0
%l1 = load <2 x i64>, <2 x i64>* %s1, align 4 %l1 = load <2 x i64>, <2 x i64>* %s1, align 4
%s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1 %s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1
%l2 = load <2 x i64>, <2 x i64>* %s2, align 4 %l2 = load <2 x i64>, <2 x i64>* %s2, align 4
%s = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %s = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesentry:
ret <16 x half> *%ret ret <16 x half> *%ret
} }
; f64 ; f64
define <4 x double> *@vst2_v2f64(<2 x double> *%src, <4 x double> *%dst) { define <4 x double> *@vst2_v2f64(<2 x double> *%src, <4 x double> *%dst) {
; CHECK-LABEL: vst2_v2f64: ; CHECK-LABEL: vst2_v2f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov.f64 d4, d2 ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f64 d5, d0 ; CHECK-NEXT: vmov.f64 d5, d0
; CHECK-NEXT: vmov.f64 d0, d3 ; CHECK-NEXT: vmov.f64 d0, d3
; CHECK-NEXT: vmov.f64 d4, d2
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vstrw.32 q2, [r1], #32 ; CHECK-NEXT: vstrw.32 q2, [r1], #32
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x double>, <2 x double>* %src, i32 0 %s1 = getelementptr <2 x double>, <2 x double>* %src, i32 0
%l1 = load <2 x double>, <2 x double>* %s1, align 4 %l1 = load <2 x double>, <2 x double>* %s1, align 4
%s2 = getelementptr <2 x double>, <2 x double>* %src, i32 1 %s2 = getelementptr <2 x double>, <2 x double>* %src, i32 1
%l2 = load <2 x double>, <2 x double>* %s2, align 4 %l2 = load <2 x double>, <2 x double>* %s2, align 4
%s = shufflevector <2 x double> %l1, <2 x double> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %s = shufflevector <2 x double> %l1, <2 x double> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
store <4 x double> %s, <4 x double> *%dst store <4 x double> %s, <4 x double> *%dst
%ret = getelementptr inbounds <4 x double>, <4 x double>* %dst, i32 1 %ret = getelementptr inbounds <4 x double>, <4 x double>* %dst, i32 1
ret <4 x double> *%ret ret <4 x double> *%ret
} }

llvm/test/CodeGen/Thumb2/mve-vst2.ll

Show All 38 Linesentry:
store <8 x i32> %s, <8 x i32> *%dst, align 4 store <8 x i32> %s, <8 x i32> *%dst, align 4
ret void ret void
} }
define void @vst2_v8i32(<8 x i32> *%src, <16 x i32> *%dst) { define void @vst2_v8i32(<8 x i32> *%src, <16 x i32> *%dst) {
; CHECK-LABEL: vst2_v8i32: ; CHECK-LABEL: vst2_v8i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vst20.32 {q0, q1}, [r1] ; CHECK-NEXT: vst20.32 {q0, q1}, [r1]
; CHECK-NEXT: vst21.32 {q0, q1}, [r1]! ; CHECK-NEXT: vst21.32 {q0, q1}, [r1]!
; CHECK-NEXT: vst20.32 {q2, q3}, [r1] ; CHECK-NEXT: vst20.32 {q2, q3}, [r1]
; CHECK-NEXT: vst21.32 {q2, q3}, [r1] ; CHECK-NEXT: vst21.32 {q2, q3}, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i32>, <8 x i32>* %src, i32 0 %s1 = getelementptr <8 x i32>, <8 x i32>* %src, i32 0
%l1 = load <8 x i32>, <8 x i32>* %s1, align 4 %l1 = load <8 x i32>, <8 x i32>* %s1, align 4
%s2 = getelementptr <8 x i32>, <8 x i32>* %src, i32 1 %s2 = getelementptr <8 x i32>, <8 x i32>* %src, i32 1
%l2 = load <8 x i32>, <8 x i32>* %s2, align 4 %l2 = load <8 x i32>, <8 x i32>* %s2, align 4
%s = shufflevector <8 x i32> %l1, <8 x i32> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %s = shufflevector <8 x i32> %l1, <8 x i32> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
store <16 x i32> %s, <16 x i32> *%dst, align 4 store <16 x i32> %s, <16 x i32> *%dst, align 4
ret void ret void
} }
define void @vst2_v16i32(<16 x i32> *%src, <32 x i32> *%dst) { define void @vst2_v16i32(<16 x i32> *%src, <32 x i32> *%dst) {
; CHECK-LABEL: vst2_v16i32: ; CHECK-LABEL: vst2_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q7, [r0, #64] ; CHECK-NEXT: vldrw.u32 q7, [r0, #64]
; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #112] ; CHECK-NEXT: vldrw.u32 q1, [r0, #112]
; CHECK-NEXT: vldrw.u32 q3, [r0, #96] ; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
; CHECK-NEXT: vldrw.u32 q5, [r0, #80] ; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16] ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: add.w r0, r1, #96 ; CHECK-NEXT: add.w r0, r1, #96
; CHECK-NEXT: add.w r2, r1, #64 ; CHECK-NEXT: add.w r2, r1, #64
; CHECK-NEXT: vst20.32 {q6, q7}, [r1] ; CHECK-NEXT: vst20.32 {q6, q7}, [r1]
; CHECK-NEXT: vst21.32 {q6, q7}, [r1]! ; CHECK-NEXT: vst21.32 {q6, q7}, [r1]!
; CHECK-NEXT: vst20.32 {q4, q5}, [r1] ; CHECK-NEXT: vst20.32 {q4, q5}, [r1]
Show All 12 Linesentry:
%s = shufflevector <16 x i32> %l1, <16 x i32> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %s = shufflevector <16 x i32> %l1, <16 x i32> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
store <32 x i32> %s, <32 x i32> *%dst, align 4 store <32 x i32> %s, <32 x i32> *%dst, align 4
ret void ret void
} }
define void @vst2_v4i32_align1(<4 x i32> *%src, <8 x i32> *%dst) { define void @vst2_v4i32_align1(<4 x i32> *%src, <8 x i32> *%dst) {
; CHECK-LABEL: vst2_v4i32_align1: ; CHECK-LABEL: vst2_v4i32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov.f64 d4, d3 ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f64 d6, d2 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s9, s2 ; CHECK-NEXT: vmov.f32 s9, s2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov.f32 s11, s3 ; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov.f32 s15, s1 ; CHECK-NEXT: vmov.f32 s12, s4
; CHECK-NEXT: vstrb.8 q2, [r1, #16] ; CHECK-NEXT: vstrb.8 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov.f32 s15, s1
; CHECK-NEXT: vstrb.8 q3, [r1] ; CHECK-NEXT: vstrb.8 q3, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0 %s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0
%l1 = load <4 x i32>, <4 x i32>* %s1, align 4 %l1 = load <4 x i32>, <4 x i32>* %s1, align 4
%s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1 %s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1
%l2 = load <4 x i32>, <4 x i32>* %s2, align 4 %l2 = load <4 x i32>, <4 x i32>* %s2, align 4
%s = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %s = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Linesentry:
store <16 x i16> %s, <16 x i16> *%dst, align 2 store <16 x i16> %s, <16 x i16> *%dst, align 2
ret void ret void
} }
define void @vst2_v16i16(<16 x i16> *%src, <32 x i16> *%dst) { define void @vst2_v16i16(<16 x i16> *%src, <32 x i16> *%dst) {
; CHECK-LABEL: vst2_v16i16: ; CHECK-LABEL: vst2_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vst20.16 {q0, q1}, [r1] ; CHECK-NEXT: vst20.16 {q0, q1}, [r1]
; CHECK-NEXT: vst21.16 {q0, q1}, [r1]! ; CHECK-NEXT: vst21.16 {q0, q1}, [r1]!
; CHECK-NEXT: vst20.16 {q2, q3}, [r1] ; CHECK-NEXT: vst20.16 {q2, q3}, [r1]
; CHECK-NEXT: vst21.16 {q2, q3}, [r1] ; CHECK-NEXT: vst21.16 {q2, q3}, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x i16>, <16 x i16>* %src, i32 0 %s1 = getelementptr <16 x i16>, <16 x i16>* %src, i32 0
%l1 = load <16 x i16>, <16 x i16>* %s1, align 4 %l1 = load <16 x i16>, <16 x i16>* %s1, align 4
%s2 = getelementptr <16 x i16>, <16 x i16>* %src, i32 1 %s2 = getelementptr <16 x i16>, <16 x i16>* %src, i32 1
%l2 = load <16 x i16>, <16 x i16>* %s2, align 4 %l2 = load <16 x i16>, <16 x i16>* %s2, align 4
%s = shufflevector <16 x i16> %l1, <16 x i16> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %s = shufflevector <16 x i16> %l1, <16 x i16> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
store <32 x i16> %s, <32 x i16> *%dst, align 2 store <32 x i16> %s, <32 x i16> *%dst, align 2
ret void ret void
} }
define void @vst2_v8i16_align1(<8 x i16> *%src, <16 x i16> *%dst) { define void @vst2_v8i16_align1(<8 x i16> *%src, <16 x i16> *%dst) {
; CHECK-LABEL: vst2_v8i16_align1: ; CHECK-LABEL: vst2_v8i16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmovx.f16 s1, s10 ; CHECK-NEXT: vmovx.f16 s1, s10
; CHECK-NEXT: vmovx.f16 s12, s6 ; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vins.f16 s1, s12
; CHECK-NEXT: vins.f16 s10, s6 ; CHECK-NEXT: vins.f16 s10, s6
; CHECK-NEXT: vmov.f32 s0, s10
; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vmovx.f16 s3, s11 ; CHECK-NEXT: vmovx.f16 s3, s11
; CHECK-NEXT: vmovx.f16 s6, s7
; CHECK-NEXT: vins.f16 s11, s7 ; CHECK-NEXT: vins.f16 s11, s7
; CHECK-NEXT: vmov.f32 s2, s11 ; CHECK-NEXT: vins.f16 s3, s6
; CHECK-NEXT: vmovx.f16 s14, s4 ; CHECK-NEXT: vmovx.f16 s6, s8
; CHECK-NEXT: vins.f16 s3, s12
; CHECK-NEXT: vmovx.f16 s12, s8
; CHECK-NEXT: vins.f16 s8, s4 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vins.f16 s12, s14 ; CHECK-NEXT: vmovx.f16 s4, s4
; CHECK-NEXT: vmov q4, q2 ; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vins.f16 s6, s4
; CHECK-NEXT: vmovx.f16 s15, s9
; CHECK-NEXT: vins.f16 s9, s5
; CHECK-NEXT: vmovx.f16 s4, s5 ; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vmov.f32 s17, s12 ; CHECK-NEXT: vins.f16 s1, s0
; CHECK-NEXT: vmov.f32 s0, s10
; CHECK-NEXT: vins.f16 s15, s4
; CHECK-NEXT: vmov.f32 s2, s11
; CHECK-NEXT: vmov.f32 s13, s6
; CHECK-NEXT: vstrb.8 q0, [r1, #16] ; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vmovx.f16 s19, s9 ; CHECK-NEXT: vmov.f32 s14, s9
; CHECK-NEXT: vins.f16 s9, s5 ; CHECK-NEXT: vstrb.8 q3, [r1]
; CHECK-NEXT: vmov.f32 s18, s9
; CHECK-NEXT: vins.f16 s19, s4
; CHECK-NEXT: vstrb.8 q4, [r1]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0 %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
%l1 = load <8 x i16>, <8 x i16>* %s1, align 4 %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
%s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1 %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
%l2 = load <8 x i16>, <8 x i16>* %s2, align 4 %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
%s = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %s = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
store <16 x i16> %s, <16 x i16> *%dst, align 1 store <16 x i16> %s, <16 x i16> *%dst, align 1
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; i64 ; i64
define void @vst2_v2i64(<2 x i64> *%src, <4 x i64> *%dst) { define void @vst2_v2i64(<2 x i64> *%src, <4 x i64> *%dst) {
; CHECK-LABEL: vst2_v2i64: ; CHECK-LABEL: vst2_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov.f64 d4, d2 ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov.f32 s10, s0 ; CHECK-NEXT: vmov.f32 s10, s0
; CHECK-NEXT: vmov.f32 s11, s1 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vstrb.8 q2, [r1], #16 ; CHECK-NEXT: vstrb.8 q2, [r1], #16
; CHECK-NEXT: vmov.f32 s1, s7 ; CHECK-NEXT: vmov.f32 s1, s7
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0 %s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0
%l1 = load <2 x i64>, <2 x i64>* %s1, align 4 %l1 = load <2 x i64>, <2 x i64>* %s1, align 4
%s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1 %s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1
%l2 = load <2 x i64>, <2 x i64>* %s2, align 4 %l2 = load <2 x i64>, <2 x i64>* %s2, align 4
%s = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %s = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
store <4 x i64> %s, <4 x i64> *%dst, align 8 store <4 x i64> %s, <4 x i64> *%dst, align 8
ret void ret void
} }
define void @vst2_v4i64(<4 x i64> *%src, <8 x i64> *%dst) { define void @vst2_v4i64(<4 x i64> *%src, <8 x i64> *%dst) {
; CHECK-LABEL: vst2_v4i64: ; CHECK-LABEL: vst2_v4i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #48] ; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vmov.f64 d6, d1 ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f64 d10, d3 ; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov.f32 s13, s3 ; CHECK-NEXT: vmov.f32 s13, s3
; CHECK-NEXT: vmov.f32 s20, s6
; CHECK-NEXT: vmov.f32 s21, s7 ; CHECK-NEXT: vmov.f32 s21, s7
; CHECK-NEXT: vmov.f32 s2, s16 ; CHECK-NEXT: vmov.f32 s2, s16
; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vmov.f32 s3, s17 ; CHECK-NEXT: vmov.f32 s3, s17
; CHECK-NEXT: vmov.f32 s7, s9 ; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vstrw.32 q0, [r1, #32] ; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vmov.f32 s15, s19 ; CHECK-NEXT: vmov.f32 s7, s9
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vstrb.8 q1, [r1], #48 ; CHECK-NEXT: vstrb.8 q1, [r1], #48
; CHECK-NEXT: vmov.f32 s23, s11 ; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.f32 s22, s10
; CHECK-NEXT: vstrw.32 q3, [r1] ; CHECK-NEXT: vstrw.32 q3, [r1]
; CHECK-NEXT: vmov.f32 s23, s11
; CHECK-NEXT: vstrw.32 q5, [r1, #-32] ; CHECK-NEXT: vstrw.32 q5, [r1, #-32]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x i64>, <4 x i64>* %src, i32 0 %s1 = getelementptr <4 x i64>, <4 x i64>* %src, i32 0
%l1 = load <4 x i64>, <4 x i64>* %s1, align 4 %l1 = load <4 x i64>, <4 x i64>* %s1, align 4
%s2 = getelementptr <4 x i64>, <4 x i64>* %src, i32 1 %s2 = getelementptr <4 x i64>, <4 x i64>* %src, i32 1
%l2 = load <4 x i64>, <4 x i64>* %s2, align 4 %l2 = load <4 x i64>, <4 x i64>* %s2, align 4
Show All 40 Linesentry:
store <8 x float> %s, <8 x float> *%dst, align 4 store <8 x float> %s, <8 x float> *%dst, align 4
ret void ret void
} }
define void @vst2_v8f32(<8 x float> *%src, <16 x float> *%dst) { define void @vst2_v8f32(<8 x float> *%src, <16 x float> *%dst) {
; CHECK-LABEL: vst2_v8f32: ; CHECK-LABEL: vst2_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vst20.32 {q0, q1}, [r1] ; CHECK-NEXT: vst20.32 {q0, q1}, [r1]
; CHECK-NEXT: vst21.32 {q0, q1}, [r1]! ; CHECK-NEXT: vst21.32 {q0, q1}, [r1]!
; CHECK-NEXT: vst20.32 {q2, q3}, [r1] ; CHECK-NEXT: vst20.32 {q2, q3}, [r1]
; CHECK-NEXT: vst21.32 {q2, q3}, [r1] ; CHECK-NEXT: vst21.32 {q2, q3}, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x float>, <8 x float>* %src, i32 0 %s1 = getelementptr <8 x float>, <8 x float>* %src, i32 0
%l1 = load <8 x float>, <8 x float>* %s1, align 4 %l1 = load <8 x float>, <8 x float>* %s1, align 4
%s2 = getelementptr <8 x float>, <8 x float>* %src, i32 1 %s2 = getelementptr <8 x float>, <8 x float>* %src, i32 1
%l2 = load <8 x float>, <8 x float>* %s2, align 4 %l2 = load <8 x float>, <8 x float>* %s2, align 4
%s = shufflevector <8 x float> %l1, <8 x float> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %s = shufflevector <8 x float> %l1, <8 x float> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
store <16 x float> %s, <16 x float> *%dst, align 4 store <16 x float> %s, <16 x float> *%dst, align 4
ret void ret void
} }
define void @vst2_v16f32(<16 x float> *%src, <32 x float> *%dst) { define void @vst2_v16f32(<16 x float> *%src, <32 x float> *%dst) {
; CHECK-LABEL: vst2_v16f32: ; CHECK-LABEL: vst2_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q7, [r0, #64] ; CHECK-NEXT: vldrw.u32 q7, [r0, #64]
; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #112] ; CHECK-NEXT: vldrw.u32 q1, [r0, #112]
; CHECK-NEXT: vldrw.u32 q3, [r0, #96] ; CHECK-NEXT: vldrw.u32 q3, [r0, #96]
; CHECK-NEXT: vldrw.u32 q5, [r0, #80] ; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16] ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: add.w r0, r1, #96 ; CHECK-NEXT: add.w r0, r1, #96
; CHECK-NEXT: add.w r2, r1, #64 ; CHECK-NEXT: add.w r2, r1, #64
; CHECK-NEXT: vst20.32 {q6, q7}, [r1] ; CHECK-NEXT: vst20.32 {q6, q7}, [r1]
; CHECK-NEXT: vst21.32 {q6, q7}, [r1]! ; CHECK-NEXT: vst21.32 {q6, q7}, [r1]!
; CHECK-NEXT: vst20.32 {q4, q5}, [r1] ; CHECK-NEXT: vst20.32 {q4, q5}, [r1]
Show All 12 Linesentry:
%s = shufflevector <16 x float> %l1, <16 x float> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %s = shufflevector <16 x float> %l1, <16 x float> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
store <32 x float> %s, <32 x float> *%dst, align 4 store <32 x float> %s, <32 x float> *%dst, align 4
ret void ret void
} }
define void @vst2_v4f32_align1(<4 x float> *%src, <8 x float> *%dst) { define void @vst2_v4f32_align1(<4 x float> *%src, <8 x float> *%dst) {
; CHECK-LABEL: vst2_v4f32_align1: ; CHECK-LABEL: vst2_v4f32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov.f64 d4, d3 ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f64 d6, d2 ; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s9, s2 ; CHECK-NEXT: vmov.f32 s9, s2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov.f32 s11, s3 ; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov.f32 s15, s1 ; CHECK-NEXT: vmov.f32 s12, s4
; CHECK-NEXT: vstrb.8 q2, [r1, #16] ; CHECK-NEXT: vstrb.8 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov.f32 s15, s1
; CHECK-NEXT: vstrb.8 q3, [r1] ; CHECK-NEXT: vstrb.8 q3, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0 %s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0
%l1 = load <4 x float>, <4 x float>* %s1, align 4 %l1 = load <4 x float>, <4 x float>* %s1, align 4
%s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1 %s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1
%l2 = load <4 x float>, <4 x float>* %s2, align 4 %l2 = load <4 x float>, <4 x float>* %s2, align 4
%s = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %s = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
Show All 31 Lines
; CHECK-LABEL: vst2_v4f16: ; CHECK-LABEL: vst2_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r2, r12, [r0] ; CHECK-NEXT: ldrd r2, r12, [r0]
; CHECK-NEXT: ldrd r3, r0, [r0, #8] ; CHECK-NEXT: ldrd r3, r0, [r0, #8]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: vmov.32 q1[0], r3 ; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: vmov.32 q0[1], r12 ; CHECK-NEXT: vmov.32 q0[1], r12
; CHECK-NEXT: vmov.32 q1[1], r0 ; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s2, s0
; CHECK-NEXT: vmovx.f16 s10, s4
; CHECK-NEXT: vins.f16 s0, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vins.f16 s8, s10 ; CHECK-NEXT: vmovx.f16 s4, s4
; CHECK-NEXT: vmovx.f16 s10, s1 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s5 ; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vins.f16 s1, s5 ; CHECK-NEXT: vins.f16 s1, s5
; CHECK-NEXT: vins.f16 s10, s4 ; CHECK-NEXT: vmovx.f16 s6, s5
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vmov.f32 s5, s8 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmov.f32 s6, s1 ; CHECK-NEXT: vmov.f32 s9, s2
; CHECK-NEXT: vmov.f32 s7, s10 ; CHECK-NEXT: vmov.f32 s10, s1
; CHECK-NEXT: vstrh.16 q1, [r1] ; CHECK-NEXT: vmov.f32 s11, s4
; CHECK-NEXT: vstrh.16 q2, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0 %s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
%l1 = load <4 x half>, <4 x half>* %s1, align 4 %l1 = load <4 x half>, <4 x half>* %s1, align 4
%s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1 %s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1
%l2 = load <4 x half>, <4 x half>* %s2, align 4 %l2 = load <4 x half>, <4 x half>* %s2, align 4
%s = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %s = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x half> %s, <8 x half> *%dst, align 2 store <8 x half> %s, <8 x half> *%dst, align 2
Show All 17 Linesentry:
store <16 x half> %s, <16 x half> *%dst, align 2 store <16 x half> %s, <16 x half> *%dst, align 2
ret void ret void
} }
define void @vst2_v16f16(<16 x half> *%src, <32 x half> *%dst) { define void @vst2_v16f16(<16 x half> *%src, <32 x half> *%dst) {
; CHECK-LABEL: vst2_v16f16: ; CHECK-LABEL: vst2_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vst20.16 {q2, q3}, [r1] ; CHECK-NEXT: vst20.16 {q2, q3}, [r1]
; CHECK-NEXT: vst21.16 {q2, q3}, [r1]! ; CHECK-NEXT: vst21.16 {q2, q3}, [r1]!
; CHECK-NEXT: vst20.16 {q0, q1}, [r1] ; CHECK-NEXT: vst20.16 {q0, q1}, [r1]
; CHECK-NEXT: vst21.16 {q0, q1}, [r1] ; CHECK-NEXT: vst21.16 {q0, q1}, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0 %s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0
%l1 = load <16 x half>, <16 x half>* %s1, align 4 %l1 = load <16 x half>, <16 x half>* %s1, align 4
%s2 = getelementptr <16 x half>, <16 x half>* %src, i32 1 %s2 = getelementptr <16 x half>, <16 x half>* %src, i32 1
%l2 = load <16 x half>, <16 x half>* %s2, align 4 %l2 = load <16 x half>, <16 x half>* %s2, align 4
%s = shufflevector <16 x half> %l1, <16 x half> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %s = shufflevector <16 x half> %l1, <16 x half> %l2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
store <32 x half> %s, <32 x half> *%dst, align 2 store <32 x half> %s, <32 x half> *%dst, align 2
ret void ret void
} }
define void @vst2_v8f16_align1(<8 x half> *%src, <16 x half> *%dst) { define void @vst2_v8f16_align1(<8 x half> *%src, <16 x half> *%dst) {
; CHECK-LABEL: vst2_v8f16_align1: ; CHECK-LABEL: vst2_v8f16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmovx.f16 s1, s6 ; CHECK-NEXT: vmovx.f16 s1, s6
; CHECK-NEXT: vmovx.f16 s12, s10 ; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vins.f16 s1, s12 ; CHECK-NEXT: vins.f16 s1, s0
; CHECK-NEXT: vins.f16 s6, s10
; CHECK-NEXT: vmovx.f16 s3, s7 ; CHECK-NEXT: vmovx.f16 s3, s7
; CHECK-NEXT: vmovx.f16 s12, s11 ; CHECK-NEXT: vmovx.f16 s0, s11
; CHECK-NEXT: vins.f16 s6, s10
; CHECK-NEXT: vins.f16 s3, s0
; CHECK-NEXT: vmovx.f16 s10, s4
; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vins.f16 s7, s11 ; CHECK-NEXT: vins.f16 s7, s11
; CHECK-NEXT: vins.f16 s3, s12
; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmovx.f16 s14, s8
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vins.f16 s12, s14 ; CHECK-NEXT: vins.f16 s10, s0
; CHECK-NEXT: vmovx.f16 s14, s5 ; CHECK-NEXT: vmovx.f16 s8, s5
; CHECK-NEXT: vins.f16 s5, s9 ; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vmovx.f16 s8, s9 ; CHECK-NEXT: vmovx.f16 s0, s9
; CHECK-NEXT: vmov q3, q1
; CHECK-NEXT: vins.f16 s8, s0
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vins.f16 s14, s8
; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmov.f32 s9, s12
; CHECK-NEXT: vmov.f32 s10, s5
; CHECK-NEXT: vmov.f32 s2, s7 ; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vmov.f32 s11, s14 ; CHECK-NEXT: vmov.f32 s13, s10
; CHECK-NEXT: vstrb.8 q0, [r1, #16] ; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vstrb.8 q2, [r1] ; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vmov.f32 s15, s8
; CHECK-NEXT: vstrb.8 q3, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0 %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
%l1 = load <8 x half>, <8 x half>* %s1, align 4 %l1 = load <8 x half>, <8 x half>* %s1, align 4
%s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1 %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
%l2 = load <8 x half>, <8 x half>* %s2, align 4 %l2 = load <8 x half>, <8 x half>* %s2, align 4
%s = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %s = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
store <16 x half> %s, <16 x half> *%dst, align 1 store <16 x half> %s, <16 x half> *%dst, align 1
ret void ret void
} }
; f64 ; f64
define void @vst2_v2f64(<2 x double> *%src, <4 x double> *%dst) { define void @vst2_v2f64(<2 x double> *%src, <4 x double> *%dst) {
; CHECK-LABEL: vst2_v2f64: ; CHECK-LABEL: vst2_v2f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f64 d4, d3 ; CHECK-NEXT: vmov.f64 d4, d3
; CHECK-NEXT: vmov.f64 d5, d1 ; CHECK-NEXT: vmov.f64 d5, d1
; CHECK-NEXT: vmov.f64 d3, d0 ; CHECK-NEXT: vmov.f64 d3, d0
; CHECK-NEXT: vstrw.32 q2, [r1, #16] ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x double>, <2 x double>* %src, i32 0 %s1 = getelementptr <2 x double>, <2 x double>* %src, i32 0
%l1 = load <2 x double>, <2 x double>* %s1, align 4 %l1 = load <2 x double>, <2 x double>* %s1, align 4
%s2 = getelementptr <2 x double>, <2 x double>* %src, i32 1 %s2 = getelementptr <2 x double>, <2 x double>* %src, i32 1
%l2 = load <2 x double>, <2 x double>* %s2, align 4 %l2 = load <2 x double>, <2 x double>* %s2, align 4
%s = shufflevector <2 x double> %l1, <2 x double> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3> %s = shufflevector <2 x double> %l1, <2 x double> %l2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
store <4 x double> %s, <4 x double> *%dst, align 8 store <4 x double> %s, <4 x double> *%dst, align 8
ret void ret void
} }
define void @vst2_v4f64(<4 x double> *%src, <8 x double> *%dst) { define void @vst2_v4f64(<4 x double> *%src, <8 x double> *%dst) {
; CHECK-LABEL: vst2_v4f64: ; CHECK-LABEL: vst2_v4f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vmov.f64 d8, d4 ; CHECK-NEXT: vmov.f64 d8, d4
; CHECK-NEXT: vmov.f64 d9, d0 ; CHECK-NEXT: vmov.f64 d9, d0
; CHECK-NEXT: vmov.f64 d0, d5 ; CHECK-NEXT: vmov.f64 d0, d5
; CHECK-NEXT: vstrw.32 q4, [r1] ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f64 d4, d6
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f64 d5, d2 ; CHECK-NEXT: vmov.f64 d5, d2
; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f64 d4, d6
; CHECK-NEXT: vmov.f64 d2, d7 ; CHECK-NEXT: vmov.f64 d2, d7
; CHECK-NEXT: vstrw.32 q2, [r1, #32] ; CHECK-NEXT: vstrw.32 q2, [r1, #32]
; CHECK-NEXT: vstrw.32 q1, [r1, #48] ; CHECK-NEXT: vstrw.32 q1, [r1, #48]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x double>, <4 x double>* %src, i32 0 %s1 = getelementptr <4 x double>, <4 x double>* %src, i32 0
%l1 = load <4 x double>, <4 x double>* %s1, align 4 %l1 = load <4 x double>, <4 x double>* %s1, align 4
%s2 = getelementptr <4 x double>, <4 x double>* %src, i32 1 %s2 = getelementptr <4 x double>, <4 x double>* %src, i32 1
%l2 = load <4 x double>, <4 x double>* %s2, align 4 %l2 = load <4 x double>, <4 x double>* %s2, align 4
%s = shufflevector <4 x double> %l1, <4 x double> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> %s = shufflevector <4 x double> %l1, <4 x double> %l2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x double> %s, <8 x double> *%dst, align 8 store <8 x double> %s, <8 x double> *%dst, align 8
ret void ret void
} }

llvm/test/CodeGen/Thumb2/mve-vst3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s
; i32 ; i32
define void @vst3_v2i32(<2 x i32> *%src, <6 x i32> *%dst) { define void @vst3_v2i32(<2 x i32> *%src, <6 x i32> *%dst) {
; CHECK-LABEL: vst3_v2i32: ; CHECK-LABEL: vst3_v2i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: ldrd lr, r12, [r0] ; CHECK-NEXT: ldrd lr, r12, [r0]
; CHECK-NEXT: ldrd r3, r2, [r0, #8] ; CHECK-NEXT: ldrd r3, r2, [r0, #8]
; CHECK-NEXT: ldrd r4, r0, [r0, #16] ; CHECK-NEXT: ldrd r4, r0, [r0, #16]
; CHECK-NEXT: vmov q1[2], q1[0], lr, r3 ; CHECK-NEXT: vmov q1[2], q1[0], lr, r3
; CHECK-NEXT: vmov.32 q0[0], r4
; CHECK-NEXT: vmov q1[3], q1[1], r12, r2 ; CHECK-NEXT: vmov q1[3], q1[1], r12, r2
; CHECK-NEXT: vmov.32 q0[1], r0 ; CHECK-NEXT: vmov.32 q0[0], r4
; CHECK-NEXT: vmov.f32 s8, s7 ; CHECK-NEXT: vmov.f32 s8, s7
; CHECK-NEXT: vmov.f32 s10, s1 ; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.f64 d4, d2
; CHECK-NEXT: vmov.f32 s9, s6 ; CHECK-NEXT: vmov.f32 s9, s6
; CHECK-NEXT: vmov.f32 s10, s0 ; CHECK-NEXT: vmov.f32 s10, s0
; CHECK-NEXT: vmov.f32 s11, s5 ; CHECK-NEXT: vmov.f32 s11, s5
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q2, [r1]
; CHECK-NEXT: strd r2, r0, [r1, #16] ; CHECK-NEXT: strd r2, r0, [r1, #16]
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
entry: entry:
%s1 = getelementptr <2 x i32>, <2 x i32>* %src, i32 0 %s1 = getelementptr <2 x i32>, <2 x i32>* %src, i32 0
%l1 = load <2 x i32>, <2 x i32>* %s1, align 4 %l1 = load <2 x i32>, <2 x i32>* %s1, align 4
%s2 = getelementptr <2 x i32>, <2 x i32>* %src, i32 1 %s2 = getelementptr <2 x i32>, <2 x i32>* %src, i32 1
%l2 = load <2 x i32>, <2 x i32>* %s2, align 4 %l2 = load <2 x i32>, <2 x i32>* %s2, align 4
%s3 = getelementptr <2 x i32>, <2 x i32>* %src, i32 2 %s3 = getelementptr <2 x i32>, <2 x i32>* %src, i32 2
%l3 = load <2 x i32>, <2 x i32>* %s3, align 4 %l3 = load <2 x i32>, <2 x i32>* %s3, align 4
%t1 = shufflevector <2 x i32> %l1, <2 x i32> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t1 = shufflevector <2 x i32> %l1, <2 x i32> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%t2 = shufflevector <2 x i32> %l3, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %t2 = shufflevector <2 x i32> %l3, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%s = shufflevector <4 x i32> %t1, <4 x i32> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> %s = shufflevector <4 x i32> %t1, <4 x i32> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
store <6 x i32> %s, <6 x i32> *%dst store <6 x i32> %s, <6 x i32> *%dst
ret void ret void
} }
define void @vst3_v4i32(<4 x i32> *%src, <12 x i32> *%dst) { define void @vst3_v4i32(<4 x i32> *%src, <12 x i32> *%dst) {
; CHECK-LABEL: vst3_v4i32: ; CHECK-LABEL: vst3_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmov.f64 d8, d6
; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s8, s5
; CHECK-NEXT: vmov.f32 s19, s13
; CHECK-NEXT: vmov.f32 s9, s1 ; CHECK-NEXT: vmov.f32 s9, s1
; CHECK-NEXT: vmov.f32 s18, s0 ; CHECK-NEXT: vmov.f32 s18, s0
; CHECK-NEXT: vmov.f32 s0, s2 ; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f32 s11, s6 ; CHECK-NEXT: vmov.f32 s11, s6
; CHECK-NEXT: vmov.f32 s1, s15
; CHECK-NEXT: vmov.f32 s10, s14 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s2, s7 ; CHECK-NEXT: vmov.f32 s16, s12
; CHECK-NEXT: vstrw.32 q2, [r1, #16] ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s19, s13
; CHECK-NEXT: vmov.f32 s1, s15
; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vstrw.32 q0, [r1, #32] ; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0 %s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0
%l1 = load <4 x i32>, <4 x i32>* %s1, align 4 %l1 = load <4 x i32>, <4 x i32>* %s1, align 4
%s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1 %s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1
%l2 = load <4 x i32>, <4 x i32>* %s2, align 4 %l2 = load <4 x i32>, <4 x i32>* %s2, align 4
%s3 = getelementptr <4 x i32>, <4 x i32>* %src, i32 2 %s3 = getelementptr <4 x i32>, <4 x i32>* %src, i32 2
%l3 = load <4 x i32>, <4 x i32>* %s3, align 4 %l3 = load <4 x i32>, <4 x i32>* %s3, align 4
%t1 = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x i32> %l1, <4 x i32> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x i32> %l3, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x i32> %l3, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x i32> %t1, <8 x i32> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x i32> %t1, <8 x i32> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x i32> %s, <12 x i32> *%dst store <12 x i32> %s, <12 x i32> *%dst
ret void ret void
} }
define void @vst3_v8i32(<8 x i32> *%src, <24 x i32> *%dst) { define void @vst3_v8i32(<8 x i32> *%src, <24 x i32> *%dst) {
; CHECK-LABEL: vst3_v8i32: ; CHECK-LABEL: vst3_v8i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q7, [r0]
; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vmov.f64 d10, d8 ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48] ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q6, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #64] ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vmov.f32 s21, s28 ; CHECK-NEXT: vmov.f32 s8, s2
; CHECK-NEXT: vmov.f64 d14, d12 ; CHECK-NEXT: vmov.f32 s20, s28
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f32 s9, s19
; CHECK-NEXT: vmov.f32 s29, s12 ; CHECK-NEXT: vmov.f32 s28, s16
; CHECK-NEXT: vmov.f32 s9, s27 ; CHECK-NEXT: vmov.f32 s31, s17
; CHECK-NEXT: vmov.f32 s31, s25 ; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vldrw.u32 q4, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s11, s3 ; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vmov.f32 s23, s29
; CHECK-NEXT: vstrw.32 q2, [r1, #80]
; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vmov.f32 s21, s24
; CHECK-NEXT: vmov.f32 s29, s12
; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f32 s30, s0 ; CHECK-NEXT: vmov.f32 s30, s0
; CHECK-NEXT: vmov.f32 s0, s13 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vstrw.32 q7, [r1, #48] ; CHECK-NEXT: vstrw.32 q7, [r1, #48]
; CHECK-NEXT: vmov.f32 s3, s14 ; CHECK-NEXT: vmov.f32 s3, s14
; CHECK-NEXT: vmov.f32 s2, s26
; CHECK-NEXT: vldrw.u32 q6, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vstrw.32 q2, [r1, #80]
; CHECK-NEXT: vmov.f32 s12, s25
; CHECK-NEXT: vmov.f32 s13, s5 ; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vmov.f32 s22, s4 ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s4, s6 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vstrw.32 q5, [r1] ; CHECK-NEXT: vmov.f32 s12, s25
; CHECK-NEXT: vmov.f32 s15, s26 ; CHECK-NEXT: vmov.f32 s15, s26
; CHECK-NEXT: vmov.f32 s5, s19
; CHECK-NEXT: vmov.f32 s14, s18 ; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.f32 s6, s27 ; CHECK-NEXT: vmov.f32 s5, s19
; CHECK-NEXT: vstrw.32 q3, [r1, #16] ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vmov.f32 s6, s27
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i32>, <8 x i32>* %src, i32 0 %s1 = getelementptr <8 x i32>, <8 x i32>* %src, i32 0
%l1 = load <8 x i32>, <8 x i32>* %s1, align 4 %l1 = load <8 x i32>, <8 x i32>* %s1, align 4
%s2 = getelementptr <8 x i32>, <8 x i32>* %src, i32 1 %s2 = getelementptr <8 x i32>, <8 x i32>* %src, i32 1
%l2 = load <8 x i32>, <8 x i32>* %s2, align 4 %l2 = load <8 x i32>, <8 x i32>* %s2, align 4
%s3 = getelementptr <8 x i32>, <8 x i32>* %src, i32 2 %s3 = getelementptr <8 x i32>, <8 x i32>* %src, i32 2
%l3 = load <8 x i32>, <8 x i32>* %s3, align 4 %l3 = load <8 x i32>, <8 x i32>* %s3, align 4
%t1 = shufflevector <8 x i32> %l1, <8 x i32> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x i32> %l1, <8 x i32> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x i32> %l3, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x i32> %l3, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x i32> %t1, <16 x i32> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x i32> %t1, <16 x i32> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x i32> %s, <24 x i32> *%dst store <24 x i32> %s, <24 x i32> *%dst
ret void ret void
} }
define void @vst3_v16i32(<16 x i32> *%src, <48 x i32> *%dst) { define void @vst3_v16i32(<16 x i32> *%src, <48 x i32> *%dst) {
; CHECK-LABEL: vst3_v16i32: ; CHECK-LABEL: vst3_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #160 ; CHECK-NEXT: .pad #144
; CHECK-NEXT: sub sp, #160 ; CHECK-NEXT: sub sp, #144
; CHECK-NEXT: vldrw.u32 q7, [r0, #96] ; CHECK-NEXT: vldrw.u32 q7, [r0, #96]
; CHECK-NEXT: vldrw.u32 q3, [r0, #160]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #128] ; CHECK-NEXT: vldrw.u32 q2, [r0, #128]
; CHECK-NEXT: vldrw.u32 q6, [r0] ; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q7, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [r0, #80] ; CHECK-NEXT: vldrw.u32 q7, [r0, #80]
; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vldrw.u32 q3, [r0, #160]
; CHECK-NEXT: vstrw.32 q7, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [r0, #48]
; CHECK-NEXT: vmov.f32 s17, s9
; CHECK-NEXT: vstrw.32 q3, [sp, #128] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s19, s2 ; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [r0, #32] ; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vmov.f32 s18, s26 ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q5, [r0, #144] ; CHECK-NEXT: vstrw.32 q3, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #176]
; CHECK-NEXT: vstrw.32 q7, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [r0, #16] ; CHECK-NEXT: vldrw.u32 q7, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112] ; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vstrw.32 q4, [r1, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #176]
; CHECK-NEXT: vmov.f64 d8, d5 ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vstrw.32 q7, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s17, s9
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vldrw.u32 q7, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q5, [r0, #144]
; CHECK-NEXT: vstrw.32 q4, [r1, #16]
; CHECK-NEXT: vmov.f32 s18, s3
; CHECK-NEXT: vmov.f32 s16, s10
; CHECK-NEXT: vmov.f32 s17, s27 ; CHECK-NEXT: vmov.f32 s17, s27
; CHECK-NEXT: vmov.f32 s19, s11 ; CHECK-NEXT: vmov.f32 s19, s11
; CHECK-NEXT: vmov.f32 s18, s3
; CHECK-NEXT: vstrw.32 q4, [r1, #32] ; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: vmov.f64 d8, d3 ; CHECK-NEXT: vmov.f32 s16, s6
; CHECK-NEXT: vmov.f32 s17, s31
; CHECK-NEXT: vmov.f32 s19, s7 ; CHECK-NEXT: vmov.f32 s19, s7
; CHECK-NEXT: vmov.f32 s18, s15 ; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vstrw.32 q4, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s18, s31
; CHECK-NEXT: vmov.f64 d8, d12 ; CHECK-NEXT: vstrw.32 q4, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov.f32 s19, s25
; CHECK-NEXT: vmov.f32 s18, s8 ; CHECK-NEXT: vmov.f32 s18, s8
; CHECK-NEXT: vmov q2, q7 ; CHECK-NEXT: vmov.f64 d4, d14
; CHECK-NEXT: vmov.f64 d0, d4
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s4, s13 ; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.f32 s4, s9
; CHECK-NEXT: vldrw.u32 q2, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov.f32 s3, s13
; CHECK-NEXT: vmov.f32 s0, s12
; CHECK-NEXT: vmov.f64 d14, d4
; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s7, s14
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s10 ; CHECK-NEXT: vmov.f32 s16, s24
; CHECK-NEXT: vmov.f32 s19, s25
; CHECK-NEXT: vstrw.32 q4, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s1
; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov.f32 s15, s3
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d0, d14
; CHECK-NEXT: vldrw.u32 q5, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vmov.f32 s7, s30
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f32 s31, s1
; CHECK-NEXT: vmov q3, q1 ; CHECK-NEXT: vmov.f64 d0, d10
; CHECK-NEXT: vmov.f32 s16, s5 ; CHECK-NEXT: vmov.f32 s16, s5
; CHECK-NEXT: vmov.f32 s17, s1
; CHECK-NEXT: vmov.f32 s19, s6 ; CHECK-NEXT: vmov.f32 s19, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s14, s7
; CHECK-NEXT: vmov.f64 d12, d11 ; CHECK-NEXT: vmov.f32 s29, s4
; CHECK-NEXT: vmov q7, q1 ; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s9, s7 ; CHECK-NEXT: vmov.f32 s24, s2
; CHECK-NEXT: vmov.f32 s18, s6 ; CHECK-NEXT: vmov.f32 s30, s4
; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s27, s3
; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov q0, q7
; CHECK-NEXT: vmov.f32 s25, s7
; CHECK-NEXT: vstrw.32 q4, [r1, #112]
; CHECK-NEXT: vmov.f32 s27, s23
; CHECK-NEXT: vldrw.u32 q5, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vldrw.u32 q3, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s29, s20
; CHECK-NEXT: vmov q5, q1
; CHECK-NEXT: vmov.f32 s31, s1
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s26, s15
; CHECK-NEXT: vstrw.32 q2, [r1, #128]
; CHECK-NEXT: vmov.f32 s30, s0
; CHECK-NEXT: vstrw.32 q6, [r1, #80]
; CHECK-NEXT: vmov.f64 d0, d2
; CHECK-NEXT: vstrw.32 q7, [r1, #96] ; CHECK-NEXT: vstrw.32 q7, [r1, #96]
; CHECK-NEXT: vmov.f32 s1, s12 ; CHECK-NEXT: vmov.f32 s4, s0
; CHECK-NEXT: vldrw.u32 q3, [sp] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s18, s10
; CHECK-NEXT: vmov.f32 s2, s12 ; CHECK-NEXT: vmov.f64 d10, d0
; CHECK-NEXT: vstrw.32 q0, [r1, #48]
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vstrw.32 q4, [r1, #112]
; CHECK-NEXT: vstrw.32 q0, [r1, #144] ; CHECK-NEXT: vstrw.32 q0, [r1, #144]
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s15, s6
; CHECK-NEXT: vstrw.32 q0, [r1, #160] ; CHECK-NEXT: vstrw.32 q0, [r1, #160]
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s22 ; CHECK-NEXT: vmov.f32 s13, s11
; CHECK-NEXT: vldrw.u32 q2, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1, #176] ; CHECK-NEXT: vstrw.32 q0, [r1, #176]
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q3, [r1, #64] ; CHECK-NEXT: vmov.f32 s25, s23
; CHECK-NEXT: vstrw.32 q3, [r1, #128]
; CHECK-NEXT: vmov.f32 s26, s11
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #160 ; CHECK-NEXT: vmov.f32 s6, s20
; CHECK-NEXT: vstrw.32 q6, [r1, #80]
; CHECK-NEXT: vmov.f32 s5, s8
; CHECK-NEXT: vmov.f32 s20, s9
; CHECK-NEXT: vstrw.32 q1, [r1, #48]
; CHECK-NEXT: vmov.f32 s23, s10
; CHECK-NEXT: vstrw.32 q5, [r1, #64]
; CHECK-NEXT: add sp, #144
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x i32>, <16 x i32>* %src, i32 0 %s1 = getelementptr <16 x i32>, <16 x i32>* %src, i32 0
%l1 = load <16 x i32>, <16 x i32>* %s1, align 4 %l1 = load <16 x i32>, <16 x i32>* %s1, align 4
%s2 = getelementptr <16 x i32>, <16 x i32>* %src, i32 1 %s2 = getelementptr <16 x i32>, <16 x i32>* %src, i32 1
%l2 = load <16 x i32>, <16 x i32>* %s2, align 4 %l2 = load <16 x i32>, <16 x i32>* %s2, align 4
%s3 = getelementptr <16 x i32>, <16 x i32>* %src, i32 2 %s3 = getelementptr <16 x i32>, <16 x i32>* %src, i32 2
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @vst3_v4i16(<4 x i16> *%src, <12 x i16> *%dst) { define void @vst3_v4i16(<4 x i16> *%src, <12 x i16> *%dst) {
; CHECK-LABEL: vst3_v4i16: ; CHECK-LABEL: vst3_v4i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vldrh.u32 q2, [r0, #16]
; CHECK-NEXT: vldrh.u32 q1, [r0] ; CHECK-NEXT: vldrh.u32 q1, [r0]
; CHECK-NEXT: vldrh.u32 q0, [r0, #8] ; CHECK-NEXT: vldrh.u32 q0, [r0, #8]
; CHECK-NEXT: vmov.f64 d6, d5 ; CHECK-NEXT: vldrh.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.f32 s13, s7
; CHECK-NEXT: vmov r0, r5, d2 ; CHECK-NEXT: vmov r0, r5, d2
; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: vmov lr, r4, d1 ; CHECK-NEXT: vmov lr, r4, d1
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vmov.16 q0[0], r0
; CHECK-NEXT: vmov.f32 s15, s11 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov.32 q3[2], r4 ; CHECK-NEXT: vmov.f32 s7, s11
; CHECK-NEXT: vmov r12, s6
; CHECK-NEXT: vmov.32 q1[2], r4
; CHECK-NEXT: vmov r0, r4, d4 ; CHECK-NEXT: vmov r0, r4, d4
; CHECK-NEXT: vstrh.32 q1, [r1, #16]
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov r12, s6
; CHECK-NEXT: vmov.16 q0[3], r5 ; CHECK-NEXT: vmov.16 q0[3], r5
; CHECK-NEXT: vstrh.32 q3, [r1, #16]
; CHECK-NEXT: vmov.16 q0[4], r3 ; CHECK-NEXT: vmov.16 q0[4], r3
; CHECK-NEXT: vmov.16 q0[5], r4 ; CHECK-NEXT: vmov.16 q0[5], r4
; CHECK-NEXT: vmov.16 q0[6], r12 ; CHECK-NEXT: vmov.16 q0[6], r12
; CHECK-NEXT: vmov.16 q0[7], lr ; CHECK-NEXT: vmov.16 q0[7], lr
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%s1 = getelementptr <4 x i16>, <4 x i16>* %src, i32 0 %s1 = getelementptr <4 x i16>, <4 x i16>* %src, i32 0
%l1 = load <4 x i16>, <4 x i16>* %s1, align 4 %l1 = load <4 x i16>, <4 x i16>* %s1, align 4
%s2 = getelementptr <4 x i16>, <4 x i16>* %src, i32 1 %s2 = getelementptr <4 x i16>, <4 x i16>* %src, i32 1
%l2 = load <4 x i16>, <4 x i16>* %s2, align 4 %l2 = load <4 x i16>, <4 x i16>* %s2, align 4
%s3 = getelementptr <4 x i16>, <4 x i16>* %src, i32 2 %s3 = getelementptr <4 x i16>, <4 x i16>* %src, i32 2
%l3 = load <4 x i16>, <4 x i16>* %s3, align 4 %l3 = load <4 x i16>, <4 x i16>* %s3, align 4
%t1 = shufflevector <4 x i16> %l1, <4 x i16> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x i16> %l1, <4 x i16> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x i16> %l3, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x i16> %l3, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x i16> %t1, <8 x i16> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x i16> %t1, <8 x i16> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x i16> %s, <12 x i16> *%dst store <12 x i16> %s, <12 x i16> *%dst
ret void ret void
} }
define void @vst3_v8i16(<8 x i16> *%src, <24 x i16> *%dst) { define void @vst3_v8i16(<8 x i16> *%src, <24 x i16> *%dst) {
; CHECK-LABEL: vst3_v8i16: ; CHECK-LABEL: vst3_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f64 d0, d4 ; CHECK-NEXT: vmov.f32 s0, s8
; CHECK-NEXT: vmov.u16 r2, q1[1] ; CHECK-NEXT: vmov.u16 r2, q1[1]
; CHECK-NEXT: vmovx.f16 s20, s8
; CHECK-NEXT: vins.f16 s0, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov.f32 s12, s9 ; CHECK-NEXT: vmov.f32 s12, s9
; CHECK-NEXT: vins.f16 s12, s5 ; CHECK-NEXT: vins.f16 s12, s5
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.f32 s3, s12 ; CHECK-NEXT: vmov.f32 s3, s12
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s1, s8 ; CHECK-NEXT: vmovx.f16 s8, s8
; CHECK-NEXT: vmov.f32 s17, s12
; CHECK-NEXT: vmov.f32 s18, s12
; CHECK-NEXT: vins.f16 s17, s20
; CHECK-NEXT: vmovx.f16 s20, s18
; CHECK-NEXT: vins.f16 s2, s20
; CHECK-NEXT: vmovx.f16 s20, s14
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s1, s17
; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vmovx.f16 s16, s6 ; CHECK-NEXT: vmovx.f16 s16, s6
; CHECK-NEXT: vins.f16 s16, s20 ; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmovx.f16 s20, s15
; CHECK-NEXT: vins.f16 s17, s7 ; CHECK-NEXT: vins.f16 s17, s7
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vins.f16 s1, s8
; CHECK-NEXT: vmovx.f16 s8, s12
; CHECK-NEXT: vins.f16 s2, s8
; CHECK-NEXT: vmovx.f16 s8, s14
; CHECK-NEXT: vins.f16 s16, s8
; CHECK-NEXT: vmovx.f16 s19, s7 ; CHECK-NEXT: vmovx.f16 s19, s7
; CHECK-NEXT: vrev32.16 q1, q1 ; CHECK-NEXT: vmovx.f16 s8, s15
; CHECK-NEXT: vins.f16 s19, s20
; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s18, s15 ; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vmovx.f16 s24, s17 ; CHECK-NEXT: vins.f16 s19, s8
; CHECK-NEXT: vmov.f32 s22, s11 ; CHECK-NEXT: vmovx.f16 s8, s17
; CHECK-NEXT: vins.f16 s21, s24 ; CHECK-NEXT: vmov.f32 s17, s11
; CHECK-NEXT: vmovx.f16 s24, s22 ; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vins.f16 s18, s24 ; CHECK-NEXT: vins.f16 s17, s8
; CHECK-NEXT: vmov.f32 s12, s13 ; CHECK-NEXT: vmovx.f16 s8, s11
; CHECK-NEXT: vmov.f32 s22, s18 ; CHECK-NEXT: vins.f16 s18, s8
; CHECK-NEXT: vmov.f32 s17, s21 ; CHECK-NEXT: vmov.f32 s8, s13
; CHECK-NEXT: vmov.f32 s18, s22 ; CHECK-NEXT: vins.f16 s8, s12
; CHECK-NEXT: vmovx.f16 s20, s9 ; CHECK-NEXT: vmovx.f16 s12, s10
; CHECK-NEXT: vins.f16 s12, s20 ; CHECK-NEXT: vins.f16 s14, s12
; CHECK-NEXT: vmovx.f16 s20, s10 ; CHECK-NEXT: vrev32.16 q1, q1
; CHECK-NEXT: vins.f16 s14, s20 ; CHECK-NEXT: vmovx.f16 s12, s13
; CHECK-NEXT: vmovx.f16 s4, s6
; CHECK-NEXT: vins.f16 s5, s12
; CHECK-NEXT: vmov.f32 s11, s14
; CHECK-NEXT: vins.f16 s10, s4
; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vstrw.32 q4, [r1, #32] ; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: vmov.f32 s15, s14 ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s14, s10 ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vmovx.f16 s8, s13 ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vins.f16 s14, s8
; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vmov.f32 s14, s6
; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0 %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
%l1 = load <8 x i16>, <8 x i16>* %s1, align 4 %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
%s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1 %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
%l2 = load <8 x i16>, <8 x i16>* %s2, align 4 %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
%s3 = getelementptr <8 x i16>, <8 x i16>* %src, i32 2 %s3 = getelementptr <8 x i16>, <8 x i16>* %src, i32 2
%l3 = load <8 x i16>, <8 x i16>* %s3, align 4 %l3 = load <8 x i16>, <8 x i16>* %s3, align 4
%t1 = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x i16> %l1, <8 x i16> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x i16> %l3, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x i16> %l3, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x i16> %t1, <16 x i16> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x i16> %t1, <16 x i16> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x i16> %s, <24 x i16> *%dst store <24 x i16> %s, <24 x i16> *%dst
ret void ret void
} }
define void @vst3_v16i16(<16 x i16> *%src, <48 x i16> *%dst) { define void @vst3_v16i16(<16 x i16> *%src, <48 x i16> *%dst) {
; CHECK-LABEL: vst3_v16i16: ; CHECK-LABEL: vst3_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #80 ; CHECK-NEXT: .pad #64
; CHECK-NEXT: sub sp, #80 ; CHECK-NEXT: sub sp, #64
; CHECK-NEXT: vldrw.u32 q5, [r0, #48] ; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q3, [r0, #80] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q6, [r0, #32] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vmovx.f16 s0, s14 ; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s8, s22 ; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vins.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s0, s15 ; CHECK-NEXT: vins.f16 s1, s7
; CHECK-NEXT: vins.f16 s9, s23 ; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmov.u16 r2, q6[1] ; CHECK-NEXT: vmovx.f16 s0, s11
; CHECK-NEXT: vmovx.f16 s11, s23 ; CHECK-NEXT: vmovx.f16 s7, s7
; CHECK-NEXT: vstrw.32 q6, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s12, s4
; CHECK-NEXT: vins.f16 s11, s0 ; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill ; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vmov.f32 s10, s15 ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmovx.f16 s4, s9 ; CHECK-NEXT: vmov.f32 s18, s11
; CHECK-NEXT: vmov q4, q2 ; CHECK-NEXT: vmov.f32 s15, s7
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vstrw.32 q6, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s11 ; CHECK-NEXT: vmov.f32 s13, s3
; CHECK-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vins.f16 s13, s4
; CHECK-NEXT: vmov.f32 s2, s11 ; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vins.f16 s18, s4 ; CHECK-NEXT: vins.f16 s18, s4
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmov.f32 s2, s18 ; CHECK-NEXT: vmov.f32 s20, s24
; CHECK-NEXT: vmov.f64 d4, d2 ; CHECK-NEXT: vins.f16 s20, s4
; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vmov.u16 r2, q1[1]
; CHECK-NEXT: vmovx.f16 s28, s4 ; CHECK-NEXT: vmov.16 q5[4], r2
; CHECK-NEXT: vins.f16 s8, s24 ; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s1 ; CHECK-NEXT: vmov.f32 s23, s25
; CHECK-NEXT: vmov.16 q2[4], r2 ; CHECK-NEXT: vmovx.f16 s4, s24
; CHECK-NEXT: vmov.f32 s11, s5
; CHECK-NEXT: vins.f16 s11, s25
; CHECK-NEXT: vldrw.u32 q6, [r0, #64] ; CHECK-NEXT: vldrw.u32 q6, [r0, #64]
; CHECK-NEXT: vmov.f32 s9, s4 ; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmov.u16 r0, q5[1] ; CHECK-NEXT: vins.f16 s23, s5
; CHECK-NEXT: vstrw.32 q3, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s5, s24 ; CHECK-NEXT: vmov.f32 s5, s24
; CHECK-NEXT: vmov.f32 s6, s24 ; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vins.f16 s5, s28 ; CHECK-NEXT: vmov.f32 s28, s0
; CHECK-NEXT: vmovx.f16 s28, s6 ; CHECK-NEXT: vins.f16 s5, s4
; CHECK-NEXT: vins.f16 s10, s28 ; CHECK-NEXT: vmovx.f16 s4, s24
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.f32 s6, s10 ; CHECK-NEXT: vins.f16 s28, s12
; CHECK-NEXT: vstrw.32 q4, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vins.f16 s22, s4
; CHECK-NEXT: vmov.f32 s9, s5 ; CHECK-NEXT: vmov.f32 s4, s1
; CHECK-NEXT: vldrw.u32 q4, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q2, [r1]
; CHECK-NEXT: vmov.f64 d14, d2
; CHECK-NEXT: vins.f16 s28, s20
; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vins.f16 s0, s21
; CHECK-NEXT: vmov.16 q7[4], r0 ; CHECK-NEXT: vmov.16 q7[4], r0
; CHECK-NEXT: vmov.f32 s31, s0 ; CHECK-NEXT: vins.f16 s4, s13
; CHECK-NEXT: vldrw.u32 q5, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vmov.f32 s1, s12 ; CHECK-NEXT: vmov.f32 s31, s4
; CHECK-NEXT: vmov.f32 s29, s4 ; CHECK-NEXT: vldrw.u32 q1, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmovx.f16 s4, s4 ; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmov.f32 s2, s12 ; CHECK-NEXT: vmov.f32 s29, s8
; CHECK-NEXT: vins.f16 s1, s4 ; CHECK-NEXT: vins.f16 s29, s0
; CHECK-NEXT: vmovx.f16 s4, s2 ; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vins.f16 s30, s4 ; CHECK-NEXT: vins.f16 s30, s0
; CHECK-NEXT: vmovx.f16 s4, s26 ; CHECK-NEXT: vmovx.f16 s4, s6
; CHECK-NEXT: vmov.f32 s2, s30 ; CHECK-NEXT: vmovx.f16 s0, s26
; CHECK-NEXT: vmov.f32 s29, s1 ; CHECK-NEXT: vldrw.u32 q4, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s12, s13 ; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmov.f32 s30, s2 ; CHECK-NEXT: vins.f16 s5, s7
; CHECK-NEXT: vmovx.f16 s0, s18 ; CHECK-NEXT: vmovx.f16 s7, s7
; CHECK-NEXT: vins.f16 s0, s4 ; CHECK-NEXT: vmovx.f16 s0, s27
; CHECK-NEXT: vmov q1, q4 ; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vins.f16 s1, s7 ; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vmov.f32 s13, s19
; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vins.f16 s13, s0
; CHECK-NEXT: vmov.f32 s14, s27
; CHECK-NEXT: vmovx.f16 s0, s19
; CHECK-NEXT: vmov.f32 s12, s25
; CHECK-NEXT: vins.f16 s14, s0
; CHECK-NEXT: vmov.f32 s0, s9
; CHECK-NEXT: vins.f16 s0, s6
; CHECK-NEXT: vmovx.f16 s6, s2
; CHECK-NEXT: vins.f16 s10, s6
; CHECK-NEXT: vmovx.f16 s6, s9
; CHECK-NEXT: vmov.f32 s3, s10
; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vstrw.32 q7, [r1, #48] ; CHECK-NEXT: vstrw.32 q7, [r1, #48]
; CHECK-NEXT: vmovx.f16 s3, s7 ; CHECK-NEXT: vrev32.16 q2, q2
; CHECK-NEXT: vmovx.f16 s4, s27 ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vins.f16 s3, s4 ; CHECK-NEXT: vmovx.f16 s8, s17
; CHECK-NEXT: vmov.f32 s5, s23 ; CHECK-NEXT: vins.f16 s9, s6
; CHECK-NEXT: vmov.f32 s2, s27 ; CHECK-NEXT: vmovx.f16 s6, s10
; CHECK-NEXT: vmovx.f16 s16, s1 ; CHECK-NEXT: vins.f16 s12, s8
; CHECK-NEXT: vmov.f32 s6, s23 ; CHECK-NEXT: vmovx.f16 s8, s18
; CHECK-NEXT: vins.f16 s5, s16 ; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vldrw.u32 q4, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmovx.f16 s20, s6 ; CHECK-NEXT: vins.f16 s26, s8
; CHECK-NEXT: vmov.f32 s24, s25 ; CHECK-NEXT: vmov.f32 s15, s26
; CHECK-NEXT: vins.f16 s2, s20 ; CHECK-NEXT: vmovx.f16 s8, s25
; CHECK-NEXT: vmovx.f16 s20, s17 ; CHECK-NEXT: vrev32.16 q6, q4
; CHECK-NEXT: vins.f16 s12, s20 ; CHECK-NEXT: vins.f16 s2, s6
; CHECK-NEXT: vmovx.f16 s20, s18 ; CHECK-NEXT: vins.f16 s25, s8
; CHECK-NEXT: vins.f16 s14, s20 ; CHECK-NEXT: vmov.f32 s1, s9
; CHECK-NEXT: vmov.f32 s6, s2 ; CHECK-NEXT: vmovx.f16 s8, s26
; CHECK-NEXT: vmov.f32 s15, s14 ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vmovx.f16 s16, s13
; CHECK-NEXT: vstr s16, [sp, #32] @ 4-byte Spill
; CHECK-NEXT: vldrw.u32 q4, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s1, s5
; CHECK-NEXT: vrev32.16 q5, q4
; CHECK-NEXT: vldr s16, [sp, #32] @ 4-byte Reload
; CHECK-NEXT: vins.f16 s21, s16
; CHECK-NEXT: vmovx.f16 s16, s22
; CHECK-NEXT: vins.f16 s14, s16
; CHECK-NEXT: vldrw.u32 q4, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmovx.f16 s4, s17
; CHECK-NEXT: vmov.f32 s22, s14
; CHECK-NEXT: vins.f16 s24, s4
; CHECK-NEXT: vmovx.f16 s4, s18
; CHECK-NEXT: vins.f16 s26, s4
; CHECK-NEXT: vmov.f32 s13, s21
; CHECK-NEXT: vmov.f32 s27, s26
; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vmov.f32 s26, s18
; CHECK-NEXT: vldrw.u32 q4, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmovx.f16 s4, s25
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vrev32.16 q4, q4 ; CHECK-NEXT: vins.f16 s10, s8
; CHECK-NEXT: vins.f16 s17, s4 ; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vmovx.f16 s4, s18 ; CHECK-NEXT: vmov.f32 s14, s10
; CHECK-NEXT: vins.f16 s26, s4 ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vmov.f32 s14, s22 ; CHECK-NEXT: vmov.f32 s13, s25
; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vstrw.32 q3, [r1, #64]
; CHECK-NEXT: vmov.f32 s25, s17
; CHECK-NEXT: vstrw.32 q0, [r1, #80] ; CHECK-NEXT: vstrw.32 q0, [r1, #80]
; CHECK-NEXT: vmov.f32 s26, s18 ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vstrw.32 q6, [r1, #16] ; CHECK-NEXT: add sp, #64
; CHECK-NEXT: add sp, #80
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x i16>, <16 x i16>* %src, i32 0 %s1 = getelementptr <16 x i16>, <16 x i16>* %src, i32 0
%l1 = load <16 x i16>, <16 x i16>* %s1, align 4 %l1 = load <16 x i16>, <16 x i16>* %s1, align 4
%s2 = getelementptr <16 x i16>, <16 x i16>* %src, i32 1 %s2 = getelementptr <16 x i16>, <16 x i16>* %src, i32 1
%l2 = load <16 x i16>, <16 x i16>* %s2, align 4 %l2 = load <16 x i16>, <16 x i16>* %s2, align 4
%s3 = getelementptr <16 x i16>, <16 x i16>* %src, i32 2 %s3 = getelementptr <16 x i16>, <16 x i16>* %src, i32 2
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesentry:
%s = shufflevector <8 x i8> %t1, <8 x i8> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x i8> %t1, <8 x i8> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x i8> %s, <12 x i8> *%dst store <12 x i8> %s, <12 x i8> *%dst
ret void ret void
} }
define void @vst3_v8i8(<8 x i8> *%src, <24 x i8> *%dst) { define void @vst3_v8i8(<8 x i8> *%src, <24 x i8> *%dst) {
; CHECK-LABEL: vst3_v8i8: ; CHECK-LABEL: vst3_v8i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrb.u16 q1, [r0, #16]
; CHECK-NEXT: vldrb.u16 q2, [r0, #8] ; CHECK-NEXT: vldrb.u16 q2, [r0, #8]
; CHECK-NEXT: vmovx.f16 s12, s6 ; CHECK-NEXT: vldrb.u16 q1, [r0, #16]
; CHECK-NEXT: vmovx.f16 s0, s10 ; CHECK-NEXT: vldrb.u16 q3, [r0]
; CHECK-NEXT: vins.f16 s0, s12
; CHECK-NEXT: vmovx.f16 s12, s7
; CHECK-NEXT: vins.f16 s1, s11 ; CHECK-NEXT: vins.f16 s1, s11
; CHECK-NEXT: vmovx.f16 s2, s6
; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vmovx.f16 s3, s11 ; CHECK-NEXT: vmovx.f16 s3, s11
; CHECK-NEXT: vins.f16 s3, s12 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vldrb.u16 q3, [r0] ; CHECK-NEXT: vmovx.f16 s2, s7
; CHECK-NEXT: vmov.f32 s2, s7 ; CHECK-NEXT: vmovx.f16 s1, s1
; CHECK-NEXT: vmovx.f16 s20, s1
; CHECK-NEXT: vmov.f32 s17, s15 ; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vins.f16 s3, s2
; CHECK-NEXT: vins.f16 s17, s1
; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vmovx.f16 s1, s15
; CHECK-NEXT: vmov.u16 r0, q3[0] ; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.f32 s18, s15 ; CHECK-NEXT: vins.f16 s2, s1
; CHECK-NEXT: vins.f16 s17, s20
; CHECK-NEXT: vmovx.f16 s20, s18
; CHECK-NEXT: vins.f16 s2, s20
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s1, s17 ; CHECK-NEXT: vmov.f32 s1, s17
; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vmov.8 q4[0], r0 ; CHECK-NEXT: vmov.8 q4[0], r0
; CHECK-NEXT: vmov.u16 r0, q2[0] ; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vstrb.16 q0, [r1, #16] ; CHECK-NEXT: vstrb.16 q0, [r1, #16]
; CHECK-NEXT: vmov.8 q4[1], r0 ; CHECK-NEXT: vmov.8 q4[1], r0
; CHECK-NEXT: vmov.u16 r0, q1[0] ; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.8 q4[2], r0 ; CHECK-NEXT: vmov.8 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[1] ; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.8 q4[3], r0 ; CHECK-NEXT: vmov.8 q4[3], r0
Show All 17 Lines
; CHECK-NEXT: vmov.8 q4[12], r0 ; CHECK-NEXT: vmov.8 q4[12], r0
; CHECK-NEXT: vmov.u16 r0, q2[4] ; CHECK-NEXT: vmov.u16 r0, q2[4]
; CHECK-NEXT: vmov.8 q4[13], r0 ; CHECK-NEXT: vmov.8 q4[13], r0
; CHECK-NEXT: vmov.u16 r0, q1[4] ; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmov.8 q4[14], r0 ; CHECK-NEXT: vmov.8 q4[14], r0
; CHECK-NEXT: vmov.u16 r0, q3[5] ; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.8 q4[15], r0 ; CHECK-NEXT: vmov.8 q4[15], r0
; CHECK-NEXT: vstrw.32 q4, [r1] ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vpop {d8, d9, d10} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i8>, <8 x i8>* %src, i32 0 %s1 = getelementptr <8 x i8>, <8 x i8>* %src, i32 0
%l1 = load <8 x i8>, <8 x i8>* %s1, align 4 %l1 = load <8 x i8>, <8 x i8>* %s1, align 4
%s2 = getelementptr <8 x i8>, <8 x i8>* %src, i32 1 %s2 = getelementptr <8 x i8>, <8 x i8>* %src, i32 1
%l2 = load <8 x i8>, <8 x i8>* %s2, align 4 %l2 = load <8 x i8>, <8 x i8>* %s2, align 4
%s3 = getelementptr <8 x i8>, <8 x i8>* %src, i32 2 %s3 = getelementptr <8 x i8>, <8 x i8>* %src, i32 2
%l3 = load <8 x i8>, <8 x i8>* %s3, align 4 %l3 = load <8 x i8>, <8 x i8>* %s3, align 4
▲ Show 20 Lines • Show All 220 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; i64 ; i64
define void @vst3_v2i64(<2 x i64> *%src, <6 x i64> *%dst) { define void @vst3_v2i64(<2 x i64> *%src, <6 x i64> *%dst) {
; CHECK-LABEL: vst3_v2i64: ; CHECK-LABEL: vst3_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f64 d6, d5
; CHECK-NEXT: vmov.f32 s13, s11
; CHECK-NEXT: vmov.f32 s14, s2 ; CHECK-NEXT: vmov.f32 s14, s2
; CHECK-NEXT: vmov.f32 s15, s3 ; CHECK-NEXT: vmov.f32 s15, s3
; CHECK-NEXT: vmov.f32 s2, s6 ; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s3, s7 ; CHECK-NEXT: vmov.f32 s3, s7
; CHECK-NEXT: vmov.f32 s6, s8 ; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vmov.f32 s7, s9 ; CHECK-NEXT: vmov.f32 s7, s9
; CHECK-NEXT: vstrb.8 q1, [r1], #32 ; CHECK-NEXT: vstrb.8 q1, [r1], #32
; CHECK-NEXT: vstrw.32 q3, [r1] ; CHECK-NEXT: vmov.f32 s12, s10
; CHECK-NEXT: vmov.f32 s13, s11
; CHECK-NEXT: vstrw.32 q0, [r1, #-16] ; CHECK-NEXT: vstrw.32 q0, [r1, #-16]
; CHECK-NEXT: vstrw.32 q3, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0 %s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0
%l1 = load <2 x i64>, <2 x i64>* %s1, align 4 %l1 = load <2 x i64>, <2 x i64>* %s1, align 4
%s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1 %s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1
%l2 = load <2 x i64>, <2 x i64>* %s2, align 4 %l2 = load <2 x i64>, <2 x i64>* %s2, align 4
%s3 = getelementptr <2 x i64>, <2 x i64>* %src, i32 2 %s3 = getelementptr <2 x i64>, <2 x i64>* %src, i32 2
%l3 = load <2 x i64>, <2 x i64>* %s3, align 4 %l3 = load <2 x i64>, <2 x i64>* %s3, align 4
%t1 = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t1 = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%t2 = shufflevector <2 x i64> %l3, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %t2 = shufflevector <2 x i64> %l3, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%s = shufflevector <4 x i64> %t1, <4 x i64> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> %s = shufflevector <4 x i64> %t1, <4 x i64> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
store <6 x i64> %s, <6 x i64> *%dst store <6 x i64> %s, <6 x i64> *%dst
ret void ret void
} }
define void @vst3_v4i64(<4 x i64> *%src, <12 x i64> *%dst) { define void @vst3_v4i64(<4 x i64> *%src, <12 x i64> *%dst) {
; CHECK-LABEL: vst3_v4i64: ; CHECK-LABEL: vst3_v4i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48] ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vmov.f64 d10, d2 ; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f32 s16, s14
; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vldrw.u32 q2, [r0, #64] ; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
; CHECK-NEXT: vmov.f64 d7, d15
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmov.f32 s20, s4
; CHECK-NEXT: vstrw.32 q4, [r1, #80]
; CHECK-NEXT: vmov.f32 s21, s5 ; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vmov.f32 s22, s28 ; CHECK-NEXT: vmov.f32 s22, s28
; CHECK-NEXT: vmov.f32 s23, s29 ; CHECK-NEXT: vmov.f32 s23, s29
; CHECK-NEXT: vmov.f64 d14, d12 ; CHECK-NEXT: vmov.f32 s4, s8
; CHECK-NEXT: vstrw.32 q5, [r1] ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f32 s5, s9
; CHECK-NEXT: vmov.f32 s28, s24
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f32 s29, s25 ; CHECK-NEXT: vmov.f32 s29, s25
; CHECK-NEXT: vmov.f64 d8, d7
; CHECK-NEXT: vmov.f32 s30, s12 ; CHECK-NEXT: vmov.f32 s30, s12
; CHECK-NEXT: vmov.f32 s17, s15
; CHECK-NEXT: vmov.f32 s31, s13 ; CHECK-NEXT: vmov.f32 s31, s13
; CHECK-NEXT: vldrw.u32 q3, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vstrw.32 q7, [r1, #48]
; CHECK-NEXT: vmov.f32 s4, s8
; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmov.f32 s2, s26 ; CHECK-NEXT: vmov.f32 s2, s26
; CHECK-NEXT: vstrw.32 q4, [r1, #80] ; CHECK-NEXT: vstrw.32 q7, [r1, #48]
; CHECK-NEXT: vmov.f32 s5, s9
; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f32 s3, s27 ; CHECK-NEXT: vmov.f32 s3, s27
; CHECK-NEXT: vmov.f32 s9, s15 ; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vstrw.32 q0, [r1, #64] ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s9, s15
; CHECK-NEXT: vstrw.32 q2, [r1, #32] ; CHECK-NEXT: vstrw.32 q2, [r1, #32]
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x i64>, <4 x i64>* %src, i32 0 %s1 = getelementptr <4 x i64>, <4 x i64>* %src, i32 0
%l1 = load <4 x i64>, <4 x i64>* %s1, align 4 %l1 = load <4 x i64>, <4 x i64>* %s1, align 4
%s2 = getelementptr <4 x i64>, <4 x i64>* %src, i32 1 %s2 = getelementptr <4 x i64>, <4 x i64>* %src, i32 1
%l2 = load <4 x i64>, <4 x i64>* %s2, align 4 %l2 = load <4 x i64>, <4 x i64>* %s2, align 4
%s3 = getelementptr <4 x i64>, <4 x i64>* %src, i32 2 %s3 = getelementptr <4 x i64>, <4 x i64>* %src, i32 2
%l3 = load <4 x i64>, <4 x i64>* %s3, align 4 %l3 = load <4 x i64>, <4 x i64>* %s3, align 4
%t1 = shufflevector <4 x i64> %l1, <4 x i64> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x i64> %l1, <4 x i64> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x i64> %l3, <4 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x i64> %l3, <4 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x i64> %t1, <8 x i64> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x i64> %t1, <8 x i64> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x i64> %s, <12 x i64> *%dst store <12 x i64> %s, <12 x i64> *%dst
ret void ret void
} }
; f32 ; f32
define void @vst3_v2f32(<2 x float> *%src, <6 x float> *%dst) { define void @vst3_v2f32(<2 x float> *%src, <6 x float> *%dst) {
; CHECK-LABEL: vst3_v2f32: ; CHECK-LABEL: vst3_v2f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldr r2, [r0, #20]
; CHECK-NEXT: vldr s0, [r0] ; CHECK-NEXT: vldr s0, [r0]
; CHECK-NEXT: vldr s3, [r0, #4] ; CHECK-NEXT: vldr s3, [r0, #4]
; CHECK-NEXT: vldr s1, [r0, #8] ; CHECK-NEXT: vldr s1, [r0, #8]
; CHECK-NEXT: ldr r2, [r0, #20]
; CHECK-NEXT: vldr s2, [r0, #16] ; CHECK-NEXT: vldr s2, [r0, #16]
; CHECK-NEXT: ldr r0, [r0, #12] ; CHECK-NEXT: ldr r0, [r0, #12]
; CHECK-NEXT: strd r0, r2, [r1, #16] ; CHECK-NEXT: strd r0, r2, [r1, #16]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x float>, <2 x float>* %src, i32 0 %s1 = getelementptr <2 x float>, <2 x float>* %src, i32 0
%l1 = load <2 x float>, <2 x float>* %s1, align 4 %l1 = load <2 x float>, <2 x float>* %s1, align 4
%s2 = getelementptr <2 x float>, <2 x float>* %src, i32 1 %s2 = getelementptr <2 x float>, <2 x float>* %src, i32 1
%l2 = load <2 x float>, <2 x float>* %s2, align 4 %l2 = load <2 x float>, <2 x float>* %s2, align 4
%s3 = getelementptr <2 x float>, <2 x float>* %src, i32 2 %s3 = getelementptr <2 x float>, <2 x float>* %src, i32 2
%l3 = load <2 x float>, <2 x float>* %s3, align 4 %l3 = load <2 x float>, <2 x float>* %s3, align 4
%t1 = shufflevector <2 x float> %l1, <2 x float> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t1 = shufflevector <2 x float> %l1, <2 x float> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%t2 = shufflevector <2 x float> %l3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %t2 = shufflevector <2 x float> %l3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%s = shufflevector <4 x float> %t1, <4 x float> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> %s = shufflevector <4 x float> %t1, <4 x float> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
store <6 x float> %s, <6 x float> *%dst store <6 x float> %s, <6 x float> *%dst
ret void ret void
} }
define void @vst3_v4f32(<4 x float> *%src, <12 x float> *%dst) { define void @vst3_v4f32(<4 x float> *%src, <12 x float> *%dst) {
; CHECK-LABEL: vst3_v4f32: ; CHECK-LABEL: vst3_v4f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmov.f64 d8, d6
; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f32 s19, s13
; CHECK-NEXT: vmov.f32 s9, s5 ; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov.f32 s18, s4 ; CHECK-NEXT: vmov.f32 s18, s4
; CHECK-NEXT: vmov.f32 s4, s6 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f32 s11, s2 ; CHECK-NEXT: vmov.f32 s11, s2
; CHECK-NEXT: vmov.f32 s5, s15
; CHECK-NEXT: vmov.f32 s10, s14 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s6, s3 ; CHECK-NEXT: vmov.f32 s16, s12
; CHECK-NEXT: vstrw.32 q2, [r1, #16] ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov.f32 s19, s13
; CHECK-NEXT: vmov.f32 s5, s15
; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0 %s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0
%l1 = load <4 x float>, <4 x float>* %s1, align 4 %l1 = load <4 x float>, <4 x float>* %s1, align 4
%s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1 %s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1
%l2 = load <4 x float>, <4 x float>* %s2, align 4 %l2 = load <4 x float>, <4 x float>* %s2, align 4
%s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2 %s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2
%l3 = load <4 x float>, <4 x float>* %s3, align 4 %l3 = load <4 x float>, <4 x float>* %s3, align 4
%t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x float> %l3, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x float> %l3, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x float> %t1, <8 x float> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x float> %t1, <8 x float> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x float> %s, <12 x float> *%dst store <12 x float> %s, <12 x float> *%dst
ret void ret void
} }
define void @vst3_v8f32(<8 x float> *%src, <24 x float> *%dst) { define void @vst3_v8f32(<8 x float> *%src, <24 x float> *%dst) {
; CHECK-LABEL: vst3_v8f32: ; CHECK-LABEL: vst3_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q6, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vmov.f64 d10, d8 ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vldrw.u32 q7, [r0, #48] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vstrw.32 q6, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q6, [sp] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #64] ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vmov.f32 s21, s24 ; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vmov.f64 d12, d4 ; CHECK-NEXT: vmov.f32 s20, s24
; CHECK-NEXT: vmov.f64 d6, d1 ; CHECK-NEXT: vmov.f32 s13, s19
; CHECK-NEXT: vmov.f32 s25, s28 ; CHECK-NEXT: vmov.f32 s24, s16
; CHECK-NEXT: vmov.f32 s13, s11 ; CHECK-NEXT: vmov.f32 s27, s17
; CHECK-NEXT: vmov.f32 s27, s9 ; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vldrw.u32 q4, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s15, s3 ; CHECK-NEXT: vmov.f32 s15, s3
; CHECK-NEXT: vmov.f32 s14, s11
; CHECK-NEXT: vmov.f32 s23, s25
; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vmov.f32 s21, s28
; CHECK-NEXT: vmov.f32 s25, s8
; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f32 s26, s0 ; CHECK-NEXT: vmov.f32 s26, s0
; CHECK-NEXT: vmov.f32 s0, s29 ; CHECK-NEXT: vmov.f32 s0, s9
; CHECK-NEXT: vstrw.32 q6, [r1, #48] ; CHECK-NEXT: vstrw.32 q6, [r1, #48]
; CHECK-NEXT: vmov.f32 s3, s30 ; CHECK-NEXT: vmov.f32 s3, s10
; CHECK-NEXT: vmov.f32 s14, s31
; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vmov.f32 s8, s29
; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s9, s5 ; CHECK-NEXT: vmov.f32 s9, s5
; CHECK-NEXT: vmov.f32 s22, s4 ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s4, s6 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vstrw.32 q5, [r1] ; CHECK-NEXT: vmov.f32 s8, s29
; CHECK-NEXT: vmov.f32 s11, s30 ; CHECK-NEXT: vmov.f32 s11, s30
; CHECK-NEXT: vmov.f32 s5, s19
; CHECK-NEXT: vmov.f32 s10, s18 ; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vmov.f32 s6, s31 ; CHECK-NEXT: vmov.f32 s5, s19
; CHECK-NEXT: vstrw.32 q2, [r1, #16] ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s6, s31
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x float>, <8 x float>* %src, i32 0 %s1 = getelementptr <8 x float>, <8 x float>* %src, i32 0
%l1 = load <8 x float>, <8 x float>* %s1, align 4 %l1 = load <8 x float>, <8 x float>* %s1, align 4
%s2 = getelementptr <8 x float>, <8 x float>* %src, i32 1 %s2 = getelementptr <8 x float>, <8 x float>* %src, i32 1
%l2 = load <8 x float>, <8 x float>* %s2, align 4 %l2 = load <8 x float>, <8 x float>* %s2, align 4
%s3 = getelementptr <8 x float>, <8 x float>* %src, i32 2 %s3 = getelementptr <8 x float>, <8 x float>* %src, i32 2
%l3 = load <8 x float>, <8 x float>* %s3, align 4 %l3 = load <8 x float>, <8 x float>* %s3, align 4
%t1 = shufflevector <8 x float> %l1, <8 x float> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x float> %l1, <8 x float> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x float> %l3, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x float> %l3, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x float> %t1, <16 x float> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x float> %t1, <16 x float> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x float> %s, <24 x float> *%dst store <24 x float> %s, <24 x float> *%dst
ret void ret void
} }
define void @vst3_v16f32(<16 x float> *%src, <48 x float> *%dst) { define void @vst3_v16f32(<16 x float> *%src, <48 x float> *%dst) {
; CHECK-LABEL: vst3_v16f32: ; CHECK-LABEL: vst3_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #160 ; CHECK-NEXT: .pad #144
; CHECK-NEXT: sub sp, #160 ; CHECK-NEXT: sub sp, #144
; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q5, [r0, #112] ; CHECK-NEXT: vldrw.u32 q5, [r0, #112]
; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #128] ; CHECK-NEXT: vldrw.u32 q2, [r0, #128]
; CHECK-NEXT: vstrw.32 q5, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vldrw.u32 q6, [r0] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vstrw.32 q7, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vldrw.u32 q7, [r0, #16]
; CHECK-NEXT: vldrw.u32 q4, [r0, #160]
; CHECK-NEXT: vstrw.32 q5, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s12, s1 ; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vstrw.32 q5, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vmov.f32 s13, s9 ; CHECK-NEXT: vmov.f32 s13, s9
; CHECK-NEXT: vmov.f32 s15, s2 ; CHECK-NEXT: vmov.f32 s15, s2
; CHECK-NEXT: vldrw.u32 q4, [r0, #160] ; CHECK-NEXT: vldrw.u32 q1, [r0, #176]
; CHECK-NEXT: vstrw.32 q5, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vmov.f32 s14, s26 ; CHECK-NEXT: vmov.f32 s14, s26
; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vldrw.u32 q7, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q4, [sp, #128] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q4, [r0, #144] ; CHECK-NEXT: vldrw.u32 q4, [r0, #144]
; CHECK-NEXT: vstrw.32 q5, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q7, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #176]
; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vstrw.32 q3, [r1, #16] ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vmov.f64 d6, d5 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vstrw.32 q7, [sp, #144] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s12, s10
; CHECK-NEXT: vldrw.u32 q7, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q4, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s13, s27 ; CHECK-NEXT: vmov.f32 s13, s27
; CHECK-NEXT: vmov.f32 s15, s11 ; CHECK-NEXT: vmov.f32 s15, s11
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vstrw.32 q3, [r1, #32] ; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vmov.f64 d6, d3
; CHECK-NEXT: vmov.f32 s13, s23 ; CHECK-NEXT: vmov.f32 s13, s23
; CHECK-NEXT: vmov.f32 s12, s6
; CHECK-NEXT: vmov.f32 s15, s7 ; CHECK-NEXT: vmov.f32 s15, s7
; CHECK-NEXT: vmov.f32 s14, s31 ; CHECK-NEXT: vmov.f32 s14, s31
; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d6, d12
; CHECK-NEXT: vmov.f32 s13, s0 ; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s15, s25
; CHECK-NEXT: vmov.f32 s14, s8 ; CHECK-NEXT: vmov.f32 s14, s8
; CHECK-NEXT: vmov q2, q7 ; CHECK-NEXT: vmov.f64 d4, d14
; CHECK-NEXT: vmov.f64 d0, d10 ; CHECK-NEXT: vmov.f32 s0, s20
; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.f32 s3, s21 ; CHECK-NEXT: vmov.f32 s3, s21
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f64 d10, d2
; CHECK-NEXT: vmov.f32 s4, s9 ; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s20
; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.f64 d14, d2
; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s22 ; CHECK-NEXT: vmov.f32 s20, s9
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s23, s30
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f32 s12, s24
; CHECK-NEXT: vmov q3, q1 ; CHECK-NEXT: vstrw.32 q5, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s20, s5 ; CHECK-NEXT: vmov.f32 s15, s25
; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s21, s1 ; CHECK-NEXT: vmov.f32 s21, s1
; CHECK-NEXT: vmov.f32 s23, s6 ; CHECK-NEXT: vmov.f32 s12, s2
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s15, s3
; CHECK-NEXT: vmov.f64 d12, d9 ; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vmov q7, q1 ; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s9, s7 ; CHECK-NEXT: vmov.f64 d0, d14
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vldrw.u32 q4, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov q0, q7
; CHECK-NEXT: vmov.f32 s25, s7
; CHECK-NEXT: vstrw.32 q5, [r1, #112]
; CHECK-NEXT: vmov.f32 s27, s19
; CHECK-NEXT: vldrw.u32 q4, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vldrw.u32 q3, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s29, s16
; CHECK-NEXT: vldrw.u32 q4, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s31, s1 ; CHECK-NEXT: vmov.f32 s31, s1
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vmov.f64 d0, d8
; CHECK-NEXT: vmov.f32 s26, s15 ; CHECK-NEXT: vmov.f32 s20, s9
; CHECK-NEXT: vstrw.32 q2, [r1, #128] ; CHECK-NEXT: vmov.f32 s23, s10
; CHECK-NEXT: vmov.f32 s30, s0 ; CHECK-NEXT: vmov.f32 s14, s11
; CHECK-NEXT: vstrw.32 q6, [r1, #80] ; CHECK-NEXT: vmov.f32 s29, s8
; CHECK-NEXT: vmov.f64 d0, d2 ; CHECK-NEXT: vldrw.u32 q2, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s24, s2
; CHECK-NEXT: vmov.f32 s30, s8
; CHECK-NEXT: vmov.f32 s27, s3
; CHECK-NEXT: vstrw.32 q7, [r1, #96] ; CHECK-NEXT: vstrw.32 q7, [r1, #96]
; CHECK-NEXT: vmov.f32 s1, s12 ; CHECK-NEXT: vmov.f32 s8, s0
; CHECK-NEXT: vmov.f32 s3, s5 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s16 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vstrw.32 q0, [r1, #48] ; CHECK-NEXT: vmov.f64 d8, d0
; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s16, s13 ; CHECK-NEXT: vstrw.32 q5, [r1, #112]
; CHECK-NEXT: vstrw.32 q0, [r1, #144] ; CHECK-NEXT: vstrw.32 q0, [r1, #144]
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vstrw.32 q0, [r1, #160] ; CHECK-NEXT: vstrw.32 q0, [r1, #160]
; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s6 ; CHECK-NEXT: vmov.f32 s13, s7
; CHECK-NEXT: vldrw.u32 q1, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1, #176] ; CHECK-NEXT: vstrw.32 q0, [r1, #176]
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q4, [r1, #64] ; CHECK-NEXT: vmov.f32 s25, s19
; CHECK-NEXT: vstrw.32 q3, [r1, #128]
; CHECK-NEXT: vmov.f32 s26, s7
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #160 ; CHECK-NEXT: vmov.f32 s10, s16
; CHECK-NEXT: vstrw.32 q6, [r1, #80]
; CHECK-NEXT: vmov.f32 s9, s4
; CHECK-NEXT: vmov.f32 s16, s5
; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s19, s6
; CHECK-NEXT: vstrw.32 q4, [r1, #64]
; CHECK-NEXT: add sp, #144
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0 %s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0
%l1 = load <16 x float>, <16 x float>* %s1, align 4 %l1 = load <16 x float>, <16 x float>* %s1, align 4
%s2 = getelementptr <16 x float>, <16 x float>* %src, i32 1 %s2 = getelementptr <16 x float>, <16 x float>* %src, i32 1
%l2 = load <16 x float>, <16 x float>* %s2, align 4 %l2 = load <16 x float>, <16 x float>* %s2, align 4
%s3 = getelementptr <16 x float>, <16 x float>* %src, i32 2 %s3 = getelementptr <16 x float>, <16 x float>* %src, i32 2
%l3 = load <16 x float>, <16 x float>* %s3, align 4 %l3 = load <16 x float>, <16 x float>* %s3, align 4
%t1 = shufflevector <16 x float> %l1, <16 x float> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %t1 = shufflevector <16 x float> %l1, <16 x float> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%t2 = shufflevector <16 x float> %l3, <16 x float> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <16 x float> %l3, <16 x float> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <32 x float> %t1, <32 x float> %t2, <48 x i32> <i32 0, i32 16, i32 32, i32 1, i32 17, i32 33, i32 2, i32 18, i32 34, i32 3, i32 19, i32 35, i32 4, i32 20, i32 36, i32 5, i32 21, i32 37, i32 6, i32 22, i32 38, i32 7, i32 23, i32 39, i32 8, i32 24, i32 40, i32 9, i32 25, i32 41, i32 10, i32 26, i32 42, i32 11, i32 27, i32 43, i32 12, i32 28, i32 44, i32 13, i32 29, i32 45, i32 14, i32 30, i32 46, i32 15, i32 31, i32 47> %s = shufflevector <32 x float> %t1, <32 x float> %t2, <48 x i32> <i32 0, i32 16, i32 32, i32 1, i32 17, i32 33, i32 2, i32 18, i32 34, i32 3, i32 19, i32 35, i32 4, i32 20, i32 36, i32 5, i32 21, i32 37, i32 6, i32 22, i32 38, i32 7, i32 23, i32 39, i32 8, i32 24, i32 40, i32 9, i32 25, i32 41, i32 10, i32 26, i32 42, i32 11, i32 27, i32 43, i32 12, i32 28, i32 44, i32 13, i32 29, i32 45, i32 14, i32 30, i32 46, i32 15, i32 31, i32 47>
store <48 x float> %s, <48 x float> *%dst store <48 x float> %s, <48 x float> *%dst
ret void ret void
} }
; f16 ; f16
define void @vst3_v2f16(<2 x half> *%src, <6 x half> *%dst) { define void @vst3_v2f16(<2 x half> *%src, <6 x half> *%dst) {
; CHECK-LABEL: vst3_v2f16: ; CHECK-LABEL: vst3_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldmia r0, {s0, s1} ; CHECK-NEXT: vldmia r0, {s0, s1}
; CHECK-NEXT: ldr r0, [r0, #8] ; CHECK-NEXT: ldr r0, [r0, #8]
; CHECK-NEXT: vmovx.f16 s8, s0 ; CHECK-NEXT: vmovx.f16 s2, s0
; CHECK-NEXT: vins.f16 s0, s1 ; CHECK-NEXT: vins.f16 s0, s1
; CHECK-NEXT: vmov.32 q1[0], r0 ; CHECK-NEXT: vmov.32 q1[0], r0
; CHECK-NEXT: vmovx.f16 s6, s4
; CHECK-NEXT: vins.f16 s4, s2
; CHECK-NEXT: vmovx.f16 s2, s1 ; CHECK-NEXT: vmovx.f16 s2, s1
; CHECK-NEXT: vmovx.f16 s10, s4
; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vins.f16 s2, s10
; CHECK-NEXT: vmov.f32 s1, s4 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vins.f16 s2, s6
; CHECK-NEXT: vmov r3, s2 ; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov r0, r2, d0 ; CHECK-NEXT: vmov r0, r2, d0
; CHECK-NEXT: stm r1!, {r0, r2, r3} ; CHECK-NEXT: stm r1!, {r0, r2, r3}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0 %s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0
%l1 = load <2 x half>, <2 x half>* %s1, align 4 %l1 = load <2 x half>, <2 x half>* %s1, align 4
%s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1 %s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1
%l2 = load <2 x half>, <2 x half>* %s2, align 4 %l2 = load <2 x half>, <2 x half>* %s2, align 4
%s3 = getelementptr <2 x half>, <2 x half>* %src, i32 2 %s3 = getelementptr <2 x half>, <2 x half>* %src, i32 2
%l3 = load <2 x half>, <2 x half>* %s3, align 4 %l3 = load <2 x half>, <2 x half>* %s3, align 4
%t1 = shufflevector <2 x half> %l1, <2 x half> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t1 = shufflevector <2 x half> %l1, <2 x half> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%t2 = shufflevector <2 x half> %l3, <2 x half> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %t2 = shufflevector <2 x half> %l3, <2 x half> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%s = shufflevector <4 x half> %t1, <4 x half> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> %s = shufflevector <4 x half> %t1, <4 x half> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
store <6 x half> %s, <6 x half> *%dst store <6 x half> %s, <6 x half> *%dst
ret void ret void
} }
define void @vst3_v4f16(<4 x half> *%src, <12 x half> *%dst) { define void @vst3_v4f16(<4 x half> *%src, <12 x half> *%dst) {
; CHECK-LABEL: vst3_v4f16: ; CHECK-LABEL: vst3_v4f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: ldrd r2, r12, [r0] ; CHECK-NEXT: ldrd r2, r12, [r0]
; CHECK-NEXT: ldrd r3, lr, [r0, #8] ; CHECK-NEXT: ldrd r3, lr, [r0, #8]
; CHECK-NEXT: vmov.32 q0[0], r2 ; CHECK-NEXT: vmov.32 q0[0], r2
; CHECK-NEXT: ldrd r2, r0, [r0, #16] ; CHECK-NEXT: ldrd r2, r0, [r0, #16]
; CHECK-NEXT: vmov.32 q1[0], r3 ; CHECK-NEXT: vmov.32 q1[0], r3
; CHECK-NEXT: vmov.32 q0[1], r12 ; CHECK-NEXT: vmov.32 q0[1], r12
; CHECK-NEXT: vmov.32 q1[1], lr ; CHECK-NEXT: vmov.32 q1[1], lr
; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmovx.f16 s10, s0
; CHECK-NEXT: vmov.f32 s8, s1 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vins.f16 s0, s2 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vins.f16 s8, s5 ; CHECK-NEXT: vins.f16 s8, s5
; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.32 q1[0], r2 ; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmov.32 q1[1], r0 ; CHECK-NEXT: vmov.32 q1[1], r0
; CHECK-NEXT: vmovx.f16 s13, s3
; CHECK-NEXT: vmovx.f16 s6, s0
; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmovx.f16 s10, s4
; CHECK-NEXT: vmovx.f16 s2, s2 ; CHECK-NEXT: vmovx.f16 s2, s2
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vins.f16 s4, s10 ; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vins.f16 s2, s12 ; CHECK-NEXT: vins.f16 s2, s10
; CHECK-NEXT: vmovx.f16 s10, s1 ; CHECK-NEXT: vmovx.f16 s10, s5
; CHECK-NEXT: vmovx.f16 s12, s5 ; CHECK-NEXT: vins.f16 s5, s6
; CHECK-NEXT: vmovx.f16 s17, s3 ; CHECK-NEXT: vins.f16 s13, s10
; CHECK-NEXT: vins.f16 s5, s10 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vins.f16 s17, s12
; CHECK-NEXT: vmov.f32 s16, s5
; CHECK-NEXT: vmov.f32 s1, s4 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vmov.f32 s3, s8 ; CHECK-NEXT: vmov.f32 s3, s8
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vmov r0, r2, d8 ; CHECK-NEXT: vmov r0, r2, d6
; CHECK-NEXT: strd r0, r2, [r1, #16] ; CHECK-NEXT: strd r0, r2, [r1, #16]
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0 %s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
%l1 = load <4 x half>, <4 x half>* %s1, align 4 %l1 = load <4 x half>, <4 x half>* %s1, align 4
%s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1 %s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1
%l2 = load <4 x half>, <4 x half>* %s2, align 4 %l2 = load <4 x half>, <4 x half>* %s2, align 4
%s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2 %s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2
%l3 = load <4 x half>, <4 x half>* %s3, align 4 %l3 = load <4 x half>, <4 x half>* %s3, align 4
%t1 = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x half> %l1, <4 x half> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x half> %l3, <4 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x half> %l3, <4 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x half> %t1, <8 x half> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x half> %t1, <8 x half> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x half> %s, <12 x half> *%dst store <12 x half> %s, <12 x half> *%dst
ret void ret void
} }
define void @vst3_v8f16(<8 x half> *%src, <24 x half> *%dst) { define void @vst3_v8f16(<8 x half> *%src, <24 x half> *%dst) {
; CHECK-LABEL: vst3_v8f16: ; CHECK-LABEL: vst3_v8f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vldrw.u32 q5, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f64 d0, d4 ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmovx.f16 s6, s20 ; CHECK-NEXT: vmov.f32 s0, s4
; CHECK-NEXT: vmovx.f16 s12, s8 ; CHECK-NEXT: vmovx.f16 s2, s12
; CHECK-NEXT: vmov.f32 s4, s9 ; CHECK-NEXT: vins.f16 s0, s12
; CHECK-NEXT: vins.f16 s0, s20 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vins.f16 s4, s21
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vmov.f32 s3, s4 ; CHECK-NEXT: vmovx.f16 s4, s4
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vmov.f32 s1, s16
; CHECK-NEXT: vmov.f32 s1, s8 ; CHECK-NEXT: vmovx.f16 s11, s15
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s8, s5
; CHECK-NEXT: vmovx.f16 s24, s7 ; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmov.f32 s18, s4 ; CHECK-NEXT: vmovx.f16 s4, s16
; CHECK-NEXT: vins.f16 s17, s12 ; CHECK-NEXT: vins.f16 s8, s13
; CHECK-NEXT: vmovx.f16 s12, s18 ; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vins.f16 s2, s12 ; CHECK-NEXT: vmovx.f16 s4, s19
; CHECK-NEXT: vmovx.f16 s15, s23 ; CHECK-NEXT: vmov.f32 s3, s8
; CHECK-NEXT: vins.f16 s15, s24 ; CHECK-NEXT: vins.f16 s11, s4
; CHECK-NEXT: vmovx.f16 s24, s6 ; CHECK-NEXT: vmovx.f16 s4, s18
; CHECK-NEXT: vmovx.f16 s12, s22 ; CHECK-NEXT: vmovx.f16 s8, s14
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vins.f16 s9, s15
; CHECK-NEXT: vins.f16 s12, s24 ; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmov.f32 s25, s11 ; CHECK-NEXT: vmovx.f16 s4, s9
; CHECK-NEXT: vins.f16 s13, s23 ; CHECK-NEXT: vmov.f32 s9, s7
; CHECK-NEXT: vmov.f32 s26, s11 ; CHECK-NEXT: vins.f16 s9, s4
; CHECK-NEXT: vmov.f32 s14, s7 ; CHECK-NEXT: vrev32.16 q3, q3
; CHECK-NEXT: vmovx.f16 s28, s13 ; CHECK-NEXT: vmov.f32 s10, s19
; CHECK-NEXT: vins.f16 s25, s28 ; CHECK-NEXT: vmovx.f16 s4, s7
; CHECK-NEXT: vmovx.f16 s28, s26 ; CHECK-NEXT: vins.f16 s10, s4
; CHECK-NEXT: vins.f16 s14, s28 ; CHECK-NEXT: vmovx.f16 s4, s5
; CHECK-NEXT: vmovx.f16 s28, s9 ; CHECK-NEXT: vmov.f32 s12, s17
; CHECK-NEXT: vmov.f32 s4, s5 ; CHECK-NEXT: vstrw.32 q2, [r1, #32]
; CHECK-NEXT: vrev32.16 q5, q5 ; CHECK-NEXT: vins.f16 s12, s4
; CHECK-NEXT: vins.f16 s4, s28 ; CHECK-NEXT: vmovx.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s28, s10 ; CHECK-NEXT: vins.f16 s18, s4
; CHECK-NEXT: vins.f16 s6, s28 ; CHECK-NEXT: vmovx.f16 s4, s17
; CHECK-NEXT: vmov.f32 s26, s14 ; CHECK-NEXT: vins.f16 s13, s4
; CHECK-NEXT: vmov.f32 s7, s6 ; CHECK-NEXT: vmovx.f16 s4, s14
; CHECK-NEXT: vmov.f32 s6, s10 ; CHECK-NEXT: vins.f16 s6, s4
; CHECK-NEXT: vmovx.f16 s8, s5 ; CHECK-NEXT: vmov.f32 s15, s18
; CHECK-NEXT: vins.f16 s21, s8 ; CHECK-NEXT: vmov.f32 s14, s6
; CHECK-NEXT: vmovx.f16 s8, s22
; CHECK-NEXT: vins.f16 s6, s8
; CHECK-NEXT: vmov.f32 s1, s17
; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s13, s25
; CHECK-NEXT: vmov.f32 s5, s21
; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vmov.f32 s14, s26
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vstrw.32 q3, [r1, #32] ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vmov.f32 s6, s22 ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0 %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
%l1 = load <8 x half>, <8 x half>* %s1, align 4 %l1 = load <8 x half>, <8 x half>* %s1, align 4
%s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1 %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
%l2 = load <8 x half>, <8 x half>* %s2, align 4 %l2 = load <8 x half>, <8 x half>* %s2, align 4
%s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2 %s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2
%l3 = load <8 x half>, <8 x half>* %s3, align 4 %l3 = load <8 x half>, <8 x half>* %s3, align 4
%t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x half> %l3, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x half> %l3, <8 x half> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x half> %t1, <16 x half> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x half> %t1, <16 x half> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x half> %s, <24 x half> *%dst store <24 x half> %s, <24 x half> *%dst
ret void ret void
} }
define void @vst3_v16f16(<16 x half> *%src, <48 x half> *%dst) { define void @vst3_v16f16(<16 x half> *%src, <48 x half> *%dst) {
; CHECK-LABEL: vst3_v16f16: ; CHECK-LABEL: vst3_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #128 ; CHECK-NEXT: .pad #96
; CHECK-NEXT: sub sp, #128 ; CHECK-NEXT: sub sp, #96
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vldrw.u32 q4, [r0, #64] ; CHECK-NEXT: vldrw.u32 q3, [r0, #64]
; CHECK-NEXT: vldrw.u32 q6, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vldrw.u32 q5, [r0, #16] ; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vmovx.f16 s0, s19 ; CHECK-NEXT: vmovx.f16 s0, s15
; CHECK-NEXT: vmovx.f16 s7, s15 ; CHECK-NEXT: vmovx.f16 s7, s11
; CHECK-NEXT: vins.f16 s7, s0 ; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vmovx.f16 s0, s18 ; CHECK-NEXT: vmov q6, q2
; CHECK-NEXT: vmovx.f16 s4, s14 ; CHECK-NEXT: vmovx.f16 s0, s14
; CHECK-NEXT: vstrw.32 q5, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vmovx.f16 s4, s10
; CHECK-NEXT: vins.f16 s1, s11
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vins.f16 s4, s0 ; CHECK-NEXT: vins.f16 s4, s0
; CHECK-NEXT: vmov.f64 d14, d12 ; CHECK-NEXT: vmovx.f16 s0, s1
; CHECK-NEXT: vins.f16 s5, s15 ; CHECK-NEXT: vstrw.32 q1, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s5, s11
; CHECK-NEXT: vmov.f32 s6, s19
; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmov.f32 s5, s27
; CHECK-NEXT: vmov.f32 s6, s27
; CHECK-NEXT: vins.f16 s28, s12
; CHECK-NEXT: vins.f16 s5, s0 ; CHECK-NEXT: vins.f16 s5, s0
; CHECK-NEXT: vmovx.f16 s0, s6 ; CHECK-NEXT: vmov.f32 s6, s15
; CHECK-NEXT: vins.f16 s10, s0 ; CHECK-NEXT: vmovx.f16 s0, s11
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov q7, q4
; CHECK-NEXT: vmov.f64 d2, d10
; CHECK-NEXT: vstrw.32 q2, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vmovx.f16 s2, s8
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s0, s21
; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vins.f16 s0, s9
; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmovx.f16 s2, s12
; CHECK-NEXT: vmov.f32 s7, s0
; CHECK-NEXT: vmovx.f16 s0, s20
; CHECK-NEXT: vmov.f32 s5, s20
; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.f32 s9, s20
; CHECK-NEXT: vmov.16 q7[4], r0
; CHECK-NEXT: vmov.f32 s10, s20
; CHECK-NEXT: vins.f16 s9, s0
; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vins.f16 s6, s0 ; CHECK-NEXT: vins.f16 s6, s0
; CHECK-NEXT: vmov.f32 s0, s25 ; CHECK-NEXT: vmovx.f16 s2, s20
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov q2, q4 ; CHECK-NEXT: vmov.f32 s4, s16
; CHECK-NEXT: vins.f16 s0, s13 ; CHECK-NEXT: vins.f16 s4, s20
; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: vmov.f32 s5, s8 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vstrw.32 q7, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s16, s4
; CHECK-NEXT: vmovx.f16 s4, s28
; CHECK-NEXT: vldrw.u32 q7, [r0, #80]
; CHECK-NEXT: vmov.16 q4[4], r2
; CHECK-NEXT: vins.f16 s0, s21
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s19, s0
; CHECK-NEXT: vmovx.f16 s0, s28
; CHECK-NEXT: vins.f16 s18, s0
; CHECK-NEXT: vmov.f64 d0, d4
; CHECK-NEXT: vstrw.32 q6, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s20, s8
; CHECK-NEXT: vmovx.f16 s8, s24
; CHECK-NEXT: vmov.f32 s22, s28
; CHECK-NEXT: vins.f16 s20, s24
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.f32 s17, s28
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vins.f16 s17, s4
; CHECK-NEXT: vmov.f32 s4, s9
; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s0, s0
; CHECK-NEXT: vmov.f32 s21, s12
; CHECK-NEXT: vmovx.f16 s24, s10
; CHECK-NEXT: vins.f16 s21, s0
; CHECK-NEXT: vmovx.f16 s0, s12
; CHECK-NEXT: vins.f16 s22, s0
; CHECK-NEXT: vmovx.f16 s0, s30
; CHECK-NEXT: vins.f16 s24, s0
; CHECK-NEXT: vmovx.f16 s0, s31
; CHECK-NEXT: vmovx.f16 s27, s11
; CHECK-NEXT: vins.f16 s4, s25
; CHECK-NEXT: vins.f16 s27, s0
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vins.f16 s25, s11
; CHECK-NEXT: vmov.f32 s23, s4
; CHECK-NEXT: vmovx.f16 s4, s25
; CHECK-NEXT: vmov.f32 s25, s3
; CHECK-NEXT: vmov.f32 s26, s31
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vins.f16 s25, s4
; CHECK-NEXT: vins.f16 s26, s0
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vmov.f32 s0, s29
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vins.f16 s30, s4
; CHECK-NEXT: vmov.f32 s6, s18
; CHECK-NEXT: vrev32.16 q2, q2
; CHECK-NEXT: vmovx.f16 s4, s29
; CHECK-NEXT: vmov.f32 s3, s30
; CHECK-NEXT: vldrw.u32 q7, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vins.f16 s9, s4
; CHECK-NEXT: vmovx.f16 s4, s10
; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s29
; CHECK-NEXT: vmov.f32 s8, s13
; CHECK-NEXT: vstrw.32 q6, [r1, #80]
; CHECK-NEXT: vins.f16 s8, s4
; CHECK-NEXT: vmovx.f16 s4, s30
; CHECK-NEXT: vins.f16 s14, s4
; CHECK-NEXT: vmov.f32 s10, s30
; CHECK-NEXT: vmov.f32 s11, s14
; CHECK-NEXT: vmovx.f16 s4, s13
; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s31, s0 ; CHECK-NEXT: vldrw.u32 q7, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmovx.f16 s0, s24 ; CHECK-NEXT: vmov.f32 s18, s6
; CHECK-NEXT: vmov.f32 s6, s8 ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vins.f16 s5, s0 ; CHECK-NEXT: vrev32.16 q3, q3
; CHECK-NEXT: vmov.f32 s29, s24 ; CHECK-NEXT: vmov.f32 s6, s30
; CHECK-NEXT: vmovx.f16 s0, s6 ; CHECK-NEXT: vldrw.u32 q7, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vins.f16 s13, s4
; CHECK-NEXT: vins.f16 s30, s0
; CHECK-NEXT: vmovx.f16 s0, s22
; CHECK-NEXT: vmovx.f16 s4, s14 ; CHECK-NEXT: vmovx.f16 s4, s14
; CHECK-NEXT: vmov.f32 s8, s9 ; CHECK-NEXT: vmov.f32 s1, s9
; CHECK-NEXT: vins.f16 s4, s0 ; CHECK-NEXT: vins.f16 s10, s4
; CHECK-NEXT: vmovx.f16 s0, s23 ; CHECK-NEXT: vmov.f32 s9, s13
; CHECK-NEXT: vmovx.f16 s7, s15 ; CHECK-NEXT: vmov.f32 s4, s28
; CHECK-NEXT: vins.f16 s7, s0
; CHECK-NEXT: vins.f16 s5, s15
; CHECK-NEXT: vldrw.u32 q3, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s23
; CHECK-NEXT: vmovx.f16 s16, s5
; CHECK-NEXT: vmov.f32 s1, s15
; CHECK-NEXT: vmov.f32 s2, s15
; CHECK-NEXT: vins.f16 s1, s16
; CHECK-NEXT: vmovx.f16 s16, s2
; CHECK-NEXT: vins.f16 s6, s16
; CHECK-NEXT: vmovx.f16 s16, s13
; CHECK-NEXT: vmov.f32 s20, s21
; CHECK-NEXT: vins.f16 s20, s16
; CHECK-NEXT: vmovx.f16 s16, s14
; CHECK-NEXT: vins.f16 s22, s16
; CHECK-NEXT: vldrw.u32 q4, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q3, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s23, s22
; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: vstrw.32 q3, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s30
; CHECK-NEXT: vstrw.32 q3, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vmov.f32 s22, s14
; CHECK-NEXT: vmovx.f16 s12, s21
; CHECK-NEXT: vstr s12, [sp, #64] @ 4-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vrev32.16 q4, q3
; CHECK-NEXT: vldr s12, [sp, #64] @ 4-byte Reload
; CHECK-NEXT: vins.f16 s17, s12
; CHECK-NEXT: vmovx.f16 s12, s18
; CHECK-NEXT: vins.f16 s22, s12
; CHECK-NEXT: vmovx.f16 s12, s25
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vins.f16 s8, s12
; CHECK-NEXT: vmovx.f16 s0, s26
; CHECK-NEXT: vmov.f32 s18, s22
; CHECK-NEXT: vins.f16 s10, s0
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s11, s10
; CHECK-NEXT: vstrw.32 q1, [r1, #80]
; CHECK-NEXT: vmov.f32 s10, s26
; CHECK-NEXT: vrev32.16 q6, q0
; CHECK-NEXT: vmovx.f16 s12, s9
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vins.f16 s25, s12
; CHECK-NEXT: vmovx.f16 s12, s26
; CHECK-NEXT: vins.f16 s10, s12
; CHECK-NEXT: vmov.f32 s29, s1
; CHECK-NEXT: vldrw.u32 q3, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s26, s10
; CHECK-NEXT: vmov.f32 s1, s13
; CHECK-NEXT: vstrw.32 q7, [r1]
; CHECK-NEXT: vmov.f32 s2, s14
; CHECK-NEXT: vldrw.u32 q3, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s14
; CHECK-NEXT: vmov.f32 s13, s1
; CHECK-NEXT: vmov.f32 s21, s17
; CHECK-NEXT: vmov.f32 s9, s25
; CHECK-NEXT: vmov.f32 s22, s18
; CHECK-NEXT: vmov.f32 s10, s26
; CHECK-NEXT: vstrw.32 q5, [r1, #64]
; CHECK-NEXT: vstrw.32 q2, [r1, #16] ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s14, s2 ; CHECK-NEXT: vmov.f32 s7, s31
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q4, [r1, #48]
; CHECK-NEXT: vstrw.32 q3, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vstrw.32 q0, [r1, #48] ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: add sp, #128 ; CHECK-NEXT: add sp, #96
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0 %s1 = getelementptr <16 x half>, <16 x half>* %src, i32 0
%l1 = load <16 x half>, <16 x half>* %s1, align 4 %l1 = load <16 x half>, <16 x half>* %s1, align 4
%s2 = getelementptr <16 x half>, <16 x half>* %src, i32 1 %s2 = getelementptr <16 x half>, <16 x half>* %src, i32 1
%l2 = load <16 x half>, <16 x half>* %s2, align 4 %l2 = load <16 x half>, <16 x half>* %s2, align 4
%s3 = getelementptr <16 x half>, <16 x half>* %src, i32 2 %s3 = getelementptr <16 x half>, <16 x half>* %src, i32 2
%l3 = load <16 x half>, <16 x half>* %s3, align 4 %l3 = load <16 x half>, <16 x half>* %s3, align 4
%t1 = shufflevector <16 x half> %l1, <16 x half> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %t1 = shufflevector <16 x half> %l1, <16 x half> %l2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%t2 = shufflevector <16 x half> %l3, <16 x half> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <16 x half> %l3, <16 x half> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <32 x half> %t1, <32 x half> %t2, <48 x i32> <i32 0, i32 16, i32 32, i32 1, i32 17, i32 33, i32 2, i32 18, i32 34, i32 3, i32 19, i32 35, i32 4, i32 20, i32 36, i32 5, i32 21, i32 37, i32 6, i32 22, i32 38, i32 7, i32 23, i32 39, i32 8, i32 24, i32 40, i32 9, i32 25, i32 41, i32 10, i32 26, i32 42, i32 11, i32 27, i32 43, i32 12, i32 28, i32 44, i32 13, i32 29, i32 45, i32 14, i32 30, i32 46, i32 15, i32 31, i32 47> %s = shufflevector <32 x half> %t1, <32 x half> %t2, <48 x i32> <i32 0, i32 16, i32 32, i32 1, i32 17, i32 33, i32 2, i32 18, i32 34, i32 3, i32 19, i32 35, i32 4, i32 20, i32 36, i32 5, i32 21, i32 37, i32 6, i32 22, i32 38, i32 7, i32 23, i32 39, i32 8, i32 24, i32 40, i32 9, i32 25, i32 41, i32 10, i32 26, i32 42, i32 11, i32 27, i32 43, i32 12, i32 28, i32 44, i32 13, i32 29, i32 45, i32 14, i32 30, i32 46, i32 15, i32 31, i32 47>
store <48 x half> %s, <48 x half> *%dst store <48 x half> %s, <48 x half> *%dst
ret void ret void
} }
; f64 ; f64
define void @vst3_v2f64(<2 x double> *%src, <6 x double> *%dst) { define void @vst3_v2f64(<2 x double> *%src, <6 x double> *%dst) {
; CHECK-LABEL: vst3_v2f64: ; CHECK-LABEL: vst3_v2f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.f64 d6, d2 ; CHECK-NEXT: vmov.f64 d6, d2
; CHECK-NEXT: vmov.f64 d7, d1 ; CHECK-NEXT: vmov.f64 d7, d1
; CHECK-NEXT: vmov.f64 d1, d4 ; CHECK-NEXT: vmov.f64 d1, d4
; CHECK-NEXT: vstrw.32 q3, [r1, #16] ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vmov.f64 d2, d5 ; CHECK-NEXT: vmov.f64 d2, d5
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
Show All 12 Linesentry:
ret void ret void
} }
define void @vst3_v4f64(<4 x double> *%src, <12 x double> *%dst) { define void @vst3_v4f64(<4 x double> *%src, <12 x double> *%dst) {
; CHECK-LABEL: vst3_v4f64: ; CHECK-LABEL: vst3_v4f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q7, [r0, #48] ; CHECK-NEXT: vldrw.u32 q7, [r0, #48]
; CHECK-NEXT: vldrw.u32 q6, [r0, #32] ; CHECK-NEXT: vldrw.u32 q6, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vmov.f64 d6, d15 ; CHECK-NEXT: vmov.f64 d6, d15
; CHECK-NEXT: vstrw.32 q6, [sp] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q4, [r0, #64] ; CHECK-NEXT: vldrw.u32 q4, [r0, #64]
; CHECK-NEXT: vmov.f64 d10, d2 ; CHECK-NEXT: vmov.f64 d15, d13
; CHECK-NEXT: vmov.f64 d7, d1 ; CHECK-NEXT: vmov.f64 d7, d1
; CHECK-NEXT: vmov.f64 d11, d12 ; CHECK-NEXT: vmov.f64 d10, d2
; CHECK-NEXT: vstrw.32 q3, [r1, #80] ; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f64 d12, d4 ; CHECK-NEXT: vmov.f64 d11, d12
; CHECK-NEXT: vmov.f64 d2, d8
; CHECK-NEXT: vstrw.32 q5, [r1] ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f64 d1, d5 ; CHECK-NEXT: vmov.f64 d1, d5
; CHECK-NEXT: vldrw.u32 q2, [sp] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f64 d2, d8 ; CHECK-NEXT: vmov.f64 d8, d15
; CHECK-NEXT: vstrw.32 q0, [r1, #64] ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f64 d12, d4
; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: vmov.f64 d13, d14 ; CHECK-NEXT: vmov.f64 d13, d14
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f64 d8, d5
; CHECK-NEXT: vstrw.32 q6, [r1, #48] ; CHECK-NEXT: vstrw.32 q6, [r1, #48]
; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x double>, <4 x double>* %src, i32 0 %s1 = getelementptr <4 x double>, <4 x double>* %src, i32 0
%l1 = load <4 x double>, <4 x double>* %s1, align 4 %l1 = load <4 x double>, <4 x double>* %s1, align 4
%s2 = getelementptr <4 x double>, <4 x double>* %src, i32 1 %s2 = getelementptr <4 x double>, <4 x double>* %src, i32 1
%l2 = load <4 x double>, <4 x double>* %s2, align 4 %l2 = load <4 x double>, <4 x double>* %s2, align 4
%s3 = getelementptr <4 x double>, <4 x double>* %src, i32 2 %s3 = getelementptr <4 x double>, <4 x double>* %src, i32 2
%l3 = load <4 x double>, <4 x double>* %s3, align 4 %l3 = load <4 x double>, <4 x double>* %s3, align 4
%t1 = shufflevector <4 x double> %l1, <4 x double> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x double> %l1, <4 x double> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x double> %l3, <4 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x double> %l3, <4 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x double> %t1, <8 x double> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x double> %t1, <8 x double> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x double> %s, <12 x double> *%dst store <12 x double> %s, <12 x double> *%dst
ret void ret void
} }

llvm/test/CodeGen/Thumb2/mve-vst4-post.ll

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; i64 ; i64
define <8 x i64> *@vst4_v2i64(<2 x i64> *%src, <8 x i64> *%dst) { define <8 x i64> *@vst4_v2i64(<2 x i64> *%src, <8 x i64> *%dst) {
; CHECK-LABEL: vst4_v2i64: ; CHECK-LABEL: vst4_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vmov.f64 d4, d8 ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s8, s16
; CHECK-NEXT: vmov.f32 s9, s17 ; CHECK-NEXT: vmov.f32 s9, s17
; CHECK-NEXT: vmov.f32 s10, s0 ; CHECK-NEXT: vmov.f32 s10, s0
; CHECK-NEXT: vmov.f32 s11, s1 ; CHECK-NEXT: vmov.f32 s11, s1
; CHECK-NEXT: vmov.f32 s0, s18 ; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: vmov.f32 s1, s19 ; CHECK-NEXT: vmov.f32 s1, s19
; CHECK-NEXT: vmov.f64 d8, d6
; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vmov.f32 s17, s13
; CHECK-NEXT: vmov.f32 s18, s4 ; CHECK-NEXT: vmov.f32 s18, s4
; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vmov.f32 s19, s5 ; CHECK-NEXT: vmov.f32 s19, s5
; CHECK-NEXT: vmov.f32 s16, s12
; CHECK-NEXT: vmov.f32 s17, s13
; CHECK-NEXT: vmov.f32 s4, s14 ; CHECK-NEXT: vmov.f32 s4, s14
; CHECK-NEXT: vstrw.32 q4, [r1, #16] ; CHECK-NEXT: vstrw.32 q4, [r1, #16]
; CHECK-NEXT: vmov.f32 s5, s15 ; CHECK-NEXT: vmov.f32 s5, s15
; CHECK-NEXT: vstrw.32 q1, [r1, #48] ; CHECK-NEXT: vstrw.32 q1, [r1, #48]
; CHECK-NEXT: vstrw.32 q2, [r1], #64 ; CHECK-NEXT: vstrw.32 q2, [r1], #64
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; f64 ; f64
define <8 x double> *@vst4_v2f64(<2 x double> *%src, <8 x double> *%dst) { define <8 x double> *@vst4_v2f64(<2 x double> *%src, <8 x double> *%dst) {
; CHECK-LABEL: vst4_v2f64: ; CHECK-LABEL: vst4_v2f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #48] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vmov.f64 d2, d6 ; CHECK-NEXT: vmov.f64 d2, d6
; CHECK-NEXT: vmov.f64 d3, d0 ; CHECK-NEXT: vmov.f64 d3, d0
; CHECK-NEXT: vmov.f64 d0, d7 ; CHECK-NEXT: vmov.f64 d0, d7
; CHECK-NEXT: vmov.f64 d6, d8
; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vmov.f64 d7, d4 ; CHECK-NEXT: vmov.f64 d7, d4
; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vmov.f64 d6, d8
; CHECK-NEXT: vmov.f64 d4, d9 ; CHECK-NEXT: vmov.f64 d4, d9
; CHECK-NEXT: vstrw.32 q3, [r1, #16] ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vstrw.32 q1, [r1], #64 ; CHECK-NEXT: vstrw.32 q1, [r1], #64
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 15 Lines

llvm/test/CodeGen/Thumb2/mve-vst4.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s
; i32 ; i32
define void @vst4_v2i32(<2 x i32> *%src, <8 x i32> *%dst) { define void @vst4_v2i32(<2 x i32> *%src, <8 x i32> *%dst) {
; CHECK-LABEL: vst4_v2i32: ; CHECK-LABEL: vst4_v2i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: add.w r6, r0, #16 ; CHECK-NEXT: add.w r6, r0, #16
; CHECK-NEXT: ldrd lr, r12, [r0] ; CHECK-NEXT: ldrd lr, r12, [r0]
; CHECK-NEXT: ldrd r3, r2, [r0, #8] ; CHECK-NEXT: ldrd r3, r2, [r0, #8]
; CHECK-NEXT: ldm r6, {r4, r5, r6} ; CHECK-NEXT: ldm r6, {r4, r5, r6}
; CHECK-NEXT: vmov q1[2], q1[0], lr, r3 ; CHECK-NEXT: vmov q1[2], q1[0], lr, r3
; CHECK-NEXT: vmov q1[3], q1[1], r12, r2
; CHECK-NEXT: ldr r0, [r0, #28] ; CHECK-NEXT: ldr r0, [r0, #28]
; CHECK-NEXT: vmov q1[3], q1[1], r12, r2
; CHECK-NEXT: vmov q0[2], q0[0], r4, r6 ; CHECK-NEXT: vmov q0[2], q0[0], r4, r6
; CHECK-NEXT: vmov.f64 d4, d2 ; CHECK-NEXT: vmov.f32 s8, s4
; CHECK-NEXT: vmov q0[3], q0[1], r5, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r5, r0
; CHECK-NEXT: vmov.f32 s9, s6 ; CHECK-NEXT: vmov.f32 s9, s6
; CHECK-NEXT: vmov.f32 s4, s5
; CHECK-NEXT: vmov.f32 s5, s7
; CHECK-NEXT: vmov.f32 s10, s0 ; CHECK-NEXT: vmov.f32 s10, s0
; CHECK-NEXT: vmov.f32 s11, s2 ; CHECK-NEXT: vmov.f32 s11, s2
; CHECK-NEXT: vmov.f32 s6, s1
; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q2, [r1]
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s7, s3
; CHECK-NEXT: vmov.f32 s9, s7 ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f32 s10, s1
; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r6, pc}
entry: entry:
%s1 = getelementptr <2 x i32>, <2 x i32>* %src, i32 0 %s1 = getelementptr <2 x i32>, <2 x i32>* %src, i32 0
%l1 = load <2 x i32>, <2 x i32>* %s1, align 4 %l1 = load <2 x i32>, <2 x i32>* %s1, align 4
%s2 = getelementptr <2 x i32>, <2 x i32>* %src, i32 1 %s2 = getelementptr <2 x i32>, <2 x i32>* %src, i32 1
%l2 = load <2 x i32>, <2 x i32>* %s2, align 4 %l2 = load <2 x i32>, <2 x i32>* %s2, align 4
%s3 = getelementptr <2 x i32>, <2 x i32>* %src, i32 2 %s3 = getelementptr <2 x i32>, <2 x i32>* %src, i32 2
%l3 = load <2 x i32>, <2 x i32>* %s3, align 4 %l3 = load <2 x i32>, <2 x i32>* %s3, align 4
Show All 35 Lines
} }
define void @vst4_v8i32(<8 x i32> *%src, <32 x i32> *%dst) { define void @vst4_v8i32(<8 x i32> *%src, <32 x i32> *%dst) {
; CHECK-LABEL: vst4_v8i32: ; CHECK-LABEL: vst4_v8i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q7, [r0, #96] ; CHECK-NEXT: vldrw.u32 q7, [r0, #96]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vldrw.u32 q6, [r0, #64] ; CHECK-NEXT: vldrw.u32 q6, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]! ; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]!
; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]
Show All 20 Lines
; CHECK-LABEL: vst4_v16i32: ; CHECK-LABEL: vst4_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5} ; CHECK-NEXT: .save {r4, r5}
; CHECK-NEXT: push {r4, r5} ; CHECK-NEXT: push {r4, r5}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #192 ; CHECK-NEXT: .pad #192
; CHECK-NEXT: sub sp, #192 ; CHECK-NEXT: sub sp, #192
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q7, [r0, #240]
; CHECK-NEXT: vldrw.u32 q3, [r0, #208]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #64 ; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldrw.u32 q7, [r0, #224] ; CHECK-NEXT: vldrw.u32 q1, [r0, #80]
; CHECK-NEXT: vldrw.u32 q3, [r0, #208]
; CHECK-NEXT: vldrw.u32 q2, [r0, #144] ; CHECK-NEXT: vldrw.u32 q2, [r0, #144]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill ; CHECK-NEXT: vstmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q1, [r0, #80] ; CHECK-NEXT: vldrw.u32 q3, [r0, #192]
; CHECK-NEXT: vldrw.u32 q2, [r0, #128]
; CHECK-NEXT: vldrw.u32 q4, [r0, #240]
; CHECK-NEXT: vstmia r2, {d2, d3, d4, d5, d6, d7, d8, d9} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q6, [r0, #176] ; CHECK-NEXT: vldrw.u32 q6, [r0, #176]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldrw.u32 q6, [r0, #160]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill ; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q5, [r0, #112] ; CHECK-NEXT: vldrw.u32 q5, [r0, #112]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill ; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q4, [r0, #48] ; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill ; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [r0, #192] ; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
; CHECK-NEXT: vldrw.u32 q2, [r0, #128] ; CHECK-NEXT: vldrw.u32 q3, [r0, #224]
; CHECK-NEXT: vldrw.u32 q1, [r0, #96]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill ; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: vmov q6, q2
; CHECK-NEXT: vmov q7, q3
; CHECK-NEXT: vmov q5, q1
; CHECK-NEXT: vldmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #64 ; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: vldmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload
; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: add.w r0, r1, #192 ; CHECK-NEXT: add.w r0, r1, #192
; CHECK-NEXT: adds r1, #128 ; CHECK-NEXT: adds r1, #128
; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]
Show All 25 Linesentry:
ret void ret void
} }
define void @vst4_v4i32_align1(<4 x i32> *%src, <16 x i32> *%dst) { define void @vst4_v4i32_align1(<4 x i32> *%src, <16 x i32> *%dst) {
; CHECK-LABEL: vst4_v4i32_align1: ; CHECK-LABEL: vst4_v4i32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vmov.f32 s12, s17 ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmov.f64 d10, d8 ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.f32 s24, s19 ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vmov.f32 s13, s9
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s25, s11
; CHECK-NEXT: vmov.f32 s14, s1 ; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov.f32 s22, s0 ; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s26, s3 ; CHECK-NEXT: vmov.f32 s26, s3
; CHECK-NEXT: vmov.f32 s0, s18 ; CHECK-NEXT: vmov.f32 s12, s17
; CHECK-NEXT: vmov.f32 s1, s10 ; CHECK-NEXT: vmov.f32 s13, s9
; CHECK-NEXT: vmov.f32 s15, s5 ; CHECK-NEXT: vmov.f32 s15, s5
; CHECK-NEXT: vmov.f32 s23, s4 ; CHECK-NEXT: vmov.f32 s20, s16
; CHECK-NEXT: vstrb.8 q3, [r1, #16] ; CHECK-NEXT: vstrb.8 q3, [r1, #16]
; CHECK-NEXT: vmov.f32 s27, s7 ; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s23, s4
; CHECK-NEXT: vmov.f32 s24, s19
; CHECK-NEXT: vstrb.8 q5, [r1] ; CHECK-NEXT: vstrb.8 q5, [r1]
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s25, s11
; CHECK-NEXT: vmov.f32 s27, s7
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: vstrb.8 q6, [r1, #48] ; CHECK-NEXT: vstrb.8 q6, [r1, #48]
; CHECK-NEXT: vmov.f32 s1, s10
; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vstrb.8 q0, [r1, #32] ; CHECK-NEXT: vstrb.8 q0, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0 %s1 = getelementptr <4 x i32>, <4 x i32>* %src, i32 0
%l1 = load <4 x i32>, <4 x i32>* %s1, align 4 %l1 = load <4 x i32>, <4 x i32>* %s1, align 4
%s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1 %s2 = getelementptr <4 x i32>, <4 x i32>* %src, i32 1
%l2 = load <4 x i32>, <4 x i32>* %s2, align 4 %l2 = load <4 x i32>, <4 x i32>* %s2, align 4
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
} }
define void @vst4_v16i16(<16 x i16> *%src, <64 x i16> *%dst) { define void @vst4_v16i16(<16 x i16> *%src, <64 x i16> *%dst) {
; CHECK-LABEL: vst4_v16i16: ; CHECK-LABEL: vst4_v16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q7, [r0, #96] ; CHECK-NEXT: vldrw.u32 q7, [r0, #96]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vldrw.u32 q6, [r0, #64] ; CHECK-NEXT: vldrw.u32 q6, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vst40.16 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst40.16 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst41.16 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst41.16 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst42.16 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst42.16 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst43.16 {q4, q5, q6, q7}, [r1]! ; CHECK-NEXT: vst43.16 {q4, q5, q6, q7}, [r1]!
; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]
Show All 14 Linesentry:
%s = shufflevector <32 x i16> %t1, <32 x i16> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> %s = shufflevector <32 x i16> %t1, <32 x i16> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>
store <64 x i16> %s, <64 x i16> *%dst, align 2 store <64 x i16> %s, <64 x i16> *%dst, align 2
ret void ret void
} }
define void @vst4_v8i16_align1(<8 x i16> *%src, <32 x i16> *%dst) { define void @vst4_v8i16_align1(<8 x i16> *%src, <32 x i16> *%dst) {
; CHECK-LABEL: vst4_v8i16_align1: ; CHECK-LABEL: vst4_v8i16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #16] ; CHECK-NEXT: vldrw.u32 q4, [r0, #16]
; CHECK-NEXT: vmovx.f16 s12, s5 ; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vmovx.f16 s0, s9 ; CHECK-NEXT: vmovx.f16 s0, s9
; CHECK-NEXT: vmovx.f16 s20, s17 ; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vins.f16 s12, s0 ; CHECK-NEXT: vins.f16 s12, s0
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: vmov.f32 s3, s12
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vmovx.f16 s27, s4 ; CHECK-NEXT: vmovx.f16 s27, s4
; CHECK-NEXT: vins.f16 s4, s8 ; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmov.f32 s3, s12
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vmov.f32 s5, s4
; CHECK-NEXT: vmovx.f16 s8, s8
; CHECK-NEXT: vmovx.f16 s0, s17
; CHECK-NEXT: vmovx.f16 s2, s13 ; CHECK-NEXT: vmovx.f16 s2, s13
; CHECK-NEXT: vins.f16 s27, s8
; CHECK-NEXT: vmovx.f16 s4, s12
; CHECK-NEXT: vmovx.f16 s8, s16
; CHECK-NEXT: vins.f16 s13, s17 ; CHECK-NEXT: vins.f16 s13, s17
; CHECK-NEXT: vins.f16 s2, s20
; CHECK-NEXT: vmovx.f16 s20, s8
; CHECK-NEXT: vins.f16 s27, s20
; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vmovx.f16 s28, s12
; CHECK-NEXT: vmovx.f16 s20, s16
; CHECK-NEXT: vins.f16 s12, s16 ; CHECK-NEXT: vins.f16 s12, s16
; CHECK-NEXT: vins.f16 s28, s20
; CHECK-NEXT: vmov q5, q3 ; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vmov.f32 s25, s4 ; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmov.f32 s22, s28 ; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vmovx.f16 s28, s11 ; CHECK-NEXT: vmovx.f16 s4, s11
; CHECK-NEXT: vmov.f32 s21, s4
; CHECK-NEXT: vmovx.f16 s8, s10
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmovx.f16 s27, s7 ; CHECK-NEXT: vmovx.f16 s27, s7
; CHECK-NEXT: vins.f16 s27, s28
; CHECK-NEXT: vins.f16 s7, s11 ; CHECK-NEXT: vins.f16 s7, s11
; CHECK-NEXT: vmov.f32 s25, s7 ; CHECK-NEXT: vins.f16 s27, s4
; CHECK-NEXT: vmovx.f16 s28, s19
; CHECK-NEXT: vmovx.f16 s26, s15 ; CHECK-NEXT: vmovx.f16 s26, s15
; CHECK-NEXT: vins.f16 s15, s19 ; CHECK-NEXT: vmovx.f16 s4, s19
; CHECK-NEXT: vins.f16 s26, s28 ; CHECK-NEXT: vmov.f32 s25, s7
; CHECK-NEXT: vmovx.f16 s31, s6 ; CHECK-NEXT: vins.f16 s26, s4
; CHECK-NEXT: vmovx.f16 s7, s6
; CHECK-NEXT: vmovx.f16 s4, s10
; CHECK-NEXT: vins.f16 s6, s10 ; CHECK-NEXT: vins.f16 s6, s10
; CHECK-NEXT: vins.f16 s31, s8 ; CHECK-NEXT: vmov.f32 s21, s5
; CHECK-NEXT: vmov.f32 s29, s6 ; CHECK-NEXT: vins.f16 s15, s19
; CHECK-NEXT: vins.f16 s7, s4
; CHECK-NEXT: vmov.f32 s5, s6
; CHECK-NEXT: vmovx.f16 s6, s14
; CHECK-NEXT: vmovx.f16 s4, s18 ; CHECK-NEXT: vmovx.f16 s4, s18
; CHECK-NEXT: vmovx.f16 s30, s14
; CHECK-NEXT: vmov.f32 s24, s15
; CHECK-NEXT: vins.f16 s14, s18 ; CHECK-NEXT: vins.f16 s14, s18
; CHECK-NEXT: vins.f16 s30, s4 ; CHECK-NEXT: vins.f16 s2, s0
; CHECK-NEXT: vmov.f32 s28, s14 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vmov.f32 s24, s15
; CHECK-NEXT: vins.f16 s6, s4
; CHECK-NEXT: vmov.f32 s4, s14
; CHECK-NEXT: vstrb.8 q6, [r1, #48] ; CHECK-NEXT: vstrb.8 q6, [r1, #48]
; CHECK-NEXT: vstrb.8 q7, [r1, #32] ; CHECK-NEXT: vstrb.8 q1, [r1, #32]
; CHECK-NEXT: vstrb.8 q0, [r1, #16] ; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vstrb.8 q5, [r1] ; CHECK-NEXT: vstrb.8 q5, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0 %s1 = getelementptr <8 x i16>, <8 x i16>* %src, i32 0
%l1 = load <8 x i16>, <8 x i16>* %s1, align 4 %l1 = load <8 x i16>, <8 x i16>* %s1, align 4
%s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1 %s2 = getelementptr <8 x i16>, <8 x i16>* %src, i32 1
%l2 = load <8 x i16>, <8 x i16>* %s2, align 4 %l2 = load <8 x i16>, <8 x i16>* %s2, align 4
%s3 = getelementptr <8 x i16>, <8 x i16>* %src, i32 2 %s3 = getelementptr <8 x i16>, <8 x i16>* %src, i32 2
%l3 = load <8 x i16>, <8 x i16>* %s3, align 4 %l3 = load <8 x i16>, <8 x i16>* %s3, align 4
▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Lines
; i64 ; i64
define void @vst4_v2i64(<2 x i64> *%src, <8 x i64> *%dst) { define void @vst4_v2i64(<2 x i64> *%src, <8 x i64> *%dst) {
; CHECK-LABEL: vst4_v2i64: ; CHECK-LABEL: vst4_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f64 d6, d8 ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vmov.f32 s13, s17
; CHECK-NEXT: vmov.f32 s21, s9
; CHECK-NEXT: vmov.f32 s14, s0 ; CHECK-NEXT: vmov.f32 s14, s0
; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vmov.f32 s15, s1 ; CHECK-NEXT: vmov.f32 s15, s1
; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vmov.f32 s23, s5 ; CHECK-NEXT: vmov.f32 s23, s5
; CHECK-NEXT: vmov.f32 s12, s16
; CHECK-NEXT: vmov.f32 s13, s17
; CHECK-NEXT: vmov.f32 s20, s8
; CHECK-NEXT: vstrw.32 q3, [r1, #16] ; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vmov.f32 s21, s9
; CHECK-NEXT: vmov.f32 s0, s18 ; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: vstrw.32 q5, [r1] ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s1, s19 ; CHECK-NEXT: vmov.f32 s1, s19
; CHECK-NEXT: vmov.f32 s5, s11 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vstrw.32 q0, [r1, #48] ; CHECK-NEXT: vstrw.32 q0, [r1, #48]
; CHECK-NEXT: vmov.f32 s5, s11
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0 %s1 = getelementptr <2 x i64>, <2 x i64>* %src, i32 0
%l1 = load <2 x i64>, <2 x i64>* %s1, align 4 %l1 = load <2 x i64>, <2 x i64>* %s1, align 4
%s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1 %s2 = getelementptr <2 x i64>, <2 x i64>* %src, i32 1
%l2 = load <2 x i64>, <2 x i64>* %s2, align 4 %l2 = load <2 x i64>, <2 x i64>* %s2, align 4
%s3 = getelementptr <2 x i64>, <2 x i64>* %src, i32 2 %s3 = getelementptr <2 x i64>, <2 x i64>* %src, i32 2
%l3 = load <2 x i64>, <2 x i64>* %s3, align 4 %l3 = load <2 x i64>, <2 x i64>* %s3, align 4
%s4 = getelementptr <2 x i64>, <2 x i64>* %src, i32 3 %s4 = getelementptr <2 x i64>, <2 x i64>* %src, i32 3
%l4 = load <2 x i64>, <2 x i64>* %s4, align 4 %l4 = load <2 x i64>, <2 x i64>* %s4, align 4
%t1 = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t1 = shufflevector <2 x i64> %l1, <2 x i64> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%t2 = shufflevector <2 x i64> %l3, <2 x i64> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t2 = shufflevector <2 x i64> %l3, <2 x i64> %l4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%s = shufflevector <4 x i64> %t1, <4 x i64> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> %s = shufflevector <4 x i64> %t1, <4 x i64> %t2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
store <8 x i64> %s, <8 x i64> *%dst, align 8 store <8 x i64> %s, <8 x i64> *%dst, align 8
ret void ret void
} }
define void @vst4_v4i64(<4 x i64> *%src, <16 x i64> *%dst) { define void @vst4_v4i64(<4 x i64> *%src, <16 x i64> *%dst) {
; CHECK-LABEL: vst4_v4i64: ; CHECK-LABEL: vst4_v4i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #48 ; CHECK-NEXT: .pad #64
; CHECK-NEXT: sub sp, #48 ; CHECK-NEXT: sub sp, #64
; CHECK-NEXT: vldrw.u32 q7, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q7, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #64]
; CHECK-NEXT: vmov.f64 d12, d14
; CHECK-NEXT: vldrw.u32 q2, [r0, #96] ; CHECK-NEXT: vldrw.u32 q2, [r0, #96]
; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q3, [r0, #64]
; CHECK-NEXT: vldrw.u32 q1, [r0, #80] ; CHECK-NEXT: vmov.f32 s6, s0
; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
; CHECK-NEXT: vldrw.u32 q5, [r0, #112] ; CHECK-NEXT: vldrw.u32 q5, [r0, #112]
; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vmov.f32 s25, s29 ; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
; CHECK-NEXT: vmov.f32 s26, s0 ; CHECK-NEXT: vmov.f64 d13, d1
; CHECK-NEXT: vmov.f32 s27, s1 ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmov.f32 s0, s30 ; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q6, [r1] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vmov.f32 s1, s31 ; CHECK-NEXT: vmov.f32 s4, s28
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s5, s29
; CHECK-NEXT: vmov.f64 d2, d6 ; CHECK-NEXT: vmov.f32 s24, s30
; CHECK-NEXT: vmov.f32 s5, s13 ; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d14, d0 ; CHECK-NEXT: vmov.f32 s25, s31
; CHECK-NEXT: vmov.f32 s29, s1 ; CHECK-NEXT: vldrw.u32 q7, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s6, s8 ; CHECK-NEXT: vmov.f32 s6, s8
; CHECK-NEXT: vstrw.32 q6, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s7, s9 ; CHECK-NEXT: vmov.f32 s7, s9
; CHECK-NEXT: vmov.f32 s4, s12
; CHECK-NEXT: vmov.f32 s5, s13
; CHECK-NEXT: vmov.f32 s8, s14 ; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f32 s9, s15 ; CHECK-NEXT: vmov.f32 s9, s15
; CHECK-NEXT: vmov.f64 d6, d0 ; CHECK-NEXT: vldrw.u32 q3, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d1, d15
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s13, s1 ; CHECK-NEXT: vmov.f64 d13, d7
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s14, s20
; CHECK-NEXT: vmov.f32 s15, s21
; CHECK-NEXT: vmov.f32 s30, s16 ; CHECK-NEXT: vmov.f32 s30, s16
; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s31, s17 ; CHECK-NEXT: vmov.f32 s31, s17
; CHECK-NEXT: vldrw.u32 q3, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s16, s2 ; CHECK-NEXT: vmov.f32 s16, s2
; CHECK-NEXT: vstrw.32 q7, [r1, #64] ; CHECK-NEXT: vstrw.32 q7, [r1, #64]
; CHECK-NEXT: vmov.f32 s17, s3 ; CHECK-NEXT: vmov.f32 s17, s3
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s20
; CHECK-NEXT: vstrw.32 q4, [r1, #96]
; CHECK-NEXT: vmov.f32 s15, s21
; CHECK-NEXT: vmov.f32 s20, s2
; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s21, s3
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s20, s26
; CHECK-NEXT: vstrw.32 q4, [r1, #96]
; CHECK-NEXT: vmov.f32 s21, s27
; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vstrw.32 q5, [r1, #112] ; CHECK-NEXT: vstrw.32 q5, [r1, #112]
; CHECK-NEXT: vstrw.32 q0, [r1, #32] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #48 ; CHECK-NEXT: add sp, #64
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x i64>, <4 x i64>* %src, i32 0 %s1 = getelementptr <4 x i64>, <4 x i64>* %src, i32 0
%l1 = load <4 x i64>, <4 x i64>* %s1, align 4 %l1 = load <4 x i64>, <4 x i64>* %s1, align 4
%s2 = getelementptr <4 x i64>, <4 x i64>* %src, i32 1 %s2 = getelementptr <4 x i64>, <4 x i64>* %src, i32 1
%l2 = load <4 x i64>, <4 x i64>* %s2, align 4 %l2 = load <4 x i64>, <4 x i64>* %s2, align 4
%s3 = getelementptr <4 x i64>, <4 x i64>* %src, i32 2 %s3 = getelementptr <4 x i64>, <4 x i64>* %src, i32 2
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
} }
define void @vst4_v8f32(<8 x float> *%src, <32 x float> *%dst) { define void @vst4_v8f32(<8 x float> *%src, <32 x float> *%dst) {
; CHECK-LABEL: vst4_v8f32: ; CHECK-LABEL: vst4_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q7, [r0, #96] ; CHECK-NEXT: vldrw.u32 q7, [r0, #96]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vldrw.u32 q6, [r0, #64] ; CHECK-NEXT: vldrw.u32 q6, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst42.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]! ; CHECK-NEXT: vst43.32 {q4, q5, q6, q7}, [r1]!
; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]
Show All 20 Lines
; CHECK-LABEL: vst4_v16f32: ; CHECK-LABEL: vst4_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5} ; CHECK-NEXT: .save {r4, r5}
; CHECK-NEXT: push {r4, r5} ; CHECK-NEXT: push {r4, r5}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #192 ; CHECK-NEXT: .pad #192
; CHECK-NEXT: sub sp, #192 ; CHECK-NEXT: sub sp, #192
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q7, [r0, #240]
; CHECK-NEXT: vldrw.u32 q3, [r0, #208]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #64 ; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldrw.u32 q7, [r0, #224] ; CHECK-NEXT: vldrw.u32 q1, [r0, #80]
; CHECK-NEXT: vldrw.u32 q3, [r0, #208]
; CHECK-NEXT: vldrw.u32 q2, [r0, #144] ; CHECK-NEXT: vldrw.u32 q2, [r0, #144]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill ; CHECK-NEXT: vstmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q1, [r0, #80] ; CHECK-NEXT: vldrw.u32 q3, [r0, #192]
; CHECK-NEXT: vldrw.u32 q2, [r0, #128]
; CHECK-NEXT: vldrw.u32 q4, [r0, #240]
; CHECK-NEXT: vstmia r2, {d2, d3, d4, d5, d6, d7, d8, d9} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q6, [r0, #176] ; CHECK-NEXT: vldrw.u32 q6, [r0, #176]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldrw.u32 q6, [r0, #160]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill ; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q5, [r0, #112] ; CHECK-NEXT: vldrw.u32 q5, [r0, #112]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill ; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #128 ; CHECK-NEXT: add r2, sp, #128
; CHECK-NEXT: vldrw.u32 q4, [r0, #48] ; CHECK-NEXT: vldrw.u32 q4, [r0, #48]
; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill ; CHECK-NEXT: vstmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Spill
; CHECK-NEXT: vldrw.u32 q3, [r0, #192] ; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
; CHECK-NEXT: vldrw.u32 q2, [r0, #128] ; CHECK-NEXT: vldrw.u32 q3, [r0, #224]
; CHECK-NEXT: vldrw.u32 q1, [r0, #96]
; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill ; CHECK-NEXT: vstmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Spill
; CHECK-NEXT: vmov q6, q2
; CHECK-NEXT: vmov q7, q3
; CHECK-NEXT: vmov q5, q1
; CHECK-NEXT: vldmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload
; CHECK-NEXT: add r2, sp, #64 ; CHECK-NEXT: add r2, sp, #64
; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vldmia r2, {d8, d9, d10, d11, d12, d13, d14, d15} @ 64-byte Reload
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q4, [r0, #32] ; CHECK-NEXT: vldrw.u32 q4, [r0, #32]
; CHECK-NEXT: mov r0, r1 ; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]! ; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]!
; CHECK-NEXT: vldmia sp, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload ; CHECK-NEXT: vldmia r2, {d0, d1, d2, d3, d4, d5, d6, d7} @ 64-byte Reload
; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst40.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst41.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst42.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0] ; CHECK-NEXT: vst43.32 {q0, q1, q2, q3}, [r0]
; CHECK-NEXT: add.w r0, r1, #192 ; CHECK-NEXT: add.w r0, r1, #192
; CHECK-NEXT: adds r1, #128 ; CHECK-NEXT: adds r1, #128
; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst40.32 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst41.32 {q4, q5, q6, q7}, [r1]
Show All 25 Linesentry:
ret void ret void
} }
define void @vst4_v4f32_align1(<4 x float> *%src, <16 x float> *%dst) { define void @vst4_v4f32_align1(<4 x float> *%src, <16 x float> *%dst) {
; CHECK-LABEL: vst4_v4f32_align1: ; CHECK-LABEL: vst4_v4f32_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vmov.f32 s12, s17 ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmov.f64 d10, d8 ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.f32 s24, s19 ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vmov.f32 s13, s9
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s25, s11
; CHECK-NEXT: vmov.f32 s14, s1 ; CHECK-NEXT: vmov.f32 s14, s1
; CHECK-NEXT: vmov.f32 s22, s0 ; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s26, s3 ; CHECK-NEXT: vmov.f32 s26, s3
; CHECK-NEXT: vmov.f32 s0, s18 ; CHECK-NEXT: vmov.f32 s12, s17
; CHECK-NEXT: vmov.f32 s1, s10 ; CHECK-NEXT: vmov.f32 s13, s9
; CHECK-NEXT: vmov.f32 s15, s5 ; CHECK-NEXT: vmov.f32 s15, s5
; CHECK-NEXT: vmov.f32 s23, s4 ; CHECK-NEXT: vmov.f32 s20, s16
; CHECK-NEXT: vstrb.8 q3, [r1, #16] ; CHECK-NEXT: vstrb.8 q3, [r1, #16]
; CHECK-NEXT: vmov.f32 s27, s7 ; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s23, s4
; CHECK-NEXT: vmov.f32 s24, s19
; CHECK-NEXT: vstrb.8 q5, [r1] ; CHECK-NEXT: vstrb.8 q5, [r1]
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s25, s11
; CHECK-NEXT: vmov.f32 s27, s7
; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: vstrb.8 q6, [r1, #48] ; CHECK-NEXT: vstrb.8 q6, [r1, #48]
; CHECK-NEXT: vmov.f32 s1, s10
; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vstrb.8 q0, [r1, #32] ; CHECK-NEXT: vstrb.8 q0, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0 %s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0
%l1 = load <4 x float>, <4 x float>* %s1, align 4 %l1 = load <4 x float>, <4 x float>* %s1, align 4
%s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1 %s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1
%l2 = load <4 x float>, <4 x float>* %s2, align 4 %l2 = load <4 x float>, <4 x float>* %s2, align 4
%s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2 %s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2
%l3 = load <4 x float>, <4 x float>* %s3, align 4 %l3 = load <4 x float>, <4 x float>* %s3, align 4
%s4 = getelementptr <4 x float>, <4 x float>* %src, i32 3 %s4 = getelementptr <4 x float>, <4 x float>* %src, i32 3
%l4 = load <4 x float>, <4 x float>* %s4, align 4 %l4 = load <4 x float>, <4 x float>* %s4, align 4
%t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x float> %l3, <4 x float> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t2 = shufflevector <4 x float> %l3, <4 x float> %l4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%s = shufflevector <8 x float> %t1, <8 x float> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> %s = shufflevector <8 x float> %t1, <8 x float> %t2, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
store <16 x float> %s, <16 x float> *%dst, align 1 store <16 x float> %s, <16 x float> *%dst, align 1
ret void ret void
} }
; f16 ; f16
define void @vst4_v2f16(<2 x half> *%src, <8 x half> *%dst) { define void @vst4_v2f16(<2 x half> *%src, <8 x half> *%dst) {
; CHECK-LABEL: vst4_v2f16: ; CHECK-LABEL: vst4_v2f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldmia r0, {s0, s1} ; CHECK-NEXT: vldr s0, [r0]
; CHECK-NEXT: vldr s5, [r0, #4]
; CHECK-NEXT: vldr s4, [r0, #8] ; CHECK-NEXT: vldr s4, [r0, #8]
; CHECK-NEXT: vmovx.f16 s2, s0 ; CHECK-NEXT: vmovx.f16 s2, s0
; CHECK-NEXT: vldr s5, [r0, #12] ; CHECK-NEXT: vldr s1, [r0, #12]
; CHECK-NEXT: vins.f16 s0, s1 ; CHECK-NEXT: vmovx.f16 s6, s5
; CHECK-NEXT: vmovx.f16 s3, s4 ; CHECK-NEXT: vmovx.f16 s3, s4
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vins.f16 s2, s6
; CHECK-NEXT: vins.f16 s4, s5 ; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vins.f16 s2, s8 ; CHECK-NEXT: vins.f16 s4, s1
; CHECK-NEXT: vmovx.f16 s8, s5 ; CHECK-NEXT: vins.f16 s0, s5
; CHECK-NEXT: vins.f16 s3, s8 ; CHECK-NEXT: vins.f16 s3, s6
; CHECK-NEXT: vmov.f32 s1, s4 ; CHECK-NEXT: vmov.f32 s1, s4
; CHECK-NEXT: vstrh.16 q0, [r1] ; CHECK-NEXT: vstrh.16 q0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0 %s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0
%l1 = load <2 x half>, <2 x half>* %s1, align 4 %l1 = load <2 x half>, <2 x half>* %s1, align 4
%s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1 %s2 = getelementptr <2 x half>, <2 x half>* %src, i32 1
%l2 = load <2 x half>, <2 x half>* %s2, align 4 %l2 = load <2 x half>, <2 x half>* %s2, align 4
Show All 16 Lines
; CHECK-NEXT: add.w lr, r0, #16 ; CHECK-NEXT: add.w lr, r0, #16
; CHECK-NEXT: ldr r2, [r0, #28] ; CHECK-NEXT: ldr r2, [r0, #28]
; CHECK-NEXT: ldm.w lr, {r3, r12, lr} ; CHECK-NEXT: ldm.w lr, {r3, r12, lr}
; CHECK-NEXT: vmov.32 q1[0], lr ; CHECK-NEXT: vmov.32 q1[0], lr
; CHECK-NEXT: vmov.32 q1[1], r2 ; CHECK-NEXT: vmov.32 q1[1], r2
; CHECK-NEXT: vmov.32 q0[0], r3 ; CHECK-NEXT: vmov.32 q0[0], r3
; CHECK-NEXT: vmov.32 q0[1], r12 ; CHECK-NEXT: vmov.32 q0[1], r12
; CHECK-NEXT: ldrd r2, r12, [r0] ; CHECK-NEXT: ldrd r2, r12, [r0]
; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: ldrd r3, r0, [r0, #8] ; CHECK-NEXT: ldrd r3, r0, [r0, #8]
; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmovx.f16 s12, s0 ; CHECK-NEXT: vmovx.f16 s12, s0
; CHECK-NEXT: vins.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s2 ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.32 q2[0], r3 ; CHECK-NEXT: vmov.32 q2[0], r3
; CHECK-NEXT: vins.f16 s12, s4 ; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmov.32 q1[0], r2 ; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q1[1], r12 ; CHECK-NEXT: vmov.32 q1[1], r12
; CHECK-NEXT: vmov.f32 s6, s8 ; CHECK-NEXT: vins.f16 s12, s2
; CHECK-NEXT: vmov.f32 s7, s9 ; CHECK-NEXT: vmovx.f16 s6, s4
; CHECK-NEXT: vmovx.f16 s14, s4 ; CHECK-NEXT: vmovx.f16 s2, s8
; CHECK-NEXT: vins.f16 s4, s6 ; CHECK-NEXT: vins.f16 s6, s2
; CHECK-NEXT: vmovx.f16 s8, s6
; CHECK-NEXT: vins.f16 s14, s8
; CHECK-NEXT: vmovx.f16 s11, s1 ; CHECK-NEXT: vmovx.f16 s11, s1
; CHECK-NEXT: vins.f16 s1, s3 ; CHECK-NEXT: vmovx.f16 s2, s3
; CHECK-NEXT: vmovx.f16 s13, s3
; CHECK-NEXT: vins.f16 s11, s13
; CHECK-NEXT: vmovx.f16 s10, s5 ; CHECK-NEXT: vmovx.f16 s10, s5
; CHECK-NEXT: vins.f16 s5, s7 ; CHECK-NEXT: vins.f16 s11, s2
; CHECK-NEXT: vmovx.f16 s13, s7 ; CHECK-NEXT: vmovx.f16 s2, s9
; CHECK-NEXT: vins.f16 s10, s13 ; CHECK-NEXT: vins.f16 s1, s3
; CHECK-NEXT: vins.f16 s5, s9
; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmov.f32 s8, s5 ; CHECK-NEXT: vmov.f32 s8, s5
; CHECK-NEXT: vmov.f32 s5, s0 ; CHECK-NEXT: vins.f16 s10, s2
; CHECK-NEXT: vmov.f32 s6, s14
; CHECK-NEXT: vmov.f32 s9, s1 ; CHECK-NEXT: vmov.f32 s9, s1
; CHECK-NEXT: vmov.f32 s7, s12 ; CHECK-NEXT: vmov.f32 s5, s0
; CHECK-NEXT: vstrh.16 q2, [r1, #16] ; CHECK-NEXT: vstrh.16 q2, [r1, #16]
; CHECK-NEXT: vmov.f32 s7, s12
; CHECK-NEXT: vstrh.16 q1, [r1] ; CHECK-NEXT: vstrh.16 q1, [r1]
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0 %s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
%l1 = load <4 x half>, <4 x half>* %s1, align 4 %l1 = load <4 x half>, <4 x half>* %s1, align 4
%s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1 %s2 = getelementptr <4 x half>, <4 x half>* %src, i32 1
%l2 = load <4 x half>, <4 x half>* %s2, align 4 %l2 = load <4 x half>, <4 x half>* %s2, align 4
%s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2 %s3 = getelementptr <4 x half>, <4 x half>* %src, i32 2
Show All 36 Lines
} }
define void @vst4_v16f16(<16 x half> *%src, <64 x half> *%dst) { define void @vst4_v16f16(<16 x half> *%src, <64 x half> *%dst) {
; CHECK-LABEL: vst4_v16f16: ; CHECK-LABEL: vst4_v16f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vldrw.u32 q7, [r0, #96] ; CHECK-NEXT: vldrw.u32 q7, [r0, #96]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vldrw.u32 q6, [r0, #64] ; CHECK-NEXT: vldrw.u32 q6, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vst40.16 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst40.16 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst41.16 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst41.16 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst42.16 {q4, q5, q6, q7}, [r1] ; CHECK-NEXT: vst42.16 {q4, q5, q6, q7}, [r1]
; CHECK-NEXT: vst43.16 {q4, q5, q6, q7}, [r1]! ; CHECK-NEXT: vst43.16 {q4, q5, q6, q7}, [r1]!
; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst40.16 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst41.16 {q0, q1, q2, q3}, [r1]
; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1] ; CHECK-NEXT: vst42.16 {q0, q1, q2, q3}, [r1]
Show All 14 Linesentry:
%s = shufflevector <32 x half> %t1, <32 x half> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> %s = shufflevector <32 x half> %t1, <32 x half> %t2, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63>
store <64 x half> %s, <64 x half> *%dst, align 2 store <64 x half> %s, <64 x half> *%dst, align 2
ret void ret void
} }
define void @vst4_v8f16_align1(<8 x half> *%src, <32 x half> *%dst) { define void @vst4_v8f16_align1(<8 x half> *%src, <32 x half> *%dst) {
; CHECK-LABEL: vst4_v8f16_align1: ; CHECK-LABEL: vst4_v8f16_align1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d9, d10, d11, d12, d13}
; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: vldrw.u32 q7, [r0, #48]
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vldrw.u32 q6, [r0, #16] ; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vmovx.f16 s2, s5 ; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vmovx.f16 s0, s29 ; CHECK-NEXT: vmovx.f16 s2, s21
; CHECK-NEXT: vins.f16 s2, s0 ; CHECK-NEXT: vins.f16 s0, s2
; CHECK-NEXT: vmovx.f16 s12, s25
; CHECK-NEXT: vstr s2, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: vmovx.f16 s2, s9 ; CHECK-NEXT: vmovx.f16 s2, s9
; CHECK-NEXT: vins.f16 s5, s29 ; CHECK-NEXT: vmovx.f16 s12, s25
; CHECK-NEXT: vins.f16 s2, s12
; CHECK-NEXT: vmovx.f16 s19, s4 ; CHECK-NEXT: vmovx.f16 s19, s4
; CHECK-NEXT: vmovx.f16 s12, s28 ; CHECK-NEXT: vins.f16 s2, s12
; CHECK-NEXT: vins.f16 s9, s25 ; CHECK-NEXT: vmovx.f16 s12, s20
; CHECK-NEXT: vins.f16 s19, s12 ; CHECK-NEXT: vins.f16 s19, s12
; CHECK-NEXT: vmovx.f16 s14, s8 ; CHECK-NEXT: vmovx.f16 s12, s8
; CHECK-NEXT: vmovx.f16 s12, s24 ; CHECK-NEXT: vmovx.f16 s14, s24
; CHECK-NEXT: vins.f16 s14, s12
; CHECK-NEXT: vins.f16 s4, s28
; CHECK-NEXT: vstr s14, [sp] @ 4-byte Spill
; CHECK-NEXT: vmovx.f16 s15, s7 ; CHECK-NEXT: vmovx.f16 s15, s7
; CHECK-NEXT: vmovx.f16 s20, s31 ; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vins.f16 s8, s24 ; CHECK-NEXT: vmovx.f16 s14, s23
; CHECK-NEXT: vins.f16 s15, s20 ; CHECK-NEXT: vins.f16 s15, s14
; CHECK-NEXT: vmovx.f16 s20, s27
; CHECK-NEXT: vmovx.f16 s14, s11 ; CHECK-NEXT: vmovx.f16 s14, s11
; CHECK-NEXT: vins.f16 s7, s31 ; CHECK-NEXT: vmovx.f16 s1, s27
; CHECK-NEXT: vins.f16 s14, s20 ; CHECK-NEXT: vins.f16 s7, s23
; CHECK-NEXT: vins.f16 s14, s1
; CHECK-NEXT: vmovx.f16 s23, s6 ; CHECK-NEXT: vmovx.f16 s23, s6
; CHECK-NEXT: vmovx.f16 s28, s30 ; CHECK-NEXT: vmovx.f16 s1, s22
; CHECK-NEXT: vins.f16 s6, s30 ; CHECK-NEXT: vins.f16 s6, s22
; CHECK-NEXT: vins.f16 s23, s28 ; CHECK-NEXT: vins.f16 s5, s21
; CHECK-NEXT: vins.f16 s11, s27 ; CHECK-NEXT: vins.f16 s4, s20
; CHECK-NEXT: vins.f16 s23, s1
; CHECK-NEXT: vmovx.f16 s22, s10 ; CHECK-NEXT: vmovx.f16 s22, s10
; CHECK-NEXT: vmovx.f16 s24, s26
; CHECK-NEXT: vldr s28, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: vins.f16 s22, s24
; CHECK-NEXT: vins.f16 s10, s26 ; CHECK-NEXT: vins.f16 s10, s26
; CHECK-NEXT: vmovx.f16 s1, s26
; CHECK-NEXT: vins.f16 s9, s25
; CHECK-NEXT: vins.f16 s8, s24
; CHECK-NEXT: vins.f16 s11, s27
; CHECK-NEXT: vmov q6, q1 ; CHECK-NEXT: vmov q6, q1
; CHECK-NEXT: vmov.f32 s27, s28 ; CHECK-NEXT: vins.f16 s22, s1
; CHECK-NEXT: vldr s28, [sp] @ 4-byte Reload
; CHECK-NEXT: vmov.f32 s0, s9
; CHECK-NEXT: vmov.f32 s1, s25 ; CHECK-NEXT: vmov.f32 s1, s25
; CHECK-NEXT: vmov.f32 s13, s7
; CHECK-NEXT: vmov.f32 s21, s6
; CHECK-NEXT: vmov.f32 s12, s11
; CHECK-NEXT: vmov.f32 s20, s10
; CHECK-NEXT: vstrb.8 q3, [r1, #48]
; CHECK-NEXT: vmov.f32 s3, s27
; CHECK-NEXT: vmov q6, q2 ; CHECK-NEXT: vmov q6, q2
; CHECK-NEXT: vmov.f32 s26, s28 ; CHECK-NEXT: vmov.f32 s3, s0
; CHECK-NEXT: vstrb.8 q5, [r1, #32] ; CHECK-NEXT: vmov.f32 s0, s9
; CHECK-NEXT: vmov.f32 s25, s4 ; CHECK-NEXT: vmov.f32 s26, s12
; CHECK-NEXT: vstrb.8 q0, [r1, #16] ; CHECK-NEXT: vstrb.8 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s25, s4
; CHECK-NEXT: vmov.f32 s27, s19 ; CHECK-NEXT: vmov.f32 s27, s19
; CHECK-NEXT: vmov.f32 s13, s7
; CHECK-NEXT: vstrb.8 q6, [r1] ; CHECK-NEXT: vstrb.8 q6, [r1]
; CHECK-NEXT: add sp, #8 ; CHECK-NEXT: vmov.f32 s12, s11
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vmov.f32 s21, s6
; CHECK-NEXT: vstrb.8 q3, [r1, #48]
; CHECK-NEXT: vmov.f32 s20, s10
; CHECK-NEXT: vstrb.8 q5, [r1, #32]
; CHECK-NEXT: vpop {d9, d10, d11, d12, d13}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0 %s1 = getelementptr <8 x half>, <8 x half>* %src, i32 0
%l1 = load <8 x half>, <8 x half>* %s1, align 4 %l1 = load <8 x half>, <8 x half>* %s1, align 4
%s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1 %s2 = getelementptr <8 x half>, <8 x half>* %src, i32 1
%l2 = load <8 x half>, <8 x half>* %s2, align 4 %l2 = load <8 x half>, <8 x half>* %s2, align 4
%s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2 %s3 = getelementptr <8 x half>, <8 x half>* %src, i32 2
%l3 = load <8 x half>, <8 x half>* %s3, align 4 %l3 = load <8 x half>, <8 x half>* %s3, align 4
%s4 = getelementptr <8 x half>, <8 x half>* %src, i32 3 %s4 = getelementptr <8 x half>, <8 x half>* %src, i32 3
%l4 = load <8 x half>, <8 x half>* %s4, align 4 %l4 = load <8 x half>, <8 x half>* %s4, align 4
%t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x half> %l1, <8 x half> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x half> %l3, <8 x half> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t2 = shufflevector <8 x half> %l3, <8 x half> %l4, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%s = shufflevector <16 x half> %t1, <16 x half> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> %s = shufflevector <16 x half> %t1, <16 x half> %t2, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>
store <32 x half> %s, <32 x half> *%dst, align 1 store <32 x half> %s, <32 x half> *%dst, align 1
ret void ret void
} }
; f64 ; f64
define void @vst4_v2f64(<2 x double> *%src, <8 x double> *%dst) { define void @vst4_v2f64(<2 x double> *%src, <8 x double> *%dst) {
; CHECK-LABEL: vst4_v2f64: ; CHECK-LABEL: vst4_v2f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f64 d8, d4 ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vmov.f64 d10, d6
; CHECK-NEXT: vmov.f64 d9, d0 ; CHECK-NEXT: vmov.f64 d9, d0
; CHECK-NEXT: vmov.f64 d8, d4
; CHECK-NEXT: vmov.f64 d11, d2 ; CHECK-NEXT: vmov.f64 d11, d2
; CHECK-NEXT: vstrw.32 q4, [r1, #16] ; CHECK-NEXT: vstrw.32 q4, [r1, #16]
; CHECK-NEXT: vmov.f64 d10, d6
; CHECK-NEXT: vmov.f64 d0, d5 ; CHECK-NEXT: vmov.f64 d0, d5
; CHECK-NEXT: vstrw.32 q5, [r1] ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f64 d2, d7 ; CHECK-NEXT: vmov.f64 d2, d7
; CHECK-NEXT: vstrw.32 q0, [r1, #48] ; CHECK-NEXT: vstrw.32 q0, [r1, #48]
; CHECK-NEXT: vstrw.32 q1, [r1, #32] ; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 15 Lines
define void @vst4_v4f64(<4 x double> *%src, <16 x double> *%dst) { define void @vst4_v4f64(<4 x double> *%src, <16 x double> *%dst) {
; CHECK-LABEL: vst4_v4f64: ; CHECK-LABEL: vst4_v4f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #64 ; CHECK-NEXT: .pad #64
; CHECK-NEXT: sub sp, #64 ; CHECK-NEXT: sub sp, #64
; CHECK-NEXT: vldrw.u32 q7, [r0, #80] ; CHECK-NEXT: vldrw.u32 q7, [r0, #80]
; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #64] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d14, d12
; CHECK-NEXT: vldrw.u32 q1, [r0, #96] ; CHECK-NEXT: vldrw.u32 q1, [r0, #96]
; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d15, d10
; CHECK-NEXT: vldrw.u32 q2, [r0, #64]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #48] ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0, #112] ; CHECK-NEXT: vldrw.u32 q4, [r0, #112]
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d15, d10 ; CHECK-NEXT: vmov.f64 d14, d12
; CHECK-NEXT: vstrw.32 q7, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d14, d4 ; CHECK-NEXT: vmov.f64 d14, d4
; CHECK-NEXT: vmov.f64 d15, d2 ; CHECK-NEXT: vmov.f64 d15, d2
; CHECK-NEXT: vmov.f64 d2, d5
; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q7, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d4, d0 ; CHECK-NEXT: vmov.f64 d4, d0
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [r1, #48] ; CHECK-NEXT: vldrw.u32 q7, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d10, d13 ; CHECK-NEXT: vmov.f64 d10, d13
; CHECK-NEXT: vmov.f64 d12, d0 ; CHECK-NEXT: vmov.f64 d2, d5
; CHECK-NEXT: vstrw.32 q5, [r1, #32] ; CHECK-NEXT: vstrw.32 q5, [r1, #32]
; CHECK-NEXT: vmov.f64 d5, d6 ; CHECK-NEXT: vmov.f64 d5, d6
; CHECK-NEXT: vstrw.32 q1, [r1, #48]
; CHECK-NEXT: vmov.f64 d13, d8 ; CHECK-NEXT: vmov.f64 d13, d8
; CHECK-NEXT: vstrw.32 q2, [r1, #64] ; CHECK-NEXT: vstrw.32 q2, [r1, #64]
; CHECK-NEXT: vmov.f64 d12, d0
; CHECK-NEXT: vmov.f64 d8, d1 ; CHECK-NEXT: vmov.f64 d8, d1
; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q6, [r1, #80] ; CHECK-NEXT: vstrw.32 q6, [r1, #80]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d6, d15 ; CHECK-NEXT: vmov.f64 d6, d15
; CHECK-NEXT: vstrw.32 q4, [r1, #112] ; CHECK-NEXT: vstrw.32 q4, [r1, #112]
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
Show All 19 Lines

llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; CHECK-LABEL: foo_v4i32: ; CHECK-LABEL: foo_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpt.s32 lt, q0, zr ; CHECK-NEXT: vpt.s32 lt, q0, zr
; CHECK-NEXT: vldrwt.u32 q4, [r0] ; CHECK-NEXT: vldrwt.u32 q4, [r0]
; CHECK-NEXT: vmov.f64 d0, d8
; CHECK-NEXT: vmov.i64 q5, #0xffffffff ; CHECK-NEXT: vmov.i64 q5, #0xffffffff
; CHECK-NEXT: vmov.f32 s0, s16
; CHECK-NEXT: vmov.f32 s2, s17 ; CHECK-NEXT: vmov.f32 s2, s17
; CHECK-NEXT: vand q6, q0, q5 ; CHECK-NEXT: vand q6, q0, q5
; CHECK-NEXT: vmov r0, r1, d13 ; CHECK-NEXT: vmov r0, r1, d13
; CHECK-NEXT: bl __aeabi_ul2d ; CHECK-NEXT: bl __aeabi_ul2d
; CHECK-NEXT: vmov r2, r3, d12 ; CHECK-NEXT: vmov r2, r3, d12
; CHECK-NEXT: vmov.f64 d0, d9 ; CHECK-NEXT: vmov.f32 s0, s18
; CHECK-NEXT: vmov.f32 s2, s19 ; CHECK-NEXT: vmov.f32 s2, s19
; CHECK-NEXT: vmov d9, r0, r1 ; CHECK-NEXT: vmov d9, r0, r1
; CHECK-NEXT: vand q5, q0, q5 ; CHECK-NEXT: vand q5, q0, q5
; CHECK-NEXT: vmov r4, r5, d11 ; CHECK-NEXT: vmov r4, r5, d11
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r3 ; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: bl __aeabi_ul2d ; CHECK-NEXT: bl __aeabi_ul2d
; CHECK-NEXT: vmov d8, r0, r1 ; CHECK-NEXT: vmov d8, r0, r1
Show All 27 Lines