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Differential D107313

[AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress
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Authored by paquette on Aug 2 2021, 2:36 PM.

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aemerson
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rGbd13c8e610ca: [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress
Summary

When a value is expected to be extended, we should emit an extended load rather than a normal G_LOAD.

Add checklines to arm64-abi.ll which show that we now emit the correct loads.

For ease of comparison: https://godbolt.org/z/8WvY6EfdE

Diff Detail

Event Timeline

paquette created this revision.Aug 2 2021, 2:36 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptAug 2 2021, 2:36 PM
paquette requested review of this revision.Aug 2 2021, 2:36 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 2 2021, 2:36 PM
paquette abandoned this revision.Aug 2 2021, 2:37 PM
This comment was removed by paquette.
paquette reclaimed this revision.Aug 2 2021, 2:37 PM

agh left the comment on the wrong patch

paquette mentioned this in D107305: [GlobalISel] Combine G_ASSERT_*EXT + G_LOAD -> G_S/ZEXTLOAD.Aug 2 2021, 2:38 PM
aemerson accepted this revision.Aug 2 2021, 2:40 PM

LGTM.

This revision is now accepted and ready to land.Aug 2 2021, 2:40 PM
This revision was landed with ongoing or failed builds.Aug 2 2021, 2:50 PM
Closed by commit rGbd13c8e610ca: [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rGbd13c8e610ca: [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress.
Harbormaster completed remote builds in B117526: Diff 363580.Aug 2 2021, 3:29 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
13 lines
test/
CodeGen/
AArch64/
GlobalISel/
8 lines
8 lines
4 lines
9 lines

Diff 363583

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Lines else {
// the LocTy for the i8/i16 hack. // the LocTy for the i8/i16 hack.
assert(LocTy.getSizeInBits() == MemTy.getSizeInBits()); assert(LocTy.getSizeInBits() == MemTy.getSizeInBits());
LocTy = MemTy; LocTy = MemTy;
} }
auto MMO = MF.getMachineMemOperand( auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, LocTy, MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, LocTy,
inferAlignFromPtrInfo(MF, MPO)); inferAlignFromPtrInfo(MF, MPO));
switch (VA.getLocInfo()) {
case CCValAssign::LocInfo::ZExt:
MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, ValVReg, Addr, *MMO);
return;
case CCValAssign::LocInfo::SExt:
MIRBuilder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, ValVReg, Addr, *MMO);
return;
default:
MIRBuilder.buildLoad(ValVReg, Addr, *MMO); MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
return;
}
} }
/// How the physical register gets marked varies between formal /// How the physical register gets marked varies between formal
/// parameters (it's a basic-block live-in), and a call instruction /// parameters (it's a basic-block live-in), and a call instruction
/// (it's an implicit-def of the BL). /// (it's an implicit-def of the BL).
virtual void markPhysRegUsed(MCRegister PhysReg) = 0; virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
}; };
▲ Show 20 Lines • Show All 966 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesdefine i32 @signext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5 ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6 ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16) ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 1 ; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[SEXTLOAD]], 1
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_SEXT]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_SEXT]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
; CHECK: $w0 = COPY [[ZEXT]](s32) ; CHECK: $w0 = COPY [[ZEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
i64 %g, i64 %h, i64 %i, i1 signext %j) { i64 %g, i64 %h, i64 %i, i1 signext %j) {
%v = zext i1 %j to i32 %v = zext i1 %j to i32
ret i32 %v ret i32 %v
} }
Show All 33 Linesdefine i8 @s8_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5 ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6 ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16) ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8) ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 8 ; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[SEXTLOAD]], 8
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
; CHECK: $w0 = COPY [[ANYEXT]](s32) ; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i, i64 %f, i64 %g, i64 %h, i64 %i,
i8 signext %j) { i8 signext %j) {
ret i8 %j ret i8 %j
} }

llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesdefine i32 @zeroext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5 ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6 ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16) ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8) ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[LOAD1]], 1 ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 1
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_ZEXT]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
; CHECK: $w0 = COPY [[ZEXT]](s32) ; CHECK: $w0 = COPY [[ZEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
i64 %g, i64 %h, i64 %i, i1 zeroext %j) { i64 %g, i64 %h, i64 %i, i1 zeroext %j) {
%v = zext i1 %j to i32 %v = zext i1 %j to i32
ret i32 %v ret i32 %v
} }
Show All 33 Linesdefine i8 @s8_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4 ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5 ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6 ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7 ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16) ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8) ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0, align 8)
; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[LOAD1]], 8 ; CHECK: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[ZEXTLOAD]], 8
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_ZEXT]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
; CHECK: $w0 = COPY [[ANYEXT]](s32) ; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
i64 %f, i64 %g, i64 %h, i64 %i, i64 %f, i64 %g, i64 %h, i64 %i,
i8 zeroext %j) { i8 zeroext %j) {
ret i8 %j ret i8 %j
} }

llvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll

; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
; CHECK-LABEL: name: test_stack_slots ; CHECK-LABEL: name: test_stack_slots
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, ; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1, ; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s8) from %fixed-stack.1, align 16) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX]](p0) :: (invariant load (s8) from %fixed-stack.1, align 16)
; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD]], 8 ; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD]], 8
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) from %fixed-stack.0)
; CHECK: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 8 ; CHECK: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 8
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT1]](s32)
; CHECK: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]] ; CHECK: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ADD]](s8) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ADD]](s8)
; CHECK: $w0 = COPY [[SEXT]](s32) ; CHECK: $w0 = COPY [[SEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) { define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
%sum = add i8 %lhs, %rhs %sum = add i8 %lhs, %rhs
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-abi.ll

; RUN: llc -mtriple=arm64-apple-darwin -mcpu=cyclone -enable-misched=false < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -mcpu=cyclone -enable-misched=false < %s | FileCheck %s
; RUN: llc -O0 -fast-isel -mtriple=arm64-apple-darwin < %s | FileCheck --check-prefix=FAST %s ; RUN: llc -O0 -fast-isel -mtriple=arm64-apple-darwin < %s | FileCheck --check-prefix=FAST %s
; RUN: llc -global-isel -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=GISEL
; rdar://9932559 ; rdar://9932559
define i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext %a5, i64 %a6, i64 %a7, i64 %a8, i8 signext %b1, i16 signext %b2, i8 signext %b3, i8 signext %b4) nounwind readnone noinline { define i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext %a5, i64 %a6, i64 %a7, i64 %a8, i8 signext %b1, i16 signext %b2, i8 signext %b3, i8 signext %b4) nounwind readnone noinline {
entry: entry:
; CHECK-LABEL: i8i16callee: ; CHECK-LABEL: i8i16callee:
; The 8th, 9th, 10th and 11th arguments are passed at sp, sp+2, sp+4, sp+5. ; The 8th, 9th, 10th and 11th arguments are passed at sp, sp+2, sp+4, sp+5.
; They are i8, i16, i8 and i8. ; They are i8, i16, i8 and i8.
; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp, #5] ; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp, #5]
; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp, #4] ; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp, #4]
; CHECK-DAG: ldrsh {{w[0-9]+}}, [sp, #2] ; CHECK-DAG: ldrsh {{w[0-9]+}}, [sp, #2]
; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp] ; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp]
; FAST-LABEL: i8i16callee: ; FAST-LABEL: i8i16callee:
; FAST-DAG: ldrsb {{w[0-9]+}}, [sp, #5] ; FAST-DAG: ldrsb {{w[0-9]+}}, [sp, #5]
; FAST-DAG: ldrsb {{w[0-9]+}}, [sp, #4] ; FAST-DAG: ldrsb {{w[0-9]+}}, [sp, #4]
; FAST-DAG: ldrsh {{w[0-9]+}}, [sp, #2] ; FAST-DAG: ldrsh {{w[0-9]+}}, [sp, #2]
; FAST-DAG: ldrsb {{w[0-9]+}}, [sp] ; FAST-DAG: ldrsb {{w[0-9]+}}, [sp]
; GISEL-LABEL: i8i16callee:
; GISEL-DAG: ldrsb {{w[0-9]+}}, [sp, #5]
; GISEL-DAG: ldrsb {{w[0-9]+}}, [sp, #4]
; GISEL-DAG: ldrsh {{w[0-9]+}}, [sp, #2]
; GISEL-DAG: ldrsb {{w[0-9]+}}, [sp]
%conv = sext i8 %a4 to i64 %conv = sext i8 %a4 to i64
%conv3 = sext i16 %a5 to i64 %conv3 = sext i16 %a5 to i64
%conv8 = sext i8 %b1 to i64 %conv8 = sext i8 %b1 to i64
%conv9 = sext i16 %b2 to i64 %conv9 = sext i16 %b2 to i64
%conv11 = sext i8 %b3 to i64 %conv11 = sext i8 %b3 to i64
%conv13 = sext i8 %b4 to i64 %conv13 = sext i8 %b4 to i64
%add10 = add i64 %a2, %a1 %add10 = add i64 %a2, %a1
%add12 = add i64 %add10, %a3 %add12 = add i64 %add10, %a3
▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Linesdeclare void @args_i1(i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext,
i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext,
i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext) i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext)
define i32 @i1_stack_incoming(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, define i32 @i1_stack_incoming(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
i64 %g, i64 %h, i64 %i, i1 zeroext %j) { i64 %g, i64 %h, i64 %i, i1 zeroext %j) {
; CHECK-LABEL: i1_stack_incoming: ; CHECK-LABEL: i1_stack_incoming:
; CHECK: ldrb w0, [sp, #8] ; CHECK: ldrb w0, [sp, #8]
; CHECK: ret ; CHECK: ret
; GISEL-LABEL: i1_stack_incoming:
; GISEL: ldrb w0, [sp, #8]
; GISEL: ret
%v = zext i1 %j to i32 %v = zext i1 %j to i32
ret i32 %v ret i32 %v
} }