[mlir][spirv] Add support for i8 serialization

[antiagainst]

Summary

Depends On D107119

mlir/lib/Target/SPIRV/Serialization/Serializer.cpp

uint32_t Serializer::prepareConstantInt(Location loc, IntegerAttr intAttr,
   auto resultID = getNextID();
   APInt value = intAttr.getValue();
   unsigned bitwidth = value.getBitWidth();
   bool isSigned = value.isSignedIntN(bitwidth);
 
   auto opcode =
       isSpec ? spirv::Opcode::OpSpecConstant : spirv::Opcode::OpConstant;
 
-  // According to SPIR-V spec, "When the type's bit width is less than 32-bits,
-  // the literal's value appears in the low-order bits of the word, and the
-  // high-order bits must be 0 for a floating-point type, or 0 for an integer
-  // type with Signedness of 0, or sign extended when Signedness is 1."
-  if (bitwidth == 32 || bitwidth == 16) {
+  switch (bitwidth) {
+    // According to SPIR-V spec, "When the type's bit width is less than
+    // 32-bits, the literal's value appears in the low-order bits of the word,
+    // and the high-order bits must be 0 for a floating-point type, or 0 for an
+    // integer type with Signedness of 0, or sign extended when Signedness
+    // is 1."
+  case 32:
+  case 16:
+  case 8: {
     uint32_t word = 0;
     if (isSigned) {
       word = static_cast<int32_t>(value.getSExtValue());
     } else {
       word = static_cast<uint32_t>(value.getZExtValue());
     }
     (void)encodeInstructionInto(typesGlobalValues, opcode,
                                 {typeID, resultID, word});
-  }
+  } break;
     // According to SPIR-V spec: "When the type's bit width is larger than one
     // word, the literal’s low-order words appear first."
-  else if (bitwidth == 64) {
+  case 64: {
     struct DoubleWord {
       uint32_t word1;
       uint32_t word2;
     } words;
     if (isSigned) {
       words = llvm::bit_cast<DoubleWord>(value.getSExtValue());
     } else {
       words = llvm::bit_cast<DoubleWord>(value.getZExtValue());
     }
     (void)encodeInstructionInto(typesGlobalValues, opcode,
                                 {typeID, resultID, words.word1, words.word2});
-  } else {
+  } break;
+  default: {
     std::string valueStr;
     llvm::raw_string_ostream rss(valueStr);
     value.print(rss, /*isSigned=*/false);
 
     emitError(loc, "cannot serialize ")
         << bitwidth << "-bit integer literal: " << rss.str();
     return 0;
   }
+  }
 
   if (!isSpec) {
     constIDMap[intAttr] = resultID;
   }
   return resultID;
 }
 
 uint32_t Serializer::prepareConstantFp(Location loc, FloatAttr floatAttr,

mlir/test/Target/SPIRV/constant.mlir

spv.func @i16_const() -> () "None" {
     %0 = spv.Constant -32768 : i16 // -2^15
     // CHECK: spv.Constant 32767 : i16
     %1 = spv.Constant 32767 : i16 //  2^15 - 1
 
     %2 = spv.IAdd %0, %1 : i16
     spv.Return
   }
 
+  // CHECK-LABEL: @i8_const
+  spv.func @i8_const() -> () "None" {
+    // CHECK: spv.Constant 0 : i8
+    %0 = spv.Constant 0 : i8
+    // CHECK: spv.Constant -1 : i8
+    %1 = spv.Constant 255 : i8
+
+    // CHECK: spv.Constant 0 : si8
+    %2 = spv.Constant 0 : si8
+    // CHECK: spv.Constant 127 : si8
+    %3 = spv.Constant 127 : si8
+    // CHECK: spv.Constant -128 : si8
+    %4 = spv.Constant -128 : si8
+
+    // CHECK: spv.Constant 0 : i8
+    %5 = spv.Constant 0 : ui8
+    // CHECK: spv.Constant -1 : i8
+    %6 = spv.Constant 255 : ui8
+
+    %10 = spv.IAdd %0, %1: i8
+    %11 = spv.IAdd %2, %3: si8
+    %12 = spv.IAdd %3, %4: si8
+    %13 = spv.IAdd %5, %6: ui8
+    spv.Return
+  }
+
   // CHECK-LABEL: @float_const
   spv.func @float_const() -> () "None" {
     // CHECK: spv.Constant 0.000000e+00 : f32
     %0 = spv.Constant 0. : f32
     // CHECK: spv.Constant 1.000000e+00 : f32
     %1 = spv.Constant 1. : f32
     // CHECK: spv.Constant -0.000000e+00 : f32
     %2 = spv.Constant -0. : f32