[GlobalISel] Allow the ArtifactValueFinder to return the best available register on failure.

[aemerson]

Summary

In some cases, like with inserts, we may have a matching size register already, but still decide to try to look further. This change adds a CurrentBest register to the value finder state, and any time a method fails to make progress, returns that register (which may just be an empty Register).

To facilitate this, add a new entry point to the findValueFromDef() function which initializes this state.

Also fix the build vector finder to return the current build_vector if all sources are being requested.

[aemerson]

I'm not convinced this is the best approach actually. Might be better to keep track of the best register as a private member, and then have a single external API entry point for queries that resets the fail reg each time.

[aemerson]

New version does the above.

[foad]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

756–759

Surely DefReg is always a safe "best" return value? Why would you ever need to return Register() instead?

[aemerson]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

756–759

I suppose it's a matter of API design/opinion. If you get a valid Register back, then you know it's going to be different from the existing register so you can RAUW it. If it can return DefReg, then you need to check if it's different first, otherwise you'll trigger lots of unnecessary observer invalidations.

[foad]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

756–759

If you get a valid Register back, then you know it's going to be different from the existing register

I'm confused: the comment specifically says that you might get DefReg back, which is what you passed in.

[aemerson]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

756–759

I think that's an obsolete comment, and I actually need to change the users to reflect the semantics.

[aemerson]

Change API to return an empty Register if the best register found is the same as the one being examined.

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

586–587

Comment is out of date?

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

 #include "llvm/ADT/SmallBitVector.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Register.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "legalizer"
 using namespace llvm::MIPatternMatch;
 
 namespace llvm {
 class LegalizationArtifactCombiner {
   MachineIRBuilder &Builder;
public:
   /// bit ranges in an artifact. The routines can look through the source
   /// registers if they're other artifacts to try to find a non-artifact source
   /// of a value.
   class ArtifactValueFinder {
     MachineRegisterInfo &MRI;
     MachineIRBuilder &MIB;
     const LegalizerInfo &LI;
 
-  private:
+    // Stores the best register found in the current query so far.
+    Register CurrentBest = Register();
+
     /// Given an concat_vector op \p Concat and a start bit and size, try to
     /// find the origin of the value defined by that start position and size.
     ///
     /// \returns A register if a value can be found, otherwise an empty
     /// Register.
     Register findValueFromConcat(GConcatVectors &Concat, unsigned StartBit,
                                  unsigned Size) {
       assert(Size > 0);
 
       // Find the source operand that provides the bits requested.
       Register Src1Reg = Concat.getSourceReg(0);
       unsigned SrcSize = MRI.getType(Src1Reg).getSizeInBits();
 
       // Operand index of the source that provides the start of the bit range.
       unsigned StartSrcIdx = (StartBit / SrcSize) + 1;
       // Offset into the source at which the bit range starts.
       unsigned InRegOffset = StartBit % SrcSize;
       // Check that the bits don't span multiple sources.
       // FIXME: we might be able return multiple sources? Or create an
       // appropriate concat to make it fit.
       if (InRegOffset + Size > SrcSize)
-        return Register();
+        return CurrentBest;
 
-      // If the bits exactly cover a single source, then return the operand as
-      // our value reg.
       Register SrcReg = Concat.getReg(StartSrcIdx);
-      if (InRegOffset == 0 && Size == SrcSize)
-        return SrcReg; // A source operand matches exactly.
+      if (InRegOffset == 0 && Size == SrcSize) {
+        CurrentBest = SrcReg;
+        return findValueFromDefImpl(SrcReg, 0, Size);
+      }
 
-      return findValueFromDef(SrcReg, InRegOffset, Size);
+      return findValueFromDefImpl(SrcReg, InRegOffset, Size);
     }
 
     /// Given an build_vector op \p BV and a start bit and size, try to find
     /// the origin of the value defined by that start position and size.
     ///
     /// \returns A register if a value can be found, otherwise an empty
     /// Register.
     Register findValueFromBuildVector(GBuildVector &BV, unsigned StartBit,
                                       unsigned Size) {
       assert(Size > 0);
 
       // Find the source operand that provides the bits requested.
       Register Src1Reg = BV.getSourceReg(0);
       unsigned SrcSize = MRI.getType(Src1Reg).getSizeInBits();
 
       // Operand index of the source that provides the start of the bit range.
       unsigned StartSrcIdx = (StartBit / SrcSize) + 1;
       // Offset into the source at which the bit range starts.
       unsigned InRegOffset = StartBit % SrcSize;
 
       if (InRegOffset != 0)
-        return Register(); // Give up, bits don't start at a scalar source.
+        return CurrentBest; // Give up, bits don't start at a scalar source.
       if (Size < SrcSize)
-        return Register(); // Scalar source is too large for requested bits.
+        return CurrentBest; // Scalar source is too large for requested bits.
 
       // If the bits cover multiple sources evenly, then create a new
       // build_vector to synthesize the required size, if that's been requested.
       if (Size > SrcSize) {
         if (Size % SrcSize > 0)
-          return Register(); // Isn't covered exactly by sources.
+          return CurrentBest; // Isn't covered exactly by sources.
 
         unsigned NumSrcsUsed = Size / SrcSize;
+        // If we're requesting all of the sources, just return this def.
+        if (NumSrcsUsed == BV.getNumSources())
+          return BV.getReg(0);
+
         LLT SrcTy = MRI.getType(Src1Reg);
         LLT NewBVTy = LLT::fixed_vector(NumSrcsUsed, SrcTy);
 
         // Check if the resulting build vector would be legal.
         LegalizeActionStep ActionStep =
             LI.getAction({TargetOpcode::G_BUILD_VECTOR, {NewBVTy, SrcTy}});
         if (ActionStep.Action != LegalizeActions::Legal)
-          return Register();
+          return CurrentBest;
 
         SmallVector<Register> NewSrcs;
         for (unsigned SrcIdx = StartSrcIdx; SrcIdx < StartSrcIdx + NumSrcsUsed;
              ++SrcIdx)
           NewSrcs.push_back(BV.getReg(SrcIdx));
         MIB.setInstrAndDebugLoc(BV);
         return MIB.buildBuildVector(NewBVTy, NewSrcs).getReg(0);
       }
Register findValueFromInsert(MachineInstr &MI, unsigned StartBit,
 
       unsigned InsertedEndBit = InsertOffset + InsertedRegTy.getSizeInBits();
       unsigned EndBit = StartBit + Size;
       unsigned NewStartBit;
       Register SrcRegToUse;
       if (EndBit <= InsertOffset || InsertedEndBit <= StartBit) {
         SrcRegToUse = ContainerSrcReg;
         NewStartBit = StartBit;
-        return findValueFromDef(SrcRegToUse, NewStartBit, Size);
+        return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size);
       }
       if (InsertOffset <= StartBit && EndBit <= InsertedEndBit) {
         SrcRegToUse = InsertedReg;
         NewStartBit = StartBit - InsertOffset;
-        return findValueFromDef(SrcRegToUse, NewStartBit, Size);
+        if (NewStartBit == 0 &&
+            Size == MRI.getType(SrcRegToUse).getSizeInBits())
+          CurrentBest = SrcRegToUse;
+        return findValueFromDefImpl(SrcRegToUse, NewStartBit, Size);
       }
       // The bit range spans both the inserted and container regions.
       return Register();
     }
 
-  public:
-    ArtifactValueFinder(MachineRegisterInfo &Mri, MachineIRBuilder &Builder,
-                        const LegalizerInfo &Info)
-        : MRI(Mri), MIB(Builder), LI(Info) {}
-
-    /// Try to find a source of the value defined in the def \p DefReg, starting
-    /// at position \p StartBit with size \p Size.
-    /// \returns an empty Register if no value could be found, or \p DefReg if
-    /// if that was the best we could do.
-    Register findValueFromDef(Register DefReg, unsigned StartBit,
+    /// Internal implementation for findValueFromDef(). findValueFromDef()
+    /// initializes some data like the CurrentBest register, which this method
+    /// and its callees rely upon.
+    Register findValueFromDefImpl(Register DefReg, unsigned StartBit,
                                   unsigned Size) {
       MachineInstr *Def = getDefIgnoringCopies(DefReg, MRI);
       // If the instruction has a single def, then simply delegate the search.
       // For unmerge however with multiple defs, we need to compute the offset
       // into the source of the unmerge.
       switch (Def->getOpcode()) {
       case TargetOpcode::G_CONCAT_VECTORS:
         return findValueFromConcat(cast<GConcatVectors>(*Def), StartBit, Size);
       case TargetOpcode::G_UNMERGE_VALUES: {
         unsigned DefStartBit = 0;
         unsigned DefSize = MRI.getType(DefReg).getSizeInBits();
         for (const auto &MO : Def->defs()) {
           if (MO.getReg() == DefReg)
             break;
           DefStartBit += DefSize;
         }
         Register SrcReg = Def->getOperand(Def->getNumOperands() - 1).getReg();
         Register SrcOriginReg =
-            findValueFromDef(SrcReg, StartBit + DefStartBit, Size);
+            findValueFromDefImpl(SrcReg, StartBit + DefStartBit, Size);
         if (SrcOriginReg)
           return SrcOriginReg;
         // Failed to find a further value. If the StartBit and Size perfectly
         // covered the requested DefReg, return that since it's better than
         // nothing.
         if (StartBit == 0 && Size == DefSize)
           return DefReg;
-        return Register();
+        return CurrentBest;
       }
       case TargetOpcode::G_BUILD_VECTOR:
         return findValueFromBuildVector(cast<GBuildVector>(*Def), StartBit,
                                         Size);
       case TargetOpcode::G_INSERT:
         return findValueFromInsert(*Def, StartBit, Size);
       default:
-        return Register();
+        return CurrentBest;
       }
     }
+
+  public:
+    ArtifactValueFinder(MachineRegisterInfo &Mri, MachineIRBuilder &Builder,
+                        const LegalizerInfo &Info)
+        : MRI(Mri), MIB(Builder), LI(Info) {}
+
+    /// Try to find a source of the value defined in the def \p DefReg, starting
+    /// at position \p StartBit with size \p Size.
+    /// \returns an empty Register if no value could be found, or \p DefReg if
+    /// if that was the best we could do.
+    Register findValueFromDef(Register DefReg, unsigned StartBit,
+                              unsigned Size) {
+      CurrentBest = Register();
+      return findValueFromDefImpl(DefReg, StartBit, Size);
+    }
   };
 
   bool tryCombineUnmergeValues(GUnmerge &MI,
                                SmallVectorImpl<MachineInstr *> &DeadInsts,
                                SmallVectorImpl<Register> &UpdatedDefs,
                                GISelChangeObserver &Observer) {
     unsigned NumDefs = MI.getNumDefs();
     Register SrcReg = MI.getSourceReg();

llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir

bb.0:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: test_inserts_s96
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
     ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
     ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT]](s32)
-    ; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[ANYEXT]], [[TRUNC]](s32), 0
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
-    ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[INSERT]](s64)
     ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
     ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
-    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
+    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s32), [[DEF]](s32)
     ; CHECK: $x0 = COPY [[MV]](s64)
     ; CHECK: $x1 = COPY [[MV1]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s64) = COPY $x1
     %2:_(s64) = COPY $x2
     %3:_(s128) = G_MERGE_VALUES %0:_(s64), %1:_(s64)
     %4:_(s96) = G_TRUNC %3(s128)
     %5:_(s32) = G_TRUNC %2(s64)
     %6:_(s96) = G_INSERT %4, %5(s32), 64
     %7:_(s128) = G_ANYEXT %6(s96)
     %8:_(s64), %9:_(s64) = G_UNMERGE_VALUES %7
     $x0 = COPY %8
     $x1 = COPY %9
 ...
 ---
 name:            test_inserts_s65
 body: |
   bb.0:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: test_inserts_s65
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
     ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s64)
     ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
-    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s1) = G_EXTRACT [[COPY1]](s64), 0
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT]](s1)
-    ; CHECK: [[INSERT:%[0-9]+]]:_(s64) = G_INSERT [[ANYEXT]], [[TRUNC]](s1), 0
     ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY3]](s64)
     ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
     ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
     ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[C1]](s64)
     ; CHECK: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
     ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
bb.0:
     ; CHECK: [[ZEXT52:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
     ; CHECK: [[LSHR52:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT52]], [[C7]](s64)
     ; CHECK: [[ZEXT53:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
     ; CHECK: [[LSHR53:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT53]], [[C9]](s64)
     ; CHECK: [[ZEXT54:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
     ; CHECK: [[LSHR54:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT54]], [[C11]](s64)
     ; CHECK: [[ZEXT55:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
     ; CHECK: [[LSHR55:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT55]], [[C13]](s64)
-    ; CHECK: [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[INSERT]](s64)
-    ; CHECK: [[ZEXT56:%[0-9]+]]:_(s32) = G_ZEXT [[UV8]](s8)
-    ; CHECK: [[LSHR56:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT56]], [[C1]](s64)
-    ; CHECK: [[ZEXT57:%[0-9]+]]:_(s32) = G_ZEXT [[UV8]](s8)
-    ; CHECK: [[LSHR57:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT57]], [[C3]](s64)
-    ; CHECK: [[ZEXT58:%[0-9]+]]:_(s32) = G_ZEXT [[UV8]](s8)
-    ; CHECK: [[LSHR58:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT58]], [[C5]](s64)
-    ; CHECK: [[ZEXT59:%[0-9]+]]:_(s32) = G_ZEXT [[UV8]](s8)
-    ; CHECK: [[LSHR59:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT59]], [[C7]](s64)
-    ; CHECK: [[ZEXT60:%[0-9]+]]:_(s32) = G_ZEXT [[UV8]](s8)
-    ; CHECK: [[LSHR60:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT60]], [[C9]](s64)
-    ; CHECK: [[ZEXT61:%[0-9]+]]:_(s32) = G_ZEXT [[UV8]](s8)
-    ; CHECK: [[LSHR61:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT61]], [[C11]](s64)
-    ; CHECK: [[ZEXT62:%[0-9]+]]:_(s32) = G_ZEXT [[UV8]](s8)
-    ; CHECK: [[LSHR62:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT62]], [[C13]](s64)
     ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
     ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C14]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
-    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C14]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C14]]
     ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
     ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY5]]
     ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
     ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C14]]
     ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C3]](s64)
     ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
     ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
     ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY7]], [[COPY8]]
bb.0:
     ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[SHL5]](s32)
     ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY19]], [[COPY20]]
     ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
     ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C14]]
     ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C13]](s64)
     ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
     ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[SHL6]](s32)
     ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY22]], [[COPY23]]
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
     ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
     ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C14]]
     ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C1]](s64)
-    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
-    ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C14]]
+    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
+    ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C14]]
     ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[SHL7]](s32)
     ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[COPY25]]
     ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
     ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C14]]
     ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C3]](s64)
     ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
     ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[SHL8]](s32)
     ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY27]], [[COPY28]]
bb.0:
     ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[SHL12]](s32)
     ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[COPY39]], [[COPY40]]
     ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
     ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C14]]
     ; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C13]](s64)
     ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[OR12]](s32)
     ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[SHL13]](s32)
     ; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[COPY42]], [[COPY43]]
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
     ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
     ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY44]], [[C14]]
     ; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C1]](s64)
-    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
-    ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C14]]
+    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
+    ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C14]]
     ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[SHL14]](s32)
     ; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[COPY45]]
     ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
     ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY46]], [[C14]]
     ; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C3]](s64)
     ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[OR14]](s32)
     ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[SHL15]](s32)
     ; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[COPY47]], [[COPY48]]
bb.0:
     ; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[SHL19]](s32)
     ; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[COPY59]], [[COPY60]]
     ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
     ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY61]], [[C14]]
     ; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C13]](s64)
     ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[OR19]](s32)
     ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[SHL20]](s32)
     ; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[COPY62]], [[COPY63]]
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
     ; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
     ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY64]], [[C14]]
     ; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C1]](s64)
-    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
-    ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C14]]
+    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
+    ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C14]]
     ; CHECK: [[COPY65:%[0-9]+]]:_(s32) = COPY [[SHL21]](s32)
     ; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[COPY65]]
     ; CHECK: [[COPY66:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
     ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY66]], [[C14]]
     ; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C3]](s64)
     ; CHECK: [[COPY67:%[0-9]+]]:_(s32) = COPY [[OR21]](s32)
     ; CHECK: [[COPY68:%[0-9]+]]:_(s32) = COPY [[SHL22]](s32)
     ; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[COPY67]], [[COPY68]]
bb.0:
     ; CHECK: [[COPY80:%[0-9]+]]:_(s32) = COPY [[SHL26]](s32)
     ; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[COPY79]], [[COPY80]]
     ; CHECK: [[COPY81:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
     ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY81]], [[C14]]
     ; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C13]](s64)
     ; CHECK: [[COPY82:%[0-9]+]]:_(s32) = COPY [[OR26]](s32)
     ; CHECK: [[COPY83:%[0-9]+]]:_(s32) = COPY [[SHL27]](s32)
     ; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[COPY82]], [[COPY83]]
-    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
     ; CHECK: [[COPY84:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
     ; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY84]], [[C14]]
     ; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C1]](s64)
-    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
-    ; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C14]]
+    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
+    ; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C14]]
     ; CHECK: [[COPY85:%[0-9]+]]:_(s32) = COPY [[SHL28]](s32)
     ; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[COPY85]]
     ; CHECK: [[COPY86:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
     ; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY86]], [[C14]]
     ; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C3]](s64)
     ; CHECK: [[COPY87:%[0-9]+]]:_(s32) = COPY [[OR28]](s32)
     ; CHECK: [[COPY88:%[0-9]+]]:_(s32) = COPY [[SHL29]](s32)
     ; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[COPY87]], [[COPY88]]
bb.0:
     ; CHECK: [[COPY100:%[0-9]+]]:_(s32) = COPY [[SHL33]](s32)
     ; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[COPY99]], [[COPY100]]
     ; CHECK: [[COPY101:%[0-9]+]]:_(s32) = COPY [[LSHR34]](s32)
     ; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY101]], [[C14]]
     ; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C13]](s64)
     ; CHECK: [[COPY102:%[0-9]+]]:_(s32) = COPY [[OR33]](s32)
     ; CHECK: [[COPY103:%[0-9]+]]:_(s32) = COPY [[SHL34]](s32)
     ; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[COPY102]], [[COPY103]]
-    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
     ; CHECK: [[COPY104:%[0-9]+]]:_(s32) = COPY [[LSHR35]](s32)
     ; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY104]], [[C14]]
     ; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C1]](s64)
-    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
-    ; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C14]]
+    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
+    ; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C14]]
     ; CHECK: [[COPY105:%[0-9]+]]:_(s32) = COPY [[SHL35]](s32)
     ; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[AND41]], [[COPY105]]
     ; CHECK: [[COPY106:%[0-9]+]]:_(s32) = COPY [[LSHR36]](s32)
     ; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY106]], [[C14]]
     ; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C3]](s64)
     ; CHECK: [[COPY107:%[0-9]+]]:_(s32) = COPY [[OR35]](s32)
     ; CHECK: [[COPY108:%[0-9]+]]:_(s32) = COPY [[SHL36]](s32)
     ; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[COPY107]], [[COPY108]]
bb.0:
     ; CHECK: [[COPY120:%[0-9]+]]:_(s32) = COPY [[SHL40]](s32)
     ; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[COPY119]], [[COPY120]]
     ; CHECK: [[COPY121:%[0-9]+]]:_(s32) = COPY [[LSHR41]](s32)
     ; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY121]], [[C14]]
     ; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C13]](s64)
     ; CHECK: [[COPY122:%[0-9]+]]:_(s32) = COPY [[OR40]](s32)
     ; CHECK: [[COPY123:%[0-9]+]]:_(s32) = COPY [[SHL41]](s32)
     ; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[COPY122]], [[COPY123]]
-    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[OR41]](s32)
+    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR41]](s32)
     ; CHECK: [[COPY124:%[0-9]+]]:_(s32) = COPY [[LSHR42]](s32)
     ; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY124]], [[C14]]
     ; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C1]](s64)
-    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
-    ; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C14]]
+    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
+    ; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C14]]
     ; CHECK: [[COPY125:%[0-9]+]]:_(s32) = COPY [[SHL42]](s32)
     ; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[AND49]], [[COPY125]]
     ; CHECK: [[COPY126:%[0-9]+]]:_(s32) = COPY [[LSHR43]](s32)
     ; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY126]], [[C14]]
     ; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C3]](s64)
     ; CHECK: [[COPY127:%[0-9]+]]:_(s32) = COPY [[OR42]](s32)
     ; CHECK: [[COPY128:%[0-9]+]]:_(s32) = COPY [[SHL43]](s32)
     ; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[COPY127]], [[COPY128]]
bb.0:
     ; CHECK: [[COPY140:%[0-9]+]]:_(s32) = COPY [[SHL47]](s32)
     ; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[COPY139]], [[COPY140]]
     ; CHECK: [[COPY141:%[0-9]+]]:_(s32) = COPY [[LSHR48]](s32)
     ; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY141]], [[C14]]
     ; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C13]](s64)
     ; CHECK: [[COPY142:%[0-9]+]]:_(s32) = COPY [[OR47]](s32)
     ; CHECK: [[COPY143:%[0-9]+]]:_(s32) = COPY [[SHL48]](s32)
     ; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[COPY142]], [[COPY143]]
-    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[OR48]](s32)
+    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[OR48]](s32)
     ; CHECK: [[COPY144:%[0-9]+]]:_(s32) = COPY [[LSHR49]](s32)
     ; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY144]], [[C14]]
     ; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C1]](s64)
-    ; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
-    ; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[ANYEXT8]], [[C14]]
+    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
+    ; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C14]]
     ; CHECK: [[COPY145:%[0-9]+]]:_(s32) = COPY [[SHL49]](s32)
     ; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[AND57]], [[COPY145]]
     ; CHECK: [[COPY146:%[0-9]+]]:_(s32) = COPY [[LSHR50]](s32)
     ; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY146]], [[C14]]
     ; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C3]](s64)
     ; CHECK: [[COPY147:%[0-9]+]]:_(s32) = COPY [[OR49]](s32)
     ; CHECK: [[COPY148:%[0-9]+]]:_(s32) = COPY [[SHL50]](s32)
     ; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[COPY147]], [[COPY148]]
bb.0:
     ; CHECK: [[COPY160:%[0-9]+]]:_(s32) = COPY [[SHL54]](s32)
     ; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[COPY159]], [[COPY160]]
     ; CHECK: [[COPY161:%[0-9]+]]:_(s32) = COPY [[LSHR55]](s32)
     ; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[COPY161]], [[C14]]
     ; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C13]](s64)
     ; CHECK: [[COPY162:%[0-9]+]]:_(s32) = COPY [[OR54]](s32)
     ; CHECK: [[COPY163:%[0-9]+]]:_(s32) = COPY [[SHL55]](s32)
     ; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[COPY162]], [[COPY163]]
-    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s8) = G_TRUNC [[OR55]](s32)
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8), [[TRUNC8]](s8)
+    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[OR55]](s32)
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8)
     ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK: [[COPY164:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
     ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY164]], [[C1]](s64)
-    ; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
-    ; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[ANYEXT9]], [[C14]]
+    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
+    ; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[TRUNC8]], [[C14]]
     ; CHECK: [[COPY165:%[0-9]+]]:_(s32) = COPY [[SHL56]](s32)
     ; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[COPY165]]
     ; CHECK: [[COPY166:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
     ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY166]], [[C3]](s64)
     ; CHECK: [[COPY167:%[0-9]+]]:_(s32) = COPY [[OR56]](s32)
     ; CHECK: [[COPY168:%[0-9]+]]:_(s32) = COPY [[SHL57]](s32)
     ; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[COPY167]], [[COPY168]]
     ; CHECK: [[COPY169:%[0-9]+]]:_(s32) = COPY [[C15]](s32)