[ARM] Implement isLoad/StoreFromStackSlot for MVE stack stores accesses

[dmgreen]

Summary

This implements the isLoadFromStackSlot and isStoreToStackSlot for MVE MVE_VSTRWU32 and MVE_VLDRWU32 functions. They behave the same as many other loads/stores, expecting a FI in Op1 and zero offset in Op2. At the same time this alters VLDR_P0_off and VSTR_P0_off to use the same code too, as they too return VPR in Op0, take a FI in Op1 and zero offset in Op2.

[NickGuy]

LGTM

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
       return MI.getOperand(0).getReg();
     }
     break;
   case ARM::STRi12:
   case ARM::t2STRi12:
   case ARM::tSTRspi:
   case ARM::VSTRD:
   case ARM::VSTRS:
+  case ARM::VSTR_P0_off:
+  case ARM::MVE_VSTRWU32:
     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
         MI.getOperand(2).getImm() == 0) {
       FrameIndex = MI.getOperand(1).getIndex();
       return MI.getOperand(0).getReg();
     }
     break;
-  case ARM::VSTR_P0_off:
-    if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
-        MI.getOperand(1).getImm() == 0) {
-      FrameIndex = MI.getOperand(0).getIndex();
-      return ARM::P0;
-    }
-    break;
   case ARM::VST1q64:
   case ARM::VST1d64TPseudo:
   case ARM::VST1d64QPseudo:
     if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
       FrameIndex = MI.getOperand(0).getIndex();
       return MI.getOperand(2).getReg();
     }
     break;
if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
       return MI.getOperand(0).getReg();
     }
     break;
   case ARM::LDRi12:
   case ARM::t2LDRi12:
   case ARM::tLDRspi:
   case ARM::VLDRD:
   case ARM::VLDRS:
+  case ARM::VLDR_P0_off:
+  case ARM::MVE_VLDRWU32:
     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
         MI.getOperand(2).getImm() == 0) {
       FrameIndex = MI.getOperand(1).getIndex();
       return MI.getOperand(0).getReg();
     }
     break;
-  case ARM::VLDR_P0_off:
-    if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
-        MI.getOperand(1).getImm() == 0) {
-      FrameIndex = MI.getOperand(0).getIndex();
-      return ARM::P0;
-    }
-    break;
   case ARM::VLD1q64:
   case ARM::VLD1d8TPseudo:
   case ARM::VLD1d16TPseudo:
   case ARM::VLD1d32TPseudo:
   case ARM::VLD1d64TPseudo:
   case ARM::VLD1d8QPseudo:
   case ARM::VLD1d16QPseudo:
   case ARM::VLD1d32QPseudo:

llvm/test/CodeGen/Thumb2/mve-gather-increment.ll

 ; CHECK-NEXT:    vmov r5, r4, d15
 ; CHECK-NEXT:    vadd.i32 q6, q0, r0
 ; CHECK-NEXT:    vmov r6, r7, d13
 ; CHECK-NEXT:    vstrw.32 q1, [sp, #152] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #296] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q0, [sp, #168] @ 16-byte Spill
 ; CHECK-NEXT:    vmov q0, q2
 ; CHECK-NEXT:    vmov q3, q5
-; CHECK-NEXT:    vstrw.32 q1, [sp, #296] @ 16-byte Spill
 ; CHECK-NEXT:    vadd.i32 q1, q1, r0
+; CHECK-NEXT:    vldrw.u32 q0, [sp, #248] @ 16-byte Reload
 ; CHECK-NEXT:    vldrw.u32 q3, [sp, #216] @ 16-byte Reload
 ; CHECK-NEXT:    vstrw.32 q5, [sp, #120] @ 16-byte Spill
+; CHECK-NEXT:    vadd.i32 q0, q0, r0
 ; CHECK-NEXT:    subs.w r11, r11, #16
 ; CHECK-NEXT:    ldrb.w r9, [r1]
 ; CHECK-NEXT:    vmov r1, r3, d14
 ; CHECK-NEXT:    ldrb r5, [r5]
 ; CHECK-NEXT:    ldrb r7, [r7]
 ; CHECK-NEXT:    ldrb r1, [r1]
 ; CHECK-NEXT:    vmov.8 q7[0], r1
 ; CHECK-NEXT:    ldrb r1, [r3]

 ; CHECK-NEXT:    vmov.8 q6[1], r3
 ; CHECK-NEXT:    vmov.8 q6[2], r5
 ; CHECK-NEXT:    vmov.8 q6[3], r7
 ; CHECK-NEXT:    ldrb.w r7, [lr]
 ; CHECK-NEXT:    vmov.8 q6[4], r9
 ; CHECK-NEXT:    vmov.8 q6[5], r7
 ; CHECK-NEXT:    ldrb r4, [r1]
 ; CHECK-NEXT:    vmov r1, r5, d3
-; CHECK-NEXT:    vldrw.u32 q1, [sp, #248] @ 16-byte Reload
-; CHECK-NEXT:    vadd.i32 q0, q1, r0
-; CHECK-NEXT:    vstrw.32 q1, [sp, #248] @ 16-byte Spill
 ; CHECK-NEXT:    vldrw.u32 q1, [sp, #232] @ 16-byte Reload
 ; CHECK-NEXT:    ldrb.w r12, [r1]
 ; CHECK-NEXT:    vmov r1, r3, d9
 ; CHECK-NEXT:    ldrb r5, [r5]
 ; CHECK-NEXT:    vldrw.u32 q4, [sp, #184] @ 16-byte Reload
 ; CHECK-NEXT:    ldrb r1, [r1]
 ; CHECK-NEXT:    ldrb r3, [r3]
 ; CHECK-NEXT:    vmov.8 q6[6], r1
 ; CHECK-NEXT:    vmov r1, r7, d0
 ; CHECK-NEXT:    vmov.8 q6[7], r3
 ; CHECK-NEXT:    ldrb r1, [r1]
 ; CHECK-NEXT:    ldrb r7, [r7]
 ; CHECK-NEXT:    vmov.8 q7[4], r1
 ; CHECK-NEXT:    vmov r1, r3, d1
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #264] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.8 q7[5], r7
-; CHECK-NEXT:    vstrw.32 q0, [sp, #264] @ 16-byte Spill
 ; CHECK-NEXT:    vadd.i32 q0, q0, r0
 ; CHECK-NEXT:    ldrb r1, [r1]
 ; CHECK-NEXT:    ldrb r3, [r3]
 ; CHECK-NEXT:    vmov.8 q7[6], r1
 ; CHECK-NEXT:    ldrb r1, [r6]
 ; CHECK-NEXT:    vmov r7, r6, d0
 ; CHECK-NEXT:    vmov.8 q7[7], r3
 ; CHECK-NEXT:    vmov r3, lr, d1
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #280] @ 16-byte Reload
 ; CHECK-NEXT:    vmov.8 q7[8], r1
-; CHECK-NEXT:    vstrw.32 q0, [sp, #280] @ 16-byte Spill
 ; CHECK-NEXT:    vadd.i32 q0, q0, r0
 ; CHECK-NEXT:    vmov.8 q7[9], r4
 ; CHECK-NEXT:    vmov r4, r1, d0
 ; CHECK-NEXT:    vmov.8 q7[10], r12
 ; CHECK-NEXT:    vmov.8 q7[11], r5
 ; CHECK-NEXT:    ldrb r7, [r7]
 ; CHECK-NEXT:    ldrb r6, [r6]
 ; CHECK-NEXT:    ldrb r3, [r3]