[AArch64][GlobalISel] Enable some select combines after legalization

[aemerson]

Summary

The legalizer generates selects for some operations, which can have constant condition values, resulting in lots of dead code if it's not folded away.

[paquette]

LGTM

[tpopp]

Hello, unless I'm mistaken, this is breaking CodeGen/AArch64/arm64-ldxr-stxr.ll. Can you confirm if that's correct and rollback this commit until it's fixed?

[tpopp]

An important piece of information: this seems to happen only with assertions disabled (-DLLVM_ENABLE_ASSERTIONS=OFF)

[aemerson]

In D106762#2907272, @tpopp wrote:

An important piece of information: this seems to happen only with assertions disabled (-DLLVM_ENABLE_ASSERTIONS=OFF)

Thanks, I'll take a look.

[aemerson]

In D106762#2908160, @aemerson wrote:

In D106762#2907272, @tpopp wrote:

An important piece of information: this seems to happen only with assertions disabled (-DLLVM_ENABLE_ASSERTIONS=OFF)

Thanks, I'll take a look.

This could be just exposing an existing issue that previously we fell back on, but without asserts we try to continue with codegen.

[aemerson]

Ok, should be fixed in a11d9a1f480f.

[tpopp]

In D106762#2908222, @aemerson wrote:

Ok, should be fixed in a11d9a1f480f.

Thank you :)

llvm/lib/Target/AArch64/AArch64Combine.td

def AArch64PostLegalizerCombinerHelper
     : GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
                        [copy_prop, erase_undef_store, combines_for_extload,
                         sext_trunc_sextload,
                         hoist_logic_op_with_same_opcode_hands,
                         redundant_and, xor_of_and_with_same_reg,
                         extractvecelt_pairwise_add, redundant_or,
                         mul_const, redundant_sext_inreg,
                         form_bitfield_extract, rotate_out_of_range,
-                        icmp_to_true_false_known_bits, merge_unmerge]> {
+                        icmp_to_true_false_known_bits, merge_unmerge,
+                        select_combines]> {
   let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
 }

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll

 
 define void @atomic_load_relaxed(i64, i64, i128* %p, i128* %p2) {
 ; CHECK-LLSC-O1-LABEL: atomic_load_relaxed:
 ; CHECK-LLSC-O1:       // %bb.0:
 ; CHECK-LLSC-O1-NEXT:    mov w8, #64
 ; CHECK-LLSC-O1-NEXT:    sub x9, x8, #64 // =64
 ; CHECK-LLSC-O1-NEXT:  .LBB4_1: // %atomicrmw.start
 ; CHECK-LLSC-O1-NEXT:    // =>This Inner Loop Header: Depth=1
-; CHECK-LLSC-O1-NEXT:    ldxp x11, x10, [x2]
-; CHECK-LLSC-O1-NEXT:    sub x12, x8, #64 // =64
-; CHECK-LLSC-O1-NEXT:    tst wzr, #0x1
-; CHECK-LLSC-O1-NEXT:    lsl x13, x10, x8
-; CHECK-LLSC-O1-NEXT:    lsr x14, x10, x9
-; CHECK-LLSC-O1-NEXT:    lsl x10, x10, x12
-; CHECK-LLSC-O1-NEXT:    csel x10, x14, x10, ne
-; CHECK-LLSC-O1-NEXT:    csel x13, x13, xzr, ne
-; CHECK-LLSC-O1-NEXT:    csel x10, xzr, x10, ne
-; CHECK-LLSC-O1-NEXT:    orr x11, x11, x13
-; CHECK-LLSC-O1-NEXT:    lsl x13, x10, x9
-; CHECK-LLSC-O1-NEXT:    lsr x12, x10, x12
-; CHECK-LLSC-O1-NEXT:    orr x13, x13, x11, lsr #0
-; CHECK-LLSC-O1-NEXT:    tst wzr, #0x1
-; CHECK-LLSC-O1-NEXT:    csel x12, x13, x12, ne
-; CHECK-LLSC-O1-NEXT:    csel x12, x11, x12, ne
-; CHECK-LLSC-O1-NEXT:    stxp w13, x11, x12, [x2]
-; CHECK-LLSC-O1-NEXT:    cbnz w13, .LBB4_1
+; CHECK-LLSC-O1-NEXT:    ldxp x10, x8, [x2]
+; CHECK-LLSC-O1-NEXT:    lsl x8, x8, x9
+; CHECK-LLSC-O1-NEXT:    lsr x11, x8, x9
+; CHECK-LLSC-O1-NEXT:    stxp w12, x10, x11, [x2]
+; CHECK-LLSC-O1-NEXT:    cbnz w12, .LBB4_1
 ; CHECK-LLSC-O1-NEXT:  // %bb.2: // %atomicrmw.end
-; CHECK-LLSC-O1-NEXT:    mov v0.d[0], x11
-; CHECK-LLSC-O1-NEXT:    mov v0.d[1], x10
+; CHECK-LLSC-O1-NEXT:    mov v0.d[0], x10
+; CHECK-LLSC-O1-NEXT:    mov v0.d[1], x8
 ; CHECK-LLSC-O1-NEXT:    str q0, [x3]
 ; CHECK-LLSC-O1-NEXT:    ret
 ;
 ; CHECK-CAS-O1-LABEL: atomic_load_relaxed:
 ; CHECK-CAS-O1:       // %bb.0:
 ; CHECK-CAS-O1-NEXT:    mov w8, #64
 ; CHECK-CAS-O1-NEXT:    sub x9, x8, #64 // =64
 ; CHECK-CAS-O1-NEXT:  .LBB4_1: // %atomicrmw.start
 ; CHECK-CAS-O1-NEXT:    // =>This Inner Loop Header: Depth=1
-; CHECK-CAS-O1-NEXT:    ldxp x11, x10, [x2]
-; CHECK-CAS-O1-NEXT:    sub x12, x8, #64 // =64
-; CHECK-CAS-O1-NEXT:    lsl x13, x10, x8
-; CHECK-CAS-O1-NEXT:    lsr x14, x10, x9
-; CHECK-CAS-O1-NEXT:    lsl x10, x10, x12
-; CHECK-CAS-O1-NEXT:    tst wzr, #0x1
-; CHECK-CAS-O1-NEXT:    csel x13, x13, xzr, ne
-; CHECK-CAS-O1-NEXT:    csel x10, x14, x10, ne
-; CHECK-CAS-O1-NEXT:    csel x10, xzr, x10, ne
-; CHECK-CAS-O1-NEXT:    orr x11, x11, x13
-; CHECK-CAS-O1-NEXT:    lsl x13, x10, x9
-; CHECK-CAS-O1-NEXT:    orr x13, x13, x11, lsr #0
-; CHECK-CAS-O1-NEXT:    lsr x12, x10, x12
-; CHECK-CAS-O1-NEXT:    tst wzr, #0x1
-; CHECK-CAS-O1-NEXT:    csel x12, x13, x12, ne
-; CHECK-CAS-O1-NEXT:    csel x12, x11, x12, ne
-; CHECK-CAS-O1-NEXT:    stxp w13, x11, x12, [x2]
-; CHECK-CAS-O1-NEXT:    cbnz w13, .LBB4_1
+; CHECK-CAS-O1-NEXT:    ldxp x10, x8, [x2]
+; CHECK-CAS-O1-NEXT:    lsl x8, x8, x9
+; CHECK-CAS-O1-NEXT:    lsr x11, x8, x9
+; CHECK-CAS-O1-NEXT:    stxp w12, x10, x11, [x2]
+; CHECK-CAS-O1-NEXT:    cbnz w12, .LBB4_1
 ; CHECK-CAS-O1-NEXT:  // %bb.2: // %atomicrmw.end
-; CHECK-CAS-O1-NEXT:    mov v0.d[0], x11
-; CHECK-CAS-O1-NEXT:    mov v0.d[1], x10
+; CHECK-CAS-O1-NEXT:    mov v0.d[0], x10
+; CHECK-CAS-O1-NEXT:    mov v0.d[1], x8
 ; CHECK-CAS-O1-NEXT:    str q0, [x3]
 ; CHECK-CAS-O1-NEXT:    ret
 ;
 ; CHECK-LLSC-O0-LABEL: atomic_load_relaxed:
 ; CHECK-LLSC-O0:       // %bb.0:
 ; CHECK-LLSC-O0-NEXT:    sub sp, sp, #64 // =64
 ; CHECK-LLSC-O0-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-LLSC-O0-NEXT:    str x2, [sp, #48] // 8-byte Folded Spill

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+---
+# select (c, x, x) -> x
+name:            test_combine_select_same_res
+legalized:       true
+body:             |
+  bb.1:
+    liveins: $x0, $x1
+    ; CHECK-LABEL: name: test_combine_select_same_res
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
+    ; CHECK: $x0 = COPY [[SELECT]](s64)
+    %0:_(s64) = COPY $x0
+    %1:_(s1) = G_TRUNC %0
+    %2:_(s64) = G_SELECT %1, %0, %0
+    $x0 = COPY %2(s64)
+...
+---
+# select (undef, x, y) -> y
+name:            test_combine_select_undef_res0_res1
+legalized:       true
+body:             |
+  bb.1:
+    liveins: $x0, $x1
+    ; CHECK-LABEL: name: test_combine_select_undef_res0_res1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+    ; CHECK: $x0 = COPY [[COPY]](s64)
+    %0:_(s64) = COPY $x0
+    %1:_(s64) = COPY $x1
+    %2:_(s1) = G_IMPLICIT_DEF
+    %3:_(s64) = G_SELECT %2, %0, %1
+    $x0 = COPY %3(s64)
+...
+---
+# select (false, x, y) -> y
+name:            test_combine_select_false_res0_res1
+legalized:       true
+body:             |
+  bb.1:
+    liveins: $x0, $x1
+    ; CHECK-LABEL: name: test_combine_select_false_res0_res1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x1
+    ; CHECK: $x0 = COPY [[COPY]](s64)
+    %0:_(s64) = COPY $x0
+    %1:_(s64) = COPY $x1
+    %2:_(s1) = G_CONSTANT i1 false
+    %3:_(s64) = G_SELECT %2, %0, %1
+    $x0 = COPY %3(s64)
+...
+---
+# select (true, x, y) -> x
+name:            test_combine_select_true_res0_res1
+legalized:       true
+body:             |
+  bb.1:
+    liveins: $x0, $x1
+    ; CHECK-LABEL: name: test_combine_select_true_res0_res1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+    ; CHECK: $x0 = COPY [[COPY]](s64)
+    %0:_(s64) = COPY $x0
+    %1:_(s64) = COPY $x1
+    %2:_(s1) = G_CONSTANT i1 true
+    %3:_(s64) = G_SELECT %2, %0, %1
+    $x0 = COPY %3(s64)
+...

llvm/test/CodeGen/AArch64/fold-global-offsets.ll

 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: f7:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adrp x8, x3+88
 ; GISEL-NEXT:    add x8, x8, :lo12:x3+88
 ; GISEL-NEXT:    mov v0.d[1], x8
 ; GISEL-NEXT:    mov w9, #64
-; GISEL-NEXT:    mov d1, v0.d[1]
+; GISEL-NEXT:    mov d0, v0.d[1]
 ; GISEL-NEXT:    sub x8, x9, #64 // =64
-; GISEL-NEXT:    fmov x10, d1
 ; GISEL-NEXT:    fmov x9, d0
-; GISEL-NEXT:    lsl x11, x10, x8
-; GISEL-NEXT:    lsr x8, x10, x8
-; GISEL-NEXT:    orr x10, x11, x9, lsr #0
-; GISEL-NEXT:    tst wzr, #0x1
-; GISEL-NEXT:    csel x8, x10, x8, ne
-; GISEL-NEXT:    csel x8, x9, x8, ne
+; GISEL-NEXT:    lsr x8, x9, x8
 ; GISEL-NEXT:    ldr w0, [x8, #20]
 ; GISEL-NEXT:    ret
 
 entry:
   %l = load i32, i32* getelementptr (i32, i32* inttoptr (i64 trunc (i128 lshr (i128 bitcast (<2 x i64> <i64 undef, i64 ptrtoint (i8** getelementptr inbounds ({ [9 x i8*], [8 x i8*] }, { [9 x i8*], [8 x i8*] }* @x3, i64 0, inrange i32 1, i64 2) to i64)> to i128), i128 64) to i64) to i32*), i64 5)
   ret i32 %l
 }