[AArch64][GlobalISel] Add identity combines to post-legal combiner.

[aemerson]

Summary

We see some shifts of zero emitted during legalization.

[aemerson]

Update a test.

[jroelofs]

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir

19

Maybe the LHS ought to be a copy from a phys reg, so this test doesn't get accidentally repurposed if someone adds a constant-folding combines to it.

[aemerson]

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir

19

Good point.

llvm/lib/Target/AArch64/AArch64Combine.td

: GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
                         sext_trunc_sextload,
                         hoist_logic_op_with_same_opcode_hands,
                         redundant_and, xor_of_and_with_same_reg,
                         extractvecelt_pairwise_add, redundant_or,
                         mul_const, redundant_sext_inreg,
                         form_bitfield_extract, rotate_out_of_range,
                         icmp_to_true_false_known_bits, merge_unmerge,
                         select_combines, fold_merge_to_zext,
-                        constant_fold]> {
+                        constant_fold, identity_combines]> {
   let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
 }

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll

 }
 
 define void @atomic_load_relaxed(i64, i64, i128* %p, i128* %p2) {
 ; CHECK-LLSC-O1-LABEL: atomic_load_relaxed:
 ; CHECK-LLSC-O1:       // %bb.0:
 ; CHECK-LLSC-O1-NEXT:  .LBB4_1: // %atomicrmw.start
 ; CHECK-LLSC-O1-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-LLSC-O1-NEXT:    ldxp x9, x8, [x2]
-; CHECK-LLSC-O1-NEXT:    lsr x8, x8, #0
-; CHECK-LLSC-O1-NEXT:    lsr x10, x8, #0
-; CHECK-LLSC-O1-NEXT:    stxp w11, x9, x10, [x2]
-; CHECK-LLSC-O1-NEXT:    cbnz w11, .LBB4_1
+; CHECK-LLSC-O1-NEXT:    stxp w10, x9, x8, [x2]
+; CHECK-LLSC-O1-NEXT:    cbnz w10, .LBB4_1
 ; CHECK-LLSC-O1-NEXT:  // %bb.2: // %atomicrmw.end
 ; CHECK-LLSC-O1-NEXT:    mov v0.d[0], x9
 ; CHECK-LLSC-O1-NEXT:    mov v0.d[1], x8
 ; CHECK-LLSC-O1-NEXT:    str q0, [x3]
 ; CHECK-LLSC-O1-NEXT:    ret
 ;
 ; CHECK-CAS-O1-LABEL: atomic_load_relaxed:
 ; CHECK-CAS-O1:       // %bb.0:
 ; CHECK-CAS-O1-NEXT:  .LBB4_1: // %atomicrmw.start
 ; CHECK-CAS-O1-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-CAS-O1-NEXT:    ldxp x9, x8, [x2]
-; CHECK-CAS-O1-NEXT:    lsr x8, x8, #0
-; CHECK-CAS-O1-NEXT:    lsr x10, x8, #0
-; CHECK-CAS-O1-NEXT:    stxp w11, x9, x10, [x2]
-; CHECK-CAS-O1-NEXT:    cbnz w11, .LBB4_1
+; CHECK-CAS-O1-NEXT:    stxp w10, x9, x8, [x2]
+; CHECK-CAS-O1-NEXT:    cbnz w10, .LBB4_1
 ; CHECK-CAS-O1-NEXT:  // %bb.2: // %atomicrmw.end
 ; CHECK-CAS-O1-NEXT:    mov v0.d[0], x9
 ; CHECK-CAS-O1-NEXT:    mov v0.d[1], x8
 ; CHECK-CAS-O1-NEXT:    str q0, [x3]
 ; CHECK-CAS-O1-NEXT:    ret
 ;
 ; CHECK-LLSC-O0-LABEL: atomic_load_relaxed:
 ; CHECK-LLSC-O0:       // %bb.0:

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            shift_of_zero
+alignment:       4
+legalized:       true
+liveins:
+  - { reg: '$w0' }
+body:             |
+  bb.1.entry:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: shift_of_zero
+    ; CHECK: %a:_(s64) = COPY $x0
+    ; CHECK: $x0 = COPY %a(s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %a:_(s64) = COPY $x0
+    %b:_(s64) = G_CONSTANT i64 0
+    %res:_(s64) = G_LSHR %a, %b
+    $x0 = COPY %res(s64)
+    RET_ReallyLR implicit $x0
+
+...

llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
 ---
 # select (c, x, x) -> x
 name:            test_combine_select_same_res
 legalized:       true
 body:             |
   bb.1:
     liveins: $x0, $x1
     ; CHECK-LABEL: name: test_combine_select_same_res
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
-    ; CHECK: $x0 = COPY [[SELECT]](s64)
+    ; CHECK: $x0 = COPY [[COPY]](s64)
     %0:_(s64) = COPY $x0
     %1:_(s1) = G_TRUNC %0
     %2:_(s64) = G_SELECT %1, %0, %0
     $x0 = COPY %2(s64)
 ...
 ---
 # select (undef, x, y) -> y
 name:            test_combine_select_undef_res0_res1

llvm/test/CodeGen/AArch64/fold-global-offsets.ll

 ;
 ; GISEL-LABEL: f7:
 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    adrp x8, x3+88
 ; GISEL-NEXT:    add x8, x8, :lo12:x3+88
 ; GISEL-NEXT:    mov v0.d[1], x8
 ; GISEL-NEXT:    mov d0, v0.d[1]
 ; GISEL-NEXT:    fmov x8, d0
-; GISEL-NEXT:    lsr x8, x8, #0
 ; GISEL-NEXT:    ldr w0, [x8, #20]
 ; GISEL-NEXT:    ret
 
 entry:
   %l = load i32, i32* getelementptr (i32, i32* inttoptr (i64 trunc (i128 lshr (i128 bitcast (<2 x i64> <i64 undef, i64 ptrtoint (i8** getelementptr inbounds ({ [9 x i8*], [8 x i8*] }, { [9 x i8*], [8 x i8*] }* @x3, i64 0, inrange i32 1, i64 2) to i64)> to i128), i128 64) to i64) to i32*), i64 5)
   ret i32 %l
 }