[RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD

[benshi001]

Summary

These test will show the following optimization by future patches.

(mul x, (power_of_2 + 2)) => (SH1ADD x, (SLLI x, bits))
(mul x, (power_of_2 + 4)) => (SH2ADD x, (SLLI x, bits))
(mul x, (power_of_2 + 8)) => (SH3ADD x, (SLLI x, bits))

[benshi001]

This patch's child revision is approved, https://reviews.llvm.org/D106648

This one also needs approval since its child depends on it.

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; RV32IBA-LABEL: mul73:
 ; RV32IBA:       # %bb.0:
 ; RV32IBA-NEXT:    addi a1, zero, 73
 ; RV32IBA-NEXT:    mul a0, a0, a1
 ; RV32IBA-NEXT:    ret
   %c = mul i32 %a, 73
   ret i32 %c
 }
+
+define i32 @mul4098(i32 %a) {
+; RV32I-LABEL: mul4098:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 2
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul4098:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1
+; RV32IB-NEXT:    addi a1, a1, 2
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul4098:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    lui a1, 1
+; RV32IBA-NEXT:    addi a1, a1, 2
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 4098
+  ret i32 %c
+}
+
+define i32 @mul4100(i32 %a) {
+; RV32I-LABEL: mul4100:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 4
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul4100:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1
+; RV32IB-NEXT:    addi a1, a1, 4
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul4100:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    lui a1, 1
+; RV32IBA-NEXT:    addi a1, a1, 4
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 4100
+  ret i32 %c
+}
+
+define i32 @mul4104(i32 %a) {
+; RV32I-LABEL: mul4104:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 8
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: mul4104:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1
+; RV32IB-NEXT:    addi a1, a1, 8
+; RV32IB-NEXT:    mul a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBA-LABEL: mul4104:
+; RV32IBA:       # %bb.0:
+; RV32IBA-NEXT:    lui a1, 1
+; RV32IBA-NEXT:    addi a1, a1, 8
+; RV32IBA-NEXT:    mul a0, a0, a1
+; RV32IBA-NEXT:    ret
+  %c = mul i32 %a, 4104
+  ret i32 %c
+}

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64IBA-LABEL: mul73:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    addi a1, zero, 73
 ; RV64IBA-NEXT:    mul a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %c = mul i64 %a, 73
   ret i64 %c
 }
+
+define i64 @mul4098(i64 %a) {
+; RV64I-LABEL: mul4098:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, 2
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul4098:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 1
+; RV64IB-NEXT:    addiw a1, a1, 2
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul4098:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    lui a1, 1
+; RV64IBA-NEXT:    addiw a1, a1, 2
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 4098
+  ret i64 %c
+}
+
+define i64 @mul4100(i64 %a) {
+; RV64I-LABEL: mul4100:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, 4
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul4100:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 1
+; RV64IB-NEXT:    addiw a1, a1, 4
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul4100:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    lui a1, 1
+; RV64IBA-NEXT:    addiw a1, a1, 4
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 4100
+  ret i64 %c
+}
+
+define i64 @mul4104(i64 %a) {
+; RV64I-LABEL: mul4104:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, 8
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: mul4104:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 1
+; RV64IB-NEXT:    addiw a1, a1, 8
+; RV64IB-NEXT:    mul a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBA-LABEL: mul4104:
+; RV64IBA:       # %bb.0:
+; RV64IBA-NEXT:    lui a1, 1
+; RV64IBA-NEXT:    addiw a1, a1, 8
+; RV64IBA-NEXT:    mul a0, a0, a1
+; RV64IBA-NEXT:    ret
+  %c = mul i64 %a, 4104
+  ret i64 %c
+}