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Differential D106531

[ARM] Turn vecreduce_add(add(x, y)) into vecreduce(x) + vecreduce(y)
ClosedPublic

Authored by dmgreen on Jul 22 2021, 2:07 AM.

Details

Reviewers
samtebbs
SjoerdMeijer
NickGuy
ostannard
simon_tatham
Commits
rG4b563067622d: [ARM] Turn vecreduce_add(add(x, y)) into vecreduce(x) + vecreduce(y)
Summary

Under MVE we can use VADDV/VADDVA's to perform integer add reductions, so it can be beneficial to use more reductions than summing subvectors and reducing once. Especially for VMLAV/VMLAVA the mul can be incorporated into the reduction, producing less instructions.

Some of the test cases currently get larger due to extra integer adds, but will be improved in a followup patch.

Diff Detail

Event Timeline

dmgreen created this revision.Jul 22 2021, 2:07 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptJul 22 2021, 2:07 AM
dmgreen requested review of this revision.Jul 22 2021, 2:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 22 2021, 2:07 AM
Harbormaster completed remote builds in B115513: Diff 360732.Jul 22 2021, 2:08 AM
NickGuy accepted this revision.Jul 26 2021, 8:35 AM

LGTM

This revision is now accepted and ready to land.Jul 26 2021, 8:35 AM
dmgreen added a child revision: D106532: [ARM] Attempt to distribute reductions.Jul 30 2021, 1:46 AM
This revision was landed with ongoing or failed builds.Jul 30 2021, 2:11 AM
Closed by commit rG4b563067622d: [ARM] Turn vecreduce_add(add(x, y)) into vecreduce(x) + vecreduce(y) (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG4b563067622d: [ARM] Turn vecreduce_add(add(x, y)) into vecreduce(x) + vecreduce(y).

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
9 lines
test/
CodeGen/
Thumb2/
27 lines
12 lines
67 lines
784 lines

Diff 362998

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 15,970 Lines • ▼ Show 20 Linesstatic SDValue PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG,
if (!ST->hasMVEIntegerOps()) if (!ST->hasMVEIntegerOps())
return SDValue(); return SDValue();
assert(N->getOpcode() == ISD::VECREDUCE_ADD); assert(N->getOpcode() == ISD::VECREDUCE_ADD);
EVT ResVT = N->getValueType(0); EVT ResVT = N->getValueType(0);
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
SDLoc dl(N); SDLoc dl(N);
// Try to turn vecreduce_add(add(x, y)) into vecreduce(x) + vecreduce(y)
if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD &&
(N0.getValueType() == MVT::v4i32 || N0.getValueType() == MVT::v8i16 ||
N0.getValueType() == MVT::v16i8)) {
SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0));
SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1));
return DAG.getNode(ISD::ADD, dl, ResVT, Red0, Red1);
}
// We are looking for something that will have illegal types if left alone, // We are looking for something that will have illegal types if left alone,
// but that we can convert to a single instruction under MVE. For example // but that we can convert to a single instruction under MVE. For example
// vecreduce_add(sext(A, v8i32)) => VADDV.s16 A // vecreduce_add(sext(A, v8i32)) => VADDV.s16 A
// or // or
// vecreduce_add(mul(zext(A, v16i32), zext(B, v16i32))) => VMLADAV.u8 A, B // vecreduce_add(mul(zext(A, v16i32), zext(B, v16i32))) => VMLADAV.u8 A, B
// The legal cases are: // The legal cases are:
// VADDV u/s 8/16/32 // VADDV u/s 8/16/32
▲ Show 20 Lines • Show All 4,813 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vaddv.ll

Show All 29 Lines
entry: entry:
%r = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1) %r = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @vaddv_v8i32_i32(<8 x i32> %s1) { define arm_aapcs_vfpcc i32 @vaddv_v8i32_i32(<8 x i32> %s1) {
; CHECK-LABEL: vaddv_v8i32_i32: ; CHECK-LABEL: vaddv_v8i32_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddv.u32 r0, q0 ; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%r = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1) %r = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i16 @vaddv_v8i16_i16(<8 x i16> %s1) { define arm_aapcs_vfpcc i16 @vaddv_v8i16_i16(<8 x i16> %s1) {
; CHECK-LABEL: vaddv_v8i16_i16: ; CHECK-LABEL: vaddv_v8i16_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddv.u16 r0, q0 ; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%r = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1) %r = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<16 x i16> %s1) { define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<16 x i16> %s1) {
; CHECK-LABEL: vaddv_v16i16_i16: ; CHECK-LABEL: vaddv_v16i16_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i16 q0, q0, q1 ; CHECK-NEXT: vaddv.u16 r0, q1
; CHECK-NEXT: vaddv.u16 r0, q0 ; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%r = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1) %r = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc i8 @vaddv_v16i8_i8(<16 x i8> %s1) { define arm_aapcs_vfpcc i8 @vaddv_v16i8_i8(<16 x i8> %s1) {
; CHECK-LABEL: vaddv_v16i8_i8: ; CHECK-LABEL: vaddv_v16i8_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddv.u8 r0, q0 ; CHECK-NEXT: vaddv.u8 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%r = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1) %r = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
ret i8 %r ret i8 %r
} }
define arm_aapcs_vfpcc i8 @vaddv_v32i8_i8(<32 x i8> %s1) { define arm_aapcs_vfpcc i8 @vaddv_v32i8_i8(<32 x i8> %s1) {
; CHECK-LABEL: vaddv_v32i8_i8: ; CHECK-LABEL: vaddv_v32i8_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i8 q0, q0, q1 ; CHECK-NEXT: vaddv.u8 r0, q1
; CHECK-NEXT: vaddv.u8 r0, q0 ; CHECK-NEXT: vaddva.u8 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%r = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1) %r = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
ret i8 %r ret i8 %r
} }
define arm_aapcs_vfpcc i64 @vaddva_v2i64_i64(<2 x i64> %s1, i64 %x) { define arm_aapcs_vfpcc i64 @vaddva_v2i64_i64(<2 x i64> %s1, i64 %x) {
; CHECK-LABEL: vaddva_v2i64_i64: ; CHECK-LABEL: vaddva_v2i64_i64:
Show All 22 Linesentry:
%t = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1) %t = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
%r = add i32 %t, %x %r = add i32 %t, %x
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i32 @vaddva_v8i32_i32(<8 x i32> %s1, i32 %x) { define arm_aapcs_vfpcc i32 @vaddva_v8i32_i32(<8 x i32> %s1, i32 %x) {
; CHECK-LABEL: vaddva_v8i32_i32: ; CHECK-LABEL: vaddva_v8i32_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vaddva.u32 r0, q0 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%t = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1) %t = call i32 @llvm.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
%r = add i32 %t, %x %r = add i32 %t, %x
ret i32 %r ret i32 %r
} }
define arm_aapcs_vfpcc i16 @vaddva_v8i16_i16(<8 x i16> %s1, i16 %x) { define arm_aapcs_vfpcc i16 @vaddva_v8i16_i16(<8 x i16> %s1, i16 %x) {
; CHECK-LABEL: vaddva_v8i16_i16: ; CHECK-LABEL: vaddva_v8i16_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddva.u16 r0, q0 ; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%t = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1) %t = call i16 @llvm.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
%r = add i16 %t, %x %r = add i16 %t, %x
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc i16 @vaddva_v16i16_i16(<16 x i16> %s1, i16 %x) { define arm_aapcs_vfpcc i16 @vaddva_v16i16_i16(<16 x i16> %s1, i16 %x) {
; CHECK-LABEL: vaddva_v16i16_i16: ; CHECK-LABEL: vaddva_v16i16_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i16 q0, q0, q1 ; CHECK-NEXT: vaddv.u16 r2, q1
; CHECK-NEXT: vaddva.u16 r0, q0 ; CHECK-NEXT: vaddva.u16 r2, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%t = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1) %t = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
%r = add i16 %t, %x %r = add i16 %t, %x
ret i16 %r ret i16 %r
} }
define arm_aapcs_vfpcc i8 @vaddva_v16i8_i8(<16 x i8> %s1, i8 %x) { define arm_aapcs_vfpcc i8 @vaddva_v16i8_i8(<16 x i8> %s1, i8 %x) {
; CHECK-LABEL: vaddva_v16i8_i8: ; CHECK-LABEL: vaddva_v16i8_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddva.u8 r0, q0 ; CHECK-NEXT: vaddva.u8 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%t = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1) %t = call i8 @llvm.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
%r = add i8 %t, %x %r = add i8 %t, %x
ret i8 %r ret i8 %r
} }
define arm_aapcs_vfpcc i8 @vaddva_v32i8_i8(<32 x i8> %s1, i8 %x) { define arm_aapcs_vfpcc i8 @vaddva_v32i8_i8(<32 x i8> %s1, i8 %x) {
; CHECK-LABEL: vaddva_v32i8_i8: ; CHECK-LABEL: vaddva_v32i8_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i8 q0, q0, q1 ; CHECK-NEXT: vaddv.u8 r2, q1
; CHECK-NEXT: vaddva.u8 r0, q0 ; CHECK-NEXT: vaddva.u8 r2, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%t = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1) %t = call i8 @llvm.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
%r = add i8 %t, %x %r = add i8 %t, %x
ret i8 %r ret i8 %r
} }

llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll

Show First 20 Lines • Show All 516 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .pad #32 ; CHECK-NEXT: .pad #32
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: add r0, sp, #16 ; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: mov r1, sp ; CHECK-NEXT: mov r1, sp
; CHECK-NEXT: vstrw.32 q1, [r0] ; CHECK-NEXT: vstrw.32 q1, [r0]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vldrb.u16 q0, [r0, #8] ; CHECK-NEXT: vldrb.u16 q0, [r0, #8]
; CHECK-NEXT: vldrb.s16 q1, [r1, #8] ; CHECK-NEXT: vldrb.s16 q1, [r1, #8]
; CHECK-NEXT: vldrb.s16 q2, [r1] ; CHECK-NEXT: vmlav.u16 r2, q1, q0
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: vldrb.u16 q1, [r0] ; CHECK-NEXT: vldrb.s16 q1, [r1]
; CHECK-NEXT: vmul.i16 q1, q2, q1 ; CHECK-NEXT: vmlava.u16 r2, q1, q0
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: sxth r0, r2
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%xx = sext <16 x i8> %x to <16 x i16> %xx = sext <16 x i8> %x to <16 x i16>
%yy = zext <16 x i8> %y to <16 x i16> %yy = zext <16 x i8> %y to <16 x i16>
%m = mul <16 x i16> %xx, %yy %m = mul <16 x i16> %xx, %yy
%z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %m) %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %m)
ret i16 %z ret i16 %z
▲ Show 20 Lines • Show All 996 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll

Show First 20 Lines • Show All 697 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: add r0, sp, #16 ; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: mov r1, sp ; CHECK-NEXT: mov r1, sp
; CHECK-NEXT: vstrw.32 q1, [r0] ; CHECK-NEXT: vstrw.32 q1, [r0]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vcmp.i8 eq, q2, zr ; CHECK-NEXT: vcmp.i8 eq, q2, zr
; CHECK-NEXT: vmov.i8 q0, #0x0 ; CHECK-NEXT: vmov.i8 q0, #0x0
; CHECK-NEXT: vmov.i8 q1, #0xff ; CHECK-NEXT: vmov.i8 q1, #0xff
; CHECK-NEXT: vldrb.u16 q2, [r0] ; CHECK-NEXT: vldrb.s16 q2, [r1, #8]
; CHECK-NEXT: vpsel q0, q1, q0 ; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vldrb.s16 q3, [r1] ; CHECK-NEXT: vmov.u8 r2, q0[8]
; CHECK-NEXT: vmov.u8 r2, q0[0] ; CHECK-NEXT: vmov.u8 r3, q0[0]
; CHECK-NEXT: vmov.16 q1[0], r2 ; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vmov.u8 r2, q0[1] ; CHECK-NEXT: vmov.u8 r2, q0[9]
; CHECK-NEXT: vmov.16 q1[1], r2 ; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov.u8 r2, q0[2] ; CHECK-NEXT: vmov.u8 r2, q0[10]
; CHECK-NEXT: vmov.16 q1[2], r2 ; CHECK-NEXT: vmov.16 q1[2], r2
; CHECK-NEXT: vmov.u8 r2, q0[3] ; CHECK-NEXT: vmov.u8 r2, q0[11]
; CHECK-NEXT: vmov.16 q1[3], r2 ; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov.u8 r2, q0[4] ; CHECK-NEXT: vmov.u8 r2, q0[12]
; CHECK-NEXT: vmov.16 q1[4], r2 ; CHECK-NEXT: vmov.16 q1[4], r2
; CHECK-NEXT: vmov.u8 r2, q0[5] ; CHECK-NEXT: vmov.u8 r2, q0[13]
; CHECK-NEXT: vmov.16 q1[5], r2 ; CHECK-NEXT: vmov.16 q1[5], r2
; CHECK-NEXT: vmov.u8 r2, q0[6] ; CHECK-NEXT: vmov.u8 r2, q0[14]
; CHECK-NEXT: vmov.16 q1[6], r2 ; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov.u8 r2, q0[7] ; CHECK-NEXT: vmov.u8 r2, q0[15]
; CHECK-NEXT: vmov.16 q1[7], r2 ; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vmov.u8 r2, q0[8]
; CHECK-NEXT: vcmp.i16 ne, q1, zr ; CHECK-NEXT: vcmp.i16 ne, q1, zr
; CHECK-NEXT: vmov.i32 q1, #0x0 ; CHECK-NEXT: vldrb.u16 q1, [r0, #8]
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i16 q1, q3, q2 ; CHECK-NEXT: vmlavt.u16 r2, q2, q1
; CHECK-NEXT: vmov.16 q2[0], r2 ; CHECK-NEXT: vmov.16 q1[0], r3
; CHECK-NEXT: vmov.u8 r2, q0[9] ; CHECK-NEXT: vmov.u8 r3, q0[1]
; CHECK-NEXT: vmov.16 q2[1], r2 ; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov.u8 r2, q0[10] ; CHECK-NEXT: vmov.u8 r3, q0[2]
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vmov.16 q1[2], r3
; CHECK-NEXT: vmov.u8 r2, q0[11] ; CHECK-NEXT: vmov.u8 r3, q0[3]
; CHECK-NEXT: vmov.16 q2[3], r2 ; CHECK-NEXT: vmov.16 q1[3], r3
; CHECK-NEXT: vmov.u8 r2, q0[12] ; CHECK-NEXT: vmov.u8 r3, q0[4]
; CHECK-NEXT: vmov.16 q2[4], r2 ; CHECK-NEXT: vmov.16 q1[4], r3
; CHECK-NEXT: vmov.u8 r2, q0[13] ; CHECK-NEXT: vmov.u8 r3, q0[5]
; CHECK-NEXT: vmov.16 q2[5], r2 ; CHECK-NEXT: vmov.16 q1[5], r3
; CHECK-NEXT: vmov.u8 r2, q0[14] ; CHECK-NEXT: vmov.u8 r3, q0[6]
; CHECK-NEXT: vmov.16 q2[6], r2 ; CHECK-NEXT: vmov.16 q1[6], r3
; CHECK-NEXT: vmov.u8 r2, q0[15] ; CHECK-NEXT: vmov.u8 r3, q0[7]
; CHECK-NEXT: vmov.16 q2[7], r2 ; CHECK-NEXT: vmov.16 q1[7], r3
; CHECK-NEXT: vldrb.u16 q0, [r0, #8] ; CHECK-NEXT: vldrb.u16 q0, [r0]
; CHECK-NEXT: vcmp.i16 ne, q2, zr ; CHECK-NEXT: vcmp.i16 ne, q1, zr
; CHECK-NEXT: vldrb.s16 q2, [r1, #8] ; CHECK-NEXT: vldrb.s16 q1, [r1]
; CHECK-NEXT: vmul.i16 q0, q2, q0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i16 q1, q1, q0 ; CHECK-NEXT: vmlavat.u16 r2, q1, q0
; CHECK-NEXT: vaddv.u16 r0, q1 ; CHECK-NEXT: sxth r0, r2
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <16 x i8> %b, zeroinitializer %c = icmp eq <16 x i8> %b, zeroinitializer
%xx = sext <16 x i8> %x to <16 x i16> %xx = sext <16 x i8> %x to <16 x i16>
%yy = zext <16 x i8> %y to <16 x i16> %yy = zext <16 x i8> %y to <16 x i16>
%m = mul <16 x i16> %xx, %yy %m = mul <16 x i16> %xx, %yy
%s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer %s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer
▲ Show 20 Lines • Show All 2,317 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vecreduce-slp.ll

Show All 28 Linesentry:
%1 = load <4 x i32>, <4 x i32>* %0, align 4 %1 = load <4 x i32>, <4 x i32>* %0, align 4
%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1) %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
ret i32 %2 ret i32 %2
} }
define i32 @addv8i32i32(i32* %x) { define i32 @addv8i32i32(i32* %x) {
; CHECK-LABEL: addv8i32i32: ; CHECK-LABEL: addv8i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddv.u32 r0, q0 ; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <8 x i32>* %0 = bitcast i32* %x to <8 x i32>*
%1 = load <8 x i32>, <8 x i32>* %0, align 4 %1 = load <8 x i32>, <8 x i32>* %0, align 4
%2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %1) %2 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %1)
ret i32 %2 ret i32 %2
} }
define i32 @addv16i32i32(i32* %x) { define i32 @addv16i32i32(i32* %x) {
; CHECK-LABEL: addv16i32i32: ; CHECK-LABEL: addv16i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vaddv.u32 r0, q0 ; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <16 x i32>* %0 = bitcast i32* %x to <16 x i32>*
%1 = load <16 x i32>, <16 x i32>* %0, align 4 %1 = load <16 x i32>, <16 x i32>* %0, align 4
%2 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %1) %2 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %1)
ret i32 %2 ret i32 %2
} }
define i32 @addv24i32i32(i32* %x) { define i32 @addv24i32i32(i32* %x) {
; CHECK-LABEL: addv24i32i32: ; CHECK-LABEL: addv24i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q1, [r0, #80]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0, #64] ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vaddv.u32 r0, q1 ; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: add.w r1, r2, r12
; CHECK-NEXT: vaddva.u32 r0, q0 ; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <8 x i32>* %0 = bitcast i32* %x to <8 x i32>*
%1 = load <8 x i32>, <8 x i32>* %0, align 4 %1 = load <8 x i32>, <8 x i32>* %0, align 4
%arrayidx.8 = getelementptr inbounds i32, i32* %x, i32 8 %arrayidx.8 = getelementptr inbounds i32, i32* %x, i32 8
%2 = bitcast i32* %arrayidx.8 to <16 x i32>* %2 = bitcast i32* %arrayidx.8 to <16 x i32>*
%3 = load <16 x i32>, <16 x i32>* %2, align 4 %3 = load <16 x i32>, <16 x i32>* %2, align 4
%4 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %3) %4 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %3)
%5 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %1) %5 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %1)
%op.rdx = add nsw i32 %4, %5 %op.rdx = add nsw i32 %4, %5
ret i32 %op.rdx ret i32 %op.rdx
} }
define i32 @addv32i32i32(i32* %x) { define i32 @addv32i32i32(i32* %x) {
; CHECK-LABEL: addv32i32i32: ; CHECK-LABEL: addv32i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #112] ; CHECK-NEXT: vldrw.u32 q1, [r0, #112]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0, #80] ; CHECK-NEXT: vldrw.u32 q1, [r0, #80]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vldrw.u32 q1, [r0, #96] ; CHECK-NEXT: vldrw.u32 q1, [r0, #96]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrw.u32 q2, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: add.w r1, r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vaddv.u32 r0, q0 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <32 x i32>* %0 = bitcast i32* %x to <32 x i32>*
%1 = load <32 x i32>, <32 x i32>* %0, align 4 %1 = load <32 x i32>, <32 x i32>* %0, align 4
%2 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %1) %2 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %1)
ret i32 %2 ret i32 %2
} }
define i32 @addv64i32i32(i32* %x) { define i32 @addv64i32i32(i32* %x) {
; CHECK-LABEL: addv64i32i32: ; CHECK-LABEL: addv64i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: vldrw.u32 q1, [r0, #240]
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vldrw.u32 q0, [r0, #112]
; CHECK-NEXT: vldrw.u32 q0, [r0, #240] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vldrw.u32 q1, [r0, #112]
; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vldrw.u32 q3, [r0, #16]
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0, #176] ; CHECK-NEXT: vldrw.u32 q1, [r0, #176]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0, #208] ; CHECK-NEXT: vldrw.u32 q1, [r0, #208]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrw.u32 q2, [r0, #144] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: add.w r1, r2, r12
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q1, [r0, #144]
; CHECK-NEXT: vldrw.u32 q2, [r0, #96] ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vldrw.u32 q1, [r0, #224] ; CHECK-NEXT: vldrw.u32 q1, [r0, #224]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vldrw.u32 q0, [r0, #96]
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: add r2, r12
; CHECK-NEXT: vldrw.u32 q3, [r0, #64] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q1, [r0, #160]
; CHECK-NEXT: vldrw.u32 q2, [r0, #192] ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q3, [r0, #128] ; CHECK-NEXT: add r1, r2
; CHECK-NEXT: vadd.i32 q3, q4, q3 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: vldrw.u32 q1, [r0, #192]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vaddv.u32 r0, q0 ; CHECK-NEXT: add.w r3, r2, r12
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vldrw.u32 q1, [r0, #128]
; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: add r0, r3
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <64 x i32>* %0 = bitcast i32* %x to <64 x i32>*
%1 = load <64 x i32>, <64 x i32>* %0, align 4 %1 = load <64 x i32>, <64 x i32>* %0, align 4
%2 = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %1) %2 = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %1)
ret i32 %2 ret i32 %2
} }
▲ Show 20 Lines • Show All 271 Lines • ▼ Show 20 Linesentry:
%2 = sext <8 x i16> %1 to <8 x i32> %2 = sext <8 x i16> %1 to <8 x i32>
%3 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %2) %3 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %2)
ret i32 %3 ret i32 %3
} }
define i32 @addv16i32i16(i16* %x) { define i32 @addv16i32i16(i16* %x) {
; CHECK-LABEL: addv16i32i16: ; CHECK-LABEL: addv16i32i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r0, #24] ; CHECK-NEXT: vldrh.s32 q1, [r0, #24]
; CHECK-NEXT: vldrh.s32 q1, [r0, #8] ; CHECK-NEXT: vldrh.s32 q0, [r0, #8]
; CHECK-NEXT: vldrh.s32 q2, [r0] ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r0, #16] ; CHECK-NEXT: vldrh.s32 q1, [r0, #16]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vaddv.u32 r0, q0 ; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <16 x i16>* %0 = bitcast i16* %x to <16 x i16>*
%1 = load <16 x i16>, <16 x i16>* %0, align 2 %1 = load <16 x i16>, <16 x i16>* %0, align 2
%2 = sext <16 x i16> %1 to <16 x i32> %2 = sext <16 x i16> %1 to <16 x i32>
%3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2) %3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)
ret i32 %3 ret i32 %3
} }
define i32 @addv24i32i16(i16* %x) { define i32 @addv24i32i16(i16* %x) {
; CHECK-LABEL: addv24i32i16: ; CHECK-LABEL: addv24i32i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r0, #24] ; CHECK-NEXT: vldrh.s32 q1, [r0, #24]
; CHECK-NEXT: vldrh.s32 q1, [r0, #8] ; CHECK-NEXT: vldrh.s32 q0, [r0, #8]
; CHECK-NEXT: vldrh.s32 q2, [r0] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r0, #16] ; CHECK-NEXT: vldrh.s32 q1, [r0, #16]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vldrh.u16 q1, [r0, #32] ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vaddv.s16 r0, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vaddva.u32 r0, q0 ; CHECK-NEXT: vldrh.u16 q0, [r0, #32]
; CHECK-NEXT: add r2, r12
; CHECK-NEXT: vaddva.s16 r2, q0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <16 x i16>* %0 = bitcast i16* %x to <16 x i16>*
%1 = load <16 x i16>, <16 x i16>* %0, align 2 %1 = load <16 x i16>, <16 x i16>* %0, align 2
%2 = sext <16 x i16> %1 to <16 x i32> %2 = sext <16 x i16> %1 to <16 x i32>
%arrayidx.16 = getelementptr inbounds i16, i16* %x, i32 16 %arrayidx.16 = getelementptr inbounds i16, i16* %x, i32 16
%3 = bitcast i16* %arrayidx.16 to <8 x i16>* %3 = bitcast i16* %arrayidx.16 to <8 x i16>*
%4 = load <8 x i16>, <8 x i16>* %3, align 2 %4 = load <8 x i16>, <8 x i16>* %3, align 2
%5 = sext <8 x i16> %4 to <8 x i32> %5 = sext <8 x i16> %4 to <8 x i32>
%6 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2) %6 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)
%7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %5) %7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %5)
%op.rdx = add nsw i32 %6, %7 %op.rdx = add nsw i32 %6, %7
ret i32 %op.rdx ret i32 %op.rdx
} }
define i32 @addv32i32i16(i16* %x) { define i32 @addv32i32i16(i16* %x) {
; CHECK-LABEL: addv32i32i16: ; CHECK-LABEL: addv32i32i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r0, #56] ; CHECK-NEXT: vldrh.s32 q1, [r0, #56]
; CHECK-NEXT: vldrh.s32 q1, [r0, #24] ; CHECK-NEXT: vldrh.s32 q0, [r0, #24]
; CHECK-NEXT: vldrh.s32 q2, [r0, #8] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vldrh.s32 q3, [r0]
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r0, #40] ; CHECK-NEXT: vldrh.s32 q1, [r0, #40]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vldrh.s32 q2, [r0, #16] ; CHECK-NEXT: vldrh.s32 q0, [r0, #8]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vldrh.s32 q1, [r0, #48] ; CHECK-NEXT: vldrh.s32 q1, [r0, #48]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrh.s32 q2, [r0, #32] ; CHECK-NEXT: vldrh.s32 q0, [r0, #16]
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: add.w r1, r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrh.s32 q1, [r0, #32]
; CHECK-NEXT: vaddv.u32 r0, q0 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <32 x i16>* %0 = bitcast i16* %x to <32 x i16>*
%1 = load <32 x i16>, <32 x i16>* %0, align 2 %1 = load <32 x i16>, <32 x i16>* %0, align 2
%2 = sext <32 x i16> %1 to <32 x i32> %2 = sext <32 x i16> %1 to <32 x i32>
%3 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %2) %3 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %2)
ret i32 %3 ret i32 %3
} }
define i32 @addv64i32i16(i16* %x) { define i32 @addv64i32i16(i16* %x) {
; CHECK-LABEL: addv64i32i16: ; CHECK-LABEL: addv64i32i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r0, #56] ; CHECK-NEXT: vldrh.s32 q1, [r0, #56]
; CHECK-NEXT: vldrh.s32 q1, [r0, #24] ; CHECK-NEXT: vldrh.s32 q0, [r0, #24]
; CHECK-NEXT: vldrh.s32 q2, [r0, #8] ; CHECK-NEXT: ldrsh.w r3, [r0, #122]
; CHECK-NEXT: vldrh.s32 q3, [r0] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r0, #40] ; CHECK-NEXT: vldrh.s32 q1, [r0, #40]
; CHECK-NEXT: ldrsh.w r1, [r0, #120] ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q0, [r0, #8]
; CHECK-NEXT: vldrh.s32 q2, [r0, #16] ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r0, #48] ; CHECK-NEXT: vldrh.s32 q1, [r0, #48]
; CHECK-NEXT: ldrsh.w r3, [r0, #122] ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q0, [r0, #16]
; CHECK-NEXT: vldrh.s32 q2, [r0, #32] ; CHECK-NEXT: add.w r1, r2, r12
; CHECK-NEXT: ldrsh.w r12, [r0, #124] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: vldrh.s32 q1, [r0, #32]
; CHECK-NEXT: vldrh.s32 q3, [r0, #64] ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vldrh.s32 q2, [r0, #72] ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r0, #88] ; CHECK-NEXT: vldrh.s32 q1, [r0, #88]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrh.s32 q2, [r0, #80] ; CHECK-NEXT: vldrh.s32 q0, [r0, #72]
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: add r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vldrh.s32 q1, [r0, #80]
; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vldrh.s32 q0, [r0, #64]
; CHECK-NEXT: add r1, r2
; CHECK-NEXT: vaddv.u32 r2, q1 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vaddva.u32 r2, q0 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrh.u16 q0, [r0, #96] ; CHECK-NEXT: vldrh.u16 q0, [r0, #96]
; CHECK-NEXT: add r2, r12
; CHECK-NEXT: ldrsh.w r12, [r0, #124]
; CHECK-NEXT: add r2, r1
; CHECK-NEXT: ldrsh.w r1, [r0, #120]
; CHECK-NEXT: vaddva.s16 r2, q0 ; CHECK-NEXT: vaddva.s16 r2, q0
; CHECK-NEXT: vldrh.s32 q0, [r0, #112] ; CHECK-NEXT: vldrh.s32 q0, [r0, #112]
; CHECK-NEXT: ldrsh.w r0, [r0, #126] ; CHECK-NEXT: ldrsh.w r0, [r0, #126]
; CHECK-NEXT: vaddva.u32 r2, q0 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: add r1, r2 ; CHECK-NEXT: add r1, r2
; CHECK-NEXT: add r1, r3 ; CHECK-NEXT: add r1, r3
; CHECK-NEXT: add r1, r12 ; CHECK-NEXT: add r1, r12
; CHECK-NEXT: add r0, r1 ; CHECK-NEXT: add r0, r1
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesentry:
%7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %5) %7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %5)
%op.rdx = add nuw nsw i32 %6, %7 %op.rdx = add nuw nsw i32 %6, %7
ret i32 %op.rdx ret i32 %op.rdx
} }
define i32 @addv32i32i8(i8* %x) { define i32 @addv32i32i8(i8* %x) {
; CHECK-LABEL: addv32i32i8: ; CHECK-LABEL: addv32i32i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u32 q0, [r0, #28] ; CHECK-NEXT: vldrb.u32 q1, [r0, #28]
; CHECK-NEXT: vldrb.u32 q1, [r0, #12] ; CHECK-NEXT: vldrb.u32 q0, [r0, #12]
; CHECK-NEXT: vldrb.u32 q2, [r0, #4] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vldrb.u32 q3, [r0]
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrb.u32 q1, [r0, #20] ; CHECK-NEXT: vldrb.u32 q1, [r0, #20]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vldrb.u32 q2, [r0, #8] ; CHECK-NEXT: vldrb.u32 q0, [r0, #4]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vldrb.u32 q1, [r0, #24] ; CHECK-NEXT: vldrb.u32 q1, [r0, #24]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrb.u32 q2, [r0, #16] ; CHECK-NEXT: vldrb.u32 q0, [r0, #8]
; CHECK-NEXT: vadd.i32 q2, q3, q2 ; CHECK-NEXT: add.w r1, r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrb.u32 q1, [r0, #16]
; CHECK-NEXT: vaddv.u32 r0, q0 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i8* %x to <32 x i8>* %0 = bitcast i8* %x to <32 x i8>*
%1 = load <32 x i8>, <32 x i8>* %0, align 1 %1 = load <32 x i8>, <32 x i8>* %0, align 1
%2 = zext <32 x i8> %1 to <32 x i32> %2 = zext <32 x i8> %1 to <32 x i32>
%3 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %2) %3 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %2)
ret i32 %3 ret i32 %3
} }
define i32 @addv64i32i8(i8* %x) { define i32 @addv64i32i8(i8* %x) {
; CHECK-LABEL: addv64i32i8: ; CHECK-LABEL: addv64i32i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u32 q0, [r0, #28] ; CHECK-NEXT: vldrb.u32 q1, [r0, #28]
; CHECK-NEXT: vldrb.u32 q1, [r0, #12] ; CHECK-NEXT: vldrb.u32 q0, [r0, #12]
; CHECK-NEXT: vldrb.u32 q2, [r0, #4] ; CHECK-NEXT: ldrb.w r3, [r0, #61]
; CHECK-NEXT: vldrb.u32 q3, [r0] ; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrb.u32 q1, [r0, #20] ; CHECK-NEXT: vldrb.u32 q1, [r0, #20]
; CHECK-NEXT: ldrb.w r1, [r0, #60] ; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrb.u32 q0, [r0, #4]
; CHECK-NEXT: vldrb.u32 q2, [r0, #8] ; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrb.u32 q1, [r0, #24] ; CHECK-NEXT: vldrb.u32 q1, [r0, #24]
; CHECK-NEXT: ldrb.w r3, [r0, #61]
; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vldrb.u32 q2, [r0, #16]
; CHECK-NEXT: ldrb.w r12, [r0, #62]
; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vldrb.u8 q1, [r0, #32]
; CHECK-NEXT: vaddv.u8 r2, q1
; CHECK-NEXT: vaddva.u32 r2, q0 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrb.u32 q0, [r0, #8]
; CHECK-NEXT: add.w r1, r2, r12
; CHECK-NEXT: vaddv.u32 r12, q1
; CHECK-NEXT: vldrb.u32 q1, [r0, #16]
; CHECK-NEXT: vaddva.u32 r12, q0
; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: vaddv.u32 r2, q1
; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: vldrb.u8 q0, [r0, #32]
; CHECK-NEXT: add r2, r12
; CHECK-NEXT: ldrb.w r12, [r0, #62]
; CHECK-NEXT: add r2, r1
; CHECK-NEXT: ldrb.w r1, [r0, #60]
; CHECK-NEXT: vaddva.u8 r2, q0
; CHECK-NEXT: vldrb.u16 q0, [r0, #48] ; CHECK-NEXT: vldrb.u16 q0, [r0, #48]
; CHECK-NEXT: vaddva.u16 r2, q0 ; CHECK-NEXT: vaddva.u16 r2, q0
; CHECK-NEXT: vldrb.u32 q0, [r0, #56] ; CHECK-NEXT: vldrb.u32 q0, [r0, #56]
; CHECK-NEXT: ldrb.w r0, [r0, #63] ; CHECK-NEXT: ldrb.w r0, [r0, #63]
; CHECK-NEXT: vaddva.u32 r2, q0 ; CHECK-NEXT: vaddva.u32 r2, q0
; CHECK-NEXT: add r1, r2 ; CHECK-NEXT: add r1, r2
; CHECK-NEXT: add r1, r3 ; CHECK-NEXT: add r1, r3
; CHECK-NEXT: add r1, r12 ; CHECK-NEXT: add r1, r12
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Linesentry:
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %1) %2 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %1)
ret i16 %2 ret i16 %2
} }
define signext i16 @addv16i16i16(i16* %x) { define signext i16 @addv16i16i16(i16* %x) {
; CHECK-LABEL: addv16i16i16: ; CHECK-LABEL: addv16i16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0, #16] ; CHECK-NEXT: vldrh.u16 q1, [r0, #16]
; CHECK-NEXT: vldrh.u16 q1, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: vaddv.u16 r0, q1
; CHECK-NEXT: vaddv.u16 r0, q0 ; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <16 x i16>* %0 = bitcast i16* %x to <16 x i16>*
%1 = load <16 x i16>, <16 x i16>* %0, align 2 %1 = load <16 x i16>, <16 x i16>* %0, align 2
%2 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %1) %2 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %1)
ret i16 %2 ret i16 %2
} }
define signext i16 @addv24i16i16(i16* %x) { define signext i16 @addv24i16i16(i16* %x) {
; CHECK-LABEL: addv24i16i16: ; CHECK-LABEL: addv24i16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0, #32] ; CHECK-NEXT: vldrh.u16 q1, [r0, #32]
; CHECK-NEXT: vldrh.u16 q1, [r0, #16] ; CHECK-NEXT: vldrh.u16 q0, [r0, #16]
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: vaddv.u16 r2, q1
; CHECK-NEXT: vldrh.u16 q1, [r0] ; CHECK-NEXT: vaddva.u16 r2, q0
; CHECK-NEXT: vaddv.u16 r0, q1 ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vaddva.u16 r0, q0 ; CHECK-NEXT: vaddva.u16 r2, q0
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <8 x i16>* %0 = bitcast i16* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%arrayidx.8 = getelementptr inbounds i16, i16* %x, i32 8 %arrayidx.8 = getelementptr inbounds i16, i16* %x, i32 8
%2 = bitcast i16* %arrayidx.8 to <16 x i16>* %2 = bitcast i16* %arrayidx.8 to <16 x i16>*
%3 = load <16 x i16>, <16 x i16>* %2, align 2 %3 = load <16 x i16>, <16 x i16>* %2, align 2
%4 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %3) %4 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %3)
%5 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %1) %5 = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %1)
%op.rdx = add i16 %4, %5 %op.rdx = add i16 %4, %5
ret i16 %op.rdx ret i16 %op.rdx
} }
define signext i16 @addv32i16i16(i16* %x) { define signext i16 @addv32i16i16(i16* %x) {
; CHECK-LABEL: addv32i16i16: ; CHECK-LABEL: addv32i16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0, #48] ; CHECK-NEXT: vldrh.u16 q1, [r0, #48]
; CHECK-NEXT: vldrh.u16 q1, [r0, #16] ; CHECK-NEXT: vldrh.u16 q0, [r0, #16]
; CHECK-NEXT: vldrh.u16 q2, [r0] ; CHECK-NEXT: vaddv.u16 r2, q1
; CHECK-NEXT: vadd.i16 q0, q1, q0
; CHECK-NEXT: vldrh.u16 q1, [r0, #32] ; CHECK-NEXT: vldrh.u16 q1, [r0, #32]
; CHECK-NEXT: vadd.i16 q1, q2, q1 ; CHECK-NEXT: vaddva.u16 r2, q0
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vaddv.u16 r0, q0 ; CHECK-NEXT: vaddv.u16 r0, q1
; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <32 x i16>* %0 = bitcast i16* %x to <32 x i16>*
%1 = load <32 x i16>, <32 x i16>* %0, align 2 %1 = load <32 x i16>, <32 x i16>* %0, align 2
%2 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %1) %2 = call i16 @llvm.vector.reduce.add.v32i16(<32 x i16> %1)
ret i16 %2 ret i16 %2
} }
define signext i16 @addv64i16i16(i16* %x) { define signext i16 @addv64i16i16(i16* %x) {
; CHECK-LABEL: addv64i16i16: ; CHECK-LABEL: addv64i16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0, #112] ; CHECK-NEXT: vldrh.u16 q1, [r0, #112]
; CHECK-NEXT: vldrh.u16 q1, [r0, #48] ; CHECK-NEXT: vldrh.u16 q0, [r0, #48]
; CHECK-NEXT: vldrh.u16 q2, [r0, #16] ; CHECK-NEXT: vaddv.u16 r12, q1
; CHECK-NEXT: vldrh.u16 q3, [r0]
; CHECK-NEXT: vadd.i16 q0, q1, q0
; CHECK-NEXT: vldrh.u16 q1, [r0, #80] ; CHECK-NEXT: vldrh.u16 q1, [r0, #80]
; CHECK-NEXT: vadd.i16 q1, q2, q1 ; CHECK-NEXT: vaddva.u16 r12, q0
; CHECK-NEXT: vldrh.u16 q2, [r0, #32] ; CHECK-NEXT: vldrh.u16 q0, [r0, #16]
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: vaddv.u16 r2, q1
; CHECK-NEXT: vldrh.u16 q1, [r0, #96] ; CHECK-NEXT: vldrh.u16 q1, [r0, #96]
; CHECK-NEXT: vadd.i16 q1, q2, q1 ; CHECK-NEXT: vaddva.u16 r2, q0
; CHECK-NEXT: vldrh.u16 q2, [r0, #64] ; CHECK-NEXT: vldrh.u16 q0, [r0, #32]
; CHECK-NEXT: vadd.i16 q2, q3, q2 ; CHECK-NEXT: add.w r1, r2, r12
; CHECK-NEXT: vadd.i16 q1, q2, q1 ; CHECK-NEXT: vaddv.u16 r2, q1
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: vldrh.u16 q1, [r0, #64]
; CHECK-NEXT: vaddv.u16 r0, q0 ; CHECK-NEXT: vaddva.u16 r2, q0
; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vaddv.u16 r0, q1
; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <64 x i16>* %0 = bitcast i16* %x to <64 x i16>*
%1 = load <64 x i16>, <64 x i16>* %0, align 2 %1 = load <64 x i16>, <64 x i16>* %0, align 2
%2 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %1) %2 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> %1)
ret i16 %2 ret i16 %2
} }
▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Linesentry:
%5 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %1) %5 = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %1)
%op.rdx = add i8 %4, %5 %op.rdx = add i8 %4, %5
ret i8 %op.rdx ret i8 %op.rdx
} }
define zeroext i8 @addv32i8i8(i8* %x) { define zeroext i8 @addv32i8i8(i8* %x) {
; CHECK-LABEL: addv32i8i8: ; CHECK-LABEL: addv32i8i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #16] ; CHECK-NEXT: vldrb.u8 q1, [r0, #16]
; CHECK-NEXT: vldrb.u8 q1, [r0] ; CHECK-NEXT: vldrb.u8 q0, [r0]
; CHECK-NEXT: vadd.i8 q0, q1, q0 ; CHECK-NEXT: vaddv.u8 r0, q1
; CHECK-NEXT: vaddv.u8 r0, q0 ; CHECK-NEXT: vaddva.u8 r0, q0
; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i8* %x to <32 x i8>* %0 = bitcast i8* %x to <32 x i8>*
%1 = load <32 x i8>, <32 x i8>* %0, align 1 %1 = load <32 x i8>, <32 x i8>* %0, align 1
%2 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %1) %2 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %1)
ret i8 %2 ret i8 %2
} }
define zeroext i8 @addv64i8i8(i8* %x) { define zeroext i8 @addv64i8i8(i8* %x) {
; CHECK-LABEL: addv64i8i8: ; CHECK-LABEL: addv64i8i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #48] ; CHECK-NEXT: vldrb.u8 q1, [r0, #48]
; CHECK-NEXT: vldrb.u8 q1, [r0, #16] ; CHECK-NEXT: vldrb.u8 q0, [r0, #16]
; CHECK-NEXT: vldrb.u8 q2, [r0] ; CHECK-NEXT: vaddv.u8 r2, q1
; CHECK-NEXT: vadd.i8 q0, q1, q0
; CHECK-NEXT: vldrb.u8 q1, [r0, #32] ; CHECK-NEXT: vldrb.u8 q1, [r0, #32]
; CHECK-NEXT: vadd.i8 q1, q2, q1 ; CHECK-NEXT: vaddva.u8 r2, q0
; CHECK-NEXT: vadd.i8 q0, q1, q0 ; CHECK-NEXT: vldrb.u8 q0, [r0]
; CHECK-NEXT: vaddv.u8 r0, q0 ; CHECK-NEXT: vaddv.u8 r0, q1
; CHECK-NEXT: vaddva.u8 r0, q0
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i8* %x to <64 x i8>* %0 = bitcast i8* %x to <64 x i8>*
%1 = load <64 x i8>, <64 x i8>* %0, align 1 %1 = load <64 x i8>, <64 x i8>* %0, align 1
%2 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %1) %2 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> %1)
ret i8 %2 ret i8 %2
} }
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Linesentry:
ret i32 %5 ret i32 %5
} }
define i32 @mlav8i32i32(i32* %x, i32* %y) { define i32 @mlav8i32i32(i32* %x, i32* %y) {
; CHECK-LABEL: mlav8i32i32: ; CHECK-LABEL: mlav8i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r1, #16] ; CHECK-NEXT: vldrw.u32 q1, [r1, #16]
; CHECK-NEXT: vldrw.u32 q2, [r1] ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <8 x i32>* %0 = bitcast i32* %x to <8 x i32>*
%1 = load <8 x i32>, <8 x i32>* %0, align 4 %1 = load <8 x i32>, <8 x i32>* %0, align 4
%2 = bitcast i32* %y to <8 x i32>* %2 = bitcast i32* %y to <8 x i32>*
%3 = load <8 x i32>, <8 x i32>* %2, align 4 %3 = load <8 x i32>, <8 x i32>* %2, align 4
%4 = mul nsw <8 x i32> %3, %1 %4 = mul nsw <8 x i32> %3, %1
%5 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %4) %5 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %4)
ret i32 %5 ret i32 %5
} }
define i32 @mlav16i32i32(i32* %x, i32* %y) { define i32 @mlav16i32i32(i32* %x, i32* %y) {
; CHECK-LABEL: mlav16i32i32: ; CHECK-LABEL: mlav16i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vldrw.u32 q1, [r1, #48] ; CHECK-NEXT: vldrw.u32 q1, [r1, #48]
; CHECK-NEXT: vldrw.u32 q2, [r1, #16] ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrw.u32 q3, [r1] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q1, [r1, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vldrw.u32 q2, [r1, #32] ; CHECK-NEXT: vldrw.u32 q1, [r1, #32]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: add.w r0, r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <16 x i32>* %0 = bitcast i32* %x to <16 x i32>*
%1 = load <16 x i32>, <16 x i32>* %0, align 4 %1 = load <16 x i32>, <16 x i32>* %0, align 4
%2 = bitcast i32* %y to <16 x i32>* %2 = bitcast i32* %y to <16 x i32>*
%3 = load <16 x i32>, <16 x i32>* %2, align 4 %3 = load <16 x i32>, <16 x i32>* %2, align 4
%4 = mul nsw <16 x i32> %3, %1 %4 = mul nsw <16 x i32> %3, %1
%5 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %4) %5 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %4)
ret i32 %5 ret i32 %5
} }
define i32 @mlav24i32i32(i32* %x, i32* %y) { define i32 @mlav24i32i32(i32* %x, i32* %y) {
; CHECK-LABEL: mlav24i32i32: ; CHECK-LABEL: mlav24i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q1, [r1, #80] ; CHECK-NEXT: vldrw.u32 q1, [r1, #80]
; CHECK-NEXT: vldrw.u32 q2, [r1, #48] ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrw.u32 q3, [r1, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q1, [r1, #48]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r1, #64] ; CHECK-NEXT: vldrw.u32 q1, [r1, #64]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q1, [r1, #32]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r1] ; CHECK-NEXT: vldrw.u32 q1, [r1, #16]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: add.w r3, r2, r12
; CHECK-NEXT: vldrw.u32 q2, [r1, #16] ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: adds r0, r3, r2
; CHECK-NEXT: vmul.i32 q2, q3, q2
; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vaddv.u32 r0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <8 x i32>* %0 = bitcast i32* %x to <8 x i32>*
%1 = load <8 x i32>, <8 x i32>* %0, align 4 %1 = load <8 x i32>, <8 x i32>* %0, align 4
%2 = bitcast i32* %y to <8 x i32>* %2 = bitcast i32* %y to <8 x i32>*
%3 = load <8 x i32>, <8 x i32>* %2, align 4 %3 = load <8 x i32>, <8 x i32>* %2, align 4
%4 = mul nsw <8 x i32> %3, %1 %4 = mul nsw <8 x i32> %3, %1
%arrayidx.8 = getelementptr inbounds i32, i32* %x, i32 8 %arrayidx.8 = getelementptr inbounds i32, i32* %x, i32 8
%arrayidx1.8 = getelementptr inbounds i32, i32* %y, i32 8 %arrayidx1.8 = getelementptr inbounds i32, i32* %y, i32 8
%5 = bitcast i32* %arrayidx.8 to <16 x i32>* %5 = bitcast i32* %arrayidx.8 to <16 x i32>*
%6 = load <16 x i32>, <16 x i32>* %5, align 4 %6 = load <16 x i32>, <16 x i32>* %5, align 4
%7 = bitcast i32* %arrayidx1.8 to <16 x i32>* %7 = bitcast i32* %arrayidx1.8 to <16 x i32>*
%8 = load <16 x i32>, <16 x i32>* %7, align 4 %8 = load <16 x i32>, <16 x i32>* %7, align 4
%9 = mul nsw <16 x i32> %8, %6 %9 = mul nsw <16 x i32> %8, %6
%10 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %9) %10 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %9)
%11 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %4) %11 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %4)
%op.rdx = add nsw i32 %10, %11 %op.rdx = add nsw i32 %10, %11
ret i32 %op.rdx ret i32 %op.rdx
} }
define i32 @mlav32i32i32(i32* %x, i32* %y) { define i32 @mlav32i32i32(i32* %x, i32* %y) {
; CHECK-LABEL: mlav32i32i32: ; CHECK-LABEL: mlav32i32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q0, [r0, #112] ; CHECK-NEXT: vldrw.u32 q0, [r0, #112]
; CHECK-NEXT: vldrw.u32 q1, [r1, #112] ; CHECK-NEXT: vldrw.u32 q1, [r1, #112]
; CHECK-NEXT: vldrw.u32 q2, [r1, #48] ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrw.u32 q3, [r1, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q1, [r1, #48]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vldrw.u32 q4, [r1] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q1, [r1, #80]
; CHECK-NEXT: vldrw.u32 q2, [r1, #80] ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #80] ; CHECK-NEXT: vldrw.u32 q1, [r1, #16]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #96]
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vldrw.u32 q1, [r1, #96]
; CHECK-NEXT: vldrw.u32 q3, [r1, #32] ; CHECK-NEXT: add.w r3, r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrw.u32 q2, [r1, #96] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrw.u32 q1, [r1, #32]
; CHECK-NEXT: vldrw.u32 q1, [r0, #96] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q1, [r1, #64]
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vldrw.u32 q3, [r1, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vldrw.u32 q2, [r0, #64] ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: add.w r0, r2, r12
; CHECK-NEXT: vldrw.u32 q3, [r0] ; CHECK-NEXT: add r0, r3
; CHECK-NEXT: vmul.i32 q3, q4, q3
; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i32* %x to <32 x i32>* %0 = bitcast i32* %x to <32 x i32>*
%1 = load <32 x i32>, <32 x i32>* %0, align 4 %1 = load <32 x i32>, <32 x i32>* %0, align 4
%2 = bitcast i32* %y to <32 x i32>* %2 = bitcast i32* %y to <32 x i32>*
%3 = load <32 x i32>, <32 x i32>* %2, align 4 %3 = load <32 x i32>, <32 x i32>* %2, align 4
%4 = mul nsw <32 x i32> %3, %1 %4 = mul nsw <32 x i32> %3, %1
%5 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %4) %5 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %4)
▲ Show 20 Lines • Show All 653 Lines • ▼ Show 20 Linesentry:
ret i32 %7 ret i32 %7
} }
define i32 @mlav16i32i16(i16* %x, i16* %y) { define i32 @mlav16i32i16(i16* %x, i16* %y) {
; CHECK-LABEL: mlav16i32i16: ; CHECK-LABEL: mlav16i32i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r0, #24] ; CHECK-NEXT: vldrh.s32 q0, [r0, #24]
; CHECK-NEXT: vldrh.s32 q1, [r1, #24] ; CHECK-NEXT: vldrh.s32 q1, [r1, #24]
; CHECK-NEXT: vldrh.s32 q2, [r1, #8] ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrh.s32 q3, [r1] ; CHECK-NEXT: vldrh.s32 q0, [r0, #8]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
; CHECK-NEXT: vldrh.s32 q1, [r0, #8] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q0, [r0, #16]
; CHECK-NEXT: vldrh.s32 q2, [r1, #16] ; CHECK-NEXT: vldrh.s32 q1, [r1, #16]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r0, #16] ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q1, [r1]
; CHECK-NEXT: vldrh.s32 q2, [r0] ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: add.w r0, r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <16 x i16>* %0 = bitcast i16* %x to <16 x i16>*
%1 = load <16 x i16>, <16 x i16>* %0, align 2 %1 = load <16 x i16>, <16 x i16>* %0, align 2
%2 = sext <16 x i16> %1 to <16 x i32> %2 = sext <16 x i16> %1 to <16 x i32>
%3 = bitcast i16* %y to <16 x i16>* %3 = bitcast i16* %y to <16 x i16>*
%4 = load <16 x i16>, <16 x i16>* %3, align 2 %4 = load <16 x i16>, <16 x i16>* %3, align 2
%5 = sext <16 x i16> %4 to <16 x i32> %5 = sext <16 x i16> %4 to <16 x i32>
%6 = mul nsw <16 x i32> %5, %2 %6 = mul nsw <16 x i32> %5, %2
%7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6) %7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)
ret i32 %7 ret i32 %7
} }
define i32 @mlav24i32i16(i16* %x, i16* %y) { define i32 @mlav24i32i16(i16* %x, i16* %y) {
; CHECK-LABEL: mlav24i32i16: ; CHECK-LABEL: mlav24i32i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.s32 q0, [r0, #40] ; CHECK-NEXT: vldrh.s32 q0, [r0, #40]
; CHECK-NEXT: vldrh.s32 q1, [r1, #40] ; CHECK-NEXT: vldrh.s32 q1, [r1, #40]
; CHECK-NEXT: vldrh.s32 q2, [r1, #24] ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrh.s32 q3, [r1, #16] ; CHECK-NEXT: vldrh.s32 q0, [r0, #24]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vldrh.s32 q1, [r1, #24]
; CHECK-NEXT: vldrh.s32 q1, [r0, #24] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q0, [r0, #32]
; CHECK-NEXT: vldrh.s32 q2, [r1, #32] ; CHECK-NEXT: vldrh.s32 q1, [r1, #32]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r0, #32] ; CHECK-NEXT: vldrh.s32 q0, [r0, #16]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q1, [r1, #16]
; CHECK-NEXT: vldrh.s32 q2, [r0, #16] ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.u16 q1, [r1]
; CHECK-NEXT: vldrh.u16 q2, [r1] ; CHECK-NEXT: add r2, r12
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vmlava.s16 r2, q1, q0
; CHECK-NEXT: vldrh.u16 q1, [r0] ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: vmlav.s16 r0, q2, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <8 x i16>* %0 = bitcast i16* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = sext <8 x i16> %1 to <8 x i32> %2 = sext <8 x i16> %1 to <8 x i32>
%3 = bitcast i16* %y to <8 x i16>* %3 = bitcast i16* %y to <8 x i16>*
%4 = load <8 x i16>, <8 x i16>* %3, align 2 %4 = load <8 x i16>, <8 x i16>* %3, align 2
%5 = sext <8 x i16> %4 to <8 x i32> %5 = sext <8 x i16> %4 to <8 x i32>
Show All 11 Linesentry:
%15 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6) %15 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6)
%op.rdx = add nsw i32 %14, %15 %op.rdx = add nsw i32 %14, %15
ret i32 %op.rdx ret i32 %op.rdx
} }
define i32 @mlav32i32i16(i16* %x, i16* %y) { define i32 @mlav32i32i16(i16* %x, i16* %y) {
; CHECK-LABEL: mlav32i32i16: ; CHECK-LABEL: mlav32i32i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrh.s32 q0, [r0, #56] ; CHECK-NEXT: vldrh.s32 q0, [r0, #56]
; CHECK-NEXT: vldrh.s32 q1, [r1, #56] ; CHECK-NEXT: vldrh.s32 q1, [r1, #56]
; CHECK-NEXT: vldrh.s32 q2, [r1, #24] ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrh.s32 q3, [r1, #8] ; CHECK-NEXT: vldrh.s32 q0, [r0, #24]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vldrh.s32 q1, [r1, #24]
; CHECK-NEXT: vldrh.s32 q1, [r0, #24] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vldrh.s32 q4, [r1] ; CHECK-NEXT: vldrh.s32 q0, [r0, #40]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q1, [r1, #40]
; CHECK-NEXT: vldrh.s32 q2, [r1, #40] ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrh.s32 q0, [r0, #8]
; CHECK-NEXT: vldrh.s32 q1, [r0, #40] ; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vldrh.s32 q2, [r0, #8] ; CHECK-NEXT: vldrh.s32 q0, [r0, #48]
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vldrh.s32 q1, [r1, #48]
; CHECK-NEXT: vldrh.s32 q3, [r1, #16] ; CHECK-NEXT: add.w r3, r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrh.s32 q2, [r1, #48] ; CHECK-NEXT: vldrh.s32 q0, [r0, #16]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrh.s32 q1, [r1, #16]
; CHECK-NEXT: vldrh.s32 q1, [r0, #48] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q0, [r0, #32]
; CHECK-NEXT: vldrh.s32 q2, [r0, #16] ; CHECK-NEXT: vldrh.s32 q1, [r1, #32]
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vldrh.s32 q3, [r1, #32] ; CHECK-NEXT: vldrh.s32 q0, [r0]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrh.s32 q1, [r1]
; CHECK-NEXT: vldrh.s32 q2, [r0, #32] ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: add.w r0, r2, r12
; CHECK-NEXT: vldrh.s32 q3, [r0] ; CHECK-NEXT: add r0, r3
; CHECK-NEXT: vmul.i32 q3, q4, q3
; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <32 x i16>* %0 = bitcast i16* %x to <32 x i16>*
%1 = load <32 x i16>, <32 x i16>* %0, align 2 %1 = load <32 x i16>, <32 x i16>* %0, align 2
%2 = sext <32 x i16> %1 to <32 x i32> %2 = sext <32 x i16> %1 to <32 x i32>
%3 = bitcast i16* %y to <32 x i16>* %3 = bitcast i16* %y to <32 x i16>*
%4 = load <32 x i16>, <32 x i16>* %3, align 2 %4 = load <32 x i16>, <32 x i16>* %3, align 2
%5 = sext <32 x i16> %4 to <32 x i32> %5 = sext <32 x i16> %4 to <32 x i32>
▲ Show 20 Lines • Show All 466 Lines • ▼ Show 20 Linesentry:
%15 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6) %15 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6)
%op.rdx = add nuw nsw i32 %14, %15 %op.rdx = add nuw nsw i32 %14, %15
ret i32 %op.rdx ret i32 %op.rdx
} }
define i32 @mlav32i32i8(i8* %x, i8* %y) { define i32 @mlav32i32i8(i8* %x, i8* %y) {
; CHECK-LABEL: mlav32i32i8: ; CHECK-LABEL: mlav32i32i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrb.u32 q0, [r0, #28] ; CHECK-NEXT: vldrb.u32 q0, [r0, #28]
; CHECK-NEXT: vldrb.u32 q1, [r1, #28] ; CHECK-NEXT: vldrb.u32 q1, [r1, #28]
; CHECK-NEXT: vldrb.u32 q2, [r1, #12] ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrb.u32 q3, [r1, #4] ; CHECK-NEXT: vldrb.u32 q0, [r0, #12]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vldrb.u32 q1, [r1, #12]
; CHECK-NEXT: vldrb.u32 q1, [r0, #12] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vldrb.u32 q4, [r1] ; CHECK-NEXT: vldrb.u32 q0, [r0, #20]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrb.u32 q1, [r1, #20]
; CHECK-NEXT: vldrb.u32 q2, [r1, #20] ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrb.u32 q0, [r0, #4]
; CHECK-NEXT: vldrb.u32 q1, [r0, #20] ; CHECK-NEXT: vldrb.u32 q1, [r1, #4]
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vldrb.u32 q2, [r0, #4] ; CHECK-NEXT: vldrb.u32 q0, [r0, #24]
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vldrb.u32 q1, [r1, #24]
; CHECK-NEXT: vldrb.u32 q3, [r1, #8] ; CHECK-NEXT: add.w r3, r2, r12
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vmlav.u32 r12, q1, q0
; CHECK-NEXT: vldrb.u32 q2, [r1, #24] ; CHECK-NEXT: vldrb.u32 q0, [r0, #8]
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vldrb.u32 q1, [r1, #8]
; CHECK-NEXT: vldrb.u32 q1, [r0, #24] ; CHECK-NEXT: vmlava.u32 r12, q1, q0
; CHECK-NEXT: vmul.i32 q1, q2, q1 ; CHECK-NEXT: vldrb.u32 q0, [r0, #16]
; CHECK-NEXT: vldrb.u32 q2, [r0, #8] ; CHECK-NEXT: vldrb.u32 q1, [r1, #16]
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vmlav.u32 r2, q1, q0
; CHECK-NEXT: vldrb.u32 q3, [r1, #16] ; CHECK-NEXT: vldrb.u32 q0, [r0]
; CHECK-NEXT: vadd.i32 q1, q2, q1 ; CHECK-NEXT: vldrb.u32 q1, [r1]
; CHECK-NEXT: vldrb.u32 q2, [r0, #16] ; CHECK-NEXT: vmlava.u32 r2, q1, q0
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: add.w r0, r2, r12
; CHECK-NEXT: vldrb.u32 q3, [r0] ; CHECK-NEXT: add r0, r3
; CHECK-NEXT: vmul.i32 q3, q4, q3
; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vadd.i32 q1, q2, q1
; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i8* %x to <32 x i8>* %0 = bitcast i8* %x to <32 x i8>*
%1 = load <32 x i8>, <32 x i8>* %0, align 1 %1 = load <32 x i8>, <32 x i8>* %0, align 1
%2 = zext <32 x i8> %1 to <32 x i32> %2 = zext <32 x i8> %1 to <32 x i32>
%3 = bitcast i8* %y to <32 x i8>* %3 = bitcast i8* %y to <32 x i8>*
%4 = load <32 x i8>, <32 x i8>* %3, align 1 %4 = load <32 x i8>, <32 x i8>* %3, align 1
%5 = zext <32 x i8> %4 to <32 x i32> %5 = zext <32 x i8> %4 to <32 x i32>
▲ Show 20 Lines • Show All 242 Lines • ▼ Show 20 Linesentry:
ret i16 %5 ret i16 %5
} }
define signext i16 @mlav16i16i16(i16* %x, i16* %y) { define signext i16 @mlav16i16i16(i16* %x, i16* %y) {
; CHECK-LABEL: mlav16i16i16: ; CHECK-LABEL: mlav16i16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0, #16] ; CHECK-NEXT: vldrh.u16 q0, [r0, #16]
; CHECK-NEXT: vldrh.u16 q1, [r1, #16] ; CHECK-NEXT: vldrh.u16 q1, [r1, #16]
; CHECK-NEXT: vldrh.u16 q2, [r1] ; CHECK-NEXT: vmlav.u16 r2, q1, q0
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vldrh.u16 q1, [r0] ; CHECK-NEXT: vldrh.u16 q1, [r1]
; CHECK-NEXT: vmul.i16 q1, q2, q1 ; CHECK-NEXT: vmlava.u16 r2, q1, q0
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: sxth r0, r2
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <16 x i16>* %0 = bitcast i16* %x to <16 x i16>*
%1 = load <16 x i16>, <16 x i16>* %0, align 2 %1 = load <16 x i16>, <16 x i16>* %0, align 2
%2 = bitcast i16* %y to <16 x i16>* %2 = bitcast i16* %y to <16 x i16>*
%3 = load <16 x i16>, <16 x i16>* %2, align 2 %3 = load <16 x i16>, <16 x i16>* %2, align 2
%4 = mul <16 x i16> %3, %1 %4 = mul <16 x i16> %3, %1
%5 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %4) %5 = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %4)
ret i16 %5 ret i16 %5
} }
define signext i16 @mlav24i16i16(i16* %x, i16* %y) { define signext i16 @mlav24i16i16(i16* %x, i16* %y) {
; CHECK-LABEL: mlav24i16i16: ; CHECK-LABEL: mlav24i16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0, #32] ; CHECK-NEXT: vldrh.u16 q0, [r0, #32]
; CHECK-NEXT: vldrh.u16 q1, [r1, #32] ; CHECK-NEXT: vldrh.u16 q1, [r1, #32]
; CHECK-NEXT: vldrh.u16 q2, [r1, #16] ; CHECK-NEXT: vmlav.u16 r2, q1, q0
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vldrh.u16 q0, [r0, #16]
; CHECK-NEXT: vldrh.u16 q1, [r0, #16] ; CHECK-NEXT: vldrh.u16 q1, [r1, #16]
; CHECK-NEXT: vmul.i16 q1, q2, q1 ; CHECK-NEXT: vmlava.u16 r2, q1, q0
; CHECK-NEXT: vadd.i16 q0, q1, q0
; CHECK-NEXT: vldrh.u16 q1, [r1]
; CHECK-NEXT: vaddv.u16 r2, q0
; CHECK-NEXT: vldrh.u16 q0, [r0] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vldrh.u16 q1, [r1]
; CHECK-NEXT: vmlava.u16 r2, q1, q0 ; CHECK-NEXT: vmlava.u16 r2, q1, q0
; CHECK-NEXT: sxth r0, r2 ; CHECK-NEXT: sxth r0, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <8 x i16>* %0 = bitcast i16* %x to <8 x i16>*
%1 = load <8 x i16>, <8 x i16>* %0, align 2 %1 = load <8 x i16>, <8 x i16>* %0, align 2
%2 = bitcast i16* %y to <8 x i16>* %2 = bitcast i16* %y to <8 x i16>*
%3 = load <8 x i16>, <8 x i16>* %2, align 2 %3 = load <8 x i16>, <8 x i16>* %2, align 2
Show All 11 Linesentry:
ret i16 %op.rdx ret i16 %op.rdx
} }
define signext i16 @mlav32i16i16(i16* %x, i16* %y) { define signext i16 @mlav32i16i16(i16* %x, i16* %y) {
; CHECK-LABEL: mlav32i16i16: ; CHECK-LABEL: mlav32i16i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrh.u16 q0, [r0, #48] ; CHECK-NEXT: vldrh.u16 q0, [r0, #48]
; CHECK-NEXT: vldrh.u16 q1, [r1, #48] ; CHECK-NEXT: vldrh.u16 q1, [r1, #48]
; CHECK-NEXT: vldrh.u16 q2, [r1, #16] ; CHECK-NEXT: vmlav.u16 r12, q1, q0
; CHECK-NEXT: vldrh.u16 q3, [r1] ; CHECK-NEXT: vldrh.u16 q0, [r0, #16]
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vldrh.u16 q1, [r1, #16]
; CHECK-NEXT: vldrh.u16 q1, [r0, #16] ; CHECK-NEXT: vmlava.u16 r12, q1, q0
; CHECK-NEXT: vmul.i16 q1, q2, q1 ; CHECK-NEXT: vldrh.u16 q0, [r0, #32]
; CHECK-NEXT: vldrh.u16 q2, [r1, #32] ; CHECK-NEXT: vldrh.u16 q1, [r1, #32]
; CHECK-NEXT: vadd.i16 q0, q1, q0 ; CHECK-NEXT: vmlav.u16 r2, q1, q0
; CHECK-NEXT: vldrh.u16 q1, [r0, #32] ; CHECK-NEXT: vldrh.u16 q0, [r0]
; CHECK-NEXT: vmul.i16 q1, q2, q1 ; CHECK-NEXT: vldrh.u16 q1, [r1]
; CHECK-NEXT: vldrh.u16 q2, [r0] ; CHECK-NEXT: vmlava.u16 r2, q1, q0
; CHECK-NEXT: vmul.i16 q2, q3, q2 ; CHECK-NEXT: add.w r0, r2, r12
; CHECK-NEXT: vadd.i16 q1, q2, q1
; CHECK-NEXT: vadd.i16 q0, q1, q0
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i16* %x to <32 x i16>* %0 = bitcast i16* %x to <32 x i16>*
%1 = load <32 x i16>, <32 x i16>* %0, align 2 %1 = load <32 x i16>, <32 x i16>* %0, align 2
%2 = bitcast i16* %y to <32 x i16>* %2 = bitcast i16* %y to <32 x i16>*
%3 = load <32 x i16>, <32 x i16>* %2, align 2 %3 = load <32 x i16>, <32 x i16>* %2, align 2
%4 = mul <32 x i16> %3, %1 %4 = mul <32 x i16> %3, %1
▲ Show 20 Lines • Show All 409 Lines • ▼ Show 20 Linesentry:
ret i8 %op.rdx ret i8 %op.rdx
} }
define zeroext i8 @mlav32i8i8(i8* %x, i8* %y) { define zeroext i8 @mlav32i8i8(i8* %x, i8* %y) {
; CHECK-LABEL: mlav32i8i8: ; CHECK-LABEL: mlav32i8i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrb.u8 q0, [r0, #16] ; CHECK-NEXT: vldrb.u8 q0, [r0, #16]
; CHECK-NEXT: vldrb.u8 q1, [r1, #16] ; CHECK-NEXT: vldrb.u8 q1, [r1, #16]
; CHECK-NEXT: vldrb.u8 q2, [r1] ; CHECK-NEXT: vmlav.u8 r2, q1, q0
; CHECK-NEXT: vmul.i8 q0, q1, q0 ; CHECK-NEXT: vldrb.u8 q0, [r0]
; CHECK-NEXT: vldrb.u8 q1, [r0] ; CHECK-NEXT: vldrb.u8 q1, [r1]
; CHECK-NEXT: vmul.i8 q1, q2, q1 ; CHECK-NEXT: vmlava.u8 r2, q1, q0
; CHECK-NEXT: vadd.i8 q0, q1, q0 ; CHECK-NEXT: uxtb r0, r2
; CHECK-NEXT: vaddv.u8 r0, q0
; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast i8* %x to <32 x i8>* %0 = bitcast i8* %x to <32 x i8>*
%1 = load <32 x i8>, <32 x i8>* %0, align 1 %1 = load <32 x i8>, <32 x i8>* %0, align 1
%2 = bitcast i8* %y to <32 x i8>* %2 = bitcast i8* %y to <32 x i8>*
%3 = load <32 x i8>, <32 x i8>* %2, align 1 %3 = load <32 x i8>, <32 x i8>* %2, align 1
%4 = mul <32 x i8> %3, %1 %4 = mul <32 x i8> %3, %1
%5 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %4) %5 = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %4)
▲ Show 20 Lines • Show All 174 Lines • Show Last 20 Lines