[PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

[NeHuang]

Summary

This patch is in a series of patches to provide builtins for compatibility with the XL compiler.
This patch adds the builtin and intrinsic for "__stbcx".

[lei]

clang/include/clang/Basic/BuiltinsPPC.def

116

maybe move this up to where __builtin_ppc_stdcx is defined. To match what you did in PPC.cpp

clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c

31

Why not just add this tc to clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c?
The other related store functions are tested there.

[NeHuang]

• Addressed review comments from Lei
• Rebased the patch

[NeHuang]

clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c

31

__stbcx is only valid with pwr8 (or later cpu)

[nemanjai]

LGTM aside from a small nit.

clang/lib/Basic/Targets/PPC.cpp

121

Nit: move just under sthcx so the order makes sense: doubleword, word, haflword, byte.

[Conanap]

clang/lib/Sema/SemaChecking.cpp

3432

would prefer if this joined the list of sthcx, lharx and lbarx right below this case

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_ppc_fmsub, "dddd", "")
 BUILTIN(__builtin_ppc_fmsubs, "ffff", "")
 BUILTIN(__builtin_ppc_fnmadd, "dddd", "")
 BUILTIN(__builtin_ppc_fnmadds, "ffff", "")
 BUILTIN(__builtin_ppc_fnmsub, "dddd", "")
 BUILTIN(__builtin_ppc_fnmsubs, "ffff", "")
 BUILTIN(__builtin_ppc_fre, "dd", "")
 BUILTIN(__builtin_ppc_fres, "ff", "")
+BUILTIN(__builtin_ppc_stbcx, "icD*i", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
 BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "")
 
 BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "")

clang/lib/Basic/Targets/PPC.cpp

static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fetch_and_and", "__builtin_ppc_fetch_and_and");
   Builder.defineMacro("__fetch_and_andlp", "__builtin_ppc_fetch_and_andlp");
   Builder.defineMacro("__fetch_and_or", "__builtin_ppc_fetch_and_or");
   Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp");
   Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap");
   Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
   Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
   Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+  Builder.defineMacro("__stbcx", "__builtin_ppc_stbcx");
   Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
   Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
   Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
   Builder.defineMacro("__tw", "__builtin_ppc_tw");
   Builder.defineMacro("__trap", "__builtin_ppc_trap");
   Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
   Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
   Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case PPC::BI__builtin_ppc_mtfsb0:
   case PPC::BI__builtin_ppc_mtfsb1:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
   case PPC::BI__builtin_ppc_mtfsf:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 255);
   case PPC::BI__builtin_ppc_mtfsfi:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) ||
            SemaBuiltinConstantArgRange(TheCall, 1, 0, 15);
+  case PPC::BI__builtin_ppc_stbcx:
+    return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
+                            diag::err_ppc_builtin_only_on_arch, "8");
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
     return SemaBuiltinPPCMMACall(TheCall, Types);
 #include "clang/Basic/BuiltinsPPC.def"
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
 }
 

clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c

+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s --check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s --check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s --check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s --check-prefix=CHECK-PWR8
+// RUN: not %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+// RUN:   -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+
+extern volatile char *c_addr;
+extern char c;
+
+// CHECK-PWR8-LABEL: @test_builtin_ppc_stbcx(
+// CHECK-PWR8:         [[TMP0:%.*]] = load i8*, i8** @c_addr, align {{[0-9]+}}
+// CHECK-PWR8-NEXT:    [[TMP1:%.*]] = load i8, i8* @c, align 1
+// CHECK-PWR8-NEXT:    [[TMP2:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-PWR8-NEXT:    [[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(i8* [[TMP0]], i32 [[TMP2]])
+// CHECK-PWR8-NEXT:    ret i32 [[TMP3]]
+
+// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
+
+int test_builtin_ppc_stbcx() {
+  return __builtin_ppc_stbcx(c_addr, c);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_lwsync : GCCBuiltin<"__builtin_ppc_lwsync">,
                        Intrinsic<[], [], []>;
   def int_ppc_iospace_lwsync : GCCBuiltin<"__builtin_ppc_iospace_lwsync">,
                                Intrinsic<[], [], []>;
   // eieio instruction
   def int_ppc_eieio : GCCBuiltin<"__builtin_ppc_eieio">,
                       Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
                               Intrinsic<[],[],[]>;
+  def int_ppc_stbcx : GCCBuiltin<"__builtin_ppc_stbcx">,
+                      Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+                                [IntrWriteMem]>;
   def int_ppc_stdcx : GCCBuiltin<"__builtin_ppc_stdcx">,
                       Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i64_ty],
                                 [IntrWriteMem]>;
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
                       Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
                                 [IntrWriteMem]>;
   // compare
   def int_ppc_cmpeqb

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 // Now both high word and low word are reversed, next
 // swap the high word and low word.
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
           (STWCX gprc:$A, ForceXForm:$dst)>;
+def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
+          (STBCX gprc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
           (TW $IMM, $A, $B)>;
 def : Pat<(int_ppc_trap gprc:$A),
           (TWI 24, $A, 0)>;
 
 def : Pat<(int_ppc_fcfid f64:$A),
         (XSCVSXDDP $A)>;
 def : Pat<(int_ppc_fcfud f64:$A),

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

 ; CHECK-32-NEXT:    mfocrf 3, 128
 ; CHECK-32-NEXT:    srwi 3, 3, 28
 ; CHECK-32-NEXT:    blr
 entry:
   %0 = bitcast i32* %a to i8*
   %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %b)
   ret i32 %1
 }
+
+declare i32 @llvm.ppc.stbcx(i8*, i32)
+define signext i32 @test_stbcx(i8* %addr, i8 signext %val) {
+; CHECK-64-LABEL: test_stbcx:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    stbcx. 4, 0, 3
+; CHECK-64-NEXT:    mfocrf 3, 128
+; CHECK-64-NEXT:    srwi 3, 3, 28
+; CHECK-64-NEXT:    extsw 3, 3
+; CHECK-64-NEXT:    blr
+;
+; CHECK-32-LABEL: test_stbcx:
+; CHECK-32:       # %bb.0: # %entry
+; CHECK-32-NEXT:    stbcx. 4, 0, 3
+; CHECK-32-NEXT:    mfocrf 3, 128
+; CHECK-32-NEXT:    srwi 3, 3, 28
+; CHECK-32-NEXT:    blr
+entry:
+  %conv = sext i8 %val to i32
+  %0 = tail call i32 @llvm.ppc.stbcx(i8* %addr, i32 %conv)
+  ret i32 %0
+}