[AArch64] Fix for custom lowering <4 x i8> loads

[SjoerdMeijer]

Summary

This is a follow up D104782 that I reverted because of a failure in the llvm test suite. This is a diff against my local repo where I have first recommitted that again, just for clarity to only show this change.

The miscompile is made visible with a Bitcast node, that is lowered to a Store followed by a Load. The new Load instruction got the wrong operand (the DAG entry), so that the store instruction was no longer connected and removed.

[SjoerdMeijer]

llvm/test/CodeGen/AArch64/aarch64-load-ext.ll

288

I think we could legalise a v4i8 bitcast in a different way, but that's for another day.

[efriedma]

LGTM.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

4507

Minor change for code clarity.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

4507

Thanks, and will fix that before committing.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::LowerLOAD(SDValue Op,
   if (LoadNode->getExtensionType() == ISD::SEXTLOAD)
     ExtType = ISD::SIGN_EXTEND;
   else if (LoadNode->getExtensionType() == ISD::ZEXTLOAD ||
            LoadNode->getExtensionType() == ISD::EXTLOAD)
     ExtType = ISD::ZERO_EXTEND;
   else
     return SDValue();
 
-  SDValue Load = DAG.getLoad(MVT::f32, DL, DAG.getEntryNode(),
+  SDValue Load = DAG.getLoad(MVT::f32, DL, Op.getOperand(0),
                              LoadNode->getBasePtr(), MachinePointerInfo());
   SDValue Chain = Load.getValue(1);
   SDValue Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f32, Load);
   SDValue BC = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Vec);
   SDValue Ext = DAG.getNode(ExtType, DL, MVT::v8i16, BC);
   Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Ext,
                     DAG.getConstant(0, DL, MVT::i64));
   if (VT == MVT::v4i32)

llvm/test/CodeGen/AArch64/aarch64-load-ext.ll

; CHECK-BE-NEXT:    ret
   ret <4 x i32> %s
 }
 
 define <4 x i8> @bitcast(i32 %0) {
 ; CHECK-LE-LABEL: bitcast:
 ; CHECK-LE:       // %bb.0:
 ; CHECK-LE-NEXT:    sub sp, sp, #16 // =16
 ; CHECK-LE-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-LE-NEXT:    str w0, [sp, #12]
 ; CHECK-LE-NEXT:    ldr s0, [sp, #12]
 ; CHECK-LE-NEXT:    ushll v0.8h, v0.8b, #0
 ; CHECK-LE-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-LE-NEXT:    add sp, sp, #16 // =16
 ; CHECK-LE-NEXT:    ret
 ;
 ; CHECK-BE-LABEL: bitcast:
 ; CHECK-BE:       // %bb.0:
 ; CHECK-BE-NEXT:    sub sp, sp, #16 // =16
 ; CHECK-BE-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-BE-NEXT:    str w0, [sp, #12]
 ; CHECK-BE-NEXT:    ldr s0, [sp, #12]
 ; CHECK-BE-NEXT:    rev32 v0.8b, v0.8b
 ; CHECK-BE-NEXT:    ushll v0.8h, v0.8b, #0
 ; CHECK-BE-NEXT:    rev64 v0.4h, v0.4h
 ; CHECK-BE-NEXT:    add sp, sp, #16 // =16
 ; CHECK-BE-NEXT:    ret
   %2 = bitcast i32 %0 to <4 x i8>
   ret <4 x i8> %2
 }