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[AArch64] Fix for custom lowering <4 x i8> loads
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Authored by SjoerdMeijer on Jun 29 2021, 6:13 AM.

Details

Summary

This is a follow up D104782 that I reverted because of a failure in the llvm test suite. This is a diff against my local repo where I have first recommitted that again, just for clarity to only show this change.

The miscompile is made visible with a Bitcast node, that is lowered to a Store followed by a Load. The new Load instruction got the wrong operand (the DAG entry), so that the store instruction was no longer connected and removed.

Diff Detail

Event Timeline

SjoerdMeijer created this revision.Jun 29 2021, 6:13 AM
SjoerdMeijer requested review of this revision.Jun 29 2021, 6:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 29 2021, 6:13 AM
SjoerdMeijer added inline comments.Jun 29 2021, 6:20 AM
llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
288

I think we could legalise a v4i8 bitcast in a different way, but that's for another day.

efriedma accepted this revision.Jun 29 2021, 11:50 AM

LGTM.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
4507

Minor change for code clarity.

This revision is now accepted and ready to land.Jun 29 2021, 11:50 AM
SjoerdMeijer added inline comments.Jun 30 2021, 1:01 AM
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
4507

Thanks, and will fix that before committing.

This revision was landed with ongoing or failed builds.Jun 30 2021, 1:18 AM
This revision was automatically updated to reflect the committed changes.