[PowerPC] Change VSRpRC allocation order

[qiucf]

Summary

On PowerPC, VSRpRC represents the pairs of even and odd VSX register ((vs0, vs1), (vs2, vs3), ...).VRRC means the latter 32 registers in VSRC. So in some cases, when we're handling incoming VRRC arguments with VSRpRC, extra copies are produced.

This patch changes the allocation order of VSRpRC to put latter 32 ones first. This should not affect ACC/UACC since they only own the first 32 VSX registers.

[nemanjai]

Thanks for fixing this. I think we should go ahead with this fix as it is certainly an improvement. However, there is still some work to do here. I think it would be useful to test a change where we allocate all volatile registers first for VSFRC, VSSRC, VSRC, VSRpRC (namely, we allocate vs34-37, vs32-vs33, vs38-vs51, vs0-vs13, vs63-vs51, vs31-vs14). Of course, the relative order of the low 32 vs. high 32 might need to be different for the different register classes, but in any case, perhaps go through all the volatiles before we dig into the non-volatiles.
Of course, it would be good if the register coalescer was smart enough that the order doesn't matter, but this is certainly an easier fix.

In any case, this particular change can go in after the nits are addressed.

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

471

Please explain the strange allocation order with something like:

// Allocate in the same order as the underlying VSX/Altivec registers
// placing the Altivec ones first in order to reduce the interference
// with accumulator registers (that are overlaid over the 32 low
// VSX registers). This will reduce the number of copies when loading
// accumulator registers - which is a very common use for paired
// VSX registers.

llvm/test/CodeGen/PowerPC/mma-outer-product.ll

81

Any idea why this sticks around? This and line 85 seem to be dead copies. Similar artifacts appear in other tests.

llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll

13

This shows a side-effect of this change that should be mentioned in the commit message and maybe the code. Namely, if we end up allocating non-volatile registers, the first 12 underlying registers we allocate are 16 bytes rather than 8 bytes (since they're non-volatile Altivec registers rather than FP registers). This increases the size of stack frames for such functions.

[jsji]

llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll

13

Maybe we should provide alternative allocation order if user care about stack frame size ? Or even better if we can detect the usage of ACC or other potential conflicts before choosing this alternative allocation order? But yeah, that can be a FIXME and follow up.

[shchenz]

llvm/test/CodeGen/PowerPC/mma-intrinsics.ll

27

Why need to copy to v3? I think we can also use v2 for follow 4 xxlor?

llvm/test/CodeGen/PowerPC/mma-outer-product.ll

81

+1, there are some unnecessary vmr after this change. Maybe we need to have a look at why. Before the change, there are no such vector copies.

llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

23

unnecessary vmr?

[qiucf]

llvm/test/CodeGen/PowerPC/mma-intrinsics.ll

27

Yes. This extra copy is from below:

undef %5.sub_vsx1:vsrprc = COPY $v2 <--
%0:g8rc_and_g8rc_nox0 = COPY $x3
%5.sub_vsx0:vsrprc = COPY %5.sub_vsx1:vsrprc
%5:vsrprc = KILL_PAIR %5:vsrprc(tied-def 0)
undef %8.sub_pair0:uaccrc = COPY %5:vsrprc
%8.sub_pair1:uaccrc = COPY %5:vsrprc
%11:accrc = BUILD_UACC %8:uaccrc
%11:accrc = XXMTACC %11:accrc(tied-def 0)
%11:accrc = XXMFACC %11:accrc(tied-def 0)

Here the copy cannot be eliminated since we specified that the assigned register is sub_vsx1 (VSX register with odd number). We need to fix how MMA intrinsics are expanded.

llvm/test/CodeGen/PowerPC/mma-outer-product.ll

81

This copy is not due to this patch. It's just scheduled up. pmxvf64gernn acc0, vsp32, v2, 0, 0 used it. But yes, it can be eliminated. I'll follow it up

llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll

13

Yes. Maybe we can provide an option to control it first and then work on to resolve it properly.

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

let SubRegIndices = [sub_pair0, sub_pair1] in {
   def UACC7 : UACC<7, "acc7", [VSRp14, VSRp15]>, DwarfRegNum<[-1, -1]>;
 }
 def UACCRC : RegisterClass<"PPC", [v512i1], 128,
                            (add UACC0, UACC1, UACC2, UACC3,
                                 UACC4, UACC5, UACC6, UACC7)> {
   let Size = 512;
 }
 
-// Allocate in the same order as the underlying VSX registers.
 def VSRpRC :
   RegisterClass<"PPC", [v256i1], 128,
-                (add (sequence "VSRp%u", 0, 6),
-                     (sequence "VSRp%u", 15, 7), VSRp17, VSRp18,
-                     VSRp16, VSRp19, VSRp20, VSRp21, VSRp22, VSRp23,
-                     VSRp24, VSRp25, VSRp31, VSRp30, VSRp29, VSRp28,
-                     VSRp27, VSRp26)> {
+                (add VSRp17, VSRp18, VSRp16, VSRp19, VSRp20, VSRp21,
+                     VSRp22, VSRp23, VSRp24, VSRp25, VSRp31, VSRp30,
+                     VSRp29, VSRp28, VSRp27, VSRp26,
+                     (sequence "VSRp%u", 0, 6),
+                     (sequence "VSRp%u", 15, 7))> {
   let Size = 256;
 }
 
 // Make AllocationOrder as similar as G8RC's to avoid potential spilling.
 // Similarly, we have an AltOrder for 64-bit ELF ABI which r2 is allocated
 // at last.
 def G8pRC :
   RegisterClass<"PPC", [i128], 128,

llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll

 ; CHECK-NEXT:  # %bb.1: # %for.body.lr.ph
 ; CHECK-NEXT:    clrldi r6, r3, 32
 ; CHECK-NEXT:    addi r3, r4, 64
 ; CHECK-NEXT:    addi r4, r5, 64
 ; CHECK-NEXT:    mtctr r6
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_2: # %for.body
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lxvp vsp0, -64(r3)
-; CHECK-NEXT:    lxvp vsp2, -32(r3)
-; CHECK-NEXT:    lxvp vsp4, 0(r3)
-; CHECK-NEXT:    lxvp vsp6, 32(r3)
+; CHECK-NEXT:    lxvp vsp34, -64(r3)
+; CHECK-NEXT:    lxvp vsp36, -32(r3)
+; CHECK-NEXT:    lxvp vsp32, 0(r3)
+; CHECK-NEXT:    lxvp vsp38, 32(r3)
 ; CHECK-NEXT:    addi r3, r3, 1
-; CHECK-NEXT:    stxvp vsp0, -64(r4)
-; CHECK-NEXT:    stxvp vsp2, -32(r4)
-; CHECK-NEXT:    stxvp vsp4, 0(r4)
-; CHECK-NEXT:    stxvp vsp6, 32(r4)
+; CHECK-NEXT:    stxvp vsp34, -64(r4)
+; CHECK-NEXT:    stxvp vsp36, -32(r4)
+; CHECK-NEXT:    stxvp vsp32, 0(r4)
+; CHECK-NEXT:    stxvp vsp38, 32(r4)
 ; CHECK-NEXT:    addi r4, r4, 1
 ; CHECK-NEXT:    bdnz .LBB0_2
 ; CHECK-NEXT:  # %bb.3: # %for.cond.cleanup
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: foo:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmplwi r3, 0
 ; CHECK-BE-NEXT:    beqlr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %for.body.lr.ph
 ; CHECK-BE-NEXT:    clrldi r6, r3, 32
 ; CHECK-BE-NEXT:    addi r3, r4, 64
 ; CHECK-BE-NEXT:    addi r4, r5, 64
 ; CHECK-BE-NEXT:    mtctr r6
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_2: # %for.body
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    lxvp vsp0, -64(r3)
-; CHECK-BE-NEXT:    lxvp vsp2, -32(r3)
-; CHECK-BE-NEXT:    lxvp vsp4, 0(r3)
-; CHECK-BE-NEXT:    lxvp vsp6, 32(r3)
+; CHECK-BE-NEXT:    lxvp vsp34, -64(r3)
+; CHECK-BE-NEXT:    lxvp vsp36, -32(r3)
+; CHECK-BE-NEXT:    lxvp vsp32, 0(r3)
+; CHECK-BE-NEXT:    lxvp vsp38, 32(r3)
 ; CHECK-BE-NEXT:    addi r3, r3, 1
-; CHECK-BE-NEXT:    stxvp vsp0, -64(r4)
-; CHECK-BE-NEXT:    stxvp vsp2, -32(r4)
-; CHECK-BE-NEXT:    stxvp vsp4, 0(r4)
-; CHECK-BE-NEXT:    stxvp vsp6, 32(r4)
+; CHECK-BE-NEXT:    stxvp vsp34, -64(r4)
+; CHECK-BE-NEXT:    stxvp vsp36, -32(r4)
+; CHECK-BE-NEXT:    stxvp vsp32, 0(r4)
+; CHECK-BE-NEXT:    stxvp vsp38, 32(r4)
 ; CHECK-BE-NEXT:    addi r4, r4, 1
 ; CHECK-BE-NEXT:    bdnz .LBB0_2
 ; CHECK-BE-NEXT:  # %bb.3: # %for.cond.cleanup
 ; CHECK-BE-NEXT:    blr
 entry:
   %cmp35.not = icmp eq i32 %n, 0
   br i1 %cmp35.not, label %for.cond.cleanup, label %for.body.lr.ph
 

llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll

 ; CHECK-NEXT:    addi r4, r5, -1
 ; CHECK-NEXT:    lxv vs0, 0(r6)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-NEXT:    addi r4, r4, 1
 ; CHECK-NEXT:    mtctr r4
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_2: # %_loop_1_do_
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lxvp vsp2, 0(r3)
-; CHECK-NEXT:    lxvp vsp4, 32(r3)
+; CHECK-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-NEXT:    lxvp vsp36, 32(r3)
 ; CHECK-NEXT:    addi r3, r3, 128
-; CHECK-NEXT:    xvadddp vs0, vs0, vs3
-; CHECK-NEXT:    xvadddp vs0, vs0, vs2
-; CHECK-NEXT:    xvadddp vs0, vs0, vs5
-; CHECK-NEXT:    xvadddp vs0, vs0, vs4
+; CHECK-NEXT:    xvadddp vs0, vs0, vs35
+; CHECK-NEXT:    xvadddp vs0, vs0, vs34
+; CHECK-NEXT:    xvadddp vs0, vs0, vs37
+; CHECK-NEXT:    xvadddp vs0, vs0, vs36
 ; CHECK-NEXT:    bdnz .LBB0_2
 ; CHECK-NEXT:  # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge
 ; CHECK-NEXT:    stxv vs0, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: foo:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    ld r5, 0(r3)
 ; CHECK-BE-NEXT:    cmpdi r5, 1
 ; CHECK-BE-NEXT:    bltlr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %_loop_1_do_.lr.ph
 ; CHECK-BE-NEXT:    addi r3, r4, 1
 ; CHECK-BE-NEXT:    addi r4, r5, -1
 ; CHECK-BE-NEXT:    lxv vs0, 0(r6)
 ; CHECK-BE-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-BE-NEXT:    addi r4, r4, 1
 ; CHECK-BE-NEXT:    mtctr r4
 ; CHECK-BE-NEXT:    .p2align 5
 ; CHECK-BE-NEXT:  .LBB0_2: # %_loop_1_do_
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    lxvp vsp2, 0(r3)
-; CHECK-BE-NEXT:    lxvp vsp4, 32(r3)
+; CHECK-BE-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-BE-NEXT:    lxvp vsp36, 32(r3)
 ; CHECK-BE-NEXT:    addi r3, r3, 128
-; CHECK-BE-NEXT:    xvadddp vs0, vs0, vs2
-; CHECK-BE-NEXT:    xvadddp vs0, vs0, vs3
-; CHECK-BE-NEXT:    xvadddp vs0, vs0, vs4
-; CHECK-BE-NEXT:    xvadddp vs0, vs0, vs5
+; CHECK-BE-NEXT:    xvadddp vs0, vs0, vs34
+; CHECK-BE-NEXT:    xvadddp vs0, vs0, vs35
+; CHECK-BE-NEXT:    xvadddp vs0, vs0, vs36
+; CHECK-BE-NEXT:    xvadddp vs0, vs0, vs37
 ; CHECK-BE-NEXT:    bdnz .LBB0_2
 ; CHECK-BE-NEXT:  # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge
 ; CHECK-BE-NEXT:    stxv vs0, 0(r6)
 ; CHECK-BE-NEXT:    blr
 entry:
   %_val_n_2 = load i64, i64* %.n, align 8
   %_grt_tmp7 = icmp slt i64 %_val_n_2, 1
   br i1 %_grt_tmp7, label %_return_bb, label %_loop_1_do_.lr.ph

llvm/test/CodeGen/PowerPC/mma-acc-memops.ll

entry:
   %3 = load <512 x i1>, <512 x i1>* %1, align 64
   store <512 x i1> %3, <512 x i1>* %2, align 64
   ret void
 }
 
 define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
-; LE-PAIRED-NEXT:    plxv vs1, g@PCREL+32(0), 1
-; LE-PAIRED-NEXT:    plxv vs0, g@PCREL+48(0), 1
-; LE-PAIRED-NEXT:    pstxv vs1, g@PCREL+64(0), 1
-; LE-PAIRED-NEXT:    pstxv vs0, g@PCREL+80(0), 1
+; LE-PAIRED-NEXT:    plxv v3, g@PCREL+32(0), 1
+; LE-PAIRED-NEXT:    plxv v2, g@PCREL+48(0), 1
+; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+64(0), 1
+; LE-PAIRED-NEXT:    pstxv v2, g@PCREL+80(0), 1
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r3, r2, g@toc@ha
 ; BE-PAIRED-NEXT:    addi r3, r3, g@toc@l
-; BE-PAIRED-NEXT:    lxv vs1, 48(r3)
-; BE-PAIRED-NEXT:    lxv vs0, 32(r3)
-; BE-PAIRED-NEXT:    stxv vs1, 80(r3)
-; BE-PAIRED-NEXT:    stxv vs0, 64(r3)
+; BE-PAIRED-NEXT:    lxv v3, 48(r3)
+; BE-PAIRED-NEXT:    lxv v2, 32(r3)
+; BE-PAIRED-NEXT:    stxv v3, 80(r3)
+; BE-PAIRED-NEXT:    stxv v2, 64(r3)
 ; BE-PAIRED-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 1
   %0 = load <256 x i1>, <256 x i1>* %arrayidx, align 64
   %arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 2
   store <256 x i1> %0, <256 x i1>* %arrayidx1, align 64
   ret void
 }
 
 define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PAIRED-LABEL: testXLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    sldi r3, r3, 5
 ; LE-PAIRED-NEXT:    paddi r5, 0, g@PCREL, 1
 ; LE-PAIRED-NEXT:    add r6, r5, r3
-; LE-PAIRED-NEXT:    lxvx vs1, r5, r3
+; LE-PAIRED-NEXT:    lxvx v3, r5, r3
 ; LE-PAIRED-NEXT:    sldi r3, r4, 5
-; LE-PAIRED-NEXT:    lxv vs0, 16(r6)
+; LE-PAIRED-NEXT:    lxv v2, 16(r6)
 ; LE-PAIRED-NEXT:    add r4, r5, r3
-; LE-PAIRED-NEXT:    stxvx vs1, r5, r3
-; LE-PAIRED-NEXT:    stxv vs0, 16(r4)
+; LE-PAIRED-NEXT:    stxvx v3, r5, r3
+; LE-PAIRED-NEXT:    stxv v2, 16(r4)
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testXLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r5, r2, g@toc@ha
 ; BE-PAIRED-NEXT:    sldi r3, r3, 5
 ; BE-PAIRED-NEXT:    addi r5, r5, g@toc@l
 ; BE-PAIRED-NEXT:    add r6, r5, r3
-; BE-PAIRED-NEXT:    lxvx vs0, r5, r3
+; BE-PAIRED-NEXT:    lxvx v2, r5, r3
 ; BE-PAIRED-NEXT:    sldi r3, r4, 5
-; BE-PAIRED-NEXT:    lxv vs1, 16(r6)
+; BE-PAIRED-NEXT:    lxv v3, 16(r6)
 ; BE-PAIRED-NEXT:    add r4, r5, r3
-; BE-PAIRED-NEXT:    stxvx vs0, r5, r3
-; BE-PAIRED-NEXT:    stxv vs1, 16(r4)
+; BE-PAIRED-NEXT:    stxvx v2, r5, r3
+; BE-PAIRED-NEXT:    stxv v3, 16(r4)
 ; BE-PAIRED-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %SrcIdx
   %0 = load <256 x i1>, <256 x i1>* %arrayidx, align 64
   %arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %DstIdx
   store <256 x i1> %0, <256 x i1>* %arrayidx1, align 64
   ret void
 }
 
 define dso_local void @testUnalignedLdStPair() {
 ; LE-PAIRED-LABEL: testUnalignedLdStPair:
 ; LE-PAIRED:       # %bb.0: # %entry
-; LE-PAIRED-NEXT:    plxv vs1, g@PCREL+11(0), 1
-; LE-PAIRED-NEXT:    plxv vs0, g@PCREL+27(0), 1
-; LE-PAIRED-NEXT:    pstxv vs1, g@PCREL+19(0), 1
-; LE-PAIRED-NEXT:    pstxv vs0, g@PCREL+35(0), 1
+; LE-PAIRED-NEXT:    plxv v3, g@PCREL+11(0), 1
+; LE-PAIRED-NEXT:    plxv v2, g@PCREL+27(0), 1
+; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+19(0), 1
+; LE-PAIRED-NEXT:    pstxv v2, g@PCREL+35(0), 1
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testUnalignedLdStPair:
 ; BE-PAIRED:       # %bb.0: # %entry
 ; BE-PAIRED-NEXT:    addis r3, r2, g@toc@ha
 ; BE-PAIRED-NEXT:    li r4, 11
 ; BE-PAIRED-NEXT:    addi r3, r3, g@toc@l
-; BE-PAIRED-NEXT:    lxvx vs0, r3, r4
+; BE-PAIRED-NEXT:    lxvx v2, r3, r4
 ; BE-PAIRED-NEXT:    li r4, 27
-; BE-PAIRED-NEXT:    lxvx vs1, r3, r4
+; BE-PAIRED-NEXT:    lxvx v3, r3, r4
 ; BE-PAIRED-NEXT:    li r4, 35
-; BE-PAIRED-NEXT:    stxvx vs1, r3, r4
+; BE-PAIRED-NEXT:    stxvx v3, r3, r4
 ; BE-PAIRED-NEXT:    li r4, 19
-; BE-PAIRED-NEXT:    stxvx vs0, r3, r4
+; BE-PAIRED-NEXT:    stxvx v2, r3, r4
 ; BE-PAIRED-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* @g to i8*
   %add.ptr = getelementptr inbounds i8, i8* %0, i64 11
   %add.ptr1 = getelementptr inbounds i8, i8* %0, i64 19
   %1 = bitcast i8* %add.ptr to <256 x i1>*
   %2 = bitcast i8* %add.ptr1 to <256 x i1>*
   %3 = load <256 x i1>, <256 x i1>* %1, align 64
   store <256 x i1> %3, <256 x i1>* %2, align 64
   ret void
 }

llvm/test/CodeGen/PowerPC/mma-acc-spill.ll

 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xvf16ger2pp acc0, v2, v4
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxvp vsp0, 64(r1)
 ; CHECK-NEXT:    stxvp vsp2, 32(r1)
 ; CHECK-NEXT:    bl foo@notoc
 ; CHECK-NEXT:    lxvp vsp0, 64(r1)
 ; CHECK-NEXT:    lxvp vsp2, 32(r1)
-; CHECK-NEXT:    lxvp vsp4, 128(r1) # 32-byte Folded Reload
-; CHECK-NEXT:    lxvp vsp6, 96(r1) # 32-byte Folded Reload
+; CHECK-NEXT:    lxvp vsp34, 128(r1) # 32-byte Folded Reload
+; CHECK-NEXT:    lxvp vsp36, 96(r1) # 32-byte Folded Reload
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    xvf16ger2pp acc0, vs4, vs6
+; CHECK-NEXT:    xvf16ger2pp acc0, v2, v4
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r30)
 ; CHECK-NEXT:    stxv vs1, 32(r30)
 ; CHECK-NEXT:    stxv vs2, 16(r30)
 ; CHECK-NEXT:    stxvx vs3, 0, r30
 ; CHECK-NEXT:    addi r1, r1, 176
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

 ; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v4
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxvp vsp0, 112(r1)
 ; CHECK-BE-NEXT:    stxvp vsp2, 144(r1)
 ; CHECK-BE-NEXT:    bl foo
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    lxvp vsp0, 112(r1)
 ; CHECK-BE-NEXT:    lxvp vsp2, 144(r1)
-; CHECK-BE-NEXT:    lxvp vsp4, 208(r1) # 32-byte Folded Reload
-; CHECK-BE-NEXT:    lxvp vsp6, 176(r1) # 32-byte Folded Reload
+; CHECK-BE-NEXT:    lxvp vsp34, 208(r1) # 32-byte Folded Reload
+; CHECK-BE-NEXT:    lxvp vsp36, 176(r1) # 32-byte Folded Reload
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    xvf16ger2pp acc0, vs4, vs6
+; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v4
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r30)
 ; CHECK-BE-NEXT:    stxvx vs0, 0, r30
 ; CHECK-BE-NEXT:    stxv vs3, 48(r30)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r30)
 ; CHECK-BE-NEXT:    ld r30, 240(r1) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    addi r1, r1, 256
 ; CHECK-BE-NEXT:    ld r0, 16(r1)

llvm/test/CodeGen/PowerPC/mma-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
 
 ; assemble_acc
 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 define void @ass_acc(<512 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_acc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs1, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-NEXT:    xxlor vs4, vs0, vs0
-; CHECK-NEXT:    xxlor vs5, vs1, vs1
-; CHECK-NEXT:    xxlor vs6, vs0, vs0
-; CHECK-NEXT:    xxlor vs7, vs1, vs1
-; CHECK-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-NEXT:    xxlor vs3, vs7, vs7
+; CHECK-NEXT:    vmr v3, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs2, v2, v2
+; CHECK-NEXT:    xxlor vs3, v3, v3
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: ass_acc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs1, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs4, vs0, vs0
-; CHECK-BE-NEXT:    xxlor vs5, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs6, vs0, vs0
-; CHECK-BE-NEXT:    xxlor vs7, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-BE-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-BE-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-BE-NEXT:    xxlor vs3, vs7, vs7
+; CHECK-BE-NEXT:    vmr v3, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs2, v2, v2
+; CHECK-BE-NEXT:    xxlor vs3, v3, v3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   store <512 x i1> %0, <512 x i1>* %ptr, align 64
   ret void
 }
 
 ; xxmtacc
 declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
 define void @int_xxmtacc(<512 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmtacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs1, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-NEXT:    xxlor vs4, vs0, vs0
-; CHECK-NEXT:    xxlor vs5, vs1, vs1
-; CHECK-NEXT:    xxlor vs6, vs0, vs0
-; CHECK-NEXT:    xxlor vs7, vs1, vs1
-; CHECK-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-NEXT:    xxlor vs3, vs7, vs7
+; CHECK-NEXT:    vmr v3, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs2, v2, v2
+; CHECK-NEXT:    xxlor vs3, v3, v3
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: int_xxmtacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs1, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs4, vs0, vs0
-; CHECK-BE-NEXT:    xxlor vs5, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs6, vs0, vs0
-; CHECK-BE-NEXT:    xxlor vs7, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-BE-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-BE-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-BE-NEXT:    xxlor vs3, vs7, vs7
+; CHECK-BE-NEXT:    vmr v3, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs2, v2, v2
+; CHECK-BE-NEXT:    xxlor vs3, v3, v3
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
 ; One xxmtacc is generated from the call to assemble.acc then one xxmtacc is
 ; generated from the call to xxmtacc then one xxmfacc is generated for the store
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
   %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)
   store <512 x i1> %1, <512 x i1>* %ptr, align 64
   ret void
 }
 
 ; xxmfacc
 declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)
 define void @int_xxmfacc(<512 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmfacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs1, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-NEXT:    xxlor vs4, vs0, vs0
-; CHECK-NEXT:    xxlor vs5, vs1, vs1
-; CHECK-NEXT:    xxlor vs6, vs0, vs0
-; CHECK-NEXT:    xxlor vs7, vs1, vs1
-; CHECK-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-NEXT:    xxlor vs3, vs7, vs7
+; CHECK-NEXT:    vmr v3, v2
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs2, v2, v2
+; CHECK-NEXT:    xxlor vs3, v3, v3
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: int_xxmfacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs1, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs4, vs0, vs0
-; CHECK-BE-NEXT:    xxlor vs5, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs6, vs0, vs0
-; CHECK-BE-NEXT:    xxlor vs7, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-BE-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-BE-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-BE-NEXT:    xxlor vs3, vs7, vs7
+; CHECK-BE-NEXT:    vmr v3, v2
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs2, v2, v2
+; CHECK-BE-NEXT:    xxlor vs3, v3, v3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
 ; One xxmtacc is generated from the call to assemble.acc then one xxmfacc is
 ; generated from the call to xxmfacc then one xxmfacc is generated for the store

 define void @test_ldst_1(i8* nocapture readonly %vqp, <256 x i1>* %vpp, <16 x i8> %vc, i8* nocapture %resp)  {
 ; CHECK-LABEL: test_ldst_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    li r3, 8
-; CHECK-NEXT:    lxvpx vsp4, r4, r3
+; CHECK-NEXT:    lxvpx vsp36, r4, r3
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    pmxvf64gernn acc0, vsp4, v2, 0, 0
+; CHECK-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    li r3, 8
-; CHECK-BE-NEXT:    lxvpx vsp4, r4, r3
+; CHECK-BE-NEXT:    lxvpx vsp36, r4, r3
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

 ; Function Attrs: nofree nounwind
 define void @test_ldst_2(i8* nocapture readonly %vqp, <256 x i1>* %vpp, <16 x i8> %vc, i8* nocapture %resp)  {
 ; CHECK-LABEL: test_ldst_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
-; CHECK-NEXT:    lxvp vsp4, 0(r4)
+; CHECK-NEXT:    lxvp vsp36, 0(r4)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    xvf64gernp acc0, vsp4, v2
+; CHECK-NEXT:    xvf64gernp acc0, vsp36, v2
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
-; CHECK-BE-NEXT:    lxvp vsp4, 0(r4)
+; CHECK-BE-NEXT:    lxvp vsp36, 0(r4)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    xvf64gernp acc0, vsp4, v2
+; CHECK-BE-NEXT:    xvf64gernp acc0, vsp36, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

 ; Function Attrs: nofree nounwind
 define void @test_ldst_3(i8* nocapture readonly %vqp, i64 %offs, <256 x i1>* %vpp, <16 x i8> %vc, i8* nocapture %resp)  {
 ; CHECK-LABEL: test_ldst_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
-; CHECK-NEXT:    lxvp vsp4, 0(r5)
+; CHECK-NEXT:    lxvp vsp36, 0(r5)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    xvf64gernp acc0, vsp4, v2
+; CHECK-NEXT:    xvf64gernp acc0, vsp36, v2
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r9)
 ; CHECK-NEXT:    stxv vs1, 32(r9)
 ; CHECK-NEXT:    stxv vs2, 16(r9)
 ; CHECK-NEXT:    stxv vs3, 0(r9)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
-; CHECK-BE-NEXT:    lxvp vsp4, 0(r5)
+; CHECK-BE-NEXT:    lxvp vsp36, 0(r5)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    xvf64gernp acc0, vsp4, v2
+; CHECK-BE-NEXT:    xvf64gernp acc0, vsp36, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r9)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r9)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r9)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r9)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

llvm/test/CodeGen/PowerPC/mma-outer-product.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
 
 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
 declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
 define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, i8* %ptr) {
 ; CHECK-LABEL: intrinsics1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
-; CHECK-NEXT:    xxlor vs1, v4, v4
+; CHECK-NEXT:    vmr v1, v4
 ; CHECK-NEXT:    vmr v4, v3
 ; CHECK-NEXT:    ld r3, 96(r1)
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs3, v2, v2
-; CHECK-NEXT:    xxlor vs2, v5, v5
-; CHECK-NEXT:    xxlor vs4, vs0, vs0
-; CHECK-NEXT:    xxlor vs5, vs1, vs1
-; CHECK-NEXT:    xxlor vs6, v4, v4
-; CHECK-NEXT:    xxlor vs7, v5, v5
-; CHECK-NEXT:    xxmtacc acc1
-; CHECK-NEXT:    xvi4ger8pp acc1, v2, v3
-; CHECK-NEXT:    xvf16ger2pp acc1, v2, vs1
-; CHECK-NEXT:    pmxvf32gerpn acc1, v3, v5, 0, 0
-; CHECK-NEXT:    pmxvf64gernp acc1, vsp2, vs0, 0, 0
-; CHECK-NEXT:    xxmfacc acc1
-; CHECK-NEXT:    stxv vs4, 48(r3)
-; CHECK-NEXT:    stxv vs5, 32(r3)
-; CHECK-NEXT:    stxv vs6, 16(r3)
-; CHECK-NEXT:    stxvx vs7, 0, r3
+; CHECK-NEXT:    vmr v0, v2
+; CHECK-NEXT:    xxlor vs0, v0, v0
+; CHECK-NEXT:    xxlor vs1, v1, v1
+; CHECK-NEXT:    xxlor vs2, v4, v4
+; CHECK-NEXT:    xxlor vs3, v5, v5
+; CHECK-NEXT:    xxmtacc acc0
+; CHECK-NEXT:    xvi4ger8pp acc0, v2, v3
+; CHECK-NEXT:    xvf16ger2pp acc0, v2, v1
+; CHECK-NEXT:    pmxvf32gerpn acc0, v3, v5, 0, 0
+; CHECK-NEXT:    vmr v3, v0
+; CHECK-NEXT:    vmr v2, v5
+; CHECK-NEXT:    pmxvf64gernp acc0, vsp34, v0, 0, 0
+; CHECK-NEXT:    xxmfacc acc0
+; CHECK-NEXT:    stxv vs0, 48(r3)
+; CHECK-NEXT:    stxv vs1, 32(r3)
+; CHECK-NEXT:    stxv vs2, 16(r3)
+; CHECK-NEXT:    stxvx vs3, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: intrinsics1:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
-; CHECK-BE-NEXT:    xxlor vs1, v4, v4
+; CHECK-BE-NEXT:    vmr v1, v4
 ; CHECK-BE-NEXT:    vmr v4, v3
 ; CHECK-BE-NEXT:    ld r3, 112(r1)
-; CHECK-BE-NEXT:    xxlor vs0, v2, v2
-; CHECK-BE-NEXT:    xxlor vs3, v2, v2
-; CHECK-BE-NEXT:    xxlor vs2, v5, v5
-; CHECK-BE-NEXT:    xxlor vs4, vs0, vs0
-; CHECK-BE-NEXT:    xxlor vs5, vs1, vs1
-; CHECK-BE-NEXT:    xxlor vs6, v4, v4
-; CHECK-BE-NEXT:    xxlor vs7, v5, v5
-; CHECK-BE-NEXT:    xxmtacc acc1
-; CHECK-BE-NEXT:    xvi4ger8pp acc1, v2, v3
-; CHECK-BE-NEXT:    xvf16ger2pp acc1, v2, vs1
-; CHECK-BE-NEXT:    pmxvf32gerpn acc1, v3, v5, 0, 0
-; CHECK-BE-NEXT:    pmxvf64gernp acc1, vsp2, vs0, 0, 0
-; CHECK-BE-NEXT:    xxmfacc acc1
-; CHECK-BE-NEXT:    stxv vs5, 16(r3)
-; CHECK-BE-NEXT:    stxvx vs4, 0, r3
-; CHECK-BE-NEXT:    stxv vs7, 48(r3)
-; CHECK-BE-NEXT:    stxv vs6, 32(r3)
+; CHECK-BE-NEXT:    vmr v0, v2
+; CHECK-BE-NEXT:    xxlor vs0, v0, v0
+; CHECK-BE-NEXT:    xxlor vs1, v1, v1
+; CHECK-BE-NEXT:    xxlor vs2, v4, v4
+; CHECK-BE-NEXT:    xxlor vs3, v5, v5
+; CHECK-BE-NEXT:    xxmtacc acc0
+; CHECK-BE-NEXT:    xvi4ger8pp acc0, v2, v3
+; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v1
+; CHECK-BE-NEXT:    pmxvf32gerpn acc0, v3, v5, 0, 0
+; CHECK-BE-NEXT:    vmr v3, v0
+; CHECK-BE-NEXT:    vmr v2, v5
+; CHECK-BE-NEXT:    pmxvf64gernp acc0, vsp34, v0, 0, 0
+; CHECK-BE-NEXT:    xxmfacc acc0
+; CHECK-BE-NEXT:    stxv vs1, 16(r3)
+; CHECK-BE-NEXT:    stxvx vs0, 0, r3
+; CHECK-BE-NEXT:    stxv vs3, 48(r3)
+; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    blr
   %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4)
   %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)
   %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
   %4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)
   %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)
   %6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)
   %7 = bitcast i8* %ptr to <512 x i1>*
   store <512 x i1> %6, <512 x i1>* %7, align 64
   ret void
 }
 
 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
 define void @intrinsics2(<16 x i8>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3, <16 x i8>* %ptr4, i8* %ptr) {
 ; CHECK-LABEL: intrinsics2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lxv vs4, 0(r3)
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs6, 0(r5)
-; CHECK-NEXT:    lxv vs7, 0(r6)
-; CHECK-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-NEXT:    xxlor vs9, vs4, vs4
-; CHECK-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-NEXT:    xxlor vs3, vs7, vs7
-; CHECK-NEXT:    xxlor vs8, vs7, vs7
-; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    xvi8ger4pp acc0, vs4, vs5
-; CHECK-NEXT:    xvf16ger2pn acc0, vs4, vs6
-; CHECK-NEXT:    pmxvf32gernn acc0, vs5, vs7, 0, 0
-; CHECK-NEXT:    pmxvf64gernn acc0, vsp8, vs4, 0, 0
+; CHECK-NEXT:    lxv v2, 0(r3)
+; CHECK-NEXT:    lxv v3, 0(r4)
+; CHECK-NEXT:    lxv v4, 0(r5)
+; CHECK-NEXT:    lxv v5, 0(r6)
+; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    vmr v1, v2
+; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs2, v4, v4
+; CHECK-NEXT:    xxlor vs3, v5, v5
+; CHECK-NEXT:    vmr v0, v5
+; CHECK-NEXT:    xxmtacc acc0
+; CHECK-NEXT:    xvi8ger4pp acc0, v2, v3
+; CHECK-NEXT:    xvf16ger2pn acc0, v2, v4
+; CHECK-NEXT:    pmxvf32gernn acc0, v3, v5, 0, 0
+; CHECK-NEXT:    pmxvf64gernn acc0, vsp32, v2, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    stxv vs2, 0(r4)
 ; CHECK-NEXT:    stxv vs1, 0(r5)
 ; CHECK-NEXT:    stxv vs0, 0(r6)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: intrinsics2:
 ; CHECK-BE:       # %bb.0:
-; CHECK-BE-NEXT:    lxv vs4, 0(r3)
-; CHECK-BE-NEXT:    lxv vs5, 0(r4)
-; CHECK-BE-NEXT:    lxv vs6, 0(r5)
-; CHECK-BE-NEXT:    lxv vs7, 0(r6)
-; CHECK-BE-NEXT:    xxlor vs0, vs4, vs4
-; CHECK-BE-NEXT:    xxlor vs9, vs4, vs4
-; CHECK-BE-NEXT:    xxlor vs1, vs5, vs5
-; CHECK-BE-NEXT:    xxlor vs2, vs6, vs6
-; CHECK-BE-NEXT:    xxlor vs3, vs7, vs7
-; CHECK-BE-NEXT:    xxlor vs8, vs7, vs7
-; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    xvi8ger4pp acc0, vs4, vs5
-; CHECK-BE-NEXT:    xvf16ger2pn acc0, vs4, vs6
-; CHECK-BE-NEXT:    pmxvf32gernn acc0, vs5, vs7, 0, 0
-; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp8, vs4, 0, 0
+; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv v3, 0(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r5)
+; CHECK-BE-NEXT:    lxv v5, 0(r6)
+; CHECK-BE-NEXT:    xxlor vs0, v2, v2
+; CHECK-BE-NEXT:    vmr v1, v2
+; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs2, v4, v4
+; CHECK-BE-NEXT:    xxlor vs3, v5, v5
+; CHECK-BE-NEXT:    vmr v0, v5
+; CHECK-BE-NEXT:    xxmtacc acc0
+; CHECK-BE-NEXT:    xvi8ger4pp acc0, v2, v3
+; CHECK-BE-NEXT:    xvf16ger2pn acc0, v2, v4
+; CHECK-BE-NEXT:    pmxvf32gernn acc0, v3, v5, 0, 0
+; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp32, v2, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    stxv vs2, 0(r5)
 ; CHECK-BE-NEXT:    stxv vs3, 0(r6)
 ; CHECK-BE-NEXT:    blr
   %vc1 = load <16 x i8>, <16 x i8>* %ptr1, align 16
   %vc2 = load <16 x i8>, <16 x i8>* %ptr2, align 16

 }
 
 
 declare <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)
 
 define void @test33(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test33:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 0(r4)
-; CHECK-NEXT:    lxv vs0, 16(r4)
-; CHECK-NEXT:    xvf64ger acc1, vsp0, v2
-; CHECK-NEXT:    xxmfacc acc1
-; CHECK-NEXT:    stxv vs4, 48(r7)
-; CHECK-NEXT:    stxv vs5, 32(r7)
-; CHECK-NEXT:    stxv vs6, 16(r7)
-; CHECK-NEXT:    stxv vs7, 0(r7)
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    xvf64ger acc0, vsp36, v2
+; CHECK-NEXT:    xxmfacc acc0
+; CHECK-NEXT:    stxv vs0, 48(r7)
+; CHECK-NEXT:    stxv vs1, 32(r7)
+; CHECK-NEXT:    stxv vs2, 16(r7)
+; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test33:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r4)
-; CHECK-BE-NEXT:    lxv vs0, 0(r4)
-; CHECK-BE-NEXT:    xvf64ger acc1, vsp0, v2
-; CHECK-BE-NEXT:    xxmfacc acc1
-; CHECK-BE-NEXT:    stxv vs5, 16(r7)
-; CHECK-BE-NEXT:    stxv vs4, 0(r7)
-; CHECK-BE-NEXT:    stxv vs7, 48(r7)
-; CHECK-BE-NEXT:    stxv vs6, 32(r7)
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    xvf64ger acc0, vsp36, v2
+; CHECK-BE-NEXT:    xxmfacc acc0
+; CHECK-BE-NEXT:    stxv vs1, 16(r7)
+; CHECK-BE-NEXT:    stxv vs0, 0(r7)
+; CHECK-BE-NEXT:    stxv vs3, 48(r7)
+; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vpp to <256 x i1>*
   %1 = load <256 x i1>, <256 x i1>* %0, align 32
   %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %1, <16 x i8> %vc)
   %3 = bitcast i8* %resp to <512 x i1>*
   store <512 x i1> %2, <512 x i1>* %3, align 64
   ret void
 }
 
 
 declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>)
 
 define void @test34(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test34:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs4, 16(r4)
-; CHECK-NEXT:    xvf64gerpp acc0, vsp4, v2
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    xvf64gerpp acc0, vsp36, v2
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test34:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp4, v2
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp36, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

 define void @test35(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test35:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs4, 16(r4)
-; CHECK-NEXT:    xvf64gerpn acc0, vsp4, v2
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    xvf64gerpn acc0, vsp36, v2
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test35:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    xvf64gerpn acc0, vsp4, v2
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    xvf64gerpn acc0, vsp36, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

 define void @test36(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test36:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs4, 16(r4)
-; CHECK-NEXT:    xvf64gernp acc0, vsp4, v2
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    xvf64gernp acc0, vsp36, v2
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test36:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    xvf64gernp acc0, vsp4, v2
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    xvf64gernp acc0, vsp36, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

 define void @test37(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test37:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs4, 16(r4)
-; CHECK-NEXT:    xvf64gernn acc0, vsp4, v2
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    xvf64gernn acc0, vsp36, v2
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test37:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    xvf64gernn acc0, vsp4, v2
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    xvf64gernn acc0, vsp36, v2
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*
   %1 = load <512 x i1>, <512 x i1>* %0, align 64
   %2 = bitcast i8* %vpp to <256 x i1>*
   %3 = load <256 x i1>, <256 x i1>* %2, align 32
   %4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> %1, <256 x i1> %3, <16 x i8> %vc)
   %5 = bitcast i8* %resp to <512 x i1>*
   store <512 x i1> %4, <512 x i1>* %5, align 64
   ret void
 }
 
 
 declare <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>)
 
 define void @test38(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test38:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 0(r4)
-; CHECK-NEXT:    lxv vs0, 16(r4)
-; CHECK-NEXT:    pmxvf64ger acc1, vsp0, v2, 0, 0
-; CHECK-NEXT:    xxmfacc acc1
-; CHECK-NEXT:    stxv vs4, 48(r7)
-; CHECK-NEXT:    stxv vs5, 32(r7)
-; CHECK-NEXT:    stxv vs6, 16(r7)
-; CHECK-NEXT:    stxv vs7, 0(r7)
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    pmxvf64ger acc0, vsp36, v2, 0, 0
+; CHECK-NEXT:    xxmfacc acc0
+; CHECK-NEXT:    stxv vs0, 48(r7)
+; CHECK-NEXT:    stxv vs1, 32(r7)
+; CHECK-NEXT:    stxv vs2, 16(r7)
+; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test38:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r4)
-; CHECK-BE-NEXT:    lxv vs0, 0(r4)
-; CHECK-BE-NEXT:    pmxvf64ger acc1, vsp0, v2, 0, 0
-; CHECK-BE-NEXT:    xxmfacc acc1
-; CHECK-BE-NEXT:    stxv vs5, 16(r7)
-; CHECK-BE-NEXT:    stxv vs4, 0(r7)
-; CHECK-BE-NEXT:    stxv vs7, 48(r7)
-; CHECK-BE-NEXT:    stxv vs6, 32(r7)
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    pmxvf64ger acc0, vsp36, v2, 0, 0
+; CHECK-BE-NEXT:    xxmfacc acc0
+; CHECK-BE-NEXT:    stxv vs1, 16(r7)
+; CHECK-BE-NEXT:    stxv vs0, 0(r7)
+; CHECK-BE-NEXT:    stxv vs3, 48(r7)
+; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vpp to <256 x i1>*
   %1 = load <256 x i1>, <256 x i1>* %0, align 32
   %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)
   %3 = bitcast i8* %resp to <512 x i1>*
   store <512 x i1> %2, <512 x i1>* %3, align 64
   ret void
 }
 
 
 declare <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1>, <16 x i8>, i32, i32)
 
 define void @test39(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test39:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs4, 16(r4)
-; CHECK-NEXT:    pmxvf64gerpp acc0, vsp4, v2, 0, 0
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    pmxvf64gerpp acc0, vsp36, v2, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test39:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    pmxvf64gerpp acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    pmxvf64gerpp acc0, vsp36, v2, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

 define void @test40(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test40:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs4, 16(r4)
-; CHECK-NEXT:    pmxvf64gerpn acc0, vsp4, v2, 0, 0
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    pmxvf64gerpn acc0, vsp36, v2, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test40:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    pmxvf64gerpn acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    pmxvf64gerpn acc0, vsp36, v2, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

 define void @test41(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test41:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs4, 16(r4)
-; CHECK-NEXT:    pmxvf64gernp acc0, vsp4, v2, 0, 0
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    pmxvf64gernp acc0, vsp36, v2, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test41:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    pmxvf64gernp acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    pmxvf64gernp acc0, vsp36, v2, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

 define void @test42(i8* %vqp, i8* %vpp, <16 x i8> %vc, i8* %resp) {
 ; CHECK-LABEL: test42:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxv vs1, 32(r3)
 ; CHECK-NEXT:    lxv vs0, 48(r3)
 ; CHECK-NEXT:    lxv vs3, 0(r3)
 ; CHECK-NEXT:    lxv vs2, 16(r3)
 ; CHECK-NEXT:    xxmtacc acc0
-; CHECK-NEXT:    lxv vs5, 0(r4)
-; CHECK-NEXT:    lxv vs4, 16(r4)
-; CHECK-NEXT:    pmxvf64gernn acc0, vsp4, v2, 0, 0
+; CHECK-NEXT:    lxv v5, 0(r4)
+; CHECK-NEXT:    lxv v4, 16(r4)
+; CHECK-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 0
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r7)
 ; CHECK-NEXT:    stxv vs1, 32(r7)
 ; CHECK-NEXT:    stxv vs2, 16(r7)
 ; CHECK-NEXT:    stxv vs3, 0(r7)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test42:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xxmtacc acc0
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp4, v2, 0, 0
+; CHECK-BE-NEXT:    lxv v5, 16(r4)
+; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 0
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r7)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r7)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r7)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r7)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i8* %vqp to <512 x i1>*

llvm/test/CodeGen/PowerPC/mma-phi-accs.ll

 define void @testPHI1(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) {
 ; CHECK-LABEL: testPHI1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r5, 3
 ; CHECK-NEXT:    xxsetaccz acc0
 ; CHECK-NEXT:    blt cr0, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    clrldi r5, r5, 32
-; CHECK-NEXT:    lxv vs4, 0(r4)
-; CHECK-NEXT:    lxv vs5, 16(r4)
+; CHECK-NEXT:    lxv v2, 0(r4)
+; CHECK-NEXT:    lxv v3, 16(r4)
 ; CHECK-NEXT:    addi r4, r4, 32
 ; CHECK-NEXT:    addi r5, r5, -2
 ; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_2: # %for.body
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lxv vs6, 0(r4)
+; CHECK-NEXT:    lxv vs4, 0(r4)
 ; CHECK-NEXT:    addi r4, r4, 16
-; CHECK-NEXT:    xvf64gerpp acc0, vsp4, vs6
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs4
 ; CHECK-NEXT:    bdnz .LBB0_2
 ; CHECK-NEXT:  .LBB0_3: # %for.cond.cleanup
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testPHI1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cmpwi r5, 3
 ; CHECK-BE-NEXT:    xxsetaccz acc0
 ; CHECK-BE-NEXT:    blt cr0, .LBB0_3
 ; CHECK-BE-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-BE-NEXT:    clrldi r5, r5, 32
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
+; CHECK-BE-NEXT:    lxv v2, 0(r4)
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
 ; CHECK-BE-NEXT:    addi r4, r4, 32
 ; CHECK-BE-NEXT:    addi r5, r5, -2
 ; CHECK-BE-NEXT:    mtctr r5
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_2: # %for.body
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    lxv vs6, 0(r4)
+; CHECK-BE-NEXT:    lxv vs4, 0(r4)
 ; CHECK-BE-NEXT:    addi r4, r4, 16
-; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp4, vs6
+; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp34, vs4
 ; CHECK-BE-NEXT:    bdnz .LBB0_2
 ; CHECK-BE-NEXT:  .LBB0_3: # %for.cond.cleanup
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    blr
for.body:
   %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
   br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
 }
 
 declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>)
 define dso_local void @testPHI2(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) {
 ; CHECK-LABEL: testPHI2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs4, 0(r4)
-; CHECK-NEXT:    lxv vs5, 16(r4)
-; CHECK-NEXT:    lxv vs6, 32(r4)
+; CHECK-NEXT:    lxv v2, 0(r4)
+; CHECK-NEXT:    lxv v3, 16(r4)
+; CHECK-NEXT:    lxv vs4, 32(r4)
 ; CHECK-NEXT:    cmpwi r5, 4
-; CHECK-NEXT:    xvf64ger acc0, vsp4, vs6
+; CHECK-NEXT:    xvf64ger acc0, vsp34, vs4
 ; CHECK-NEXT:    blt cr0, .LBB1_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    clrldi r5, r5, 32
 ; CHECK-NEXT:    addi r4, r4, 48
 ; CHECK-NEXT:    addi r5, r5, -3
 ; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB1_2: # %for.body
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lxv vs6, 0(r4)
+; CHECK-NEXT:    lxv vs4, 0(r4)
 ; CHECK-NEXT:    addi r4, r4, 16
-; CHECK-NEXT:    xvf64gerpp acc0, vsp4, vs6
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs4
 ; CHECK-NEXT:    bdnz .LBB1_2
 ; CHECK-NEXT:  .LBB1_3: # %for.cond.cleanup
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs3, 0(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testPHI2:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs4, 0(r4)
-; CHECK-BE-NEXT:    lxv vs5, 16(r4)
-; CHECK-BE-NEXT:    lxv vs6, 32(r4)
+; CHECK-BE-NEXT:    lxv v2, 0(r4)
+; CHECK-BE-NEXT:    lxv v3, 16(r4)
+; CHECK-BE-NEXT:    lxv vs4, 32(r4)
 ; CHECK-BE-NEXT:    cmpwi r5, 4
-; CHECK-BE-NEXT:    xvf64ger acc0, vsp4, vs6
+; CHECK-BE-NEXT:    xvf64ger acc0, vsp34, vs4
 ; CHECK-BE-NEXT:    blt cr0, .LBB1_3
 ; CHECK-BE-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-BE-NEXT:    clrldi r5, r5, 32
 ; CHECK-BE-NEXT:    addi r4, r4, 48
 ; CHECK-BE-NEXT:    addi r5, r5, -3
 ; CHECK-BE-NEXT:    mtctr r5
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB1_2: # %for.body
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    lxv vs6, 0(r4)
+; CHECK-BE-NEXT:    lxv vs4, 0(r4)
 ; CHECK-BE-NEXT:    addi r4, r4, 16
-; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp4, vs6
+; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp34, vs4
 ; CHECK-BE-NEXT:    bdnz .LBB1_2
 ; CHECK-BE-NEXT:  .LBB1_3: # %for.cond.cleanup
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    blr

 ; to xvf64gerpp. The compiler should replace this PHI node by a primed
 ; accumulator PHI node.
 define void @testImplicitDef(<16 x i8>* %ptr) {
 ; CHECK-LABEL: testImplicitDef:
 ; CHECK:       # %bb.0: # %label1
 ; CHECK-NEXT:    # implicit-def: $acc0
 ; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB2_2
 ; CHECK-NEXT:  # %bb.1: # %label2
-; CHECK-NEXT:    xvf64gerpp acc0, vsp0, vs0
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
 ; CHECK-NEXT:  .LBB2_2: # %label3
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxv vs0, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testImplicitDef:
 ; CHECK-BE:       # %bb.0: # %label1
 ; CHECK-BE-NEXT:    # implicit-def: $acc0
 ; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB2_2
 ; CHECK-BE-NEXT:  # %bb.1: # %label2
-; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp0, vs0
+; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp34, vs0
 ; CHECK-BE-NEXT:  .LBB2_2: # %label3
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxv vs3, 0(r3)
 ; CHECK-BE-NEXT:    blr
 label1:
   br i1 undef, label %label3, label %label2
 
 label2:

llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr10 < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-p:64:64-n32:64-v256:256:256-v512:512:512"
 target triple = "powerpc64le-unknown-linux-gnu"
 
 %_elem_type_of_a = type <{ double }>
 %_elem_type_of_x = type <{ double }>
 
 define void @foo(i32* %.m, i32* %.n, [0 x %_elem_type_of_a]* %.a, [0 x %_elem_type_of_x]* %.x, i32* %.l, <2 x double>* %.vy01, <2 x double>* %.vy02, <2 x double>* %.vy03, <2 x double>* %.vy04, <2 x double>* %.vy05, <2 x double>* %.vy06, <2 x double>* %.vy07, <2 x double>* %.vy08, <2 x double>* %.vy09, <2 x double>* %.vy0a, <2 x double>* %.vy0b, <2 x double>* %.vy0c, <2 x double>* %.vy21, <2 x double>* %.vy22, <2 x double>* %.vy23, <2 x double>* %.vy24, <2 x double>* %.vy25, <2 x double>* %.vy26, <2 x double>* %.vy27, <2 x double>* %.vy28, <2 x double>* %.vy29, <2 x double>* %.vy2a, <2 x double>* %.vy2b, <2 x double>* %.vy2c) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stdu 1, -480(1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 480
-; CHECK-NEXT:    .cfi_offset r14, -256
-; CHECK-NEXT:    .cfi_offset r15, -248
-; CHECK-NEXT:    .cfi_offset r16, -240
-; CHECK-NEXT:    .cfi_offset r17, -232
-; CHECK-NEXT:    .cfi_offset r18, -224
-; CHECK-NEXT:    .cfi_offset r19, -216
-; CHECK-NEXT:    .cfi_offset r20, -208
-; CHECK-NEXT:    .cfi_offset r21, -200
-; CHECK-NEXT:    .cfi_offset r22, -192
-; CHECK-NEXT:    .cfi_offset r23, -184
-; CHECK-NEXT:    .cfi_offset r24, -176
-; CHECK-NEXT:    .cfi_offset r25, -168
-; CHECK-NEXT:    .cfi_offset r26, -160
-; CHECK-NEXT:    .cfi_offset r27, -152
-; CHECK-NEXT:    .cfi_offset r28, -144
-; CHECK-NEXT:    .cfi_offset r29, -136
-; CHECK-NEXT:    .cfi_offset r30, -128
-; CHECK-NEXT:    .cfi_offset r31, -120
-; CHECK-NEXT:    .cfi_offset f18, -112
-; CHECK-NEXT:    .cfi_offset f19, -104
-; CHECK-NEXT:    .cfi_offset f20, -96
-; CHECK-NEXT:    .cfi_offset f21, -88
-; CHECK-NEXT:    .cfi_offset f22, -80
-; CHECK-NEXT:    .cfi_offset f23, -72
-; CHECK-NEXT:    .cfi_offset f24, -64
-; CHECK-NEXT:    .cfi_offset f25, -56
-; CHECK-NEXT:    .cfi_offset f26, -48
-; CHECK-NEXT:    .cfi_offset f27, -40
-; CHECK-NEXT:    .cfi_offset f28, -32
-; CHECK-NEXT:    .cfi_offset f29, -24
+; CHECK-NEXT:    stdu 1, -576(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 576
+; CHECK-NEXT:    .cfi_offset r14, -160
+; CHECK-NEXT:    .cfi_offset r15, -152
+; CHECK-NEXT:    .cfi_offset r16, -144
+; CHECK-NEXT:    .cfi_offset r17, -136
+; CHECK-NEXT:    .cfi_offset r18, -128
+; CHECK-NEXT:    .cfi_offset r19, -120
+; CHECK-NEXT:    .cfi_offset r20, -112
+; CHECK-NEXT:    .cfi_offset r21, -104
+; CHECK-NEXT:    .cfi_offset r22, -96
+; CHECK-NEXT:    .cfi_offset r23, -88
+; CHECK-NEXT:    .cfi_offset r24, -80
+; CHECK-NEXT:    .cfi_offset r25, -72
+; CHECK-NEXT:    .cfi_offset r26, -64
+; CHECK-NEXT:    .cfi_offset r27, -56
+; CHECK-NEXT:    .cfi_offset r28, -48
+; CHECK-NEXT:    .cfi_offset r29, -40
+; CHECK-NEXT:    .cfi_offset r30, -32
+; CHECK-NEXT:    .cfi_offset r31, -24
 ; CHECK-NEXT:    .cfi_offset f30, -16
 ; CHECK-NEXT:    .cfi_offset f31, -8
+; CHECK-NEXT:    .cfi_offset v20, -352
+; CHECK-NEXT:    .cfi_offset v21, -336
+; CHECK-NEXT:    .cfi_offset v22, -320
+; CHECK-NEXT:    .cfi_offset v23, -304
+; CHECK-NEXT:    .cfi_offset v24, -288
+; CHECK-NEXT:    .cfi_offset v25, -272
+; CHECK-NEXT:    .cfi_offset v26, -256
+; CHECK-NEXT:    .cfi_offset v27, -240
+; CHECK-NEXT:    .cfi_offset v28, -224
+; CHECK-NEXT:    .cfi_offset v29, -208
+; CHECK-NEXT:    .cfi_offset v30, -192
+; CHECK-NEXT:    .cfi_offset v31, -176
 ; CHECK-NEXT:    lwz 4, 0(4)
-; CHECK-NEXT:    std 14, 224(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 15, 232(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 14, 416(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 15, 424(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stxv 52, 224(1) # 16-byte Folded Spill
+; CHECK-NEXT:    stxv 53, 240(1) # 16-byte Folded Spill
+; CHECK-NEXT:    stxv 54, 256(1) # 16-byte Folded Spill
+; CHECK-NEXT:    std 16, 432(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 17, 440(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stxv 55, 272(1) # 16-byte Folded Spill
+; CHECK-NEXT:    std 18, 448(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 19, 456(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stxv 56, 288(1) # 16-byte Folded Spill
+; CHECK-NEXT:    stxv 57, 304(1) # 16-byte Folded Spill
+; CHECK-NEXT:    std 20, 464(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 21, 472(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stxv 58, 320(1) # 16-byte Folded Spill
+; CHECK-NEXT:    std 22, 480(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 23, 488(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stxv 59, 336(1) # 16-byte Folded Spill
+; CHECK-NEXT:    stxv 60, 352(1) # 16-byte Folded Spill
+; CHECK-NEXT:    std 24, 496(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 25, 504(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stxv 61, 368(1) # 16-byte Folded Spill
+; CHECK-NEXT:    std 26, 512(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 27, 520(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stxv 62, 384(1) # 16-byte Folded Spill
+; CHECK-NEXT:    stxv 63, 400(1) # 16-byte Folded Spill
+; CHECK-NEXT:    std 28, 528(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 29, 536(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    cmpwi 4, 1
-; CHECK-NEXT:    std 16, 240(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 17, 248(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 18, 256(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 19, 264(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 20, 272(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 21, 280(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 22, 288(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 23, 296(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 24, 304(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 25, 312(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 26, 320(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 27, 328(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 28, 336(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 29, 344(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 30, 352(1) # 8-byte Folded Spill
-; CHECK-NEXT:    std 31, 360(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 18, 368(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 19, 376(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 20, 384(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 21, 392(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 22, 400(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 23, 408(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 24, 416(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 25, 424(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 26, 432(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 27, 440(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 28, 448(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 29, 456(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 30, 464(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 31, 472(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 30, 544(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 31, 552(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stfd 30, 560(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stfd 31, 568(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    blt 0, .LBB0_7
 ; CHECK-NEXT:  # %bb.1: # %_loop_1_do_.lr.ph
 ; CHECK-NEXT:    mr 23, 5
 ; CHECK-NEXT:    lwz 5, 0(3)
 ; CHECK-NEXT:    cmpwi 5, 1
 ; CHECK-NEXT:    blt 0, .LBB0_7
 ; CHECK-NEXT:  # %bb.2: # %_loop_1_do_.preheader
 ; CHECK-NEXT:    addi 5, 5, 1
 ; CHECK-NEXT:    li 20, 9
-; CHECK-NEXT:    ld 28, 728(1)
-; CHECK-NEXT:    ld 19, 616(1)
+; CHECK-NEXT:    ld 28, 824(1)
+; CHECK-NEXT:    ld 19, 712(1)
 ; CHECK-NEXT:    lwa 3, 0(7)
-; CHECK-NEXT:    ld 7, 688(1)
-; CHECK-NEXT:    ld 12, 680(1)
-; CHECK-NEXT:    ld 11, 672(1)
-; CHECK-NEXT:    ld 2, 664(1)
-; CHECK-NEXT:    ld 29, 736(1)
+; CHECK-NEXT:    ld 7, 784(1)
+; CHECK-NEXT:    ld 12, 776(1)
+; CHECK-NEXT:    ld 11, 768(1)
+; CHECK-NEXT:    ld 2, 760(1)
+; CHECK-NEXT:    ld 29, 832(1)
 ; CHECK-NEXT:    cmpldi 5, 9
-; CHECK-NEXT:    ld 27, 720(1)
-; CHECK-NEXT:    ld 26, 712(1)
-; CHECK-NEXT:    ld 25, 704(1)
-; CHECK-NEXT:    ld 24, 696(1)
+; CHECK-NEXT:    ld 27, 816(1)
+; CHECK-NEXT:    ld 26, 808(1)
+; CHECK-NEXT:    ld 25, 800(1)
+; CHECK-NEXT:    ld 24, 792(1)
 ; CHECK-NEXT:    iselgt 5, 5, 20
-; CHECK-NEXT:    ld 30, 656(1)
-; CHECK-NEXT:    ld 22, 648(1)
-; CHECK-NEXT:    ld 21, 640(1)
-; CHECK-NEXT:    ld 20, 632(1)
-; CHECK-NEXT:    ld 18, 608(1)
-; CHECK-NEXT:    ld 17, 600(1)
-; CHECK-NEXT:    ld 16, 592(1)
-; CHECK-NEXT:    ld 14, 584(1)
+; CHECK-NEXT:    ld 30, 752(1)
+; CHECK-NEXT:    ld 22, 744(1)
+; CHECK-NEXT:    ld 21, 736(1)
+; CHECK-NEXT:    ld 20, 728(1)
+; CHECK-NEXT:    ld 18, 704(1)
+; CHECK-NEXT:    ld 17, 696(1)
+; CHECK-NEXT:    ld 16, 688(1)
+; CHECK-NEXT:    ld 14, 680(1)
 ; CHECK-NEXT:    sldi 0, 3, 2
 ; CHECK-NEXT:    std 5, 216(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 28, 208(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    mr 5, 4
-; CHECK-NEXT:    ld 4, 624(1)
+; CHECK-NEXT:    ld 4, 720(1)
 ; CHECK-NEXT:    std 19, 96(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 4, 104(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    lxv 11, 0(4)
 ; CHECK-NEXT:    mr 4, 5
 ; CHECK-NEXT:    ld 5, 216(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 15, 576(1)
+; CHECK-NEXT:    ld 15, 672(1)
 ; CHECK-NEXT:    sldi 31, 3, 1
 ; CHECK-NEXT:    std 8, 32(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 9, 40(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    lxv 41, 0(8)
 ; CHECK-NEXT:    mr 8, 6
 ; CHECK-NEXT:    sldi 6, 3, 3
 ; CHECK-NEXT:    std 2, 144(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std 11, 152(1) # 8-byte Folded Spill

 ; CHECK-NEXT:  .LBB0_4: # %_loop_2_do_
 ; CHECK-NEXT:    # Parent Loop BB0_3 Depth=1
 ; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    lxvp 42, 0(6)
 ; CHECK-NEXT:    lxvp 44, 0(16)
 ; CHECK-NEXT:    lxvp 46, 0(17)
 ; CHECK-NEXT:    lxvp 48, 0(18)
 ; CHECK-NEXT:    lxvp 50, 0(19)
-; CHECK-NEXT:    lxvp 30, 0(20)
-; CHECK-NEXT:    lxvp 28, 0(21)
-; CHECK-NEXT:    lxvp 26, 32(6)
-; CHECK-NEXT:    lxvp 24, 32(16)
-; CHECK-NEXT:    lxvp 22, 32(17)
-; CHECK-NEXT:    lxvp 20, 32(18)
-; CHECK-NEXT:    lxvp 18, 32(19)
+; CHECK-NEXT:    lxvp 62, 0(20)
+; CHECK-NEXT:    lxvp 60, 0(21)
+; CHECK-NEXT:    lxvp 58, 32(6)
+; CHECK-NEXT:    lxvp 56, 32(16)
+; CHECK-NEXT:    lxvp 54, 32(17)
+; CHECK-NEXT:    lxvp 52, 32(18)
+; CHECK-NEXT:    lxvp 30, 32(19)
 ; CHECK-NEXT:    addi 6, 6, 64
 ; CHECK-NEXT:    addi 16, 16, 64
 ; CHECK-NEXT:    addi 17, 17, 64
 ; CHECK-NEXT:    addi 18, 18, 64
 ; CHECK-NEXT:    addi 19, 19, 64
 ; CHECK-NEXT:    xvmaddadp 41, 45, 43
 ; CHECK-NEXT:    xvmaddadp 40, 47, 43
 ; CHECK-NEXT:    xvmaddadp 39, 49, 43
 ; CHECK-NEXT:    xvmaddadp 38, 51, 43
-; CHECK-NEXT:    xvmaddadp 33, 31, 43
-; CHECK-NEXT:    xvmaddadp 32, 29, 43
+; CHECK-NEXT:    xvmaddadp 33, 63, 43
+; CHECK-NEXT:    xvmaddadp 32, 61, 43
 ; CHECK-NEXT:    xvmaddadp 37, 44, 42
 ; CHECK-NEXT:    xvmaddadp 35, 46, 42
 ; CHECK-NEXT:    xvmaddadp 13, 48, 42
 ; CHECK-NEXT:    xvmaddadp 11, 50, 42
-; CHECK-NEXT:    xvmaddadp 10, 30, 42
-; CHECK-NEXT:    xvmaddadp 8, 28, 42
+; CHECK-NEXT:    xvmaddadp 10, 62, 42
+; CHECK-NEXT:    xvmaddadp 8, 60, 42
 ; CHECK-NEXT:    lxvp 42, 32(20)
 ; CHECK-NEXT:    lxvp 44, 32(21)
 ; CHECK-NEXT:    addi 20, 20, 64
 ; CHECK-NEXT:    addi 21, 21, 64
-; CHECK-NEXT:    xvmaddadp 6, 25, 27
-; CHECK-NEXT:    xvmaddadp 4, 23, 27
-; CHECK-NEXT:    xvmaddadp 3, 21, 27
-; CHECK-NEXT:    xvmaddadp 2, 19, 27
-; CHECK-NEXT:    xvmaddadp 36, 24, 26
-; CHECK-NEXT:    xvmaddadp 34, 22, 26
-; CHECK-NEXT:    xvmaddadp 12, 20, 26
-; CHECK-NEXT:    xvmaddadp 9, 18, 26
-; CHECK-NEXT:    xvmaddadp 1, 43, 27
-; CHECK-NEXT:    xvmaddadp 0, 45, 27
-; CHECK-NEXT:    xvmaddadp 7, 42, 26
-; CHECK-NEXT:    xvmaddadp 5, 44, 26
+; CHECK-NEXT:    xvmaddadp 6, 57, 59
+; CHECK-NEXT:    xvmaddadp 4, 55, 59
+; CHECK-NEXT:    xvmaddadp 3, 53, 59
+; CHECK-NEXT:    xvmaddadp 2, 31, 59
+; CHECK-NEXT:    xvmaddadp 36, 56, 58
+; CHECK-NEXT:    xvmaddadp 34, 54, 58
+; CHECK-NEXT:    xvmaddadp 12, 52, 58
+; CHECK-NEXT:    xvmaddadp 9, 30, 58
+; CHECK-NEXT:    xvmaddadp 1, 43, 59
+; CHECK-NEXT:    xvmaddadp 0, 45, 59
+; CHECK-NEXT:    xvmaddadp 7, 42, 58
+; CHECK-NEXT:    xvmaddadp 5, 44, 58
 ; CHECK-NEXT:    bdnz .LBB0_4
 ; CHECK-NEXT:  # %bb.5: # %_loop_2_endl_
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi 25, 25, 6
 ; CHECK-NEXT:    add 5, 5, 26
 ; CHECK-NEXT:    add 11, 11, 26
 ; CHECK-NEXT:    add 30, 30, 26
 ; CHECK-NEXT:    add 12, 12, 26

 ; CHECK-NEXT:    stxv 12, 0(3)
 ; CHECK-NEXT:    ld 3, 200(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    stxv 9, 0(3)
 ; CHECK-NEXT:    ld 3, 208(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    stxv 7, 0(3)
 ; CHECK-NEXT:    ld 3, 216(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    stxv 5, 0(3)
 ; CHECK-NEXT:  .LBB0_7: # %_return_bb
-; CHECK-NEXT:    lfd 31, 472(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 30, 464(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 31, 360(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 30, 352(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 29, 344(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 28, 336(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 27, 328(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 26, 320(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 25, 312(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 29, 456(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 24, 304(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 23, 296(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 22, 288(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 28, 448(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 21, 280(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 20, 272(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 19, 264(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 27, 440(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 18, 256(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 17, 248(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 16, 240(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 26, 432(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 15, 232(1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld 14, 224(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 25, 424(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 24, 416(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 23, 408(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 22, 400(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 21, 392(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 20, 384(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 19, 376(1) # 8-byte Folded Reload
-; CHECK-NEXT:    lfd 18, 368(1) # 8-byte Folded Reload
-; CHECK-NEXT:    addi 1, 1, 480
+; CHECK-NEXT:    lxv 63, 400(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 62, 384(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 61, 368(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 60, 352(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 59, 336(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 58, 320(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 57, 304(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 56, 288(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 55, 272(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 54, 256(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 53, 240(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lxv 52, 224(1) # 16-byte Folded Reload
+; CHECK-NEXT:    lfd 31, 568(1) # 8-byte Folded Reload
+; CHECK-NEXT:    lfd 30, 560(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 31, 552(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 30, 544(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 29, 536(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 28, 528(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 27, 520(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 26, 512(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 25, 504(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 24, 496(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 23, 488(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 22, 480(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 21, 472(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 20, 464(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 19, 456(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 18, 448(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 17, 440(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 16, 432(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 15, 424(1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld 14, 416(1) # 8-byte Folded Reload
+; CHECK-NEXT:    addi 1, 1, 576
 ; CHECK-NEXT:    blr
 entry:
   %_val_l_ = load i32, i32* %.l, align 4
   %_conv = sext i32 %_val_l_ to i64
   %_mult_tmp = shl nsw i64 %_conv, 3
   %_sub_tmp4 = sub nuw nsw i64 -8, %_mult_tmp
   %_val_n_ = load i32, i32* %.n, align 4
   %_leq_tmp.not116 = icmp slt i32 %_val_n_, 1

llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll

 ; This test also checks that the paired vector intrinsics are available even
 ; when MMA is disabled.
 
 ; assemble_pair
 declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
 define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_pair:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xxlor vs1, v2, v2
-; CHECK-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-NEXT:    stxv vs1, 16(r3)
-; CHECK-NEXT:    stxv vs1, 0(r3)
+; CHECK-NEXT:    vmr v3, v2
+; CHECK-NEXT:    stxv v2, 16(r3)
+; CHECK-NEXT:    stxv v3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: ass_pair:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    xxlor vs1, v2, v2
-; CHECK-NOMMA-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-NOMMA-NEXT:    stxv vs1, 16(r3)
-; CHECK-NOMMA-NEXT:    stxv vs1, 0(r3)
+; CHECK-NOMMA-NEXT:    vmr v3, v2
+; CHECK-NOMMA-NEXT:    stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:    stxv v3, 0(r3)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: ass_pair:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxlor vs1, v2, v2
-; CHECK-BE-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-BE-NEXT:    stxv vs1, 16(r3)
-; CHECK-BE-NEXT:    stxv vs0, 0(r3)
+; CHECK-BE-NEXT:    vmr v3, v2
+; CHECK-BE-NEXT:    stxv v2, 16(r3)
+; CHECK-BE-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: ass_pair:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    xxlor vs1, v2, v2
-; CHECK-BE-NOMMA-NEXT:    xxlor vs0, vs1, vs1
-; CHECK-BE-NOMMA-NEXT:    stxv vs1, 16(r3)
-; CHECK-BE-NOMMA-NEXT:    stxv vs0, 0(r3)
+; CHECK-BE-NOMMA-NEXT:    vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
   store <256 x i1> %0, <256 x i1>* %ptr, align 32
   ret void
 }
 
 ; disassemble_pair
 declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
 define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
 ; CHECK-LABEL: disass_pair:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxv vs1, 0(r3)
-; CHECK-NEXT:    lxv vs0, 16(r3)
-; CHECK-NEXT:    stxv vs1, 0(r4)
-; CHECK-NEXT:    stxv vs0, 0(r5)
+; CHECK-NEXT:    lxv v3, 0(r3)
+; CHECK-NEXT:    lxv v2, 16(r3)
+; CHECK-NEXT:    stxv v3, 0(r4)
+; CHECK-NEXT:    stxv v2, 0(r5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: disass_pair:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxv vs1, 0(r3)
-; CHECK-NOMMA-NEXT:    lxv vs0, 16(r3)
-; CHECK-NOMMA-NEXT:    stxv vs1, 0(r4)
-; CHECK-NOMMA-NEXT:    stxv vs0, 0(r5)
+; CHECK-NOMMA-NEXT:    lxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:    lxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:    stxv v3, 0(r4)
+; CHECK-NOMMA-NEXT:    stxv v2, 0(r5)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: disass_pair:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NEXT:    stxv vs0, 0(r4)
-; CHECK-BE-NEXT:    stxv vs1, 0(r5)
+; CHECK-BE-NEXT:    lxv v3, 16(r3)
+; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    stxv v2, 0(r4)
+; CHECK-BE-NEXT:    stxv v3, 0(r5)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: disass_pair:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxv vs1, 16(r3)
-; CHECK-BE-NOMMA-NEXT:    lxv vs0, 0(r3)
-; CHECK-BE-NOMMA-NEXT:    stxv vs0, 0(r4)
-; CHECK-BE-NOMMA-NEXT:    stxv vs1, 0(r5)
+; CHECK-BE-NOMMA-NEXT:    lxv v3, 16(r3)
+; CHECK-BE-NOMMA-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r4)
+; CHECK-BE-NOMMA-NEXT:    stxv v3, 0(r5)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
   %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %0)
   %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
   %3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
   store <16 x i8> %2, <16 x i8>* %ptr2, align 16
   store <16 x i8> %3, <16 x i8>* %ptr3, align 16
   ret void
 }
 
 define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
 ; CHECK-LABEL: test_ldst_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvp vsp0, 0(r3)
-; CHECK-NEXT:    stxvp vsp0, 0(r4)
+; CHECK-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-NEXT:    stxvp vsp34, 0(r4)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_1:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvp vsp0, 0(r3)
-; CHECK-NOMMA-NEXT:    stxvp vsp0, 0(r4)
+; CHECK-NOMMA-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-NOMMA-NEXT:    stxvp vsp34, 0(r4)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_1:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvp vsp0, 0(r3)
-; CHECK-BE-NEXT:    stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_1:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvp vsp0, 0(r3)
-; CHECK-BE-NOMMA-NEXT:    stxvp vsp0, 0(r4)
+; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 0(r4)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
   %2 = bitcast <256 x i1>* %vp2 to i8*
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
   ret void
 }
 
 declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
 declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*)
 
 define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvpx vsp0, r3, r4
-; CHECK-NEXT:    stxvpx vsp0, r5, r4
+; CHECK-NEXT:    lxvpx vsp34, r3, r4
+; CHECK-NEXT:    stxvpx vsp34, r5, r4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_2:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvpx vsp0, r3, r4
-; CHECK-NOMMA-NEXT:    stxvpx vsp0, r5, r4
+; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r4
+; CHECK-NOMMA-NEXT:    stxvpx vsp34, r5, r4
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_2:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvpx vsp0, r3, r4
-; CHECK-BE-NEXT:    stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT:    lxvpx vsp34, r3, r4
+; CHECK-BE-NEXT:    stxvpx vsp34, r5, r4
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_2:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvpx vsp0, r3, r4
-; CHECK-BE-NOMMA-NEXT:    stxvpx vsp0, r5, r4
+; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r4
+; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r5, r4
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 %offset
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 %offset
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r5, 18
-; CHECK-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_3:
 ; CHECK-NOMMA:       # %bb.0: # %entry
 ; CHECK-NOMMA-NEXT:    li r5, 18
-; CHECK-NOMMA-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-NOMMA-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-NOMMA-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li r5, 18
-; CHECK-BE-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-BE-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-BE-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_3:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
 ; CHECK-BE-NOMMA-NEXT:    li r5, 18
-; CHECK-BE-NOMMA-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-BE-NOMMA-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 18
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 18
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_4:
 ; CHECK-NOMMA:       # %bb.0: # %entry
 ; CHECK-NOMMA-NEXT:    li r5, 1
-; CHECK-NOMMA-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-NOMMA-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-NOMMA-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li r5, 1
-; CHECK-BE-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-BE-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-BE-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_4:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
 ; CHECK-BE-NOMMA-NEXT:    li r5, 1
-; CHECK-BE-NOMMA-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-BE-NOMMA-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 1
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 1
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_5:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li r5, 42
-; CHECK-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_5:
 ; CHECK-NOMMA:       # %bb.0: # %entry
 ; CHECK-NOMMA-NEXT:    li r5, 42
-; CHECK-NOMMA-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-NOMMA-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-NOMMA-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_5:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li r5, 42
-; CHECK-BE-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-BE-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-BE-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_5:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
 ; CHECK-BE-NOMMA-NEXT:    li r5, 42
-; CHECK-BE-NOMMA-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-BE-NOMMA-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 42
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 42
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_6(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; CHECK-LABEL: test_ldst_6:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lxvp vsp0, 4096(r3)
-; CHECK-NEXT:    stxvp vsp0, 4096(r4)
+; CHECK-NEXT:    lxvp vsp34, 4096(r3)
+; CHECK-NEXT:    stxvp vsp34, 4096(r4)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_6:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    lxvp vsp0, 4096(r3)
-; CHECK-NOMMA-NEXT:    stxvp vsp0, 4096(r4)
+; CHECK-NOMMA-NEXT:    lxvp vsp34, 4096(r3)
+; CHECK-NOMMA-NEXT:    stxvp vsp34, 4096(r4)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_6:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxvp vsp0, 4096(r3)
-; CHECK-BE-NEXT:    stxvp vsp0, 4096(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, 4096(r3)
+; CHECK-BE-NEXT:    stxvp vsp34, 4096(r4)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_6:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    lxvp vsp0, 4096(r3)
-; CHECK-BE-NOMMA-NEXT:    stxvp vsp0, 4096(r4)
+; CHECK-BE-NOMMA-NEXT:    lxvp vsp34, 4096(r3)
+; CHECK-BE-NOMMA-NEXT:    stxvp vsp34, 4096(r4)
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = getelementptr <256 x i1>, <256 x i1>* %vpp, i64 128
   %1 = bitcast <256 x i1>* %0 to i8*
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = getelementptr <256 x i1>, <256 x i1>* %vp2, i64 128
   %4 = bitcast <256 x i1>* %3 to i8*
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }
 
 define void @test_ldst_7(<256 x i1>* %vpp, <256 x i1>* %vp2)  {
 ; FIXME: A prefixed load (plxvp) is expected here as the offset in this
 ; test case is a constant that fits within 34-bits.
 ; CHECK-LABEL: test_ldst_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pli r5, 32799
-; CHECK-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: test_ldst_7:
 ; CHECK-NOMMA:       # %bb.0: # %entry
 ; CHECK-NOMMA-NEXT:    pli r5, 32799
-; CHECK-NOMMA-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-NOMMA-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-NOMMA-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-NOMMA-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_ldst_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    pli r5, 32799
-; CHECK-BE-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-BE-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-BE-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: test_ldst_7:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
 ; CHECK-BE-NOMMA-NEXT:    pli r5, 32799
-; CHECK-BE-NOMMA-NEXT:    lxvpx vsp0, r3, r5
-; CHECK-BE-NOMMA-NEXT:    stxvpx vsp0, r4, r5
+; CHECK-BE-NOMMA-NEXT:    lxvpx vsp34, r3, r5
+; CHECK-BE-NOMMA-NEXT:    stxvpx vsp34, r4, r5
 ; CHECK-BE-NOMMA-NEXT:    blr
 entry:
   %0 = bitcast <256 x i1>* %vpp to i8*
   %1 = getelementptr i8, i8* %0, i64 32799
   %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
   %3 = bitcast <256 x i1>* %vp2 to i8*
   %4 = getelementptr i8, i8* %3, i64 32799
   tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
   ret void
 }

llvm/test/CodeGen/PowerPC/spill-vec-pair.ll

 ; CHECK-NEXT:    stfd f26, 352(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd f27, 360(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stxv v30, 224(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stfd f28, 368(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd f29, 376(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stxv v31, 240(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stfd f30, 384(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd f31, 392(r1) # 8-byte Folded Spill
-; CHECK-NEXT:    lxvp vsp0, 0(r3)
-; CHECK-NEXT:    stxvp vsp0, 32(r1) # 32-byte Folded Spill
+; CHECK-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-NEXT:    stxvp vsp34, 32(r1) # 32-byte Folded Spill
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    lxvp vsp0, 32(r1) # 32-byte Folded Reload
-; CHECK-NEXT:    stxvp vsp0, 0(r4)
+; CHECK-NEXT:    lxvp vsp34, 32(r1) # 32-byte Folded Reload
+; CHECK-NEXT:    stxvp vsp34, 0(r4)
 ; CHECK-NEXT:    lxv v31, 240(r1) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v30, 224(r1) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v29, 208(r1) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v28, 192(r1) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v27, 176(r1) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v26, 160(r1) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v25, 144(r1) # 16-byte Folded Reload
 ; CHECK-NEXT:    lxv v24, 128(r1) # 16-byte Folded Reload

 ; CHECK-BE-NEXT:    stfd f26, 368(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    stfd f27, 376(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v30, 240(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stfd f28, 384(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    stfd f29, 392(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    stxv v31, 256(r1) # 16-byte Folded Spill
 ; CHECK-BE-NEXT:    stfd f30, 400(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    stfd f31, 408(r1) # 8-byte Folded Spill
-; CHECK-BE-NEXT:    lxvp vsp0, 0(r3)
-; CHECK-BE-NEXT:    stxvp vsp0, 48(r1) # 32-byte Folded Spill
+; CHECK-BE-NEXT:    lxvp vsp34, 0(r3)
+; CHECK-BE-NEXT:    stxvp vsp34, 48(r1) # 32-byte Folded Spill
 ; CHECK-BE-NEXT:    #APP
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    #NO_APP
-; CHECK-BE-NEXT:    lxvp vsp0, 48(r1) # 32-byte Folded Reload
-; CHECK-BE-NEXT:    stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:    lxvp vsp34, 48(r1) # 32-byte Folded Reload
+; CHECK-BE-NEXT:    stxvp vsp34, 0(r4)
 ; CHECK-BE-NEXT:    lxv v31, 256(r1) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    lxv v30, 240(r1) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    lxv v29, 224(r1) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    lxv v28, 208(r1) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    lxv v27, 192(r1) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    lxv v26, 176(r1) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    lxv v25, 160(r1) # 16-byte Folded Reload
 ; CHECK-BE-NEXT:    lxv v24, 144(r1) # 16-byte Folded Reload