[AIX] Use VSSRC/VSFRC Register classes for f32/f64 callee arguments on P8 and above

[ZarkoCA]

Summary

Adding usage of VSSRC and VSFRC when adding the live in registers on AIX.
This matches the behaviour of the rest of PPC Subtargets.

[qiucf]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6743–6745

Better to comment it if this method is only for AIX?

llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll

6

Maybe better to pre-commit this file? (or at least generate diff after staging it)

[ZarkoCA]

Added comment to clarify getRegClassforSVT() is only used by AIX.
Modified test case.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll

6

I could do that if you feel strongly about it but I'd like the test case to be associated with this patch since we already have many AIX calling convention test cases. I don't think adding it alone add any value besides what this patch will show and in that case, in my opinion, it's better to have in the patch.

I did add a RUN step for running with -mcpu=pwr8 but with -power8-vector to show try and address your concern in some way. Does that work?

[qiucf]

llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll

6

Got it. Actually this also looks good :-) since we can easily tell the difference between pwr7 and pwr8.

We may not need -mcpu=pwr8 -mattr=-power8-vector here? I think that option set should be just for testing pwr8 scheduling under pwr7 instructions only.

[ZarkoCA]

• Remove no-p8-vector RUN line
• use Register instead of unsigned for Reg variable as per clang-tidy check

[ZarkoCA]

ping @qiucf Have your comments been addressed sufficiently?

[qiucf]

Not sure if other reviewers have any comments, this looks fine to me.

[lkail]

llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll

2

Maybe it's missing REQUIRES:asserts or -debug-only won't work.

-stop-after=finalize-isel should work already? IIRC, machine-cp is a very late pass.

[ZarkoCA]

• Use vsfr when the target has vsx not only on P8 and above
• use stop-after=finalize-isel instead of debug-only option

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll

2

Thank you, that is much better.

[nemanjai]

Other than a small test case nit, LGTM.

llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll

7

I think you should probably also have a PWR7 VSX run line since we will use VSFRC for f64 with that combination (i.e. we don't need Power8 vector in order to use VSFRC).

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

for (unsigned I = 0; I != VecSize; I += PtrSize) {
           CCValAssign::getCustomReg(ValNo, ValVT, Reg, RegVT, LocInfo));
     }
     return false;
   }
   }
   return true;
 }
 
+// So far, this function is only used by LowerFormalArguments_AIX()
 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
-                                                    bool IsPPC64) {
+                                                    bool IsPPC64,
+                                                    bool HasP8Vector,
+                                                    bool HasVSX) {
   assert((IsPPC64 || SVT != MVT::i64) &&
          "i64 should have been split for 32-bit codegen.");
 
   switch (SVT) {
   default:
     report_fatal_error("Unexpected value type for formal argument");
   case MVT::i1:
   case MVT::i32:
   case MVT::i64:
     return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
   case MVT::f32:
-    return &PPC::F4RCRegClass;
+    return HasP8Vector ? &PPC::VSSRCRegClass : &PPC::F4RCRegClass;
   case MVT::f64:
-    return &PPC::F8RCRegClass;
+    return HasVSX ? &PPC::VSFRCRegClass : &PPC::F8RCRegClass;
   case MVT::v4f32:
   case MVT::v4i32:
   case MVT::v8i16:
   case MVT::v16i8:
   case MVT::v2i64:
   case MVT::v2f64:
   case MVT::v1i128:
     return &PPC::VRRCRegClass;
if (VA.isMemLoc() && VA.needsCustom()) {
         assert(I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom() &&
                "Missing custom RegLoc.");
         VA = ArgLocs[I++];
         assert(VA.getValVT().isVector() &&
                "Unexpected Val type for custom RegLoc.");
         assert(VA.getValNo() == OriginalValNo &&
                "ValNo mismatch between custom MemLoc and RegLoc.");
         MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy;
-        MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
+        MF.addLiveIn(VA.getLocReg(),
+                     getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
+                                       Subtarget.hasVSX()));
       };
 
       HandleMemLoc();
       // In 64-bit there will be exactly 2 custom RegLocs that follow, and in
       // in 32-bit there will be 2 custom RegLocs if we are passing in R9 and
       // R10.
       HandleCustomVecRegLoc();
       HandleCustomVecRegLoc();
if (Flags.isByVal()) {
         ++I;
       }
 
       continue;
     }
 
     if (VA.isRegLoc() && !VA.needsCustom()) {
       MVT::SimpleValueType SVT = ValVT.SimpleTy;
-      unsigned VReg =
-          MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
+      Register VReg =
+          MF.addLiveIn(VA.getLocReg(),
+                       getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
+                                         Subtarget.hasVSX()));
       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
       if (ValVT.isScalarInteger() &&
           (ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) {
         ArgValue =
             truncateScalarIntegerArg(Flags, ValVT, DAG, ArgValue, LocVT, dl);
       }
       InVals.push_back(ArgValue);
       continue;

llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll

+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN:   -verify-machineinstrs -stop-after=finalize-isel  < %s | \
+; RUN:   FileCheck --check-prefixes=POWR8,VSX %s
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
+; RUN:   -verify-machineinstrs -mattr=-vsx -stop-after=finalize-isel \
+; RUN:    < %s | FileCheck %s --check-prefixes=NOVSX,NOP8V
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
+; RUN:   -verify-machineinstrs -mattr=vsx -stop-after=finalize-isel \
+; RUN:    < %s | FileCheck %s --check-prefixes=VSX,NOP8V
+
+define float @vssr(float %a, float %b, float %c, float %d, float %e) {
+entry:
+  %add = fadd float %a, %b
+  %add1 = fadd float %add, %c
+  %add2 = fadd float %add1, %d
+  %add3 = fadd float %add2, %e
+  ret float %add3
+}
+
+; POWR8-LABEL: name:            vssr
+; POWR8:       - { id: 0, class: vssrc, preferred-register: '' }
+; POWR8:       - { id: 1, class: vssrc, preferred-register: '' }
+; POWR8:       - { id: 2, class: vssrc, preferred-register: '' }
+; POWR8:       - { id: 3, class: vssrc, preferred-register: '' }
+; POWR8:       - { id: 4, class: vssrc, preferred-register: '' }
+; POWR8:       - { id: 5, class: vssrc, preferred-register: '' }
+; POWR8:       - { id: 6, class: vssrc, preferred-register: '' }
+; POWR8:       - { id: 7, class: vssrc, preferred-register: '' }
+; POWR8:       - { id: 8, class: vssrc, preferred-register: '' }
+; POWR8:       %4:vssrc = COPY $f5
+; POWR8:       %3:vssrc = COPY $f4
+; POWR8:       %2:vssrc = COPY $f3
+; POWR8:       %1:vssrc = COPY $f2
+; POWR8:       %0:vssrc = COPY $f1
+; POWR8:       %5:vssrc = nofpexcept XSADDSP %0, %1
+; POWR8:       %6:vssrc = nofpexcept XSADDSP killed %5, %2
+; POWR8:       %7:vssrc = nofpexcept XSADDSP killed %6, %3
+; POWR8:       %8:vssrc = nofpexcept XSADDSP killed %7, %4
+; POWR8:       $f1 = COPY %8
+
+; NOP8V-LABEL: name:            vssr
+; NOP8V:       registers:
+; NOP8V:       - { id: 0, class: f4rc, preferred-register: '' }
+; NOP8V:       - { id: 1, class: f4rc, preferred-register: '' }
+; NOP8V:       - { id: 2, class: f4rc, preferred-register: '' }
+; NOP8V:       - { id: 3, class: f4rc, preferred-register: '' }
+; NOP8V:       - { id: 4, class: f4rc, preferred-register: '' }
+; NOP8V:       - { id: 5, class: f4rc, preferred-register: '' }
+; NOP8V:       - { id: 6, class: f4rc, preferred-register: '' }
+; NOP8V:       - { id: 7, class: f4rc, preferred-register: '' }
+; NOP8V:       - { id: 8, class: f4rc, preferred-register: '' }
+; NOP8V:        %4:f4rc = COPY $f5
+; NOP8V:        %3:f4rc = COPY $f4
+; NOP8V:        %2:f4rc = COPY $f3
+; NOP8V:        %1:f4rc = COPY $f2
+; NOP8V:        %0:f4rc = COPY $f1
+; NOP8V:        %5:f4rc = nofpexcept FADDS %0, %1, implicit $rm
+; NOP8V:        %6:f4rc = nofpexcept FADDS killed %5, %2, implicit $rm
+; NOP8V:        %7:f4rc = nofpexcept FADDS killed %6, %3, implicit $rm
+; NOP8V:        %8:f4rc = nofpexcept FADDS killed %7, %4, implicit $rm
+; NOP8V:        $f1 = COPY %8
+
+define double @vsfr(double %a, double %b, double %c, double %d, double %e) {
+entry:
+  %add = fadd double %a, %b
+  %add1 = fadd double %add, %c
+  %add2 = fadd double %add1, %d
+  %add3 = fadd double %add2, %e
+  ret double %add3
+}
+
+; VSX-LABEL:   vsfr
+; VSX:         registers:
+; VSX:          - { id: 0, class: vsfrc, preferred-register: '' }
+; VSX:          - { id: 1, class: vsfrc, preferred-register: '' }
+; VSX:          - { id: 2, class: vsfrc, preferred-register: '' }
+; VSX:          - { id: 3, class: vsfrc, preferred-register: '' }
+; VSX:          - { id: 4, class: vsfrc, preferred-register: '' }
+; VSX:          - { id: 5, class: vsfrc, preferred-register: '' }
+; VSX:          - { id: 6, class: vsfrc, preferred-register: '' }
+; VSX:          - { id: 7, class: vsfrc, preferred-register: '' }
+; VSX:          - { id: 8, class: vsfrc, preferred-register: '' }
+; VSX:          %4:vsfrc = COPY $f5
+; VSX:          %3:vsfrc = COPY $f4
+; VSX:          %2:vsfrc = COPY $f3
+; VSX:          %1:vsfrc = COPY $f2
+; VSX:          %0:vsfrc = COPY $f1
+; VSX:          %5:vsfrc = nofpexcept XSADDDP %0, %1, implicit $rm
+; VSX:          %6:vsfrc = nofpexcept XSADDDP killed %5, %2, implicit $rm
+; VSX:          %7:vsfrc = nofpexcept XSADDDP killed %6, %3, implicit $rm
+; VSX:          %8:vsfrc = nofpexcept XSADDDP killed %7, %4, implicit $rm
+; VSX:          $f1 = COPY %8
+
+; NOVSX-LABEL:  vsfr
+; NOVSX:        registers:
+; NOVSX:        - { id: 0, class: f8rc, preferred-register: '' }
+; NOVSX:        - { id: 1, class: f8rc, preferred-register: '' }
+; NOVSX:        - { id: 2, class: f8rc, preferred-register: '' }
+; NOVSX:        - { id: 3, class: f8rc, preferred-register: '' }
+; NOVSX:        - { id: 4, class: f8rc, preferred-register: '' }
+; NOVSX:        - { id: 5, class: f8rc, preferred-register: '' }
+; NOVSX:        - { id: 6, class: f8rc, preferred-register: '' }
+; NOVSX:        - { id: 7, class: f8rc, preferred-register: '' }
+; NOVSX:        - { id: 8, class: f8rc, preferred-register: '' }
+; NOVSX:        %4:f8rc = COPY $f5
+; NOVSX:        %3:f8rc = COPY $f4
+; NOVSX:        %2:f8rc = COPY $f3
+; NOVSX:        %1:f8rc = COPY $f2
+; NOVSX:        %0:f8rc = COPY $f1
+; NOVSX:        %5:f8rc = nofpexcept FADD %0, %1, implicit $rm
+; NOVSX:        %6:f8rc = nofpexcept FADD killed %5, %2, implicit $rm
+; NOVSX:        %7:f8rc = nofpexcept FADD killed %6, %3, implicit $rm
+; NOVSX:        %8:f8rc = nofpexcept FADD killed %7, %4, implicit $rm
+; NOVSX:        $f1 = COPY %8
+