[lld][ELF][SPARC] Implement and fixup GOT/PLT relocations

[LemonBoy]

Summary

• Support R_SPARC_GOT13 relocation, completing the support for 32bit PIC model.
• Support the R_SPARC_GOTDATA_OP_ family of relocations and its optimizations.
• Reserve a GOT entry as required by the ABI.
• Emit RELA entries as required by the ABI.
• Avoid the use of .got.plt.
• Apply the R_SPARC_JMP_SLOT relocation on PLT entries.

[jrtc27]

Please stop putting the rela change into tangentially-related revisions.

[jrtc27]

Commits should be something like:

1. Fix lld to use rela
2. Finish GOT support
3. Add IE TLS
4. Add LD TLS
5. Add GD TLS

[LemonBoy]

Depends on D102986.

[MaskRay]

I dislike that we are fixing these stuff increasingly with so many patches.

See the history of Arch/PPC.cpp - most stuff are implemented with very few commits.

[LemonBoy]

In D102985#2776028, @MaskRay wrote:

I dislike that we are fixing these stuff increasingly with so many patches.

See the history of Arch/PPC.cpp - most stuff are implemented with very few commits.

I'm getting a bit tired of splitting and merging patches, can we please decide on what the best course of action is and end this suffering?

[jrtc27]

In D102985#2776031, @LemonBoy wrote:

In D102985#2776028, @MaskRay wrote:

I dislike that we are fixing these stuff increasingly with so many patches.

See the history of Arch/PPC.cpp - most stuff are implemented with very few commits.

I'm getting a bit tired of splitting and merging patches, can we please decide on what the best course of action is and end this suffering?

Hm, MaskRay makes a good point. I guess my real complaint when I stop and think about it is not combining multiple things into one commit, but having a commit that says "do X" when it's really "do X and Y". One commit that's "fix everything", or two commits "fix everything except TLS" and "finish TLS", seems fine to me, so long as the descriptions are correct and don't sneak in changes that are unrelated to the commit _message_.

[MaskRay]

I think the problem is the existing port is too broken. Aside from that, some relocation types are clearly not tested. Some GOT/PLT relocations are likely not properly tested.
The bar for the initial check-in was too low I'd say.

I think for a mature port, fixing things incrementally make for good commit history. But I cannot feel similarly for sparcv9 which apparently misses many things.
Personally I like the test organization of ppc32-* the most. Not too many tests (x86_64 tends to have the problem that there are too many files) but sufficient coverage is provided.
By looking at the history, you can see that I ensured GOT/PLT and every related things are correct in one commit and we never need to fix the implemented stuff.

[MaskRay]

I think it is useful to set up a minimal goal. When you fix/implement GOT/PLT, make sure some basic programs with GOT/PLT are really working.

If we do "fix GOT a" "fot GOT b" "fix PLT c", it is very likely that a subsequent commit may update an earlier commit. This is less elegant.

So what's the state of this port? When I implemented ppc32 support and added riscv support, I made sure glibc/musl ppc32/riscv dynamically linking programs work.

Some (candidate) milestones: (1) support -fno-pic -no-pie -nostdlib link (2) support dynamic linking (many stuff are here: RELATIVE/COPY/GOT/PLT/...) (3) support tls (4) support extra things that glibc static links require

[LemonBoy]

In D102985#2776038, @MaskRay wrote:

I think it is useful to set up a minimal goal. When you fix/implement GOT/PLT, make sure some basic programs with GOT/PLT are really working.

If we do "fix GOT a" "fot GOT b" "fix PLT c", it is very likely that a subsequent commit may update an earlier commit. This is less elegant.

So what's the state of this port? When I implemented ppc32 support and added riscv support, I made sure glibc/musl ppc32/riscv dynamically linking programs work.

Some (candidate) milestones: (1) support -fno-pic -no-pie -nostdlib link (2) support dynamic linking (many stuff are here: RELATIVE/COPY/GOT/PLT/...) (3) support tls (4) support extra things that glibc static links require

The port is good enough to be able to successfully link the whole Zig compiler and its test suite.
This set of patches is part of my effort to let it build and run a whole Zig program that's dynamically linked against glibc, I'm progressively fixing lld as needed.

My current roadmap is:

• Implement the remaining TLS models {IE, GD, LD}
• Implement the GOTDATA relocations.

Some fixup commits to fix what was broken/missing are perhaps inelegant but necessary.

[LemonBoy]

Add back the RELA bit, no explicit test is needed as the existing ones are already covering that bit.

[MaskRay]

Is dynamic linking fully functional?

[LemonBoy]

In D102985#2827315, @MaskRay wrote:

Is dynamic linking fully functional?

Sort of. I managed to link and run (under Qemu) a dynamically-linked PIE executable after applying a few more touch-ups, the idea is to turn this patchset into one targeting GOT/PLT support, as you suggested.
No updated patch was uploaded because I've hit a problem with (I think) how LLD handles GOT entries and how SPARC GOTDATA relocations are supposed to work. At the moment the plan is to avoid implementing the GOTDATA optimizations and treat them as regular GOT-relative relocations instead.
Below you can find the set of relocations emitted by GCC for a small hello-world program, the six GOTDATA triplets reference six different objects in the .rodata sections ... by means of a STT_SECTION reference with non-zero addend. Since all the six relocations point to the same symbol LLD generates a single GOT entry (every call to isInGot returns true) and that generates binaries that are crashing at runtime.

As you can see the code sequence for this kind of relocation expects a single GOT entry for each relocation w/ different addends:

sethi %gdop_hix22(symbol), %l1
xor   %l1, %gdop_lox10(symbol), %l1
ld    [%l7 + %l1], %l2, %gdop(symbol)

I'm open to suggestions on how to overcome this problem, of course relaxing this relocation kind solves the problem at hand (even though that opens another can of worms, RelExpr already has 64 elements and RelExprMaskBuilder requires some work to accommodate more entries) but I wonder if that'd be only papering over a bigger problem.

Section (3) .rela.text {
  0x4 R_SPARC_PC22 _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFFFFFFFFF8
  0x8 R_SPARC_PC10 _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFFFFFFFFFC
  0xC R_SPARC_WPLT30 __sparc_get_pc_thunk.l7 0x0
  0x24 R_SPARC_GOTDATA_OP_HIX22 .rodata 0x0
  0x28 R_SPARC_GOTDATA_OP_LOX10 .rodata 0x0
  0x2C R_SPARC_GOTDATA_OP .rodata 0x0
  0x34 R_SPARC_WPLT30 puts 0x0
  0x3C R_SPARC_GOTDATA_OP_HIX22 .rodata 0x10
  0x40 R_SPARC_GOTDATA_OP_LOX10 .rodata 0x10
  0x44 R_SPARC_GOTDATA_OP .rodata 0x10
  0x4C R_SPARC_GOTDATA_OP_HIX22 .rodata 0x18
  0x50 R_SPARC_GOTDATA_OP_LOX10 .rodata 0x18
  0x54 R_SPARC_GOTDATA_OP .rodata 0x18
  0x5C R_SPARC_WPLT30 fopen 0x0
  0x74 R_SPARC_GOTDATA_OP_HIX22 .rodata 0x28
  0x78 R_SPARC_GOTDATA_OP_LOX10 .rodata 0x28
  0x7C R_SPARC_GOTDATA_OP .rodata 0x28
  0x84 R_SPARC_WPLT30 puts 0x0
  0x98 R_SPARC_GOTDATA_OP_HIX22 .rodata 0x30
  0x9C R_SPARC_GOTDATA_OP_LOX10 .rodata 0x30
  0xA0 R_SPARC_GOTDATA_OP .rodata 0x30
  0xA8 R_SPARC_WPLT30 fwrite 0x0
  0xB4 R_SPARC_WPLT30 fclose 0x0
  0xBC R_SPARC_GOTDATA_OP_HIX22 .rodata 0x38
  0xC0 R_SPARC_GOTDATA_OP_LOX10 .rodata 0x38
  0xC4 R_SPARC_GOTDATA_OP .rodata 0x38
  0xCC R_SPARC_WPLT30 puts 0x0
}

[jrtc27]

Ok, so you need R_RELAX_GOT_OFF to match R_RELAX_GOT_PC?

[LemonBoy]

In D102985#2829305, @jrtc27 wrote:

Ok, so you need R_RELAX_GOT_OFF to match R_RELAX_GOT_PC?

A relocation that behaves as R_GOT_OFF or, when it's possible to relax it, as a R_GOTREL.

[jrtc27]

In D102985#2829308, @LemonBoy wrote:

In D102985#2829305, @jrtc27 wrote:

Ok, so you need R_RELAX_GOT_OFF to match R_RELAX_GOT_PC?

A relocation that behaves as R_GOT_OFF or, when it's possible to relax it, as a R_GOTREL.

Yes, the R_GOT_OFF version of what R_RELAX_GOT_PC is to R_GOT_PC (e.g. movq foo@GOTPCREL(%rip), %rax -> leaq foo(%rip), %rax, where the latter means leaq foo@PCREL(%rip) but that's implied by the %rip base).

[LemonBoy]

In D102985#2829310, @jrtc27 wrote:

In D102985#2829308, @LemonBoy wrote:

In D102985#2829305, @jrtc27 wrote:

Ok, so you need R_RELAX_GOT_OFF to match R_RELAX_GOT_PC?

A relocation that behaves as R_GOT_OFF or, when it's possible to relax it, as a R_GOTREL.

Yes, the R_GOT_OFF version of what R_RELAX_GOT_PC is to R_GOT_PC (e.g. movq foo@GOTPCREL(%rip), %rax -> leaq foo(%rip), %rax, where the latter means leaq foo@PCREL(%rip) but that's implied by the %rip base).

Oh. Yes, that's the idea. At the moment I'm treating all of them as R_GOT_OFF but, as explained above, that's not working for every binary.

[LemonBoy]

Here's the updated patch, I'm now able to link and run several small programs linked against glibc (in both PIC/PIE mode), shared libraries and some basic examples w/ ifuncs.

The use of uint128_t is a hack that works pretty well, suggestions are welcome.

Once D102575 I'll be able to commit some tests.

[jrtc27]

32-bit architectures don't support int128_t.

[jrtc27]

Downstream we turned it into a std::pair<uint64_t, uint64_t> (https://github.com/CTSRD-CHERI/llvm-project/blob/de58a2a25c32471b4b3c2aec77fee624e24120cd/lld/ELF/Relocations.cpp#L136-L179), though something more general where it's parameterised on the number of words might be nicer rather than hand-rolling a pair version.

[LemonBoy]

In D102985#2830779, @jrtc27 wrote:

Downstream we turned it into a std::pair<uint64_t, uint64_t> (https://github.com/CTSRD-CHERI/llvm-project/blob/de58a2a25c32471b4b3c2aec77fee624e24120cd/lld/ELF/Relocations.cpp#L136-L179), though something more general where it's parameterised on the number of words might be nicer rather than hand-rolling a pair version.

Interesting, I started implementing it in terms of an array of uint64_t elements.
Using a std::pair looks good to me, it's quite unlikely for RelExpr to become bigger than 128 (hopefully). Do you plan on upstreaming this change?

lld/ELF/Arch/SPARCV9.cpp

 using namespace lld::elf;
 
 namespace {
 class SPARCV9 final : public TargetInfo {
 public:
   SPARCV9();
   RelExpr getRelExpr(RelType type, const Symbol &s,
                      const uint8_t *loc) const override;
+  RelExpr adjustGotOffExpr(RelType type, const Symbol &sym, int64_t addend,
+                           const uint8_t *loc) const override;
+  RelType getDynRel(RelType type) const;
+  void relaxGot(uint8_t *loc, const Relocation &rel,
+                uint64_t val) const override;
+  void writeGotHeader(uint8_t *buf) const override;
   void writePlt(uint8_t *buf, const Symbol &sym,
                 uint64_t pltEntryAddr) const override;
   void relocate(uint8_t *loc, const Relocation &rel,
                 uint64_t val) const override;
 };
 } // namespace
 
 SPARCV9::SPARCV9() {
   copyRel = R_SPARC_COPY;
   gotRel = R_SPARC_GLOB_DAT;
   noneRel = R_SPARC_NONE;
   pltRel = R_SPARC_JMP_SLOT;
   relativeRel = R_SPARC_RELATIVE;
   symbolicRel = R_SPARC_64;
   pltEntrySize = 32;
   pltHeaderSize = 4 * pltEntrySize;
 
   defaultCommonPageSize = 8192;
   defaultMaxPageSize = 0x100000;
   defaultImageBase = 0x100000;
+
+  // .got[0] = _DYNAMIC
+  gotBaseSymInGotPlt = false;
+  gotHeaderEntriesNum = 1;
+
+  needsGotPlt = false;
+}
+
+void SPARCV9::writeGotHeader(uint8_t *buf) const {
+  write64(buf, mainPart->dynamic->getVA());
+}
+
+RelType SPARCV9::getDynRel(RelType type) const {
+  if (type == R_SPARC_64)
+    return type;
+  return R_SPARC_NONE;
+}
+
+RelExpr SPARCV9::adjustGotOffExpr(RelType type, const Symbol &sym,
+                                  int64_t addend, const uint8_t *loc) const {
+  return sym.isLocal() ? R_RELAX_GOT_OFF : R_GOT_OFF;
+}
+
+void SPARCV9::relaxGot(uint8_t *loc, const Relocation &rel,
+                       uint64_t val) const {
+  switch (rel.type) {
+  case R_SPARC_GOTDATA_OP_LOX10:
+  case R_SPARC_GOTDATA_OP_HIX22:
+    relocate(loc, rel, val);
+    break;
+  case R_SPARC_GOTDATA_OP:
+    // ldx [%rs1 + %rs2], %rd -> add %rs1, %rs2, %rd
+    write32(loc, (read32(loc) & 0x3e07c01f) | 0x80000000);
+    break;
+  default:
+    llvm_unreachable("unexpected relocation kind");
+  }
 }
 
 RelExpr SPARCV9::getRelExpr(RelType type, const Symbol &s,
                             const uint8_t *loc) const {
   switch (type) {
   case R_SPARC_32:
   case R_SPARC_UA32:
   case R_SPARC_64:
   case R_SPARC_UA64:
   case R_SPARC_H44:
   case R_SPARC_M44:
   case R_SPARC_L44:
   case R_SPARC_HH22:
   case R_SPARC_HM10:
   case R_SPARC_LM22:
   case R_SPARC_HI22:
   case R_SPARC_LO10:
     return R_ABS;
   case R_SPARC_PC10:
   case R_SPARC_PC22:
   case R_SPARC_DISP32:
   case R_SPARC_WDISP30:
     return R_PC;
   case R_SPARC_GOT10:
-    return R_GOT_OFF;
+  case R_SPARC_GOT13:
   case R_SPARC_GOT22:
     return R_GOT_OFF;
   case R_SPARC_WPLT30:
     return R_PLT_PC;
   case R_SPARC_NONE:
     return R_NONE;
   case R_SPARC_TLS_LE_HIX22:
   case R_SPARC_TLS_LE_LOX10:
     return R_TPREL;
+  case R_SPARC_GOTDATA_OP_LOX10:
+  case R_SPARC_GOTDATA_OP_HIX22:
+  case R_SPARC_GOTDATA_OP:
+    return R_GOT_OFF;
   default:
     error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
           ") against symbol " + toString(s));
     return R_NONE;
   }
 }
 
 void SPARCV9::relocate(uint8_t *loc, const Relocation &rel,
case R_SPARC_HI22:
     checkUInt(loc, val >> 10, 22, rel);
     write32be(loc, (read32be(loc) & ~0x003fffff) | ((val >> 10) & 0x003fffff));
     break;
   case R_SPARC_WDISP19:
     // V-disp19
     checkInt(loc, val, 21, rel);
     write32be(loc, (read32be(loc) & ~0x0007ffff) | ((val >> 2) & 0x0007ffff));
     break;
+  case R_SPARC_GOT13:
+    // V-simm13
+    checkInt(loc, val, 13, rel);
+    write32be(loc, (read32be(loc) & ~0x00001fff) | (val & 0x000003ff));
+    break;
   case R_SPARC_GOT10:
   case R_SPARC_PC10:
     // T-simm10
     write32be(loc, (read32be(loc) & ~0x000003ff) | (val & 0x000003ff));
     break;
   case R_SPARC_LO10:
     // T-simm13
     write32be(loc, (read32be(loc) & ~0x00001fff) | (val & 0x000003ff));
void SPARCV9::relocate(uint8_t *loc, const Relocation &rel,
   case R_SPARC_L44:
     // T-imm13
     write32be(loc, (read32be(loc) & ~0x00001fff) | (val & 0x00000fff));
     break;
   case R_SPARC_TLS_LE_HIX22:
     // T-imm22
     write32be(loc, (read32be(loc) & ~0x003fffff) | ((~val >> 10) & 0x003fffff));
     break;
+  case R_SPARC_GOTDATA_OP_LOX10:
+    if ((int64_t)val < 0)
+      write32be(loc,
+                (read32be(loc) & ~0x00001fff) | (val & 0x000003ff) | 0x1C00);
+    else
+      write32be(loc, (read32be(loc) & ~0x00001fff) | (val & 0x000003ff));
+    break;
+  case R_SPARC_GOTDATA_OP_HIX22:
+    if ((int64_t)val < 0)
+      write32be(loc,
+                (read32be(loc) & ~0x003fffff) | ((~val >> 10) & 0x003fffff));
+    else
+      write32be(loc,
+                (read32be(loc) & ~0x003fffff) | ((val >> 10) & 0x003fffff));
+    break;
+  case R_SPARC_GOTDATA_OP:
+    break;
   case R_SPARC_TLS_LE_LOX10:
     // T-simm13
     write32be(loc, (read32be(loc) & ~0x00001fff) | (val & 0x000003ff) | 0x1C00);
     break;
   default:
     llvm_unreachable("unknown relocation");
   }
 }
 
-void SPARCV9::writePlt(uint8_t *buf, const Symbol & /*sym*/,
+void SPARCV9::writePlt(uint8_t *buf, const Symbol &sym,
                        uint64_t pltEntryAddr) const {
   const uint8_t pltData[] = {
       0x03, 0x00, 0x00, 0x00, // sethi   (. - .PLT0), %g1
       0x30, 0x68, 0x00, 0x00, // ba,a    %xcc, .PLT1
       0x01, 0x00, 0x00, 0x00, // nop
       0x01, 0x00, 0x00, 0x00, // nop
       0x01, 0x00, 0x00, 0x00, // nop
       0x01, 0x00, 0x00, 0x00, // nop

lld/ELF/Driver.cpp

if (s == "rel")
       return false;
     if (s == "rela")
       return true;
   }
 
   // Otherwise use the psABI defined relocation entry format.
   uint16_t m = config->emachine;
   return m == EM_AARCH64 || m == EM_AMDGPU || m == EM_HEXAGON || m == EM_PPC ||
-         m == EM_PPC64 || m == EM_RISCV || m == EM_X86_64;
+         m == EM_PPC64 || m == EM_RISCV || m == EM_SPARCV9 || m == EM_X86_64;
 }
 
 static void parseClangOption(StringRef opt, const Twine &msg) {
   std::string err;
   raw_string_ostream os(err);
 
   const char *argv[] = {config->progName.data(), opt.data()};
   if (cl::ParseCommandLineOptions(2, argv, "", &os))

lld/ELF/InputSection.cpp

uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type,
   case R_RELAX_TLS_GD_TO_IE_ABS:
     return sym.getGotVA() + a;
   case R_GOTONLY_PC:
     return in.got->getVA() + a - p;
   case R_GOTPLTONLY_PC:
     return in.gotPlt->getVA() + a - p;
   case R_GOTREL:
   case R_PPC64_RELAX_TOC:
+  case R_RELAX_GOT_OFF:
     return sym.getVA(a) - in.got->getVA();
   case R_GOTPLTREL:
     return sym.getVA(a) - in.gotPlt->getVA();
   case R_GOTPLT:
   case R_RELAX_TLS_GD_TO_IE_GOTPLT:
     return sym.getGotVA() + a - in.gotPlt->getVA();
   case R_TLSLD_GOT_OFF:
   case R_GOT_OFF:

 void InputSectionBase::relocateAlloc(uint8_t *buf, uint8_t *bufEnd) {
   assert(flags & SHF_ALLOC);
   const unsigned bits = config->wordsize * 8;
   uint64_t lastPPCRelaxedRelocOff = UINT64_C(-1);
 
   for (const Relocation &rel : relocations) {
     if (rel.expr == R_NONE)
       continue;
+
     uint64_t offset = rel.offset;
     uint8_t *bufLoc = buf + offset;
     RelType type = rel.type;
 
     uint64_t addrLoc = getOutputSection()->addr + offset;
     if (auto *sec = dyn_cast<InputSection>(this))
       addrLoc += sec->outSecOff;
     RelExpr expr = rel.expr;
     uint64_t targetVA = SignExtend64(
         getRelocTargetVA(file, type, rel.addend, addrLoc, *rel.sym, expr),
         bits);
 
     switch (expr) {
     case R_RELAX_GOT_PC:
     case R_RELAX_GOT_PC_NOPIC:
+    case R_RELAX_GOT_OFF:
       target->relaxGot(bufLoc, rel, targetVA);
       break;
     case R_PPC64_RELAX_GOT_PC: {
       // The R_PPC64_PCREL_OPT relocation must appear immediately after
       // R_PPC64_GOT_PCREL34 in the relocations table at the same offset.
       // We can only relax R_PPC64_PCREL_OPT if we have also relaxed
       // the associated R_PPC64_GOT_PCREL34 since only the latter has an
       // associated symbol. So save the offset when relaxing R_PPC64_GOT_PCREL34

lld/ELF/Relocations.h

enum RelExpr {
   R_GOTPLTREL,
   R_GOTREL,
   R_NONE,
   R_PC,
   R_PLT,
   R_PLT_PC,
   R_RELAX_GOT_PC,
   R_RELAX_GOT_PC_NOPIC,
+  R_RELAX_GOT_OFF,
   R_RELAX_TLS_GD_TO_IE,
   R_RELAX_TLS_GD_TO_IE_ABS,
   R_RELAX_TLS_GD_TO_IE_GOT_OFF,
   R_RELAX_TLS_GD_TO_IE_GOTPLT,
   R_RELAX_TLS_GD_TO_LE,
   R_RELAX_TLS_GD_TO_LE_NEG,
   R_RELAX_TLS_IE_TO_LE,
   R_RELAX_TLS_LD_TO_LE,

lld/ELF/Relocations.cpp

void elf::reportRangeError(uint8_t *loc, int64_t v, int n, const Symbol &sym,
   if (!sym.getName().empty())
     hint = "; references " + lld::toString(sym) + getDefinedLocation(sym);
   errorOrWarn(errPlace.loc + msg + " is out of range: " + Twine(v) +
               " is not in [" + Twine(llvm::minIntN(n)) + ", " +
               Twine(llvm::maxIntN(n)) + "]" + hint);
 }
 
 namespace {
+typedef unsigned __int128 uint128_t;
 // Build a bitmask with one bit set for each RelExpr.
 //
 // Constexpr function arguments can't be used in static asserts, so we
 // use template arguments to build the mask.
 // But function template partial specializations don't exist (needed
 // for base case of the recursion), so we need a dummy struct.
 template <RelExpr... Exprs> struct RelExprMaskBuilder {
-  static inline uint64_t build() { return 0; }
+  static inline uint128_t build() { return 0; }
 };
 
 // Specialization for recursive case.
 template <RelExpr Head, RelExpr... Tail>
 struct RelExprMaskBuilder<Head, Tail...> {
-  static inline uint64_t build() {
-    static_assert(0 <= Head && Head < 64,
-                  "RelExpr is too large for 64-bit mask!");
-    return (uint64_t(1) << Head) | RelExprMaskBuilder<Tail...>::build();
+  static inline uint128_t build() {
+    static_assert(0 <= Head && Head < 128,
+                  "RelExpr is too large for 128-bit mask!");
+    return (uint128_t(1) << Head) | RelExprMaskBuilder<Tail...>::build();
   }
 };
 } // namespace
 
 // Return true if `Expr` is one of `Exprs`.
 // There are fewer than 64 RelExpr's, so we can represent any set of
 // RelExpr's as a constant bit mask and test for membership with a
 // couple cheap bitwise operations.
 template <RelExpr... Exprs> bool oneof(RelExpr expr) {
-  assert(0 <= expr && (int)expr < 64 &&
-         "RelExpr is too large for 64-bit mask!");
-  return (uint64_t(1) << expr) & RelExprMaskBuilder<Exprs...>::build();
+  assert(0 <= expr && (int)expr < 128 &&
+         "RelExpr is too large for 128-bit mask!");
+  return (uint128_t(1) << expr) & RelExprMaskBuilder<Exprs...>::build();
 }
 
 // This function is similar to the `handleTlsRelocation`. MIPS does not
 // support any relaxations for TLS relocations so by factoring out MIPS
 // handling in to the separate function we can simplify the code and do not
 // pollute other `handleTlsRelocation` by MIPS `ifs` statements.
 // Mips has a custom MipsGotSection that handles the writing of GOT entries
 // without dynamic relocations.
return oneof<R_GOT, R_GOT_OFF, R_MIPS_GOT_LOCAL_PAGE, R_MIPS_GOT_OFF,
                R_AARCH64_GOT_PAGE>(expr);
 }
 
 // True if this expression is of the form Sym - X, where X is a position in the
 // file (PC, or GOT for example).
 static bool isRelExpr(RelExpr expr) {
   return oneof<R_PC, R_GOTREL, R_GOTPLTREL, R_MIPS_GOTREL, R_PPC64_CALL,
                R_PPC64_RELAX_TOC, R_AARCH64_PAGE_PC, R_RELAX_GOT_PC,
-               R_RISCV_PC_INDIRECT, R_PPC64_RELAX_GOT_PC>(expr);
+               R_RISCV_PC_INDIRECT, R_PPC64_RELAX_GOT_PC, R_RELAX_GOT_OFF>(
+      expr);
 }
 
 // Returns true if a given relocation can be computed at link-time.
 //
 // For instance, we know the offset from a relocation to its target at
 // link-time if the relocation is PC-relative and refers a
 // non-interposable function in the same executable. This function
 // will return true for such relocation.
if (part.relrDyn && isec->alignment >= 2 && offsetInSec % 2 == 0) {
     return;
   }
   part.relaDyn->addReloc(target->relativeRel, isec, offsetInSec, sym, addend,
                          expr, type);
 }
 
 template <class PltSection, class GotPltSection>
 static void addPltEntry(PltSection *plt, GotPltSection *gotPlt,
-                        RelocationBaseSection *rel, RelType type, Symbol &sym) {
+                        RelocationBaseSection *rel, bool indirect,
+                        Symbol &sym) {
+  RelType type = indirect ? target->iRelativeRel : target->pltRel;
+
+  if (target->needsGotPlt) {
     plt->addEntry(sym);
     gotPlt->addEntry(sym);
+    // The relocation is applied to the .got.plt entry.
     rel->addReloc(
         {type, gotPlt, sym.getGotPltOffset(), !sym.isPreemptible, &sym, 0});
+  } else {
+    plt->addEntry(sym);
+    // The relocation is applied to the .plt entry.
+    rel->addReloc({type, plt, sym.getPltOffset(), !sym.isPreemptible, &sym, 0});
+  }
 }
 
 static void addGotEntry(Symbol &sym) {
   in.got->addEntry(sym);
 
   RelExpr expr = sym.isTls() ? R_TPREL : R_ABS;
   uint64_t off = sym.getGotOffset();
 
if (!config->shared) {
     // * If a library definition gets preempted to the executable, it will have
     //   the wrong ebx value.
     if (sym.isFunc()) {
       if (config->pie && config->emachine == EM_386)
         errorOrWarn("symbol '" + toString(sym) +
                     "' cannot be preempted; recompile with -fPIE" +
                     getLocation(sec, sym, offset));
       if (!sym.isInPlt())
-        addPltEntry(in.plt, in.gotPlt, in.relaPlt, target->pltRel, sym);
+        addPltEntry(in.plt, in.gotPlt, in.relaPlt, false, sym);
       if (!sym.isDefined()) {
         replaceWithDefined(
             sym, in.plt,
             target->pltHeaderSize + target->pltEntrySize * sym.pltIndex, 0);
         if (config->emachine == EM_PPC) {
           // PPC32 canonical PLT entries are at the beginning of .glink
           cast<Defined>(sym).value = in.plt->headerSize;
           in.plt->headerSize += 16;
static void scanReloc(InputSectionBase &sec, OffsetGetter &getOffset, RelTy *&i,
   //
   // If we know that a PLT entry will be resolved within the same ELF module, we
   // can skip PLT access and directly jump to the destination function. For
   // example, if we are linking a main executable, all dynamic symbols that can
   // be resolved within the executable will actually be resolved that way at
   // runtime, because the main executable is always at the beginning of a search
   // list. We can leverage that fact.
   if (!sym.isPreemptible && (!sym.isGnuIFunc() || config->zIfuncNoplt)) {
-    if (expr != R_GOT_PC) {
+    if (expr != R_GOT_PC && expr != R_GOT_OFF) {
       // The 0x8000 bit of r_addend of R_PPC_PLTREL24 is used to choose call
       // stub type. It should be ignored if optimized to R_PC.
       if (config->emachine == EM_PPC && expr == R_PPC32_PLTREL)
         addend &= ~0x8000;
       // R_HEX_GD_PLT_B22_PCREL (call a@GDPLT) is transformed into
       // call __tls_get_addr even if the symbol is non-preemptible.
       if (!(config->emachine == EM_HEXAGON &&
            (type == R_HEX_GD_PLT_B22_PCREL ||
             type == R_HEX_GD_PLT_B22_PCREL_X ||
             type == R_HEX_GD_PLT_B32_PCREL_X)))
       expr = fromPlt(expr);
     } else if (!isAbsoluteValue(sym)) {
+      if (expr == R_GOT_PC)
         expr = target->adjustGotPcExpr(type, addend, relocatedAddr);
+      else if (expr == R_GOT_OFF)
+        expr = target->adjustGotOffExpr(type, sym, addend, relocatedAddr);
     }
   }
 
   // If the relocation does not emit a GOT or GOTPLT entry but its computation
   // uses their addresses, we need GOT or GOTPLT to be created.
   //
   // The 4 types that relative GOTPLT are all x86 and x86-64 specific.
   if (oneof<R_GOTPLTONLY_PC, R_GOTPLTREL, R_GOTPLT, R_TLSGD_GOTPLT>(expr)) {
if (sym.isGnuIFunc() && config->zIfuncNoplt) {
     return;
   }
 
   // Non-preemptible ifuncs require special handling. First, handle the usual
   // case where the symbol isn't one of these.
   if (!sym.isGnuIFunc() || sym.isPreemptible) {
     // If a relocation needs PLT, we create PLT and GOTPLT slots for the symbol.
     if (needsPlt(expr) && !sym.isInPlt())
-      addPltEntry(in.plt, in.gotPlt, in.relaPlt, target->pltRel, sym);
+      addPltEntry(in.plt, in.gotPlt, in.relaPlt, false, sym);
 
     // Create a GOT slot if a relocation needs GOT.
     if (needsGot(expr)) {
       if (config->emachine == EM_MIPS) {
         // MIPS ABI has special rules to process GOT entries and doesn't
         // require relocation entries for them. A special case is TLS
         // relocations. In that case dynamic loader applies dynamic
         // relocations to initialize TLS GOT entries.
if (!sym.isInPlt()) {
       // Create a copy of the symbol to use as the target of the IRELATIVE
       // relocation in the igotPlt. This is in case we make the PLT canonical
       // later, which would overwrite the original symbol.
       //
       // FIXME: Creating a copy of the symbol here is a bit of a hack. All
       // that's really needed to create the IRELATIVE is the section and value,
       // so ideally we should just need to copy those.
       auto *directSym = make<Defined>(cast<Defined>(sym));
-      addPltEntry(in.iplt, in.igotPlt, in.relaIplt, target->iRelativeRel,
-                  *directSym);
+      addPltEntry(in.iplt, in.igotPlt, in.relaIplt, true, *directSym);
       sym.pltIndex = directSym->pltIndex;
     }
     if (needsGot(expr)) {
       // Redirect GOT accesses to point to the Igot.
       //
       // This field is also used to keep track of whether we ever needed a GOT
       // entry. If we did and we make the PLT canonical later, we'll need to
       // create a GOT entry pointing to the PLT entry for Sym.
if (!sym)
     return;
   bool needEntry = true;
   forEachInputSectionDescription(
       outputSections, [&](OutputSection *os, InputSectionDescription *isd) {
         for (InputSection *isec : isd->sections)
           for (Relocation &rel : isec->relocations)
             if (rel.sym->type == llvm::ELF::STT_TLS && rel.expr == R_PLT_PC) {
               if (needEntry) {
-                addPltEntry(in.plt, in.gotPlt, in.relaPlt, target->pltRel,
-                            *sym);
+                addPltEntry(in.plt, in.gotPlt, in.relaPlt, false, *sym);
                 needEntry = false;
               }
               rel.sym = sym;
             }
       });
 }
 
 template void elf::scanRelocations<ELF32LE>(InputSectionBase &);
 template void elf::scanRelocations<ELF32BE>(InputSectionBase &);
 template void elf::scanRelocations<ELF64LE>(InputSectionBase &);
 template void elf::scanRelocations<ELF64BE>(InputSectionBase &);
 template void elf::reportUndefinedSymbols<ELF32LE>();
 template void elf::reportUndefinedSymbols<ELF32BE>();
 template void elf::reportUndefinedSymbols<ELF64LE>();
 template void elf::reportUndefinedSymbols<ELF64BE>();

lld/ELF/Symbols.h

public:
 
   uint64_t getVA(int64_t addend = 0) const;
 
   uint64_t getGotOffset() const;
   uint64_t getGotVA() const;
   uint64_t getGotPltOffset() const;
   uint64_t getGotPltVA() const;
   uint64_t getPltVA() const;
+  uint64_t getPltOffset() const;
   uint64_t getSize() const;
   OutputSection *getOutputSection() const;
 
   // The following two functions are used for symbol resolution.
   //
   // You are expected to call mergeProperties for all symbols in input
   // files so that attributes that are attached to names rather than
   // indivisual symbol (such as visibility) are merged together.

lld/ELF/Symbols.cpp

uint64_t Symbol::getPltVA() const {
   // While linking microMIPS code PLT code are always microMIPS
   // code. Set the less-significant bit to track that fact.
   // See detailed comment in the `getSymVA` function.
   if (config->emachine == EM_MIPS && isMicroMips())
     outVA |= 1;
   return outVA;
 }
 
+uint64_t Symbol::getPltOffset() const {
+  if (isInIplt)
+    return pltIndex * target->ipltEntrySize;
+  return target->pltHeaderSize + pltIndex * target->pltEntrySize;
+}
+
 uint64_t Symbol::getSize() const {
   if (const auto *dr = dyn_cast<Defined>(this))
     return dr->size;
   return cast<SharedSymbol>(this)->size;
 }
 
 OutputSection *Symbol::getOutputSection() const {
   if (auto *s = dyn_cast<Defined>(this)) {

lld/ELF/SyntheticSections.cpp

void RelocationBaseSection::finalizeContents() {
   // case.
   if (symTab && symTab->getParent())
     getParent()->link = symTab->getParent()->sectionIndex;
   else
     getParent()->link = 0;
 
   if (in.relaPlt == this) {
     getParent()->flags |= ELF::SHF_INFO_LINK;
+    if (target->needsGotPlt)
       getParent()->info = in.gotPlt->getParent()->sectionIndex;
+    else
+      getParent()->info = in.plt->getParent()->sectionIndex;
   }
   if (in.relaIplt == this) {
     getParent()->flags |= ELF::SHF_INFO_LINK;
+    if (target->needsGotPlt)
       getParent()->info = in.igotPlt->getParent()->sectionIndex;
+    else
+      getParent()->info = in.iplt->getParent()->sectionIndex;
   }
 }
 
 RelrBaseSection::RelrBaseSection()
     : SyntheticSection(SHF_ALLOC,
                        config->useAndroidRelrTags ? SHT_ANDROID_RELR : SHT_RELR,
                        config->wordsize, ".relr.dyn") {}
 

 }
 
 IpltSection::IpltSection()
     : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 16, ".iplt") {
   if (config->emachine == EM_PPC || config->emachine == EM_PPC64) {
     name = ".glink";
     alignment = 4;
   }
+
+  // The PLT needs to be writable on SPARC as the dynamic linker will
+  // modify the instructions in the PLT entries.
+  if (config->emachine == EM_SPARCV9)
+    this->flags |= SHF_WRITE;
 }
 
 void IpltSection::writeTo(uint8_t *buf) {
   uint32_t off = 0;
   for (const Symbol *sym : entries) {
     target->writeIplt(buf + off, *sym, getVA() + off);
     off += target->ipltEntrySize;
   }

lld/ELF/Target.h

public:
 
   // At least on x86_64 positions 1 and 2 are used by the first plt entry
   // to support lazy loading.
   unsigned gotPltHeaderEntriesNum = 3;
 
   // On PPC ELF V2 abi, the first entry in the .got is the .TOC.
   unsigned gotHeaderEntriesNum = 0;
 
+  bool needsGotPlt = true;
+
   bool needsThunks = false;
 
   // A 4-byte field corresponding to one or more trap instructions, used to pad
   // executable OutputSections.
   std::array<uint8_t, 4> trapInstr;
 
   // Stores the NOP instructions of different sizes for the target and is used
   // to pad sections that are relaxed.
   llvm::Optional<std::vector<std::vector<uint8_t>>> nopInstrs;
 
   // If a target needs to rewrite calls to __morestack to instead call
   // __morestack_non_split when a split-stack enabled caller calls a
   // non-split-stack callee this will return true. Otherwise returns false.
   bool needsMoreStackNonSplit = true;
 
   virtual RelExpr adjustTlsExpr(RelType type, RelExpr expr) const;
   virtual RelExpr adjustGotPcExpr(RelType type, int64_t addend,
                                   const uint8_t *loc) const;
+  virtual RelExpr adjustGotOffExpr(RelType type, const Symbol &sym,
+                                   int64_t addend, const uint8_t *loc) const;
   virtual void relaxGot(uint8_t *loc, const Relocation &rel,
                         uint64_t val) const;
   virtual void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
                               uint64_t val) const;
   virtual void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
                               uint64_t val) const;
   virtual void relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
                               uint64_t val) const;

lld/ELF/Target.cpp

RelExpr TargetInfo::adjustTlsExpr(RelType type, RelExpr expr) const {
   return expr;
 }
 
 RelExpr TargetInfo::adjustGotPcExpr(RelType type, int64_t addend,
                                     const uint8_t *data) const {
   return R_GOT_PC;
 }
 
+RelExpr TargetInfo::adjustGotOffExpr(RelType type, const Symbol &sym,
+                                     int64_t addend,
+                                     const uint8_t *data) const {
+  return R_GOT_OFF;
+}
+
 void TargetInfo::relaxGot(uint8_t *loc, const Relocation &rel,
                           uint64_t val) const {
   llvm_unreachable("Should not have claimed to be relaxable");
 }
 
 void TargetInfo::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel,
                                 uint64_t val) const {
   llvm_unreachable("Should not have claimed to be relaxable");

lld/test/ELF/sparcv9-reloc-got.s

+# REQUIRES: sparc
+# RUN: llvm-mc -filetype=obj -triple=sparcv9 %s -o %t.o
+# RUN: ld.lld -shared %t.o -o %t.so
+# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s
+# RUN: llvm-readobj -r %t.so | FileCheck --check-prefix=RELOC %s
+
+# 13-bit PIC
+
+# CHECK: ldx [%l7+8], %o0
+ldx [%l7 + %got13(x)], %o0
+
+# 32-bit PIC
+
+# CHECK-NEXT: sethi 0, %o1
+# CHECK-NEXT: add %o1, 16, %o1
+# CHECK-NEXT: ldx [%l7+%o1], %o0
+sethi %got22(y), %o1
+add %o1, %got10(y), %o1
+ldx [%l7 + %o1], %o0
+
+# RELOC: .rela.dyn {
+# RELOC-NEXT: R_SPARC_GLOB_DAT x 0x0
+# RELOC-NEXT: R_SPARC_GLOB_DAT y 0x0
+# RELOC-NEXT: }