[RISCV][test] Add new tests of or/xor in the zbs extension

[jrtc27]

llvm/test/CodeGen/RISCV/rv32zbs.ll

805

Everything should always be optimised, but you mean a specific optimisation doesn't apply

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

122 ↗

(On Diff #346777)

What if bit 11 is the most significant set bit. We can use BSETI/BINVI for it and leave bits 10:0 for the ORI/XORI

130 ↗

(On Diff #346777)

I think it's ok to use isPowerOf2_64 even for RV32. I was zero extended so the upper bits are 0.

[benshi001]

llvm/test/CodeGen/RISCV/rv32zbs.ll

805

This patch will show how

lui r1, xxx
addi r1, r1, yyy
or r0, r0, r1

will be optimized to

ori r0, r0, zzz
bseti r0, 11
bseti r0, hi

An extra register is saved.

[craig.topper]

Did you mean to replace the previous patch with new tests?

llvm/test/CodeGen/RISCV/rv32zbs.ll

805

I think @jrtc27 means the comment should be understandable by someone in the future without needing to know about a specific patch/commit.

[jrtc27]

llvm/test/CodeGen/RISCV/rv32zbs.ll

805

Yes, the comment is complete nonsense when you read the file, it only makes some amount of sense when looking specifically at this diff, but even then is not the best way to express that.

[benshi001]

In D102854#2772576, @craig.topper wrote:

Did you mean to replace the previous patch with new tests?

Sorry. I mean to replace the previous patch with new tests. And I will submit the optimization patch later.

llvm/test/CodeGen/RISCV/rv32zbs.ll

805

I see. I will pay attention my way in the future.

llvm/test/CodeGen/RISCV/rv32zbs.ll

 ; RV32IBS-NEXT:    lui a1, 16
 ; RV32IBS-NEXT:    addi a1, a1, 1365
 ; RV32IBS-NEXT:    xor a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %xor = xor i32 %a, 66901
   ret i32 %xor
 }
 
+define i32 @xor_i32_6147(i32 %a) nounwind {
+; RV32I-LABEL: xor_i32_6147:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 2
+; RV32I-NEXT:    addi a1, a1, -2045
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: xor_i32_6147:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 2
+; RV32IB-NEXT:    addi a1, a1, -2045
+; RV32IB-NEXT:    xor a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: xor_i32_6147:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 2
+; RV32IBS-NEXT:    addi a1, a1, -2045
+; RV32IBS-NEXT:    xor a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %xor = xor i32 %a, 6147
+  ret i32 %xor
+}
+
 define i32 @or_i32_4098(i32 %a) nounwind {
 ; RV32I-LABEL: or_i32_4098:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;

 ; RV32IBS:       # %bb.0:
 ; RV32IBS-NEXT:    lui a1, 16
 ; RV32IBS-NEXT:    addi a1, a1, 1365
 ; RV32IBS-NEXT:    or a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %or = or i32 %a, 66901
   ret i32 %or
 }
+
+define i32 @or_i32_6147(i32 %a) nounwind {
+; RV32I-LABEL: or_i32_6147:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 2
+; RV32I-NEXT:    addi a1, a1, -2045
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: or_i32_6147:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 2
+; RV32IB-NEXT:    addi a1, a1, -2045
+; RV32IB-NEXT:    or a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: or_i32_6147:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 2
+; RV32IBS-NEXT:    addi a1, a1, -2045
+; RV32IBS-NEXT:    or a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %or = or i32 %a, 6147
+  ret i32 %or
+}

llvm/test/CodeGen/RISCV/rv64zbs.ll

 ; RV64IBS-NEXT:    lui a1, 16
 ; RV64IBS-NEXT:    addiw a1, a1, 1365
 ; RV64IBS-NEXT:    xor a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %xor = xor i64 %a, 66901
   ret i64 %xor
 }
 
+define i64 @xor_i64_6147(i64 %a) nounwind {
+; RV64I-LABEL: xor_i64_6147:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 2
+; RV64I-NEXT:    addiw a1, a1, -2045
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: xor_i64_6147:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 2
+; RV64IB-NEXT:    addiw a1, a1, -2045
+; RV64IB-NEXT:    xor a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: xor_i64_6147:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 2
+; RV64IBS-NEXT:    addiw a1, a1, -2045
+; RV64IBS-NEXT:    xor a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %xor = xor i64 %a, 6147
+  ret i64 %xor
+}
+
 define i64 @or_i64_4099(i64 %a) nounwind {
 ; RV64I-LABEL: or_i64_4099:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, 3
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;

 ; RV64IBS:       # %bb.0:
 ; RV64IBS-NEXT:    lui a1, 16
 ; RV64IBS-NEXT:    addiw a1, a1, 1365
 ; RV64IBS-NEXT:    or a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %or = or i64 %a, 66901
   ret i64 %or
 }
+
+define i64 @or_i64_6147(i64 %a) nounwind {
+; RV64I-LABEL: or_i64_6147:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 2
+; RV64I-NEXT:    addiw a1, a1, -2045
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: or_i64_6147:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 2
+; RV64IB-NEXT:    addiw a1, a1, -2045
+; RV64IB-NEXT:    or a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: or_i64_6147:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 2
+; RV64IBS-NEXT:    addiw a1, a1, -2045
+; RV64IBS-NEXT:    or a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %xor = or i64 %a, 6147
+  ret i64 %xor
+}