[SPARC][MC] Support more relocation types

[LemonBoy]

Summary

This patch introduces support for %hix, %lox, %gdop_hix22, %gdop_lox10 and %gdop.

An extra test is introduced to make sure the fixups are correctly applied.

[jrtc27]

llvm/test/MC/Sparc/sparc-relocations.s

84

Hm, if I understand correctly, this parses fine despite ld only taking one memory operand and one destination register because TLS_LDrr matches this case as we just have def TLSSym : Operand<iPTR>;. That should probably be cleaned up as part of this (possibly split out into a separate patch depending on the route you take).

[jrtc27]

llvm/test/MC/Sparc/sparc-relocations.s

74

Although it technically doesn't matter for the test, we should use xor as that's what these relocations are to be used with.

84

Should probably also be ldx given this is 64-bit code, which leads me to conclude that we don't actually have the TableGen definitions for parsing 64-bit TLS ldx either, only 32-bit ld (ie lduw)?

[LemonBoy]

llvm/test/MC/Sparc/sparc-relocations.s

84

I tried to keep the file v8-compatible. Using ldx works because of the TLS_LDXrr pattern, I'll use that over ld if you prefer.

Cleaning the parser is IMO orthogonal to the relocation work, beside the misleading name of the tablegen class it does work as expected.

[jrtc27]

llvm/test/MC/Sparc/sparc-relocations.s

84

I prefer to not have tests that test things that shouldn't be working but do due to historical accidents. Currently the parser accepts more than it should, but all valid input we claim to support is parsed in a sensible way. This diff changes that so valid input is no longer parsed in a sensible way.

Arguably %gdop should be rejected on anything other than a pointer load (though binutils allows it on _any_ load, not that we should start adding more pseudos so _that_ works IMO, but I would be tempted to predicate TLS_LDrr, and a future GDOP one, on Is32Bit), and I don't want to have an example that's wrong. So yes, please change it to sensible code. Thanks for pointing out TLS_LDXrr, somehow I'd managed to miss that.

[LemonBoy]

Distinguish %gdop and TLS-relocations applied to ld and ldx at parser level.

[jrtc27]

Is "tail reloc" a standard term for this? Seems like that could be confused with the notion of tail calls...

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

863

Make this an enum class (and pass it as a string in TableGen rather than an int)

895–896

These want to be separate kinds so you can stop people using %tie_ld with ldx

llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

109

Give it a capital first letter as you're touching the code

llvm/lib/Target/Sparc/SparcISelLowering.h

51

Line up with the others?

llvm/lib/Target/Sparc/SparcInstrInfo.td

1381

Doesn't belong under TLS

[LemonBoy]

Is "tail reloc" a standard term for this?

Not really, the operand matches relocation operands in tail position hence the name. I'm open to suggestions.

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

863

Will do, I can see that having the Kind as bare numbers can be confusing.

895–896

The idea is to perform only a minimum amount of parsing + backtracking in the parser, this kind of check is better suited to a validateInstruction hook as many other targets do.

llvm/lib/Target/Sparc/SparcInstrInfo.td

1381

Oh well, I completely missed the ASCII-art header. I'll move it.

[LemonBoy]

Address review comments.

[jrtc27]

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

57

Load isn't a great name given there's Load_TLS. Should say GOT or similar in it.

1521

This should be followed

[LemonBoy]

Address review comments.

[LemonBoy]

Ping

[brad]

ping

[dcederman]

This looks good to me. Maybe change TailRelocSym to TailOpRelocSym or TailOperandRelocSym to make it more clear that it refers to the tail operand?

[brad]

ping.

[brad]

LemonBoy?

[brad]

ping.

[brad]

LemonBoy seems to have disappeared for the time being. Anyway of moving this forward?

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

 
 namespace {
 
 class SparcOperand;
 
 class SparcAsmParser : public MCTargetAsmParser {
   MCAsmParser &Parser;
 
   /// @name Auto-generated Match Functions
   /// {
 
 #define GET_ASSEMBLER_HEADER
 #include "SparcGenAsmMatcher.inc"
 
   /// }
 
   // public interface of the MCTargetAsmParser.
#include "SparcGenAsmMatcher.inc"
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   // Custom parse functions for Sparc specific operands.
   OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
 
   OperandMatchResultTy parseMembarTag(OperandVector &Operands);
 
+  template <unsigned Kind>
+  OperandMatchResultTy parseTailRelocSym(OperandVector &Operands);
+
   template <unsigned N>
   OperandMatchResultTy parseShiftAmtImm(OperandVector &Operands);
 
   OperandMatchResultTy parseCallTarget(OperandVector &Operands);
 
   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
 
   OperandMatchResultTy
#include "SparcGenAsmMatcher.inc"
 
   bool is64Bit() const {
     return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
   }
 
   bool expandSET(MCInst &Inst, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
+  SMLoc getLoc() const { return getParser().getTok().getLoc(); }
+
 public:
   SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
                 const MCInstrInfo &MII,
                 const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
     Parser.addAliasForDirective(".half", ".2byte");
     Parser.addAliasForDirective(".uahalf", ".2byte");
     Parser.addAliasForDirective(".word", ".4byte");
public:
 
   bool isToken() const override { return Kind == k_Token; }
   bool isReg() const override { return Kind == k_Register; }
   bool isImm() const override { return Kind == k_Immediate; }
   bool isMem() const override { return isMEMrr() || isMEMri(); }
   bool isMEMrr() const { return Kind == k_MemoryReg; }
   bool isMEMri() const { return Kind == k_MemoryImm; }
   bool isMembarTag() const { return Kind == k_Immediate; }
+  bool isTailRelocSym() const { return Kind == k_Immediate; }
 
   bool isCallTarget() const {
     if (!isImm())
       return false;
 
     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val))
       return CE->getValue() % 4 == 0;
 
void addMembarTagOperands(MCInst &Inst, unsigned N) const {
     addExpr(Inst, Expr);
   }
 
   void addCallTargetOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     addExpr(Inst, getImm());
   }
 
+  void addTailRelocSymOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    addExpr(Inst, getImm());
+  }
+
   static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
     auto Op = std::make_unique<SparcOperand>(k_Token);
     Op->Tok.Data = Str.data();
     Op->Tok.Length = Str.size();
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
if (!isUInt<N>(CE->getValue())) {
     Error(S, "immediate shift value out of range");
     return MatchOperand_ParseFail;
   }
 
   Operands.push_back(SparcOperand::CreateImm(Expr, S, E));
   return MatchOperand_Success;
 }
 
+template <unsigned Kind>
+OperandMatchResultTy SparcAsmParser::parseTailRelocSym(OperandVector &Operands) {
+  SMLoc S = getLoc();
+  SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
+
+  auto MatchesKind = [](SparcMCExpr::VariantKind VK) -> bool {
+    switch (Kind) {
+    case 0:
+      // Non-TLS relocations on ld (or ldx).
+      // ld [%rr + %rr], %rr, %rel(sym)
+      switch (VK) {
+        case SparcMCExpr::VK_Sparc_GOTDATA_OP:
+          return true;
+        default:
+          return false;
+      }
+    case 1:
+      // TLS relocations on add.
+      // add %rr, %rr, %rr, %rel(sym)
+      switch (VK) {
+        case SparcMCExpr::VK_Sparc_TLS_GD_ADD:
+        case SparcMCExpr::VK_Sparc_TLS_IE_ADD:
+        case SparcMCExpr::VK_Sparc_TLS_LDM_ADD:
+        case SparcMCExpr::VK_Sparc_TLS_LDO_ADD:
+          return true;
+        default:
+          return false;
+      }
+    case 2:
+      // TLS relocations on ld (or ldx).
+      // ld[x] %addr, %rr, %rel(sym)
+      switch (VK) {
+        case SparcMCExpr::VK_Sparc_TLS_IE_LD:
+        case SparcMCExpr::VK_Sparc_TLS_IE_LDX:
+          return true;
+        default:
+          return false;
+      }
+    case 3:
+      // TLS relocations on call.
+      // call sym, %rel(sym)
+      switch (VK) {
+        case SparcMCExpr::VK_Sparc_TLS_GD_CALL:
+        case SparcMCExpr::VK_Sparc_TLS_LDM_CALL:
+          return true;
+        default:
+          return false;
+      }
+    default:
+      llvm_unreachable("Unexpected kind parameter");
+    }
+  };
+
+  if (getLexer().getKind() != AsmToken::Percent) {
+    Error(getLoc(), "expected '%' for operand modifier");
+    return MatchOperand_ParseFail;
+  }
+
+  const AsmToken Tok = Parser.getTok();
+  getParser().Lex(); // Eat '%'
+
+  if (getLexer().getKind() != AsmToken::Identifier) {
+    Error(getLoc(), "expected valid identifier for operand modifier");
+    return MatchOperand_ParseFail;
+  }
+
+  StringRef Name = getParser().getTok().getIdentifier();
+  SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(Name);
+  if (VK == SparcMCExpr::VK_Sparc_None) {
+    Error(getLoc(), "invalid operand modifier");
+    return MatchOperand_ParseFail;
+  }
+
+  if (!MatchesKind(VK)) {
+    // Did not match the specified set of relocation types, put '%' back.
+    getLexer().UnLex(Tok);
+    return MatchOperand_NoMatch;
+  }
+
+  Parser.Lex(); // Eat the identifier.
+  if (getLexer().getKind() != AsmToken::LParen) {
+    Error(getLoc(), "expected '('");
+    return MatchOperand_ParseFail;
+  }
+
+  getParser().Lex(); // Eat '('
+  const MCExpr *SubExpr;
+  if (getParser().parseParenExpression(SubExpr, E)) {
+    return MatchOperand_ParseFail;
+  }
+
+  const MCExpr *Val = adjustPICRelocation(VK, SubExpr);
+  Operands.push_back(SparcOperand::CreateImm(Val, S, E));
+  return MatchOperand_Success;
+}
+
 OperandMatchResultTy SparcAsmParser::parseMembarTag(OperandVector &Operands) {
   SMLoc S = Parser.getTok().getLoc();
   const MCExpr *EVal;
   int64_t ImmVal = 0;
 
   std::unique_ptr<SparcOperand> Mask;
   if (parseSparcAsmOperand(Mask) == MatchOperand_Success) {
     if (!Mask->isImm() || !Mask->getImm()->evaluateAsAbsolute(ImmVal) ||
bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
 
   StringRef name = Tok.getString();
 
   SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
 
   if (VK == SparcMCExpr::VK_Sparc_None)
     return false;
 
   Parser.Lex(); // Eat the identifier.
   if (Parser.getTok().getKind() != AsmToken::LParen)
     return false;
 
   Parser.Lex(); // Eat the LParen token.
   const MCExpr *subExpr;
   if (Parser.parseParenExpression(subExpr, EndLoc))
     return false;
 

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

case Sparc::fixup_sparc_br19:
     return (Value >> 2) & 0x7ffff;
 
   case Sparc::fixup_sparc_br16_2:
     return (Value >> 2) & 0xc000;
 
   case Sparc::fixup_sparc_br16_14:
     return (Value >> 2) & 0x3fff;
 
+  case Sparc::fixup_sparc_hix22:
+    return (~Value >> 10) & 0x3fffff;
+
   case Sparc::fixup_sparc_pc22:
   case Sparc::fixup_sparc_got22:
   case Sparc::fixup_sparc_tls_gd_hi22:
   case Sparc::fixup_sparc_tls_ldm_hi22:
   case Sparc::fixup_sparc_tls_ie_hi22:
   case Sparc::fixup_sparc_hi22:
   case Sparc::fixup_sparc_lm:
     return (Value >> 10) & 0x3fffff;
 
   case Sparc::fixup_sparc_got13:
   case Sparc::fixup_sparc_13:
     return Value & 0x1fff;
 
+  case Sparc::fixup_sparc_lox10:
+    return (Value & 0x3ff) | 0x1c00;
+
   case Sparc::fixup_sparc_pc10:
   case Sparc::fixup_sparc_got10:
   case Sparc::fixup_sparc_tls_gd_lo10:
   case Sparc::fixup_sparc_tls_ldm_lo10:
   case Sparc::fixup_sparc_tls_ie_lo10:
   case Sparc::fixup_sparc_lo10:
     return Value & 0x3ff;
 
static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
   case Sparc::fixup_sparc_tls_gd_add:
   case Sparc::fixup_sparc_tls_gd_call:
   case Sparc::fixup_sparc_tls_ldm_add:
   case Sparc::fixup_sparc_tls_ldm_call:
   case Sparc::fixup_sparc_tls_ldo_add:
   case Sparc::fixup_sparc_tls_ie_ld:
   case Sparc::fixup_sparc_tls_ie_ldx:
   case Sparc::fixup_sparc_tls_ie_add:
+  case Sparc::fixup_sparc_gotdata_lox10:
+  case Sparc::fixup_sparc_gotdata_hix22:
+  case Sparc::fixup_sparc_gotdata_op:
     return 0;
   }
 }
 
 /// getFixupKindNumBytes - The number of bytes the fixup may change.
 static unsigned getFixupKindNumBytes(unsigned Kind) {
     switch (Kind) {
   default:
SparcAsmBackend(const Target &T)
           TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
 
     unsigned getNumFixupKinds() const override {
       return Sparc::NumTargetFixupKinds;
     }
 
     const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
       const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br19",      13,     19,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br16_2",    10,      2,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br16_14",   18,     14,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_13",        19,     13,  0 },
         { "fixup_sparc_hi22",      10,     22,  0 },
         { "fixup_sparc_lo10",      22,     10,  0 },
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
         { "fixup_sparc_tls_ldo_lox10", 22, 10,  0 },
         { "fixup_sparc_tls_ldo_add",    0,  0,  0 },
         { "fixup_sparc_tls_ie_hi22",   10, 22,  0 },
         { "fixup_sparc_tls_ie_lo10",   22, 10,  0 },
         { "fixup_sparc_tls_ie_ld",      0,  0,  0 },
         { "fixup_sparc_tls_ie_ldx",     0,  0,  0 },
         { "fixup_sparc_tls_ie_add",     0,  0,  0 },
         { "fixup_sparc_tls_le_hix22",   0,  0,  0 },
-        { "fixup_sparc_tls_le_lox10",   0,  0,  0 }
+        { "fixup_sparc_tls_le_lox10",   0,  0,  0 },
+        { "fixup_sparc_hix22",         10, 22,  0 },
+        { "fixup_sparc_lox10",         19, 13,  0 },
+        { "fixup_sparc_gotdata_hix22",  0,  0,  0 },
+        { "fixup_sparc_gotdata_lox10",  0,  0,  0 },
+        { "fixup_sparc_gotdata_op",     0,  0,  0 },
       };
 
       const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
         // name                    offset bits  flags
         { "fixup_sparc_call30",     0,     30,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br22",       0,     22,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br19",       0,     19,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br16_2",    20,      2,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_br16_14",    0,     14,  MCFixupKindInfo::FKF_IsPCRel },
         { "fixup_sparc_13",         0,     13,  0 },
         { "fixup_sparc_hi22",       0,     22,  0 },
         { "fixup_sparc_lo10",       0,     10,  0 },
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
         { "fixup_sparc_tls_ldo_lox10",  0, 10,  0 },
         { "fixup_sparc_tls_ldo_add",    0,  0,  0 },
         { "fixup_sparc_tls_ie_hi22",    0, 22,  0 },
         { "fixup_sparc_tls_ie_lo10",    0, 10,  0 },
         { "fixup_sparc_tls_ie_ld",      0,  0,  0 },
         { "fixup_sparc_tls_ie_ldx",     0,  0,  0 },
         { "fixup_sparc_tls_ie_add",     0,  0,  0 },
         { "fixup_sparc_tls_le_hix22",   0,  0,  0 },
-        { "fixup_sparc_tls_le_lox10",   0,  0,  0 }
+        { "fixup_sparc_tls_le_lox10",   0,  0,  0 },
+        { "fixup_sparc_hix22",          0, 22,  0 },
+        { "fixup_sparc_lox10",          0, 13,  0 },
+        { "fixup_sparc_gotdata_hix22",  0,  0,  0 },
+        { "fixup_sparc_gotdata_lox10",  0,  0,  0 },
+        { "fixup_sparc_gotdata_op",     0,  0,  0 },
       };
 
       if (Kind < FirstTargetFixupKind)
         return MCAsmBackend::getFixupKindInfo(Kind);
 
       assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
              "Invalid kind!");
       if (Endian == support::little)

llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp

unsigned SparcELFObjectWriter::getRelocType(MCContext &Ctx,
   case Sparc::fixup_sparc_tls_ldo_add:   return ELF::R_SPARC_TLS_LDO_ADD;
   case Sparc::fixup_sparc_tls_ie_hi22:   return ELF::R_SPARC_TLS_IE_HI22;
   case Sparc::fixup_sparc_tls_ie_lo10:   return ELF::R_SPARC_TLS_IE_LO10;
   case Sparc::fixup_sparc_tls_ie_ld:     return ELF::R_SPARC_TLS_IE_LD;
   case Sparc::fixup_sparc_tls_ie_ldx:    return ELF::R_SPARC_TLS_IE_LDX;
   case Sparc::fixup_sparc_tls_ie_add:    return ELF::R_SPARC_TLS_IE_ADD;
   case Sparc::fixup_sparc_tls_le_hix22:  return ELF::R_SPARC_TLS_LE_HIX22;
   case Sparc::fixup_sparc_tls_le_lox10:  return ELF::R_SPARC_TLS_LE_LOX10;
+  case Sparc::fixup_sparc_hix22:         return ELF::R_SPARC_HIX22;
+  case Sparc::fixup_sparc_lox10:         return ELF::R_SPARC_LOX10;
+  case Sparc::fixup_sparc_gotdata_hix22: return ELF::R_SPARC_GOTDATA_HIX22;
+  case Sparc::fixup_sparc_gotdata_lox10: return ELF::R_SPARC_GOTDATA_LOX10;
+  case Sparc::fixup_sparc_gotdata_op:    return ELF::R_SPARC_GOTDATA_OP;
   }
 
   return ELF::R_SPARC_NONE;
 }
 
 bool SparcELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym,
                                                  unsigned Type) const {
   switch (Type) {

llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h

 //===-- SparcFixupKinds.h - Sparc Specific Fixup Entries --------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCFIXUPKINDS_H
 #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCFIXUPKINDS_H
 
 #include "llvm/MC/MCFixup.h"
 
 namespace llvm {
   namespace Sparc {
     enum Fixups {
       // fixup_sparc_call30 - 30-bit PC relative relocation for call
       fixup_sparc_call30 = FirstTargetFixupKind,
 
       /// fixup_sparc_br22 - 22-bit PC relative relocation for
       /// branches
       fixup_sparc_br22,
 
       /// fixup_sparc_br19 - 19-bit PC relative relocation for
enum Fixups {
       fixup_sparc_tls_ie_hi22,
       fixup_sparc_tls_ie_lo10,
       fixup_sparc_tls_ie_ld,
       fixup_sparc_tls_ie_ldx,
       fixup_sparc_tls_ie_add,
       fixup_sparc_tls_le_hix22,
       fixup_sparc_tls_le_lox10,
 
+      /// 22-bit fixup corresponding to %hix(foo)
+      fixup_sparc_hix22,
+      /// 13-bit fixup corresponding to %lox(foo)
+      fixup_sparc_lox10,
+
+      /// 22-bit fixup corresponding to %gdop_hix22(foo)
+      fixup_sparc_gotdata_hix22,
+      /// 13-bit fixup corresponding to %gdop_lox10(foo)
+      fixup_sparc_gotdata_lox10,
+      /// 32-bit fixup corresponding to %gdop(foo)
+      fixup_sparc_gotdata_op,
+
       // Marker
       LastTargetFixupKind,
       NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
     };
   }
 }
 
 #endif

llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                            const MCSubtargetInfo &STI) const {
   verifyInstructionPredicates(MI,
                               computeAvailableFeatures(STI.getFeatureBits()));
 
   unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
   support::endian::write(OS, Bits,
                          Ctx.getAsmInfo()->isLittleEndian() ? support::little
                                                             : support::big);
-  unsigned tlsOpNo = 0;
+
+  // Some instructions have phantom operands that only contribute a fixup entry.
+  unsigned symOpNo = 0;
   switch (MI.getOpcode()) {
   default: break;
-  case SP::TLS_CALL:   tlsOpNo = 1; break;
+  case SP::TLS_CALL:   symOpNo = 1; break;
+  case SP::GDOP_LDrr:
+  case SP::GDOP_LDXrr:
   case SP::TLS_ADDrr:
   case SP::TLS_ADDXrr:
   case SP::TLS_LDrr:
-  case SP::TLS_LDXrr:  tlsOpNo = 3; break;
+  case SP::TLS_LDXrr:  symOpNo = 3; break;
   }
-  if (tlsOpNo != 0) {
-    const MCOperand &MO = MI.getOperand(tlsOpNo);
+  if (symOpNo != 0) {
+    const MCOperand &MO = MI.getOperand(symOpNo);
     uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
     assert(op == 0 && "Unexpected operand value!");
     (void)op; // suppress warning.
   }
 
   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
 }
 

llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h

enum VariantKind {
     VK_Sparc_TLS_LDO_LOX10,
     VK_Sparc_TLS_LDO_ADD,
     VK_Sparc_TLS_IE_HI22,
     VK_Sparc_TLS_IE_LO10,
     VK_Sparc_TLS_IE_LD,
     VK_Sparc_TLS_IE_LDX,
     VK_Sparc_TLS_IE_ADD,
     VK_Sparc_TLS_LE_HIX22,
-    VK_Sparc_TLS_LE_LOX10
+    VK_Sparc_TLS_LE_LOX10,
+    VK_Sparc_HIX22,
+    VK_Sparc_LOX10,
+    VK_Sparc_GOTDATA_HIX22,
+    VK_Sparc_GOTDATA_LOX10,
+    VK_Sparc_GOTDATA_OP,
   };
 
 private:
   const VariantKind Kind;
   const MCExpr *Expr;
 
   explicit SparcMCExpr(VariantKind Kind, const MCExpr *Expr)
       : Kind(Kind), Expr(Expr) {}

llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp

bool SparcMCExpr::printVariantKind(raw_ostream &OS, VariantKind Kind)
   case VK_Sparc_TLS_LDO_ADD:   OS << "%tldo_add(";   return true;
   case VK_Sparc_TLS_IE_HI22:   OS << "%tie_hi22(";   return true;
   case VK_Sparc_TLS_IE_LO10:   OS << "%tie_lo10(";   return true;
   case VK_Sparc_TLS_IE_LD:     OS << "%tie_ld(";     return true;
   case VK_Sparc_TLS_IE_LDX:    OS << "%tie_ldx(";    return true;
   case VK_Sparc_TLS_IE_ADD:    OS << "%tie_add(";    return true;
   case VK_Sparc_TLS_LE_HIX22:  OS << "%tle_hix22(";  return true;
   case VK_Sparc_TLS_LE_LOX10:  OS << "%tle_lox10(";  return true;
+  case VK_Sparc_HIX22:         OS << "%hix(";        return true;
+  case VK_Sparc_LOX10:         OS << "%lox(";        return true;
+  case VK_Sparc_GOTDATA_HIX22: OS << "%gdop_hix22("; return true;
+  case VK_Sparc_GOTDATA_LOX10: OS << "%gdop_lox10("; return true;
+  case VK_Sparc_GOTDATA_OP:    OS << "%gdop(";       return true;
   }
   llvm_unreachable("Unhandled SparcMCExpr::VariantKind");
 }
 
 SparcMCExpr::VariantKind SparcMCExpr::parseVariantKind(StringRef name)
 {
   return StringSwitch<SparcMCExpr::VariantKind>(name)
     .Case("lo",  VK_Sparc_LO)
     .Case("hi",  VK_Sparc_HI)
     .Case("h44", VK_Sparc_H44)
     .Case("m44", VK_Sparc_M44)
     .Case("l44", VK_Sparc_L44)
     .Case("hh",  VK_Sparc_HH)
     .Case("hm",  VK_Sparc_HM)
     .Case("lm",  VK_Sparc_LM)
     .Case("pc22",  VK_Sparc_PC22)
return StringSwitch<SparcMCExpr::VariantKind>(name)
     .Case("tldo_add",   VK_Sparc_TLS_LDO_ADD)
     .Case("tie_hi22",   VK_Sparc_TLS_IE_HI22)
     .Case("tie_lo10",   VK_Sparc_TLS_IE_LO10)
     .Case("tie_ld",     VK_Sparc_TLS_IE_LD)
     .Case("tie_ldx",    VK_Sparc_TLS_IE_LDX)
     .Case("tie_add",    VK_Sparc_TLS_IE_ADD)
     .Case("tle_hix22",  VK_Sparc_TLS_LE_HIX22)
     .Case("tle_lox10",  VK_Sparc_TLS_LE_LOX10)
+    .Case("hix",        VK_Sparc_HIX22)
+    .Case("lox",        VK_Sparc_LOX10)
+    .Case("gdop_hix22", VK_Sparc_GOTDATA_HIX22)
+    .Case("gdop_lox10", VK_Sparc_GOTDATA_LOX10)
+    .Case("gdop",       VK_Sparc_GOTDATA_OP)
     .Default(VK_Sparc_None);
 }
 
 Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) {
   switch (Kind) {
   default: llvm_unreachable("Unhandled SparcMCExpr::VariantKind");
   case VK_Sparc_LO:       return Sparc::fixup_sparc_lo10;
   case VK_Sparc_HI:       return Sparc::fixup_sparc_hi22;
Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) {
   case VK_Sparc_TLS_LDO_ADD:   return Sparc::fixup_sparc_tls_ldo_add;
   case VK_Sparc_TLS_IE_HI22:   return Sparc::fixup_sparc_tls_ie_hi22;
   case VK_Sparc_TLS_IE_LO10:   return Sparc::fixup_sparc_tls_ie_lo10;
   case VK_Sparc_TLS_IE_LD:     return Sparc::fixup_sparc_tls_ie_ld;
   case VK_Sparc_TLS_IE_LDX:    return Sparc::fixup_sparc_tls_ie_ldx;
   case VK_Sparc_TLS_IE_ADD:    return Sparc::fixup_sparc_tls_ie_add;
   case VK_Sparc_TLS_LE_HIX22:  return Sparc::fixup_sparc_tls_le_hix22;
   case VK_Sparc_TLS_LE_LOX10:  return Sparc::fixup_sparc_tls_le_lox10;
+  case VK_Sparc_HIX22:         return Sparc::fixup_sparc_hix22;
+  case VK_Sparc_LOX10:         return Sparc::fixup_sparc_lox10;
+  case VK_Sparc_GOTDATA_HIX22: return Sparc::fixup_sparc_gotdata_hix22;
+  case VK_Sparc_GOTDATA_LOX10: return Sparc::fixup_sparc_gotdata_lox10;
+  case VK_Sparc_GOTDATA_OP:    return Sparc::fixup_sparc_gotdata_op;
   }
 }
 
 bool
 SparcMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
                                        const MCAsmLayout *Layout,
                                        const MCFixup *Fixup) const {
   return getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup);

llvm/lib/Target/Sparc/SparcISelLowering.h

 
 #include "Sparc.h"
 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {
   class SparcSubtarget;
 
   namespace SPISD {
     enum NodeType : unsigned {
       FIRST_NUMBER = ISD::BUILTIN_OP_END,
       CMPICC,      // Compare two GPR operands, set icc+xcc.
       CMPFCC,      // Compare two FP operands, set fcc.
       BRICC,       // Branch to dest on icc condition
       BRXCC,       // Branch to dest on xcc condition (64-bit only).
       BRFCC,       // Branch to dest on fcc condition
       SELECT_ICC,  // Select between two values using the current ICC flags.
       SELECT_XCC,  // Select between two values using the current XCC flags.
       SELECT_FCC,  // Select between two values using the current FCC flags.
 
       Hi, Lo,      // Hi/Lo operations, typically on a global address.
 
       FTOI,        // FP to Int within a FP register.
       ITOF,        // Int to FP within a FP register.
       FTOX,        // FP to Int64 within a FP register.
       XTOF,        // Int64 to FP within a FP register.
 
       CALL,        // A call instruction.
       RET_FLAG,    // Return with a flag operand.
       GLOBAL_BASE_REG, // Global base reg for PIC.
       FLUSHW,      // FLUSH register windows to stack.
 
       TLS_ADD,     // For Thread Local Storage (TLS).
       TLS_LD,
-      TLS_CALL
+      TLS_CALL,
+
+      LOAD_GDOP, // Load operation w/ gdop relocation.
     };
   }
 
   class SparcTargetLowering : public TargetLowering {
     const SparcSubtarget *Subtarget;
   public:
     SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

llvm/lib/Target/Sparc/SparcISelLowering.cpp

const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case SPISD::XTOF:            return "SPISD::XTOF";
   case SPISD::CALL:            return "SPISD::CALL";
   case SPISD::RET_FLAG:        return "SPISD::RET_FLAG";
   case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
   case SPISD::FLUSHW:          return "SPISD::FLUSHW";
   case SPISD::TLS_ADD:         return "SPISD::TLS_ADD";
   case SPISD::TLS_LD:          return "SPISD::TLS_LD";
   case SPISD::TLS_CALL:        return "SPISD::TLS_CALL";
+  case SPISD::LOAD_GDOP:       return "SPISD::LOAD_GDOP";
   }
   return nullptr;
 }
 
 EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
                                             EVT VT) const {
   if (!VT.isVector())
     return MVT::i32;

llvm/lib/Target/Sparc/SparcInstr64Bit.td

def XNORXrr  : F3_1<2, 0b000111,
                    (outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
                    "xnor $b, $c, $dst",
                    [(set i64:$dst, (not (xor i64:$b, i64:$c)))]>;
 
 defm ADDX    : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>;
 defm SUBX    : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>;
 
 def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
-                   (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
+                   (ins I64Regs:$rs1, I64Regs:$rs2, TailRelocSymTLSAdd:$sym),
                    "add $rs1, $rs2, $rd, $sym",
                    [(set i64:$rd,
                        (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
 
 // "LEA" form of add
 def LEAX_ADDri : F3_2<2, 0b000000,
                      (outs I64Regs:$dst), (ins MEMri:$addr),
                      "add ${addr:arith}, $dst",

 // SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
 
 let Predicates = [Is64Bit] in {
 
 // 64-bit loads.
 let DecoderMethod = "DecodeLoadInt" in
   defm LDX   : Load<"ldx", 0b001011, load, I64Regs, i64>;
 
-let mayLoad = 1, isAsmParserOnly = 1 in
+let mayLoad = 1, isAsmParserOnly = 1 in {
   def TLS_LDXrr : F3_1<3, 0b001011,
-                       (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
+                       (outs IntRegs:$dst),
+                       (ins MEMrr:$addr, TailRelocSymTLSLoad:$sym),
                        "ldx [$addr], $dst, $sym",
                        [(set i64:$dst,
                            (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
+  def GDOP_LDXrr : F3_1<3, 0b001011,
+                       (outs I64Regs:$dst),
+                       (ins MEMrr:$addr, TailRelocSymLoad:$sym),
+                       "ldx [$addr], $dst, $sym",
+                       [(set i64:$dst,
+                           (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>;
+}
 
 // Extending loads to i64.
 def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
 def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
 def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
 def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
 
 def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;

llvm/lib/Target/Sparc/SparcInstrInfo.td

def MEMrr : Operand<iPTR> {
   let ParserMatchClass = SparcMEMrrAsmOperand;
 }
 def MEMri : Operand<iPTR> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops ptr_rc, i32imm);
   let ParserMatchClass = SparcMEMriAsmOperand;
 }
 
-def TLSSym : Operand<iPTR>;
+// Represents a tail relocation operand for instructions such as add, ld, call.
+class SparcTailRelocSymAsmOperand<int Kind> : AsmOperandClass {
+  let Name = "TailRelocSym" # Kind;
+  let RenderMethod = "addTailRelocSymOperands";
+  let PredicateMethod = "isTailRelocSym";
+  let ParserMethod = "parseTailRelocSym<" # Kind # ">";
+}
+
+def TailRelocSymLoad : Operand<iPTR> {
+  let ParserMatchClass = SparcTailRelocSymAsmOperand<0>;
+}
+
+def TailRelocSymTLSAdd : Operand<iPTR> {
+  let ParserMatchClass = SparcTailRelocSymAsmOperand<1>;
+}
+
+def TailRelocSymTLSLoad : Operand<iPTR> {
+  let ParserMatchClass = SparcTailRelocSymAsmOperand<2>;
+}
+
+def TailRelocSymTLSCall : Operand<iPTR> {
+  let ParserMatchClass = SparcTailRelocSymAsmOperand<3>;
+}
 
 def SparcMembarTagAsmOperand : AsmOperandClass {
   let Name = "MembarTag";
   let ParserMethod = "parseMembarTag";
 }
 
 def MembarTag : Operand<i32> {
   let PrintMethod = "printMembarTag";

 def SDTSPXTOF :
 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
 
 def SDTSPtlsadd :
 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
 def SDTSPtlsld :
 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
 
+def SDTSPloadgdop :
+SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
+
 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
 
 def SPhi    : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
 def SPlo    : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
def flushw        : SDNode<"SPISD::FLUSHW", SDTNone,
                            [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
 
 def tlsadd        : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
 def tlsld         : SDNode<"SPISD::TLS_LD",  SDTSPtlsld>;
 def tlscall       : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
                             [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                              SDNPVariadic]>;
 
+def load_gdop : SDNode<"SPISD::LOAD_GDOP",  SDTSPloadgdop>;
+
 def getPCX        : Operand<iPTR> {
   let PrintMethod = "printGetPCX";
 }
 
 //===----------------------------------------------------------------------===//
 // SPARC Flag Conditions
 //===----------------------------------------------------------------------===//
 

 }
 
 //===----------------------------------------------------------------------===//
 // Instructions for Thread Local Storage(TLS).
 //===----------------------------------------------------------------------===//
 let isAsmParserOnly = 1 in {
 def TLS_ADDrr : F3_1<2, 0b000000,
                     (outs IntRegs:$rd),
-                    (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
+                    (ins IntRegs:$rs1, IntRegs:$rs2, TailRelocSymTLSAdd:$sym),
                     "add $rs1, $rs2, $rd, $sym",
                     [(set i32:$rd,
                         (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
 
-let mayLoad = 1 in
+let mayLoad = 1 in {
   def TLS_LDrr : F3_1<3, 0b000000,
-                      (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
+                      (outs IntRegs:$dst),
+                      (ins MEMrr:$addr, TailRelocSymTLSLoad:$sym),
                       "ld [$addr], $dst, $sym",
                       [(set i32:$dst,
                           (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
+  def GDOP_LDrr : F3_1<3, 0b000000,
+                      (outs IntRegs:$dst),
+                      (ins MEMrr:$addr, TailRelocSymLoad:$sym),
+                      "ld [$addr], $dst, $sym",
+                      [(set i32:$dst,
+                          (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>;
+}
 
 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
   def TLS_CALL : InstSP<(outs),
-                        (ins calltarget:$disp, TLSSym:$sym, variable_ops),
+                        (ins calltarget:$disp, TailRelocSymTLSCall:$sym,
+                         variable_ops),
                         "call $disp, $sym",
                         [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)],
                         IIC_jmp_or_call> {
   bits<30> disp;
   let op = 1;
   let Inst{29-0} = disp;
 }
 }

llvm/test/MC/Sparc/sparc-fixups.s

+! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-objdump -dr - | FileCheck %s
+.text
+
+! Check that fixups are correctly applied.
+
+.set sym, 0xfedcba98
+
+! CHECK: sethi 4175662, %o0
+sethi %hi(sym), %o0
+! CHECK: xor %o0, 664, %o0
+xor %o0, %lo(sym), %o0
+
+! CHECK: sethi 1019, %o0
+sethi %h44(sym), %o0
+! CHECK: or %o0, 459, %o0
+or %o0, %m44(sym), %o0
+! CHECK: ld [%o0+2712], %o0
+ld [%o0 + %l44(sym)], %o0
+
+! CHECK: sethi 0, %o0
+sethi %hh(sym), %o0
+! CHECK: sethi 4175662, %o0
+sethi %lm(sym), %o0
+! CHECK: or %o0, 0, %o0
+or %o0, %hm(sym), %o0
+
+! CHECK: sethi 18641, %o0
+sethi %hix(sym), %o0
+! CHECK: xor %o0, -360, %o0
+xor %o0, %lox(sym), %o0

llvm/test/MC/Sparc/sparc-relocations.s

 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -r - | FileCheck %s --check-prefix=CHECK-OBJ
 
         ! CHECK-OBJ: Format: elf64-sparc
-        ! CHECK-OBJ: Relocations [
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_WDISP30 foo
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_LO10 sym
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_HI22 sym
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_H44 sym
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_M44 sym
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_L44 sym
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_HH22 sym
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_HM10 sym
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_LM22 sym
-        ! CHECK-OBJ: 0x{{[0-9,A-F]+}} R_SPARC_13 sym
-        ! CHECK-ELF: ]
+        ! CHECK-OBJ: .rela.text {
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_WDISP30 foo
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_LO10 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_HI22 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_H44 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_M44 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_L44 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_HH22 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_HM10 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_LM22 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_13 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_13 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_HIX22 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_LOX10 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_GOTDATA_HIX22 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_GOTDATA_LOX10 sym
+        ! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_GOTDATA_OP sym
+        ! CHECK-OBJ-NEXT: }
 
         ! CHECK: call foo     ! encoding: [0b01AAAAAA,A,A,A]
         ! CHECK:              !   fixup A - offset: 0, value: foo, kind: fixup_sparc_call30
         call foo
 
         ! CHECK: or %g1, %lo(sym), %g3 ! encoding: [0x86,0x10,0b011000AA,A]
         ! CHECK-NEXT:                  !   fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10
         or %g1, %lo(sym), %g3
! RUN: llvm-mc %s -arch=sparcv9 -filetype=obj | llvm-readobj -r - | FileCheck %s --check-prefix=CHECK-OBJ
         ! CHECK: or %g1, sym, %g3 ! encoding: [0x86,0x10,0b011AAAAA,A]
         ! CHECK-NEXT:                  !   fixup A - offset: 0, value: sym, kind: fixup_sparc_13
         or %g1, sym, %g3
 
         ! CHECK: or %g1, sym+4, %g3 ! encoding: [0x86,0x10,0b011AAAAA,A]
         ! CHECK-NEXT:                  ! fixup A - offset: 0, value: sym+4, kind: fixup_sparc_13
         or %g1, (sym+4), %g3
 
+        ! CHECK: sethi %hix(sym), %g1 ! encoding: [0x03,0b00AAAAAA,A,A]
+        ! CHECK-NEXT:                 ! fixup A - offset: 0, value: %hix(sym), kind: fixup_sparc_hix22
+        sethi %hix(sym), %g1
+
+        ! CHECK: xor %g1, %lox(sym), %g1 ! encoding: [0x82,0x18,0b011AAAAA,A]
+        ! CHECK-NEXT:                    ! fixup A - offset: 0, value: %lox(sym), kind: fixup_sparc_lox10
+        xor %g1, %lox(sym), %g1
+
+        ! CHECK: sethi %gdop_hix22(sym), %l1 ! encoding: [0x23,0x00,0x00,0x00]
+        ! CHECK-NEXT:                        ! fixup A - offset: 0, value: %gdop_hix22(sym), kind: fixup_sparc_gotdata_hix22
+        sethi %gdop_hix22(sym), %l1
+
+        ! CHECK: or %l1, %gdop_lox10(sym), %l1 ! encoding: [0xa2,0x14,0x60,0x00]
+        ! CHECK-NEXT:                          ! fixup A - offset: 0, value: %gdop_lox10(sym), kind: fixup_sparc_gotdata_lox10
+        or %l1, %gdop_lox10(sym), %l1
+
+        ! CHECK: ldx [%l7+%l1], %l2, %gdop(sym) ! encoding: [0xe4,0x5d,0xc0,0x11]
+        ! CHECK-NEXT:                           ! fixup A - offset: 0, value: %gdop(sym), kind: fixup_sparc_gotdata_op
+        ldx [%l7 + %l1], %l2, %gdop(sym)
+
         ! This test needs to placed last in the file
         ! CHECK: .half  a-.Ltmp0
         .half a - .
         .byte a - .
 a: