[X86] Modify LOOP*, HLT control flow attributes

[Amir]

Summary

Add missing control flow attributes:

• LOOP*: isBranch, isTerminator
• HLT: isTerminator

This helps downstream disassemblers (such as BOLT) reconstruct the control
flow graph more accurately.

[craig.topper]

Why adding encoding information to TAILJMP? It's morphed in X86MCInstLower.cpp before it gets to the encoder.

[efriedma]

Needs an explanation of what this accomplishes.

Needs some sort of test, or an explanation of why it can't be tested.

[epastor]

Marking as Request Changes to get it off of my dashboard until the other comments get a response.

[Amir]

Removed TAILJMP encoding changes.

[craig.topper]

LGTM

[Amir]

@craig.topper: looks like there were no objections in a week. Can you please land this diff for me? (I don't have a commit access yet)

llvm/lib/Target/X86/X86InstrControl.td

let mayLoad = 1 in {
     def FARJMP16m  : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
                        "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
     def FARJMP32m  : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
                        "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
   }
 }
 
 // Loop instructions
-let SchedRW = [WriteJump] in {
+let isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
 def LOOP   : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
 def LOOPE  : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
 }
 
 //===----------------------------------------------------------------------===//
 //  Call Instructions...
 //
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
   def TCRETURNdi : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$offset),
                            []>, Sched<[WriteJump]>, NotMemoryFoldable;
   def TCRETURNri : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset),
                            []>, Sched<[WriteJump]>, NotMemoryFoldable;
   let mayLoad = 1 in
   def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset),
                            []>, Sched<[WriteJumpLd]>;
 
-  def TAILJMPd : PseudoI<(outs), (ins i32imm_brtarget:$dst),
-                         []>, Sched<[WriteJump]>;
+  def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), (ins i32imm_brtarget:$dst),
+                           "jmp\t$dst", []>, Sched<[WriteJump]>;
 
-  def TAILJMPr : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
-                         []>, Sched<[WriteJump]>;
+  let isIndirectBranch = 1 in {
+    def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
+                     "jmp{l}\t{*}$dst", []>, Sched<[WriteJump]>;
     let mayLoad = 1 in
-  def TAILJMPm : PseudoI<(outs), (ins i32mem_TC:$dst),
-                         []>, Sched<[WriteJumpLd]>;
+    def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
+                     "jmp{l}\t{*}$dst", []>, Sched<[WriteJumpLd]>;
+  }
 }
 
 // Conditional tail calls are similar to the above, but they are branches
 // rather than barriers, and they use EFLAGS.
 let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
     isCodeGenOnly = 1, SchedRW = [WriteJump] in
   let Uses = [ESP, EFLAGS, SSP] in {
   def TCRETURNdicc : PseudoI<(outs),

llvm/lib/Target/X86/X86InstrSystem.td

let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
   def UD1Wr   : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
                   "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
   def UD1Lr   : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
                   "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
   def UD1Qr   : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
                    "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
 }
 
+let isTerminator = 1 in
   def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
 
 // Interrupt and SysCall Instructions.
 let Uses = [EFLAGS] in
   def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
 
 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;