[AMDGPU] Switch AnnotateUniformValues to MemorySSA

[rampitec]

Summary

This shall speedup compilation and also remove threshold
limitations used by memory dependency analysis.

It also seem to fix the bug in the coalescer_remat.ll
where an SMRD load was used in presence of a potentially
clobbering store.

Fixes: SWDEV-272132

[rampitec]

• Drop now unused dfs include.
• Forgot to add llc-pipeline test.
• Make clang-tidy happy.

[rampitec]

• SetVector include also not needed anymore.
• MSSAWalker is not always needed and cached by the MSSA anyway, so request it only when needed.

PSDB passed, I am about to submit it after check-llvm.

llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp

 //===-- AMDGPUAnnotateUniformValues.cpp - ---------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// This pass adds amdgpu.uniform metadata to IR values so this information
 /// can be used during instruction selection.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPU.h"
 #include "Utils/AMDGPUBaseInfo.h"
-#include "llvm/ADT/DepthFirstIterator.h"
-#include "llvm/ADT/SetVector.h"
 #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
-#include "llvm/Analysis/LoopInfo.h"
-#include "llvm/Analysis/MemoryDependenceAnalysis.h"
+#include "llvm/Analysis/MemorySSA.h"
 #include "llvm/IR/InstVisitor.h"
 #include "llvm/InitializePasses.h"
 
 #define DEBUG_TYPE "amdgpu-annotate-uniform"
 
 using namespace llvm;
 
 namespace {
 
 class AMDGPUAnnotateUniformValues : public FunctionPass,
                        public InstVisitor<AMDGPUAnnotateUniformValues> {
   LegacyDivergenceAnalysis *DA;
-  MemoryDependenceResults *MDR;
-  LoopInfo *LI;
+  MemorySSA *MSSA;
   DenseMap<Value*, GetElementPtrInst*> noClobberClones;
   bool isEntryFunc;
 
 public:
   static char ID;
   AMDGPUAnnotateUniformValues() :
     FunctionPass(ID) { }
   bool doInitialization(Module &M) override;
   bool runOnFunction(Function &F) override;
   StringRef getPassName() const override {
     return "AMDGPU Annotate Uniform Values";
   }
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<LegacyDivergenceAnalysis>();
-    AU.addRequired<MemoryDependenceWrapperPass>();
-    AU.addRequired<LoopInfoWrapperPass>();
+    AU.addRequired<MemorySSAWrapperPass>();
     AU.setPreservesAll();
  }
 
   void visitBranchInst(BranchInst &I);
   void visitLoadInst(LoadInst &I);
   bool isClobberedInFunction(LoadInst * Load);
 };
 
 } // End anonymous namespace
 
 INITIALIZE_PASS_BEGIN(AMDGPUAnnotateUniformValues, DEBUG_TYPE,
                       "Add AMDGPU uniform metadata", false, false)
 INITIALIZE_PASS_DEPENDENCY(LegacyDivergenceAnalysis)
-INITIALIZE_PASS_DEPENDENCY(MemoryDependenceWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MemorySSAWrapperPass)
 INITIALIZE_PASS_END(AMDGPUAnnotateUniformValues, DEBUG_TYPE,
                     "Add AMDGPU uniform metadata", false, false)
 
 char AMDGPUAnnotateUniformValues::ID = 0;
 
 static void setUniformMetadata(Instruction *I) {
   I->setMetadata("amdgpu.uniform", MDNode::get(I->getContext(), {}));
 }
 static void setNoClobberMetadata(Instruction *I) {
   I->setMetadata("amdgpu.noclobber", MDNode::get(I->getContext(), {}));
 }
 
 bool AMDGPUAnnotateUniformValues::isClobberedInFunction(LoadInst * Load) {
-  // 1. get Loop for the Load->getparent();
-  // 2. if it exists, collect all the BBs from the most outer
-  // loop and check for the writes. If NOT - start DFS over all preds.
-  // 3. Start DFS over all preds from the most outer loop header.
-  SetVector<BasicBlock *> Checklist;
-  BasicBlock *Start = Load->getParent();
-  Checklist.insert(Start);
-  const Value *Ptr = Load->getPointerOperand();
-  const Loop *L = LI->getLoopFor(Start);
-  if (L) {
-    const Loop *P = L;
-    do {
-      L = P;
-      P = P->getParentLoop();
-    } while (P);
-    Checklist.insert(L->block_begin(), L->block_end());
-    Start = L->getHeader();
-  }
-
-  Checklist.insert(idf_begin(Start), idf_end(Start));
-  for (auto &BB : Checklist) {
-    BasicBlock::iterator StartIt = (!L && (BB == Load->getParent())) ?
-      BasicBlock::iterator(Load) : BB->end();
-    auto Q = MDR->getPointerDependencyFrom(
-        MemoryLocation::getBeforeOrAfter(Ptr), true, StartIt, BB, Load);
-    if (Q.isClobber() || Q.isUnknown() ||
-        // Store defines the load and thus clobbers it.
-        (Q.isDef() && Q.getInst()->mayWriteToMemory()))
-      return true;
-  }
-  return false;
+  const MemoryAccess *MA = MSSA->getWalker()->getClobberingMemoryAccess(Load);
+  return !MSSA->isLiveOnEntryDef(MA);
 }
 
 void AMDGPUAnnotateUniformValues::visitBranchInst(BranchInst &I) {
   if (DA->isUniform(&I))
     setUniformMetadata(&I);
 }
 
 void AMDGPUAnnotateUniformValues::visitLoadInst(LoadInst &I) {

 bool AMDGPUAnnotateUniformValues::doInitialization(Module &M) {
   return false;
 }
 
 bool AMDGPUAnnotateUniformValues::runOnFunction(Function &F) {
   if (skipFunction(F))
     return false;
 
-  DA  = &getAnalysis<LegacyDivergenceAnalysis>();
-  MDR = &getAnalysis<MemoryDependenceWrapperPass>().getMemDep();
-  LI  = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
+  DA = &getAnalysis<LegacyDivergenceAnalysis>();
+  MSSA = &getAnalysis<MemorySSAWrapperPass>().getMSSA();
   isEntryFunc = AMDGPU::isEntryFunctionCC(F.getCallingConv());
 
   visit(F);
   noClobberClones.clear();
   return true;
 }
 
 FunctionPass *
 llvm::createAMDGPUAnnotateUniformValues() {
   return new AMDGPUAnnotateUniformValues();
 }

llvm/test/CodeGen/AMDGPU/coalescer_remat.ll

 ; RUN: llc -march=amdgcn -verify-machineinstrs -mtriple=amdgcn-- -o - %s | FileCheck %s
 
 declare float @llvm.fma.f32(float, float, float)
 
 ; This checks that rematerialization support of the coalescer does not
 ; unnecessarily widen the register class. Without those fixes > 20 VGprs
 ; are used here
 ; Also check that some rematerialization of the 0 constant happened.
 ; CHECK-LABEL: foobar
 ; CHECK:  v_mov_b32_e32 v{{[0-9]+}}, 0
 ; CHECK:  v_mov_b32_e32 v{{[0-9]+}}, 0
 ; CHECK:  v_mov_b32_e32 v{{[0-9]+}}, 0
 ; CHECK:  v_mov_b32_e32 v{{[0-9]+}}, 0
 ; It's probably OK if this is slightly higher:
-; CHECK: ; NumVgprs: 4
-define amdgpu_kernel void @foobar(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in, i32 %flag) {
+; CHECK: ; NumVgprs: 8
+define amdgpu_kernel void @foobar(<4 x float> addrspace(1)* noalias %out, <4 x float> addrspace(1)* noalias %in, i32 %flag) {
 entry:
   %cmpflag = icmp eq i32 %flag, 1
   br i1 %cmpflag, label %loop, label %exit
 
 loop:
   %c = phi i32 [0, %entry], [%cnext, %loop]
   %v0 = phi float [0.0, %entry], [%fma.0, %loop]
   %v1 = phi float [0.0, %entry], [%fma.1, %loop]

llvm/test/CodeGen/AMDGPU/global-smrd-unknown.ll

 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji  -memdep-block-scan-limit=1 -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
 
 ; GCN-LABEL: {{^}}unknown_memdep_analysis:
 ; GCN: flat_load_dword
 ; GCN: flat_load_dword
 ; GCN: flat_store_dword
-define amdgpu_kernel void @unknown_memdep_analysis(float addrspace(1)* nocapture readonly %arg, float %arg1) #0 {
+define void @unknown_memdep_analysis(float addrspace(1)* nocapture readonly %arg, float %arg1) #0 {
 bb:
   %tmp53 = load float, float addrspace(1)* undef, align 4
   %tmp54 = getelementptr inbounds float, float addrspace(1)* %arg, i32 31
   %tmp55 = load float, float addrspace(1)* %tmp54, align 4
   %tmp56 = tail call float @llvm.fmuladd.f32(float %arg1, float %tmp53, float %tmp55)
   store float %tmp56, float addrspace(1)* undef, align 4
   ret void
 }
 
 declare float @llvm.fmuladd.f32(float, float, float) #1
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone speculatable }

llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

 ; GCN-O0-NEXT:       Region Pass Manager
 ; GCN-O0-NEXT:         Structurize control flow
 ; GCN-O0-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O0-NEXT:       Function Alias Analysis Results
 ; GCN-O0-NEXT:       Natural Loop Information
 ; GCN-O0-NEXT:       Code sinking
 ; GCN-O0-NEXT:       Post-Dominator Tree Construction
 ; GCN-O0-NEXT:       Legacy Divergence Analysis
-; GCN-O0-NEXT:       Phi Values Analysis
 ; GCN-O0-NEXT:       Function Alias Analysis Results
-; GCN-O0-NEXT:       Memory Dependence Analysis
+; GCN-O0-NEXT:       Memory SSA
 ; GCN-O0-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O0-NEXT:       SI annotate control flow
 ; GCN-O0-NEXT:       Natural Loop Information
 ; GCN-O0-NEXT:       LCSSA Verifier
 ; GCN-O0-NEXT:       Loop-Closed SSA Form Pass
 ; GCN-O0-NEXT:     CallGraph Construction
 ; GCN-O0-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O0-NEXT:       DummyCGSCCPass

 ; GCN-O1-NEXT:       Region Pass Manager
 ; GCN-O1-NEXT:         Structurize control flow
 ; GCN-O1-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O1-NEXT:       Function Alias Analysis Results
 ; GCN-O1-NEXT:       Natural Loop Information
 ; GCN-O1-NEXT:       Code sinking
 ; GCN-O1-NEXT:       Post-Dominator Tree Construction
 ; GCN-O1-NEXT:       Legacy Divergence Analysis
-; GCN-O1-NEXT:       Phi Values Analysis
 ; GCN-O1-NEXT:       Function Alias Analysis Results
-; GCN-O1-NEXT:       Memory Dependence Analysis
+; GCN-O1-NEXT:       Memory SSA
 ; GCN-O1-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O1-NEXT:       SI annotate control flow
 ; GCN-O1-NEXT:       Natural Loop Information
 ; GCN-O1-NEXT:       LCSSA Verifier
 ; GCN-O1-NEXT:       Loop-Closed SSA Form Pass
 ; GCN-O1-NEXT:     CallGraph Construction
 ; GCN-O1-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O1-NEXT:       DummyCGSCCPass

 ; GCN-O1-OPTS-NEXT:       Region Pass Manager
 ; GCN-O1-OPTS-NEXT:         Structurize control flow
 ; GCN-O1-OPTS-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O1-OPTS-NEXT:       Function Alias Analysis Results
 ; GCN-O1-OPTS-NEXT:       Natural Loop Information
 ; GCN-O1-OPTS-NEXT:       Code sinking
 ; GCN-O1-OPTS-NEXT:       Post-Dominator Tree Construction
 ; GCN-O1-OPTS-NEXT:       Legacy Divergence Analysis
-; GCN-O1-OPTS-NEXT:       Phi Values Analysis
 ; GCN-O1-OPTS-NEXT:       Function Alias Analysis Results
-; GCN-O1-OPTS-NEXT:       Memory Dependence Analysis
+; GCN-O1-OPTS-NEXT:       Memory SSA
 ; GCN-O1-OPTS-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O1-OPTS-NEXT:       SI annotate control flow
 ; GCN-O1-OPTS-NEXT:       Natural Loop Information
 ; GCN-O1-OPTS-NEXT:       LCSSA Verifier
 ; GCN-O1-OPTS-NEXT:       Loop-Closed SSA Form Pass
 ; GCN-O1-OPTS-NEXT:     CallGraph Construction
 ; GCN-O1-OPTS-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O1-OPTS-NEXT:       DummyCGSCCPass

 ; GCN-O2-NEXT:       Region Pass Manager
 ; GCN-O2-NEXT:         Structurize control flow
 ; GCN-O2-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O2-NEXT:       Function Alias Analysis Results
 ; GCN-O2-NEXT:       Natural Loop Information
 ; GCN-O2-NEXT:       Code sinking
 ; GCN-O2-NEXT:       Post-Dominator Tree Construction
 ; GCN-O2-NEXT:       Legacy Divergence Analysis
-; GCN-O2-NEXT:       Phi Values Analysis
 ; GCN-O2-NEXT:       Function Alias Analysis Results
-; GCN-O2-NEXT:       Memory Dependence Analysis
+; GCN-O2-NEXT:       Memory SSA
 ; GCN-O2-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O2-NEXT:       SI annotate control flow
 ; GCN-O2-NEXT:       Natural Loop Information
 ; GCN-O2-NEXT:       LCSSA Verifier
 ; GCN-O2-NEXT:       Loop-Closed SSA Form Pass
 ; GCN-O2-NEXT:     CallGraph Construction
 ; GCN-O2-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O2-NEXT:       DummyCGSCCPass

 ; GCN-O3-NEXT:       Region Pass Manager
 ; GCN-O3-NEXT:         Structurize control flow
 ; GCN-O3-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O3-NEXT:       Function Alias Analysis Results
 ; GCN-O3-NEXT:       Natural Loop Information
 ; GCN-O3-NEXT:       Code sinking
 ; GCN-O3-NEXT:       Post-Dominator Tree Construction
 ; GCN-O3-NEXT:       Legacy Divergence Analysis
-; GCN-O3-NEXT:       Phi Values Analysis
 ; GCN-O3-NEXT:       Function Alias Analysis Results
-; GCN-O3-NEXT:       Memory Dependence Analysis
+; GCN-O3-NEXT:       Memory SSA
 ; GCN-O3-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O3-NEXT:       SI annotate control flow
 ; GCN-O3-NEXT:       Natural Loop Information
 ; GCN-O3-NEXT:       LCSSA Verifier
 ; GCN-O3-NEXT:       Loop-Closed SSA Form Pass
 ; GCN-O3-NEXT:     CallGraph Construction
 ; GCN-O3-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O3-NEXT:       DummyCGSCCPass

llvm/test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 < %s | FileCheck %s
 
 ; FIXME: The wide loads and bundles introduce so much spilling.
-define protected amdgpu_kernel void @excess_soft_clause_reg_pressure(float addrspace(4)* %wei_ptr, float addrspace(1)* %out_ptr) {
+define protected amdgpu_kernel void @excess_soft_clause_reg_pressure(float addrspace(4)* %wei_ptr, float addrspace(1)* %out_ptr, float addrspace(1)* %in) {
 ; CHECK-LABEL: excess_soft_clause_reg_pressure:
 ; CHECK:  BB0_1: ; %for.cond28.preheader
-; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK:         global_load_dword
 ; CHECK-NEXT:    global_load_dword
 ; CHECK-NEXT:    global_load_dword
 ; CHECK-NEXT:    global_load_dword
 
 ; CHECK:         s_load_dwordx16
 ; CHECK-NEXT:    s_load_dwordx16
 ; CHECK-NEXT:    s_load_dwordx16
+; CHECK-NEXT:    s_load_dwordx16
 
 ; CHECK:         v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    s_load_dwordx16
-; CHECK-NEXT:    s_load_dwordx16
 
 ; CHECK:         v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
 ; CHECK-NEXT:    v_writelane_b32
-; CHECK-NEXT:    s_load_dwordx16
 
 ; CHECK:         v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 
 ; CHECK:         s_load_dwordx16
-; CHECK-NEXT:    s_load_dwordx16
-; CHECK-NEXT:    v_readlane_b32
+; CHECK:         s_load_dwordx16
+; CHECK:         s_load_dwordx16
+
+; CHECK:         v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
 ; CHECK-NEXT:    v_readlane_b32
entry:
   %i4 = shl i32 %i3, 8
   %i5 = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !5
   %i6 = add i32 %i4, %i5
   %i7 = trunc i64 %i2 to i32
   %conv = add i32 %i6, %i7
   %conv.frozen = freeze i32 %conv
   %div = udiv i32 %conv.frozen, 49
   %add.ptr22 = getelementptr inbounds float, float addrspace(4)* %wei_ptr, i64 undef
+  %in.ptr1 = getelementptr inbounds float, float addrspace(1)* %in, i32 %i5
   br label %for.cond28.preheader
 
 for.cond28.preheader:                             ; preds = %for.cond28.preheader, %entry
   %accum.sroa.110.0 = phi float [ 0.000000e+00, %entry ], [ %i251, %for.cond28.preheader ]
   %accum.sroa.106.0 = phi float [ 0.000000e+00, %entry ], [ %i247, %for.cond28.preheader ]
   %accum.sroa.102.0 = phi float [ 0.000000e+00, %entry ], [ %i243, %for.cond28.preheader ]
   %accum.sroa.98.0 = phi float [ 0.000000e+00, %entry ], [ %i239, %for.cond28.preheader ]
   %accum.sroa.94.0 = phi float [ 0.000000e+00, %entry ], [ %i235, %for.cond28.preheader ]
for.cond28.preheader:                             ; preds = %for.cond28.preheader, %entry
   %accum.sroa.14.0 = phi float [ 0.000000e+00, %entry ], [ %i155, %for.cond28.preheader ]
   %accum.sroa.10.0 = phi float [ 0.000000e+00, %entry ], [ %i151, %for.cond28.preheader ]
   %accum.sroa.6.0 = phi float [ 0.000000e+00, %entry ], [ %i147, %for.cond28.preheader ]
   %accum.sroa.0.0 = phi float [ 0.000000e+00, %entry ], [ %i143, %for.cond28.preheader ]
   %accum.sroa.114.0 = phi float [ 0.000000e+00, %entry ], [ %i255, %for.cond28.preheader ]
   %accum.sroa.118.0 = phi float [ 0.000000e+00, %entry ], [ %i259, %for.cond28.preheader ]
   %accum.sroa.122.0 = phi float [ 0.000000e+00, %entry ], [ %i263, %for.cond28.preheader ]
   %accum.sroa.126.0 = phi float [ 0.000000e+00, %entry ], [ %i267, %for.cond28.preheader ]
-  %i_ptr.0288 = phi float addrspace(1)* [ undef, %entry ], [ %add.ptr47.3, %for.cond28.preheader ]
+  %i_ptr.0288 = phi float addrspace(1)* [ %in.ptr1, %entry ], [ %add.ptr47.3, %for.cond28.preheader ]
   %w_ptr.0287 = phi float addrspace(4)* [ %add.ptr22, %entry ], [ %add.ptr74, %for.cond28.preheader ]
   %ci.0286 = phi i32 [ 0, %entry ], [ %inc116, %for.cond28.preheader ]
   %i8 = load float, float addrspace(1)* %i_ptr.0288, align 4
   %add.ptr47 = getelementptr inbounds float, float addrspace(1)* %i_ptr.0288, i64 49
   %i9 = load float, float addrspace(1)* %add.ptr47, align 4
   %add.ptr47.1 = getelementptr inbounds float, float addrspace(1)* %i_ptr.0288, i64 98
   %i10 = load float, float addrspace(1)* %add.ptr47.1, align 4
   %add.ptr47.2 = getelementptr inbounds float, float addrspace(1)* %i_ptr.0288, i64 147