[M68k][GloballSel] Adding initial GlobalISel infrastructure

[sushmaunnibhavi]

Summary

Add GlobalISel infrastructure up to the point where we can select a ret void.

[xgupta]

Hi @RKSimon,

Implementing GlobalISel for M68k is one of the Outreachy (3-month internship, 24 May to 24 Aug) projects. Sushma is one of the candidates for this project. To select the candidate there is currently a contribution period(till 9 May) is going on. This patch is a kind of task to check the skills of candiadate.

So we (project mentor: Anshil & Myself) don't have an industry use case, it is more about education purpose. and then further improve it to a stable state. We know that currently, GlobalISel doesn't have big-endian targets support. But we had listed this project after an email conversation with Amara and Quentin.

So yes it is also our responsibility to add big-endian targets in GlobalISel. We ask Amara and Quentin about how we can implement this part. So I think I should also share their response with Sushma.

Amara :

The places where you’re most likely to run into issues with big endian are in the IRTranslator (including CallLowering), and the legalizer (in LegalizerHelper.cpp) (which has to deal with illegal memory operations, and therefore can split them into pieces that may not be correct when using big-endian).

The majority of this code I don’t expect to require many changes. The issue I see is that unless you already have a M68000 GISel backend, how you’re going to try test cases to see what needs fixing is going to be hard. Perhaps you could try using AArch64 scalar code with big-endian to see what problems come up (IIRC AArch64’s big-endian scheme w.r.t vectors may be different to other backends in SelectionDAG).

Quentin:

+1 on the IRTranslator and the Legalizer. Basically anything that
breaks down chunks of bytes into smaller chunks of bytes may need
fixing (e.g., lowering a structure, legalizing a large load by
splitting it in smaller loads, etc.).

Unfortunately, we didn't get much time to look at the source code to implement the support. We are also kind of inexperienced in this field and open to any suggestions from the community. But I want to assure you that as soon as or before that we select the intern we will look into this also.

[myhsu]

Can you mark this as a draft until it’s ready for review?

[sushmaunnibhavi]

In D101819#2736241, @myhsu wrote:

Can you mark this as a draft until it’s ready for review?

Yes will do it!

[sushmaunnibhavi]

@myhsu

While implementing RegBankInfo for M68k, since it has 3 register classes .ie. data, address and index register classes, should I define 3 register banks in the registerBanks.td file?

[xgupta]

In D101819#2739005, @sushmaunnibhavi wrote:

@myhsu

While implementing RegBankInfo for M68k, since it has 3 register classes .ie. data, address and index register classes, should I define 3 register banks in the registerBanks.td file?

@sushmaunnibhavi For this patch, I think you only care about the general-purpose register bank. Have you looked at RISCV:https://reviews.llvm.org/D65219 , PowerPC:https://reviews.llvm.org/D83100 or Mips: https://reviews.llvm.org/D43583 implementations and read the https://llvm.org/docs/GlobalISel/GMIR.html#register-bank.

Please try to start with a test case and minimal implementation to support it as described in Head First into GlobalISel Tutorial.

(I wish you have something before 10-12 May to commit.)

[xgupta]

I guess it is better to implement an initial but complete (all passes) skeleton of GlobalISel infrastructure for M68k than doing in pass by pass starting with IRTranslator. I saw the most previous implementations in this way.

(but I also don't have actual experience in implementing them so don't know which way is better)

[sushmaunnibhavi]

Refreshing diff

[RKSimon]

some minor style cleanups

llvm/lib/Target/M68k/CMakeLists.txt

7

(style) match indentation of the other entries

26

(style) sorting

39

(style) sorting

llvm/lib/Target/M68k/M68k.h

21

(style) sorting

llvm/lib/Target/M68k/M68kCallLowering.cpp

53 ↗

(On Diff #343856)

(style) missing newline

llvm/lib/Target/M68k/M68kCallLowering.h

45 ↗

(On Diff #343856)

(style) missing newline

llvm/lib/Target/M68k/M68kInstructionSelector.cpp

60 ↗

(On Diff #343856)

(style) missing newline

llvm/lib/Target/M68k/M68kLegalizerInfo.cpp

23 ↗

(On Diff #343856)

(style) missing newline

llvm/lib/Target/M68k/M68kLegalizerInfo.h

28 ↗

(On Diff #343856)

(style) missing newline

llvm/lib/Target/M68k/M68kRegisterBankInfo.cpp

27 ↗

(On Diff #343856)

(style) missing newline

llvm/lib/Target/M68k/M68kRegisterBankInfo.h

38 ↗

(On Diff #343856)

(style) missing newline

llvm/lib/Target/M68k/M68kRegisterBanks.td

14 ↗

(On Diff #343856)

(style) missing newline

[qcolombet]

Hi,

Add GlobalISel infrastructure up to the point where we can select a ret void.

Could you add a test case for that?

E.g., something as simple as:

; RUN: llc -global-isel %s -o - | FileCheck %s

; CHECK-LABEL: noArgRetVoid:
; CHECK: <whatever is your return instruction here>
define void @noArgRetVoid() {
  ret void
}

[sushmaunnibhavi]

In D101819#2778522, @qcolombet wrote:

Hi,

Add GlobalISel infrastructure up to the point where we can select a ret void.

Could you add a test case for that?

E.g., something as simple as:

; RUN: llc -global-isel %s -o - | FileCheck %s

; CHECK-LABEL: noArgRetVoid:
; CHECK: <whatever is your return instruction here>
define void @noArgRetVoid() {
  ret void
}

Yes, I added this

; RUN: llc -mtriple=m68k -global-isel  %s -o - | FileCheck %s
  
; CHECK: name: f
; CHECK: RET
define void @f() {
  ret void
}

And when I run this test case, I get an error saying:

        .text
        .file   "irtranslator-ret.ll"
LLVM ERROR: unable to translate in big endian mode (in function: f)
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: ./build/bin/llc -mtriple=m68k -global-isel /home/sushma/Desktop/llvm-project/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll -o -
1.      Running pass 'Function Pass Manager' on module '/home/sushma/Desktop/llvm-project/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll'.
2.      Running pass 'IRTranslator' on function '@f'
 #0 0x000055615e5e371c llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (./build/bin/llc+0x2dcf71c)
 #1 0x000055615e5e1524 llvm::sys::RunSignalHandlers() (./build/bin/llc+0x2dcd524)
 #2 0x000055615e5e1693 SignalHandler(int) Signals.cpp:0:0
 #3 0x00007ffbb3cc2f40 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x13f40)
 #4 0x00007ffbb376bed7 raise /build/glibc-KRRWSm/glibc-2.29/signal/../sysdeps/unix/sysv/linux/raise.c:51:1
 #5 0x00007ffbb374d535 abort /build/glibc-KRRWSm/glibc-2.29/stdlib/abort.c:81:7
 #6 0x000055615e549f46 llvm::report_fatal_error(llvm::Twine const&, bool) (./build/bin/llc+0x2d35f46)
 #7 0x000055615e54a09e (./build/bin/llc+0x2d3609e)
 #8 0x000055615ec7f9d9 reportTranslationError(llvm::MachineFunction&, llvm::TargetPassConfig const&, llvm::OptimizationRemarkEmitter&, llvm::OptimizationRemarkMissed&) IRTranslator.cpp:0:0
 #9 0x000055615ec9491f llvm::IRTranslator::runOnMachineFunction(llvm::MachineFunction&) (./build/bin/llc+0x348091f)
#10 0x000055615da0c925 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (./build/bin/llc+0x21f8925)
#11 0x000055615de51a14 llvm::FPPassManager::runOnFunction(llvm::Function&) (./build/bin/llc+0x263da14)
#12 0x000055615de52559 llvm::FPPassManager::runOnModule(llvm::Module&) (./build/bin/llc+0x263e559)
#13 0x000055615de51331 llvm::legacy::PassManagerImpl::run(llvm::Module&) (./build/bin/llc+0x263d331)
#14 0x000055615c1d251d compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#15 0x000055615c117c72 main (./build/bin/llc+0x903c72)
#16 0x00007ffbb374eb6b __libc_start_main /build/glibc-KRRWSm/glibc-2.29/csu/../csu/libc-start.c:342:3
#17 0x000055615c1c949a _start (./build/bin/llc+0x9b549a)
Aborted (core dumped)

And I am working on this right now.

[sushmaunnibhavi]

In D101819#2776766, @RKSimon wrote:

some minor style cleanups

Yes, I will do these changes.

[qcolombet]

Hi,

LLVM ERROR: unable to translate in big endian mode (in function: f)

You'll need to turn that into a warning, otherwise effectively, none of your GISel changes will be testable (as in running the generated code on an actual target) until the support is complete, which is not a realistic constraint to have when bringing up a new GISel backend.

Cheers,
-Quentin

[sushmaunnibhavi]

Added test case to check for ret void.

[RKSimon]

llvm/CMakeLists.txt

315 ↗

(On Diff #348675)

M68k is an experimental target - it should NOT be added to any default target list

[sushmaunnibhavi]

Refreshing diff

[sushmaunnibhavi]

Refreshing diff

[sushmaunnibhavi]

Refreshing diff.

[sushmaunnibhavi]

Refreshing diff

[sushmaunnibhavi]

Refreshing diff

[sushmaunnibhavi]

Resolved clang-tidy warnings

[sushmaunnibhavi]

clang format

[sushmaunnibhavi]

Refreshing diff

[sushmaunnibhavi]

Refreshing diff

[sushmaunnibhavi]

Removing reportTranslationError() in IRtranslator.cpp file until big endian is supported.

[sushmaunnibhavi]

refreshing diff

[sushmaunnibhavi]

llvm/CMakeLists.txt

315 ↗

(On Diff #348675)

I will be temporarily keeping this in default targets since if I don't then when I submit the patch it will show "M68kGenRegisterBank.inc file not found" error. Maybe the buildbot does not check M68k backend with experimental_target_build flag. So I am keeping M68k in default targets temporarily.

[sushmaunnibhavi]

In D101819#2780892, @qcolombet wrote:

Hi,

LLVM ERROR: unable to translate in big endian mode (in function: f)

You'll need to turn that into a warning, otherwise effectively, none of your GISel changes will be testable (as in running the generated code on an actual target) until the support is complete, which is not a realistic constraint to have when bringing up a new GISel backend.

Cheers,
-Quentin

Hi @qcolombet ,
When I do a git grep with that error message, I find that it comes from IRTranslator.cpp file and in the runOnMachineFunction() function where it checks for big endian and throws a reportTranslationError() which is where that error comes from. By removing the reportTranslationError() temporarily in order to test my implementation, that would cause errors in other targets. Can you please suggest me any other way to solve this issue?

Thanks,
Sushma

[aemerson]

In D101819#2798940, @sushmaunnibhavi wrote:

In D101819#2780892, @qcolombet wrote:

Hi,

LLVM ERROR: unable to translate in big endian mode (in function: f)

You'll need to turn that into a warning, otherwise effectively, none of your GISel changes will be testable (as in running the generated code on an actual target) until the support is complete, which is not a realistic constraint to have when bringing up a new GISel backend.

Cheers,
-Quentin

Hi @qcolombet ,
When I do a git grep with that error message, I find that it comes from IRTranslator.cpp file and in the runOnMachineFunction() function where it checks for big endian and throws a reportTranslationError() which is where that error comes from. By removing the reportTranslationError() temporarily in order to test my implementation, that would cause errors in other targets. Can you please suggest me any other way to solve this issue?

Thanks,
Sushma

You can add a hook to TargetLoweringInfo so that only targets which want to use big-endian in GlobalISel can enable it (just M68k for now). Then check this hook, if it false then do the current fallback code.

llvm/CMakeLists.txt

315 ↗

(On Diff #348675)

I'm not familiar with this issue, but it sounds like a problem with the build system/cmake config. Either way, even adding this temporarily to the default targets can't be done if you want to have this committed.

[qcolombet]

Hi,

By removing the reportTranslationError() temporarily in order to test my implementation, that would cause errors in other targets. Can you please suggest me any other way to solve this issue?

That kind of errors are you seeing in other targets?

Also like Amara said, you can turn that into a warning on for M68k with a target hook.

Cheers,
-Quentin

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3133

Instead of purely removing it, turn that into a warning.

[sushmaunnibhavi]

In D101819#2799331, @aemerson wrote:

In D101819#2798940, @sushmaunnibhavi wrote:

In D101819#2780892, @qcolombet wrote:

Hi,

LLVM ERROR: unable to translate in big endian mode (in function: f)

You'll need to turn that into a warning, otherwise effectively, none of your GISel changes will be testable (as in running the generated code on an actual target) until the support is complete, which is not a realistic constraint to have when bringing up a new GISel backend.

Cheers,
-Quentin

Hi @qcolombet ,
When I do a git grep with that error message, I find that it comes from IRTranslator.cpp file and in the runOnMachineFunction() function where it checks for big endian and throws a reportTranslationError() which is where that error comes from. By removing the reportTranslationError() temporarily in order to test my implementation, that would cause errors in other targets. Can you please suggest me any other way to solve this issue?

Thanks,
Sushma

You can add a hook to TargetLoweringInfo so that only targets which want to use big-endian in GlobalISel can enable it (just M68k for now). Then check this hook, if it false then do the current fallback code.

Thanks for the suggestion. I will do this.

[sushmaunnibhavi]

In D101819#2799694, @qcolombet wrote:

Hi,

By removing the reportTranslationError() temporarily in order to test my implementation, that would cause errors in other targets. Can you please suggest me any other way to solve this issue?

That kind of errors are you seeing in other targets?

Also like Amara said, you can turn that into a warning on for M68k with a target hook.

Cheers,
-Quentin

Yes I see those errors only in other targets after removing reportTranslationError(). The M68k test case doesn't fail.
Yes, I will do as Amara said.

[sushmaunnibhavi]

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3133

@qcolombet , @aemerson
Is it right if I do this instead?

if (Triple(MF->getTarget().getTargetTriple()).getArch() != Triple::m68k) {
      reportTranslationError(*MF, *TPC, *ORE, R);
    }

This would not call reportTranslationError only for m68k but would not affect any other targets.

[aemerson]

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3133

It's less preferable than a TLI hook because it encodes target specific behavior into the translator.

[sushmaunnibhavi]

• Changed the test case name to noArgRetVoid

• Removed M68k from default targets in CMakeList.txt file

• Added enableBigEndian() hook so that targets which want to use big endian can enable it.

[RKSimon]

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3136

(style) Drop unnecessary braces

llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

33

(style) Drop unnecessary braces

llvm/lib/Target/M68k/GlSel/M68kInstructionSelector.cpp

78

(style) Drop unnecessary braces and move comment above if()

llvm/lib/Target/M68k/GlSel/M68kLegalizerInfo.h

28

(style) Missing // LLVM_LIB_TARGET_M68K_GLSEL_M68KLEGALIZERINFO_H

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

8

add newline

[sushmaunnibhavi]

Updated the patch according to @RKSimon comments.

[sushmaunnibhavi]

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3133

I have created an enableBigEndian() hook which the targets can use if they want to use big-endian. I ran the tests locally and the tests passed. But some of the unit tests fail when I submitted the patch which is not related to globalisel. What could be the reason for that?

I am new to compilers so wanted to know where I am going wrong.

[sushmaunnibhavi]

Refreshing diff

[sushmaunnibhavi]

@aemerson , @qcolombet , @RKSimon, @myhsu can you review the patch?

I think the clang-tidy errors in M68kRegisterBankInfo.h come because the buildbot doesn't build with DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD="M68k". But when built with DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD="M68k" no such errors occur.

I have created an enableBigEndian() hook in llvm/CodeGen/GlobalISel/CallLowering.h which the targets can use if they want to use big-endian. For now only M68k uses this. Then in the IRTranslator.cpp file I check if the target wants to use big-endian, if yes that the reportTranslationError(*MF, *TPC, *ORE, R) will not be called.

[RKSimon]

In D101819#2809759, @sushmaunnibhavi wrote:

I think the clang-tidy errors in M68kRegisterBankInfo.h come because the buildbot doesn't build with DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD="M68k". But when built with DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD="M68k" no such errors occur.

That's exactly the issue - I don't think there's a way to force the buildbot to run for a particular LLVM_EXPERIMENTAL_TARGETS_TO_BUILD. This works in the other way too - changes to common code don't get tested on experimental targets. In both cases its up to the target maintainers to handle any regressions.

[RKSimon]

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3125–3127

Would this be better:

if (!DL->isLittleEndian() && !CLI->enableBigEndian()) {

I'm not sure if we should always emit at least a warning that big-endian gisel isn't properly supported.

[aemerson]

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3125–3127

+1

3133

Which tests are failing? Have you checked if they pass without your changes?

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

573

I don't think this should be added. You already know the endianness from the datalayout

[aemerson]

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

573

The point is that even if a DL says we're using big-endian, without properly implemented and tested support we don't want to actually use GlobalISel. This hook will let us override the fallback for targets like M68K while it's under development.

[sushmaunnibhavi]

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3125–3127

Ok, I will update the patch with this.

3133

There was a problem with the patch I submitted previously, now with the updated patch no tests fail.

[sushmaunnibhavi]

Updated patch according to the comments.

[sushmaunnibhavi]

@aemerson , @RKSimon does the patch look good now?

[gandhi21299]

@sushmaunnibhavi There is still a clang-tidy error : 'M68kGenRegisterBank.inc' file not found

[gandhi21299]

Please excuse my previous comment, this patch LGTM

[myhsu]

First of all, big thanks for doing this :-)
Sorry for coming in late. This patch LGTM in general, just have some formatting / coding style comments.

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

3132

(nit) please remove this empty line if it's not necessary

llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

30

llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

11

Can you use the same file-level comment as M68kCallLowering.cpp?

26

Can you also a TODO here (or in the implementation side) to note that we're only supporting return instruction with no value at this time point

llvm/lib/Target/M68k/GlSel/M68kInstructionSelector.cpp

17

llvm/lib/Target/M68k/GlSel/M68kLegalizerInfo.h

10

23

(nit) Can you use struct instead of class since there is not private member here?

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.cpp

23

ditto, missing #undef?

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.h

20

should there be a #undef GET_REGBANK_DECLARATIONS? right after this line?

30

ditto, should there be a #undef here?

llvm/lib/Target/M68k/GlSel/M68kRegisterBanks.td

9

Can you add a brief file-level comment?

llvm/lib/Target/M68k/M68kSubtarget.cpp

64

this casting seems to be redundant

[sushmaunnibhavi]

Updated the patch according to @myhsu comments.

[sushmaunnibhavi]

Updated the patch according to @myhsu comments in M68kSubtarget.cpp file.

[sushmaunnibhavi]

@myhsu does the patch look good now?

[myhsu]

I recommend you to check the "Done" checkbox by an inline comment when you resolve a comment. With that you can easily navigate through unresolved comments by clicking on the "X/Y Comments" button on the top-right corner.

llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

2

this should be .h not .cpp, I think you forget to change this when copy the comments

llvm/lib/Target/M68k/GlSel/M68kLegalizerInfo.h

10

still outstanding

[sushmaunnibhavi]

Updated patch according to @myhsu comments.

[sushmaunnibhavi]

Updated patch according to @myhsu comments.

[sushmaunnibhavi]

Refreshing diff

[sushmaunnibhavi]

llvm/lib/Target/M68k/M68kSubtarget.cpp

64

But when I remove that cast it causes build errors when I build M68k

[sushmaunnibhavi]

@myhsu does the patch look good now?

[myhsu]

llvm/lib/Target/M68k/M68kSubtarget.cpp

64

In revision 351840, you changed the line into createM68kInstructionSelector(&TM, ...) but the first argument of createM68kInstructionSelector takes value of type const M68kTargetMachine& so of course it didn't compile. I think createM68kInstructionSelector(TM, ...) is the right way.

I recommend you to read the compile error message.

[sushmaunnibhavi]

Changed

InstSelector.reset(createM68kInstructionSelector(
      *static_cast<const M68kTargetMachine *>(&TM), *this, *RBI));

to

InstSelector.reset(createM68kInstructionSelector(TM, *this, *RBI))

[sushmaunnibhavi]

@myhsu how does the patch look now?

[myhsu]

LGTM Cheers!
Do you have commit access?

[sushmaunnibhavi]

In D101819#2821138, @myhsu wrote:

LGTM Cheers!
Do you have commit access?

No, I don't have commit access.

[gandhi21299]

LGTM I can merge this patch in.

[myhsu]

In D101819#2822247, @gandhi21299 wrote:

LGTM I can merge this patch in.

Thank you, please do

[glaubitz]

Impressive work. Thanks a lot to everyone involved, especially to sushmaunnibhavi!

[sushmaunnibhavi]

In D101819#2824360, @glaubitz wrote:

Impressive work. Thanks a lot to everyone involved, especially to sushmaunnibhavi!

Thank you!

[xgupta]

This comment was removed by xgupta.

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

public:
   /// range of an immediate jump.
   ///
   /// \return true if the lowering succeeded, false otherwise.
   bool lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &Call,
                  ArrayRef<Register> ResRegs,
                  ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
                  std::function<unsigned()> GetCalleeReg) const;
 
+  /// For targets which want to use big-endian can enable it with
+  /// enableBigEndian() hook
+  virtual bool enableBigEndian() const { return false; }
+
   /// For targets which support the "returned" parameter attribute, returns
   /// true if the given type is a valid one to use with "returned".
   virtual bool isTypeIsValidForThisReturn(EVT Ty) const { return false; }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
 
   SL = std::make_unique<GISelSwitchLowering>(this, FuncInfo);
   SL->init(TLI, TM, *DL);
 
 
 
   assert(PendingPHIs.empty() && "stale PHIs");
 
-  if (!DL->isLittleEndian()) {
+  // Targets which want to use big endian can enable it using
+  // enableBigEndian()
+  if (!DL->isLittleEndian() && !CLI->enableBigEndian()) {
     // Currently we don't properly handle big endian code.
     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
                                F.getSubprogram(), &F.getEntryBlock());
     R << "unable to translate in big endian mode";
     reportTranslationError(*MF, *TPC, *ORE, R);
   }
 
   // Release the per-function state when we return, whether we succeeded or not.
   auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
 
   // Setup a separate basic-block for the arguments and constants
   MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
   MF->push_back(EntryBB);
   EntryBuilder->setMBB(*EntryBB);
 
   DebugLoc DbgLoc = F.getEntryBlock().getFirstNonPHI()->getDebugLoc();
   SwiftError.setFunction(CurMF);

llvm/lib/Target/M68k/CMakeLists.txt

 add_llvm_component_group(M68k)
 
 set(LLVM_TARGET_DEFINITIONS M68k.td)
 
+tablegen(LLVM M68kGenGlobalISel.inc       -gen-global-isel)
 tablegen(LLVM M68kGenRegisterInfo.inc     -gen-register-info)
+tablegen(LLVM M68kGenRegisterBank.inc     -gen-register-bank)
 tablegen(LLVM M68kGenInstrInfo.inc        -gen-instr-info)
 tablegen(LLVM M68kGenSubtargetInfo.inc    -gen-subtarget)
 tablegen(LLVM M68kGenMCCodeBeads.inc      -gen-code-beads)
 tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM M68kGenDAGISel.inc          -gen-dag-isel)
 tablegen(LLVM M68kGenCallingConv.inc      -gen-callingconv)
 tablegen(LLVM M68kGenAsmWriter.inc        -gen-asm-writer)
 tablegen(LLVM M68kGenAsmMatcher.inc       -gen-asm-matcher)
 
 add_public_tablegen_target(M68kCommonTableGen)
 
 add_llvm_target(M68kCodeGen
+  GlSel/M68kCallLowering.cpp
+  GlSel/M68kInstructionSelector.cpp
+  GlSel/M68kLegalizerInfo.cpp
+  GlSel/M68kRegisterBankInfo.cpp
   M68kAsmPrinter.cpp
   M68kCollapseMOVEMPass.cpp
   M68kExpandPseudo.cpp
   M68kFrameLowering.cpp
   M68kInstrInfo.cpp
   M68kISelLowering.cpp
   M68kISelDAGToDAG.cpp
   M68kMachineFunction.cpp
   M68kMCInstLower.cpp
   M68kRegisterInfo.cpp
   M68kSubtarget.cpp
   M68kTargetMachine.cpp
   M68kTargetObjectFile.cpp
 
   LINK_COMPONENTS
   Analysis
   AsmPrinter
   CodeGen
   Core
+  GlobalISel
   MC
   SelectionDAG
   Support
   Target
   M68kDesc
   M68kInfo
 
   ADD_TO_COMPONENT
   M68k
 )
 
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)

llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

+//===-- M68kCallLowering.h - Call lowering -------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// This file implements the lowering of LLVM calls to machine code calls for
+/// GlobalISel.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_M68K_GLSEL_M68KCALLLOWERING_H
+#define LLVM_LIB_TARGET_M68K_GLSEL_M68KCALLLOWERING_H
+
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/GlobalISel/CallLowering.h"
+#include "llvm/CodeGen/ValueTypes.h"
+
+namespace llvm {
+
+class M68kTargetLowering;
+
+class M68kCallLowering : public CallLowering {
+  // TODO: We are only supporting return instruction with no value at this time
+  // point
+
+public:
+  M68kCallLowering(const M68kTargetLowering &TLI);
+
+  bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
+                   ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
+                   Register SwiftErrorVReg) const override;
+
+  bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
+                            ArrayRef<ArrayRef<Register>> VRegs,
+                            FunctionLoweringInfo &FLI) const override;
+
+  bool lowerCall(MachineIRBuilder &MIRBuilder,
+                 CallLoweringInfo &Info) const override;
+
+  bool enableBigEndian() const override;
+};
+
+} // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_M68K_GLSEL_M68KCALLLOWERING_H

llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

+//===-- M68kCallLowering.cpp - Call lowering -------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// This file implements the lowering of LLVM calls to machine code calls for
+/// GlobalISel.
+//
+//===----------------------------------------------------------------------===//
+
+#include "M68kCallLowering.h"
+#include "M68kISelLowering.h"
+#include "M68kInstrInfo.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+using namespace llvm;
+
+M68kCallLowering::M68kCallLowering(const M68kTargetLowering &TLI)
+    : CallLowering(&TLI) {}
+
+bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
+                                   const Value *Val, ArrayRef<Register> VRegs,
+                                   FunctionLoweringInfo &FLI,
+                                   Register SwiftErrorVReg) const {
+
+  if (Val)
+    return false;
+  MIRBuilder.buildInstr(M68k::RTS);
+  return true;
+}
+
+bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
+                                            const Function &F,
+                                            ArrayRef<ArrayRef<Register>> VRegs,
+                                            FunctionLoweringInfo &FLI) const {
+
+  if (F.arg_empty())
+    return true;
+
+  return false;
+}
+
+bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
+                                 CallLoweringInfo &Info) const {
+  return false;
+}
+
+bool M68kCallLowering::enableBigEndian() const { return true; }

llvm/lib/Target/M68k/GlSel/M68kInstructionSelector.cpp

+//===- M68kInstructionSelector.cpp ------------------------------*- C++ -*-===//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file implements the targeting of the InstructionSelector class for
+/// M68k.
+/// \todo This should be generated by TableGen.
+//===----------------------------------------------------------------------===//
+
+#include "M68kRegisterBankInfo.h"
+#include "M68kSubtarget.h"
+#include "M68kTargetMachine.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "m68k-isel"
+
+using namespace llvm;
+
+#define GET_GLOBALISEL_PREDICATE_BITSET
+#include "M68kGenGlobalISel.inc"
+#undef GET_GLOBALISEL_PREDICATE_BITSET
+
+namespace {
+
+class M68kInstructionSelector : public InstructionSelector {
+public:
+  M68kInstructionSelector(const M68kTargetMachine &TM, const M68kSubtarget &STI,
+                          const M68kRegisterBankInfo &RBI);
+
+  bool select(MachineInstr &I) override;
+  static const char *getName() { return DEBUG_TYPE; }
+
+private:
+  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+
+  const M68kTargetMachine &TM;
+  const M68kInstrInfo &TII;
+  const M68kRegisterInfo &TRI;
+  const M68kRegisterBankInfo &RBI;
+
+#define GET_GLOBALISEL_PREDICATES_DECL
+#include "M68kGenGlobalISel.inc"
+#undef GET_GLOBALISEL_PREDICATES_DECL
+
+#define GET_GLOBALISEL_TEMPORARIES_DECL
+#include "M68kGenGlobalISel.inc"
+#undef GET_GLOBALISEL_TEMPORARIES_DECL
+};
+
+} // end anonymous namespace
+
+#define GET_GLOBALISEL_IMPL
+#include "M68kGenGlobalISel.inc"
+#undef GET_GLOBALISEL_IMPL
+
+M68kInstructionSelector::M68kInstructionSelector(
+    const M68kTargetMachine &TM, const M68kSubtarget &STI,
+    const M68kRegisterBankInfo &RBI)
+    : InstructionSelector(), TM(TM), TII(*STI.getInstrInfo()),
+      TRI(*STI.getRegisterInfo()), RBI(RBI),
+
+#define GET_GLOBALISEL_PREDICATES_INIT
+#include "M68kGenGlobalISel.inc"
+#undef GET_GLOBALISEL_PREDICATES_INIT
+#define GET_GLOBALISEL_TEMPORARIES_INIT
+#include "M68kGenGlobalISel.inc"
+#undef GET_GLOBALISEL_TEMPORARIES_INIT
+{
+}
+
+bool M68kInstructionSelector::select(MachineInstr &I) {
+  // Certain non-generic instructions also need some special handling.
+  if (!isPreISelGenericOpcode(I.getOpcode()))
+    return true;
+
+  if (selectImpl(I, *CoverageInfo))
+    return true;
+
+  return false;
+}
+
+namespace llvm {
+InstructionSelector *
+createM68kInstructionSelector(const M68kTargetMachine &TM,
+                              const M68kSubtarget &Subtarget,
+                              const M68kRegisterBankInfo &RBI) {
+  return new M68kInstructionSelector(TM, Subtarget, RBI);
+}
+} // end namespace llvm

llvm/lib/Target/M68k/GlSel/M68kLegalizerInfo.h

+//===- M68kLegalizerInfo --------------------------------------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares the targeting of the MachineLegalizer class for
+/// M68k.
+/// \todo This should be generated by TableGen.
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_M68K_GLSEL_M68KLEGALIZERINFO_H
+#define LLVM_LIB_TARGET_M68K_GLSEL_M68KLEGALIZERINFO_H
+
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+
+namespace llvm {
+
+class M68kSubtarget;
+
+/// This struct provides the information for the target register banks.
+struct M68kLegalizerInfo : public LegalizerInfo {
+public:
+  M68kLegalizerInfo(const M68kSubtarget &ST);
+};
+} // end namespace llvm
+#endif // LLVM_LIB_TARGET_M68K_GLSEL_M68KLEGALIZERINFO_H

llvm/lib/Target/M68k/GlSel/M68kLegalizerInfo.cpp

+//===-- M68kLegalizerInfo.cpp ----------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file implements the targeting of the Machinelegalizer class for M68k.
+//===----------------------------------------------------------------------===//
+
+#include "M68kLegalizerInfo.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Type.h"
+
+using namespace llvm;
+
+M68kLegalizerInfo::M68kLegalizerInfo(const M68kSubtarget &ST) {
+  getLegacyLegalizerInfo().computeTables();
+}

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.h

+//===-- M68kRegisterBankInfo.h ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file declares the targeting of the RegisterBankInfo class for M68k.
+/// \todo This should be generated by TableGen.
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_M68K_GLSEL_M68KREGISTERBANKINFO_H
+#define LLVM_LIB_TARGET_M68K_GLSEL_M68KREGISTERBANKINFO_H
+
+#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+
+#define GET_REGBANK_DECLARATIONS
+#include "M68kGenRegisterBank.inc"
+#undef GET_REGBANK_DECLARATIONS
+
+namespace llvm {
+
+class TargetRegisterInfo;
+
+class M68kGenRegisterBankInfo : public RegisterBankInfo {
+protected:
+#define GET_TARGET_REGBANK_CLASS
+#include "M68kGenRegisterBank.inc"
+#undef GET_TARGET_REGBANK_CLASS
+};
+
+/// This class provides the information for the target register banks.
+class M68kRegisterBankInfo final : public M68kGenRegisterBankInfo {
+public:
+  M68kRegisterBankInfo(const TargetRegisterInfo &TRI);
+};
+} // end namespace llvm
+#endif

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.cpp

+//===-- M68kRegisterBankInfo.cpp -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file implements the targeting of the RegisterBankInfo class for M68k.
+/// \todo This should be generated by TableGen.
+//===----------------------------------------------------------------------===//
+
+#include "M68kRegisterBankInfo.h"
+#include "MCTargetDesc/M68kMCTargetDesc.h"
+#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
+#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+#define GET_TARGET_REGBANK_IMPL
+#include "M68kGenRegisterBank.inc"
+#undef GET_TARGET_REGBANK_IMPL
+
+using namespace llvm;
+
+M68kRegisterBankInfo::M68kRegisterBankInfo(const TargetRegisterInfo &TRI)
+    : M68kGenRegisterBankInfo() {}

llvm/lib/Target/M68k/GlSel/M68kRegisterBanks.td

+//===-- M68kRegisterBanks.td - Describe the M68k Banks -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// Define the M68k register banks used for GlobalISel.
+///
+//===----------------------------------------------------------------------===//
+
+/// General Purpose Registers. Here we define a register bank with name AnyGPR
+def GPRRegBank : RegisterBank<"AnyGPR", [DR8]>;

llvm/lib/Target/M68k/M68k.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_M68K_M68K_H
 #define LLVM_LIB_TARGET_M68K_M68K_H
 
 namespace llvm {
 
 class FunctionPass;
+class InstructionSelector;
+class M68kRegisterBankInfo;
+class M68kSubtarget;
 class M68kTargetMachine;
 
 /// This pass converts a legalized DAG into a M68k-specific DAG, ready for
 /// instruction scheduling.
 FunctionPass *createM68kISelDag(M68kTargetMachine &TM);
 
 /// Return a Machine IR pass that expands M68k-specific pseudo
 /// instructions into a sequence of actual instructions. This pass

 
 /// Finds MOVE instructions before any conditioanl branch instruction and
 /// replaces them with MOVEM instruction. Motorola's MOVEs do trash(V,C) flags
 /// register which prevents branch from taking the correct route. This pass
 /// has to be run after all pseudo expansions and prologue/epilogue emission
 /// so that all possible MOVEs are present.
 FunctionPass *createM68kConvertMOVToMOVMPass();
 
+InstructionSelector *
+createM68kInstructionSelector(const M68kTargetMachine &, const M68kSubtarget &,
+                              const M68kRegisterBankInfo &);
+
 } // namespace llvm
 
 #endif

llvm/lib/Target/M68k/M68k.td

 def : Proc<"M68040",  [ FeatureISA40 ]>;
 def : Proc<"M68060",  [ FeatureISA60 ]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "M68kRegisterInfo.td"
+include "GlSel/M68kRegisterBanks.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "M68kInstrInfo.td"
 
 def M68kInstrInfo : InstrInfo;

llvm/lib/Target/M68k/M68kSubtarget.h

 #ifndef LLVM_LIB_TARGET_CPU0_M68KSUBTARGET_H
 #define LLVM_LIB_TARGET_CPU0_M68KSUBTARGET_H
 
 #include "M68kFrameLowering.h"
 #include "M68kISelLowering.h"
 #include "M68kInstrInfo.h"
 
 #include "llvm/ADT/BitVector.h"
+#include "llvm/CodeGen/GlobalISel/CallLowering.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/Support/Alignment.h"
 
 #include <string>
 
public:
 
   const M68kTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
 
   const InstrItineraryData *getInstrItineraryData() const override {
     return &InstrItins;
   }
+
+protected:
+  // GlobalISel related APIs.
+  std::unique_ptr<CallLowering> CallLoweringInfo;
+  std::unique_ptr<InstructionSelector> InstSelector;
+  std::unique_ptr<LegalizerInfo> Legalizer;
+  std::unique_ptr<RegisterBankInfo> RegBankInfo;
+
+public:
+  const CallLowering *getCallLowering() const override;
+  InstructionSelector *getInstructionSelector() const override;
+  const LegalizerInfo *getLegalizerInfo() const override;
+  const RegisterBankInfo *getRegBankInfo() const override;
 };
 } // namespace llvm
 
 #endif

llvm/lib/Target/M68k/M68kSubtarget.cpp

 //===-- M68kSubtarget.cpp - M68k Subtarget Information ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file implements the M68k specific subclass of TargetSubtargetInfo.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "M68kSubtarget.h"
+#include "GlSel/M68kCallLowering.h"
+#include "GlSel/M68kLegalizerInfo.h"
+#include "GlSel/M68kRegisterBankInfo.cpp"
 
 #include "M68k.h"
 #include "M68kMachineFunction.h"
 #include "M68kRegisterInfo.h"
 #include "M68kTargetMachine.h"
 
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/IR/Attributes.h"

 void M68kSubtarget::anchor() {}
 
 M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
                              const M68kTargetMachine &TM)
     : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
       UserReservedRegister(M68k::NUM_TARGET_REGS), TM(TM), TSInfo(),
       InstrInfo(initializeSubtargetDependencies(CPU, TT, FS, TM)),
       FrameLowering(*this, this->getStackAlignment()), TLInfo(TM, *this),
-      TargetTriple(TT) {}
+      TargetTriple(TT) {
+  CallLoweringInfo.reset(new M68kCallLowering(*getTargetLowering()));
+  Legalizer.reset(new M68kLegalizerInfo(*this));
+
+  auto *RBI = new M68kRegisterBankInfo(*getRegisterInfo());
+  RegBankInfo.reset(RBI);
+  InstSelector.reset(createM68kInstructionSelector(TM, *this, *RBI));
+}
+
+const CallLowering *M68kSubtarget::getCallLowering() const {
+  return CallLoweringInfo.get();
+}
+
+InstructionSelector *M68kSubtarget::getInstructionSelector() const {
+  return InstSelector.get();
+}
+
+const LegalizerInfo *M68kSubtarget::getLegalizerInfo() const {
+  return Legalizer.get();
+}
+
+const RegisterBankInfo *M68kSubtarget::getRegBankInfo() const {
+  return RegBankInfo.get();
+}
 
 bool M68kSubtarget::isPositionIndependent() const {
   return TM.isPositionIndependent();
 }
 
 bool M68kSubtarget::isLegalToCallImmediateAddr() const { return true; }
 
 bool M68kSubtarget::abiUsesSoftFloat() const { return true; }

llvm/lib/Target/M68k/M68kTargetMachine.cpp

 //===-- M68kTargetMachine.cpp - M68k target machine ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file contains implementation for M68k target machine.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "M68kTargetMachine.h"
 #include "M68k.h"
-#include "TargetInfo/M68kTargetInfo.h"
-
 #include "M68kSubtarget.h"
 #include "M68kTargetObjectFile.h"
-
+#include "TargetInfo/M68kTargetInfo.h"
+#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
+#include "llvm/CodeGen/GlobalISel/Legalizer.h"
+#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/LegacyPassManager.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/PassRegistry.h"
 #include "llvm/Support/TargetRegistry.h"
 #include <memory>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "m68k"
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTarget() {
   RegisterTargetMachine<M68kTargetMachine> X(getTheM68kTarget());
+  auto *PR = PassRegistry::getPassRegistry();
+  initializeGlobalISel(*PR);
 }
 
 namespace {
 
 std::string computeDataLayout(const Triple &TT, StringRef CPU,
                               const TargetOptions &Options) {
   std::string Ret = "";
   // M68k is Big Endian
public:
 
   M68kTargetMachine &getM68kTargetMachine() const {
     return getTM<M68kTargetMachine>();
   }
 
   const M68kSubtarget &getM68kSubtarget() const {
     return *getM68kTargetMachine().getSubtargetImpl();
   }
-
+  bool addIRTranslator() override;
+  bool addLegalizeMachineIR() override;
+  bool addRegBankSelect() override;
+  bool addGlobalInstructionSelect() override;
   bool addInstSelector() override;
   void addPreSched2() override;
   void addPreEmitPass() override;
 };
 } // namespace
 
 TargetPassConfig *M68kTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new M68kPassConfig(*this, PM);
 }
 
 bool M68kPassConfig::addInstSelector() {
   // Install an instruction selector.
   addPass(createM68kISelDag(getM68kTargetMachine()));
   addPass(createM68kGlobalBaseRegPass());
   return false;
 }
 
+bool M68kPassConfig::addIRTranslator() {
+  addPass(new IRTranslator());
+  return false;
+}
+
+bool M68kPassConfig::addLegalizeMachineIR() {
+  addPass(new Legalizer());
+  return false;
+}
+
+bool M68kPassConfig::addRegBankSelect() {
+  addPass(new RegBankSelect());
+  return false;
+}
+
+bool M68kPassConfig::addGlobalInstructionSelect() {
+  addPass(new InstructionSelect());
+  return false;
+}
+
 void M68kPassConfig::addPreSched2() { addPass(createM68kExpandPseudoPass()); }
 
 void M68kPassConfig::addPreEmitPass() {
   addPass(createM68kCollapseMOVEMPass());
 }

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

+; RUN: llc -mtriple=m68k -global-isel -stop-after=irtranslator < %s | FileCheck %s
+
+; CHECK: name: noArgRetVoid
+; CHECK: RTS
+define void @noArgRetVoid() {
+  ret void
+}