[AMDGPU] Set number vgprs used in PS shaders based on input registers actually used

[dstuttard]

Summary

For PS shaders we can use the input SPI_PS_INPUT_ENA and SPI_PS_INPUT_ADDR
registers

Calculate the number of VGPR registers used as input VGPRs based on these
registers rather than the arguments passed in (this conservatively always
allocates the maximum).

[foad]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

724

Doesn't LastEna need to be initialized here too? I assume all these initializations are just to avoid "may be used uninitialized" warnings.

728

Should this be getPSInputAddr, and if so why didn't the tests you added fail?

730

Can InputEna ever be zero, and if so what should LastEna be?

758

Comma instead of dash?

782–784

What effect does setting NumArchVGPR here have, given that it was not being set before?

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h

56 ↗

(On Diff #341899)

This function (and possibly the ones next to it) could do with a comment. It's not obvious to me what TotalNumVGPRs means, given that one of the inputs is already called NumVGPR.

[dstuttard]

Some modifications based on review feedback

[dstuttard]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

724

Yes, I've added an initialization for consistency.

728

Yes, it should be getPSInputAddr.

It is actually very hard to generate a case where this makes a difference! It is when no input args are used, there is an PSInputAddr that sets inputs as allocated, plus there are extra args, which are also unused. Test is added.

The reason is makes little difference is that the line setting the NumVGPRs uses a max of the value calculated here and the actual allocation done for inputs - this usually fixes any discrepancies.
The reason we can't just use the allocation is that when there are extra arguments it will get a different result.

730

InputEna can never be zero - I should probably put in an assert for that.

782–784

NumArchVGPR was introduced to hold the original NumVGPRs (it's set to that at the start of this function). This is useful on architectures with AGPR support as the NumVGPRs (total vgprs) is adjusted with any AGPR registers that are used.

Since we're altering the original VGPR use with this change - we have to alter that value and set NumVGPRs to a new total with AGPR use (for architectures that support it).

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h

56 ↗

(On Diff #341899)

It is slightly confusing. The issue is that there's a difference between "actual number of VGPR registers required" and the NumVGPRs which is the number of explicitly tracked VGPR registers. Depending on the architecture, AGPR registers are included in the total VGPRs - and there are some alignment constraints too, which make the total different.

[dstuttard]

Ping?

Do you think that I should add any other reviewers?

[foad]

Do you think that I should add any other reviewers?

Probably a good idea!

[critson]

To confirm, this reduces the minimum number of VGPRs used by PS?
I am not sure the language in the description makes this clear.

The code makes sense to me.
Since this has been in review for a while now, assuming it passes CTS, we should probably accept it?

[sebastian-ne]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

719–720

Checking for AMDGPU_PS is enough, having this calling convention in AmdHsaOS would throw an error in SITargetLowering::LowerFormalArguments.
Also, maybe the name IsPixelShader is clearer? (It’s called that in AMDGPUAtomicOptimizer.cpp.)

738

nit: I think InputEna || InputAddr is normally used in conditions.

[dstuttard]

Rebase and address some of the review comments

[dstuttard]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

719–720

Actually, removing the AmdHsaOS check causes one of the lit tests to fail: no-hsa-graphics-shaders.ll

[dstuttard]

ping?

[dstuttard]

@critson @foad @Flakebi - are you happy with the changes? Can someone approve?

[sebastian-ne]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

742

Missing . between the sentences

754–779

Could you add braces for the if as well?

769

Should this be an increment or a += NumRegs?

[sebastian-ne]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

719–720

The lit test fails because the assertion assert((InputEna || InputAddr)) fails and the error message that amdgpu_ps is unsupported in HSA is not printed anymore. So amdgpu_ps in HSA is illegal. Not sure if there’s a better way to handle this though.

[dstuttard]

Address review comments

[dstuttard]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

719–720

Let's leave it as-is for now then.

769

It should be += NumRegs - I've renamed PSVGPRCount to PSArgCount instead

[dstuttard]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

769

For clarification - I meant, the += NumRegs in the lines above are correct, the ++ on PSArgCount is also correct.
PSArgCount is effectively counting through the bits in InputAddr - each arg can be more than one VGPR hence calculating and adding NumRegs for the NumVGPR counters, but only incrementing the PSArgCount.

[sebastian-ne]

Thanks, LGTM

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 
   const Function &F = MF.getFunction();
 
   // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
   // dispatch registers are function args.
   unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
 
   if (isShader(F.getCallingConv())) {
+    bool IsPixelShader =
+        F.getCallingConv() == CallingConv::AMDGPU_PS && !STM.isAmdHsaOS();
+
+    // Calculate the number of VGPR registers based on the SPI input registers
+    uint32_t InputEna = 0;
+    uint32_t InputAddr = 0;
+    unsigned LastEna = 0;
+
+    if (IsPixelShader) {
+      // Note for IsPixelShader:
+      // By this stage, all enabled inputs are tagged in InputAddr as well.
+      // We will use InputAddr to determine whether the input counts against the
+      // vgpr total and only use the InputEnable to determine the last input
+      // that is relevant - if extra arguments are used, then we have to honour
+      // the InputAddr for any intermediate non-enabled inputs.
+      InputEna = MFI->getPSInputEnable();
+      InputAddr = MFI->getPSInputAddr();
+
+      // We only need to consider input args up to the last used arg.
+      assert((InputEna || InputAddr) &&
+             "PSInputAddr and PSInputEnable should "
+             "never both be 0 for AMDGPU_PS shaders");
+      // There are some rare circumstances where InputAddr is non-zero and
+      // InputEna can be set to 0. In this case we default to setting LastEna
+      // to 1.
+      LastEna = InputEna ? findLastSet(InputEna) + 1 : 1;
+    }
+
     // FIXME: We should be using the number of registers determined during
     // calling convention lowering to legalize the types.
     const DataLayout &DL = F.getParent()->getDataLayout();
+    unsigned PSArgCount = 0;
+    unsigned IntermediateVGPR = 0;
     for (auto &Arg : F.args()) {
       unsigned NumRegs = (DL.getTypeSizeInBits(Arg.getType()) + 31) / 32;
-      if (Arg.hasAttribute(Attribute::InReg))
+      if (Arg.hasAttribute(Attribute::InReg)) {
         WaveDispatchNumSGPR += NumRegs;
+      } else {
+        // If this is a PS shader and we're processing the PS Input args (first
+        // 16 VGPR), use the InputEna and InputAddr bits to define how many
+        // VGPRs are actually used.
+        // Any extra VGPR arguments are handled as normal arguments (and
+        // contribute to the VGPR count whether they're used or not).
+        if (IsPixelShader && PSArgCount < 16) {
+          if ((1 << PSArgCount) & InputAddr) {
+            if (PSArgCount < LastEna)
+              WaveDispatchNumVGPR += NumRegs;
             else
+              IntermediateVGPR += NumRegs;
+          }
+          PSArgCount++;
+        } else {
+          // If there are extra arguments we have to include the allocation for
+          // the non-used (but enabled with InputAddr) input arguments
+          if (IntermediateVGPR) {
+            WaveDispatchNumVGPR += IntermediateVGPR;
+            IntermediateVGPR = 0;
+          }
           WaveDispatchNumVGPR += NumRegs;
         }
+      }
+    }
     ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
-    ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
+    ProgInfo.NumArchVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
+    ProgInfo.NumVGPR =
+        Info.getTotalNumVGPRs(STM, Info.NumAGPR, ProgInfo.NumArchVGPR);
   }
 
   // Adjust number of registers used to meet default/requested minimum/maximum
   // number of waves per execution unit request.
   ProgInfo.NumSGPRsForWavesPerEU = std::max(
     std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
   ProgInfo.NumVGPRsForWavesPerEU = std::max(
     std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));

llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.h

struct SIFunctionResourceInfo {
     uint64_t PrivateSegmentSize = 0;
     bool UsesVCC = false;
     bool UsesFlatScratch = false;
     bool HasDynamicallySizedStack = false;
     bool HasRecursion = false;
     bool HasIndirectCall = false;
 
     int32_t getTotalNumSGPRs(const GCNSubtarget &ST) const;
+    // Total number of VGPRs is actually a combination of AGPR and VGPR
+    // depending on architecture - and some alignment constraints
+    int32_t getTotalNumVGPRs(const GCNSubtarget &ST, int32_t NumAGPR,
+                             int32_t NumVGPR) const;
     int32_t getTotalNumVGPRs(const GCNSubtarget &ST) const;
   };
 
   AMDGPUResourceUsageAnalysis() : CallGraphSCCPass(ID) {}
 
   bool runOnSCC(CallGraphSCC &SCC) override;
 
   bool doInitialization(CallGraph &CG) override {

llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp

 int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumSGPRs(
     const GCNSubtarget &ST) const {
   return NumExplicitSGPR +
          IsaInfo::getNumExtraSGPRs(&ST, UsesVCC, UsesFlatScratch,
                                    ST.getTargetID().isXnackOnOrAny());
 }
 
 int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs(
+    const GCNSubtarget &ST, int32_t ArgNumAGPR, int32_t ArgNumVGPR) const {
+  if (ST.hasGFX90AInsts() && ArgNumAGPR)
+    return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
+  return std::max(ArgNumVGPR, ArgNumAGPR);
+}
+
+int32_t AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs(
     const GCNSubtarget &ST) const {
-  if (ST.hasGFX90AInsts() && NumAGPR)
-    return alignTo(NumVGPR, 4) + NumAGPR;
-  return std::max(NumVGPR, NumAGPR);
+  return getTotalNumVGPRs(ST, NumAGPR, NumVGPR);
 }
 
 bool AMDGPUResourceUsageAnalysis::runOnSCC(CallGraphSCC &SCC) {
   auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
   if (!TPC)
     return false;
 
   const TargetMachine &TM = TPC->getTM<TargetMachine>();

llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll

+;RUN: llc < %s -mtriple=amdgcn-pal -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+;RUN: llc < %s -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+; ;CHECK-LABEL: {{^}}_amdgpu_ps_1_arg:
+; ;CHECK: NumVgprs: 4
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_1_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret2 = insertvalue { <4 x float> } undef, <4 x float> %ret1, 0
+  ret { <4 x float> } %ret2
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_3_arg:
+; CHECK: NumVgprs: 6
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_3_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %i2 = extractelement <2 x float> %arg4, i32 0
+  %i3 = extractelement <2 x float> %arg5, i32 1
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
+  %ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
+  %ret2 = insertvalue { <4 x float> } undef, <4 x float> %ret1.2, 0
+  ret { <4 x float> } %ret2
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_2_arg_gap:
+; CHECK: NumVgprs: 4
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_gap(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %i3 = extractelement <2 x float> %arg5, i32 1
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret1.2 = insertelement <4 x float> %ret1, float %i3, i32 1
+  %ret2 = insertvalue { <4 x float> } undef, <4 x float> %ret1.2, 0
+  ret { <4 x float> } %ret2
+}
+
+; Using InitialPSInputAddr of 0x2 causes the 2nd VGPR arg to be included in the packing - this increases the total number of VGPRs and in turn makes arg3 not be packed to be
+; adjacent to arg1 (the only 2 used arguments)
+; CHECK-LABEL: {{^}}_amdgpu_ps_2_arg_no_pack:
+; CHECK: NumVgprs: 6
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_no_pack(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #1 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %i3 = extractelement <2 x float> %arg5, i32 1
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret1.2 = insertelement <4 x float> %ret1, float %i3, i32 1
+  %ret2 = insertvalue { <4 x float> } undef, <4 x float> %ret1.2, 0
+  ret { <4 x float> } %ret2
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_arg:
+; CHECK: NumVgprs: 24
+define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %i2 = extractelement <2 x float> %arg4, i32 0
+  %i3 = extractelement <2 x float> %arg5, i32 1
+  %i4 = extractelement <3 x float> %arg6, i32 1
+  %i5 = extractelement <2 x float> %arg7, i32 0
+  %i6 = extractelement <2 x float> %arg8, i32 0
+  %i7 = extractelement <2 x float> %arg9, i32 1
+
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
+  %ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
+  %ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
+
+  %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+  %ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
+  %ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
+  %ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
+
+  %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+  %ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
+  %ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
+  %ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
+
+  %arg15.f = bitcast i32 %arg15 to float
+  %arg16.f = bitcast i32 %arg16 to float
+  %arg17.f = bitcast i32 %arg17 to float
+  %arg18.f = bitcast i32 %arg18 to float
+
+  %ret4 = insertelement <4 x float> undef, float %arg15.f, i32 0
+  %ret4.1 = insertelement <4 x float> %ret4, float %arg16.f, i32 1
+  %ret4.2 = insertelement <4 x float> %ret4.1, float %arg17.f, i32 2
+  %ret4.3 = insertelement <4 x float> %ret4.2, float %arg18.f, i32 3
+
+  %ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
+  %ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
+  %ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
+  %ret.res  = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.3, 3
+
+  ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
+}
+
+; Extra arguments have to be allocated even if they're unused
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_arg_extra_unused:
+; CHECK: NumVgprs: 26
+define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg_extra_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %i2 = extractelement <2 x float> %arg4, i32 0
+  %i3 = extractelement <2 x float> %arg5, i32 1
+  %i4 = extractelement <3 x float> %arg6, i32 1
+  %i5 = extractelement <2 x float> %arg7, i32 0
+  %i6 = extractelement <2 x float> %arg8, i32 0
+  %i7 = extractelement <2 x float> %arg9, i32 1
+
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
+  %ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
+  %ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
+
+  %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+  %ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
+  %ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
+  %ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
+
+  %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+  %ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
+  %ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
+  %ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
+
+  %arg15.f = bitcast i32 %arg15 to float
+  %arg16.f = bitcast i32 %arg16 to float
+  %arg17.f = bitcast i32 %arg17 to float
+  %arg18.f = bitcast i32 %arg18 to float
+
+  %ret4 = insertelement <4 x float> undef, float %arg15.f, i32 0
+  %ret4.1 = insertelement <4 x float> %ret4, float %arg16.f, i32 1
+  %ret4.2 = insertelement <4 x float> %ret4.1, float %arg17.f, i32 2
+  %ret4.3 = insertelement <4 x float> %ret4.2, float %arg18.f, i32 3
+
+  %ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
+  %ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
+  %ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
+  %ret.res  = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.3, 3
+
+  ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_arg_extra:
+; CHECK: NumVgprs: 26
+; CHECK: NumVGPRsForWavesPerEU: 26
+define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_all_arg_extra(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %i2 = extractelement <2 x float> %arg4, i32 0
+  %i3 = extractelement <2 x float> %arg5, i32 1
+  %i4 = extractelement <3 x float> %arg6, i32 1
+  %i5 = extractelement <2 x float> %arg7, i32 0
+  %i6 = extractelement <2 x float> %arg8, i32 0
+  %i7 = extractelement <2 x float> %arg9, i32 1
+
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
+  %ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
+  %ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
+
+  %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+  %ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
+  %ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
+  %ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
+
+  %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+  %ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
+  %ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
+  %ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
+
+  %arg15.f = bitcast i32 %arg15 to float
+  %arg16.f = bitcast i32 %arg16 to float
+  %arg17.f = bitcast i32 %arg17 to float
+  %arg18.f = bitcast i32 %arg18 to float
+
+  %arg15_16.f = fadd float %arg15.f, %arg16.f
+  %arg17_18.f = fadd float %arg17.f, %arg18.f
+
+  %ret4 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+  %ret4.1 = insertelement <4 x float> %ret4, float %extra_arg2, i32 1
+  %ret4.2 = insertelement <4 x float> %ret4.1, float %arg15_16.f, i32 2
+  %ret4.3 = insertelement <4 x float> %ret4.2, float %arg17_18.f, i32 3
+
+  %ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
+  %ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
+  %ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
+  %ret.res  = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.3, 3
+
+  ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
+}
+
+; Check that when no input args are used we get the minimum allocation - note that we always enable the first input
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused:
+; CHECK: NumVgprs: 4
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
+.entry:
+  ret { <4 x float> } undef
+}
+
+; Check that when no input args are used we get the minimum allocation - note that we always enable the first input
+; Additionally set the PSInputAddr to 0 via the metadata
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_ia0:
+; CHECK: NumVgprs: 4
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_ia0(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #3 {
+.entry:
+  ret { <4 x float> } undef
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_extra_used:
+; CHECK: NumVgprs: 4
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
+.entry:
+  %ret4.1 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+  %ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg2, i32 1
+
+  %ret.res  = insertvalue { <4 x float> } undef, <4 x float> %ret4.2, 0
+
+  ret { <4 x float> } %ret.res
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_part_unused_extra_used:
+; CHECK: NumVgprs: 5
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_used(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
+.entry:
+  %ret4.1 = insertelement <4 x float> undef, float %arg14, i32 0
+  %ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg1, i32 1
+  %ret4.3 = insertelement <4 x float> %ret4.2, float %extra_arg2, i32 2
+
+  %ret.res  = insertvalue { <4 x float> } undef, <4 x float> %ret4.3, 0
+
+  ret { <4 x float> } %ret.res
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_part_unused_extra_unused:
+; CHECK: NumVgprs: 7
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
+.entry:
+  %ret4.1 = insertelement <4 x float> undef, float %arg12, i32 0
+  %ret4.2 = insertelement <4 x float> %ret4.1, float %arg13, i32 1
+  %ret4.3 = insertelement <4 x float> %ret4.2, float %arg14, i32 2
+
+  %ret.res  = insertvalue { <4 x float> } undef, <4 x float> %ret4.3, 0
+
+  ret { <4 x float> } %ret.res
+}
+
+; Extra unused inputs are always added to the allocation
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_extra_unused:
+; CHECK: NumVgprs: 4
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
+.entry:
+
+  ret { <4 x float> } undef
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_extra_used_no_packing:
+; CHECK: NumVgprs: 26
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used_no_packing(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #2 {
+.entry:
+  %ret4.1 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+  %ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg2, i32 1
+
+  %ret.res  = insertvalue { <4 x float> } undef, <4 x float> %ret4.2, 0
+
+  ret { <4 x float> } %ret.res
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_all_unused_extra_unused_no_packing:
+; CHECK: NumVgprs: 26
+define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_unused_no_packing(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #2 {
+.entry:
+  ret { <4 x float> } undef
+}
+
+; CHECK-LABEL: {{^}}_amdgpu_ps_some_unused_arg_extra:
+; CHECK: NumVgprs: 24
+; CHECK: NumVGPRsForWavesPerEU: 24
+define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_some_unused_arg_extra(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %i2 = extractelement <2 x float> %arg4, i32 0
+  %i3 = extractelement <2 x float> %arg5, i32 1
+  %i4 = extractelement <3 x float> %arg6, i32 1
+  %i5 = extractelement <2 x float> %arg7, i32 0
+  %i6 = extractelement <2 x float> %arg8, i32 0
+  %i7 = extractelement <2 x float> %arg9, i32 1
+
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
+  %ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
+  %ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
+
+  %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+  %ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
+  %ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
+  %ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
+
+  %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+  %ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
+  %ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
+  %ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
+
+  %arg15.f = bitcast i32 %arg15 to float
+  %arg16.f = bitcast i32 %arg16 to float
+
+  %ret4 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+  %ret4.1 = insertelement <4 x float> %ret4, float %extra_arg2, i32 1
+  %ret4.2 = insertelement <4 x float> %ret4.1, float %arg15.f, i32 2
+  %ret4.3 = insertelement <4 x float> %ret4.2, float %arg16.f, i32 3
+
+  %ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
+  %ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
+  %ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
+  %ret.res  = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.3, 3
+
+  ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
+}
+
+;CHECK-LABEL: {{^}}_amdgpu_ps_some_unused_no_packing_arg_extra:
+;CHECK: NumVgprs: 26
+;CHECK: NumVGPRsForWavesPerEU: 26
+define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @_amdgpu_ps_some_unused_no_packing_arg_extra(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #2 {
+.entry:
+  %i1 = extractelement <2 x float> %arg3, i32 1
+  %i2 = extractelement <2 x float> %arg4, i32 0
+  %i3 = extractelement <2 x float> %arg5, i32 1
+  %i4 = extractelement <3 x float> %arg6, i32 1
+  %i5 = extractelement <2 x float> %arg7, i32 0
+  %i6 = extractelement <2 x float> %arg8, i32 0
+  %i7 = extractelement <2 x float> %arg9, i32 1
+
+  %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+  %ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
+  %ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
+  %ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
+
+  %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+  %ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
+  %ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
+  %ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
+
+  %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+  %ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
+  %ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
+  %ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
+
+  %ret4 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+  %ret4.1 = insertelement <4 x float> %ret4, float %extra_arg2, i32 1
+
+  %ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
+  %ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
+  %ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
+  %ret.res  = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.1, 3
+
+  ret { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res
+}
+
+attributes #0 = { nounwind "target-features"=",+wavefrontsize64,+cumode"  }
+attributes #1 = { nounwind "InitialPSInputAddr"="2" "target-features"=",+wavefrontsize64,+cumode" }
+attributes #2 = { nounwind "InitialPSInputAddr"="0xffff" "target-features"=",+wavefrontsize64,+cumode" }
+attributes #3 = { nounwind "InitialPSInputAddr"="0" "target-features"=",+wavefrontsize64,+cumode" }