[PowerPC] Remove extra swap for extract+vperm on LE

[qiucf]

Summary

This is a simple fix on LE. On BE, vector shuffles are categorized into different ops. We may need more work to eliminate these in tablegen/pre-isel.

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2957

Nit: get rid of the unrelated change.

[maryammo]

This patch is functionally incorrect

one.c:

#include <stdio.h>
extern double test10(vector int a, vector int b);
int main() {
  double res;
                 //   0           1           2           3
  vector int a = {0x404c38d4, 0x40460e14, 0x404c38d4, 0x7ae147ae};
                 //   4           5           6           7
  vector int b = {0x4027fae1, 0xfdf3b646, 0x47ae147b, 0x40563851};
  res = test10(a, b);
  printf("res: %f\n", res);
  return 0;
}

two.c:

double test10(vector int a, vector int b) {
  //vector int c = __builtin_shufflevector(a, b, 5, 2, 3, 7);
  //                5     2     3     7
  vector int c = { b[1], a[2], a[3], b[3] };
  return ((vector double)c)[0] + 11.0;
}

Expected result:
res: 67.444000

Actual result:
res: -45563434706068069391700044011884519815891525610042006390324289980530809059647691943421443695410413568.000000

So we have decided to revert it.

[qiucf]

In D101605#3748991, @maryammo wrote:

This patch is functionally incorrect

one.c:

#include <stdio.h>
extern double test10(vector int a, vector int b);
int main() {
  double res;
                 //   0           1           2           3
  vector int a = {0x404c38d4, 0x40460e14, 0x404c38d4, 0x7ae147ae};
                 //   4           5           6           7
  vector int b = {0x4027fae1, 0xfdf3b646, 0x47ae147b, 0x40563851};
  res = test10(a, b);
  printf("res: %f\n", res);
  return 0;
}

two.c:

double test10(vector int a, vector int b) {
  //vector int c = __builtin_shufflevector(a, b, 5, 2, 3, 7);
  //                5     2     3     7
  vector int c = { b[1], a[2], a[3], b[3] };
  return ((vector double)c)[0] + 11.0;
}

Expected result:
res: 67.444000

Actual result:
res: -45563434706068069391700044011884519815891525610042006390324289980530809059647691943421443695410413568.000000

So we have decided to revert it.

Thanks for catching this! The pattern should only work in a very limited condition, which is not profitable.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 
 // Any little endian VSX subtarget.
 let Predicates = [HasVSX, IsLittleEndian] in {
 defm : ScalToVecWPermute<v2f64, (f64 f64:$A),
                          (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
                                    (SUBREG_TO_REG (i64 1), $A, sub_64), 0),
                          (SUBREG_TO_REG (i64 1), $A, sub_64)>;
 
+def : Pat<(f64 (extractelt (v2f64 (bitconvert (v16i8
+                 (PPCvperm v16i8:$A, v16i8:$B, v16i8:$C)))), 0)),
+          (f64 (EXTRACT_SUBREG (VPERM $B, $A, $C), sub_64))>;
 def : Pat<(f64 (extractelt v2f64:$S, 0)),
           (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
 def : Pat<(f64 (extractelt v2f64:$S, 1)),
           (f64 (EXTRACT_SUBREG $S, sub_64))>;
 
 def : Pat<(v2f64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
 def : Pat<(PPCst_vec_be v2f64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
 def : Pat<(v4f32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
 def : Pat<(PPCst_vec_be v4f32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>;
 def : Pat<(v2i64 (PPCld_vec_be ForceXForm:$src)), (LXVD2X ForceXForm:$src)>;
 def : Pat<(PPCst_vec_be v2i64:$rS, ForceXForm:$dst), (STXVD2X $rS, ForceXForm:$dst)>;
 def : Pat<(v4i32 (PPCld_vec_be ForceXForm:$src)), (LXVW4X ForceXForm:$src)>;
 def : Pat<(PPCst_vec_be v4i32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>;
 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
           (f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
 

llvm/test/CodeGen/PowerPC/vec_extract_p9.ll

 
 define double @test10(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LE-LABEL: test10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
 ; CHECK-LE-NEXT:    lxvx 36, 0, 3
 ; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
-; CHECK-LE-NEXT:    lfs 1, .LCPI9_1@toc@l(3)
-; CHECK-LE-NEXT:    vperm 2, 2, 3, 4
-; CHECK-LE-NEXT:    xxswapd 0, 34
-; CHECK-LE-NEXT:    xsadddp 1, 0, 1
+; CHECK-LE-NEXT:    lfs 0, .LCPI9_1@toc@l(3)
+; CHECK-LE-NEXT:    vperm 2, 3, 2, 4
+; CHECK-LE-NEXT:    xsadddp 1, 34, 0
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test10:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-BE-NEXT:    vmrghw 3, 3, 2
 ; CHECK-BE-NEXT:    lfs 0, .LCPI9_0@toc@l(3)
 ; CHECK-BE-NEXT:    vmrglw 2, 3, 2