[PowerPC] Enable safe for 32bit vins* P10 instructions

[ZarkoCA]

Summary

Correctly emit vinsinstructions that are safe in 32bit mode.

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10344

It would seem that all we need to change this condition and the one below to not emit PPCISD::VECINSERT for 64-bit element widths (v2i64, v2f64). Why do we need to disable this lowering on 32-bit targets altogether?

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10344

It looks like all of the pattern matches for VINS* in PPCInstrPrefix.td hardcode i64:
eg:

  def : Pat<(v16i8 (PPCvecinsertelt v16i8:$vDi, i32:$rA, i64:$rB)),
            (VINSBLX $vDi, InsertEltShift.Sub32Left0, $rA)>;
...
 foreach i = [0, 1] in
    def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, (i64 i))),
              (VINSD $vDi, !mul(i, 8), $rA)>;
}

So we can't emit the VECINSERT safely in 32bit mode due to this.

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10344

Sure, so those won't match. You might be able to change i64 to iPTR (I'm not sure about that) or provide patterns with i32 instead of i64.

[ZarkoCA]

• Enable safe for 32bit vins p10 instructions

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10344

Thanks for the suggestion and help. It's much better to emit these when we can in 32bit mode.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2758 ↗

(On Diff #343455)

I preferred to split the 32/64bit implementations mainly to keep 64bit as is. I noticed that there were no other predicate definitions in this file and they can be moved if that's preferred.

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1238

I don't really understand how we are custom lowering this on 32-bit targets now since you've added this. Where are the PPC-specific insert nodes coming from?

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2758 ↗

(On Diff #343455)

This is fine.

2771 ↗

(On Diff #343455)

Nit: line too long (here and elsewhere).

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1238

We don't need this now, I don't think. Forgot to remove it in the previous diff.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2758 ↗

(On Diff #343455)

Thanks.

2771 ↗

(On Diff #343455)

I noticed that but also there are several lines in IsISA3_1, HasVSX, IsLittleEndian and IsISA3_1, HasVSX, IsBigEndian, IsPPC64 that were too long as well. Thought it may be ok but I fixed it now for this case.

[ZarkoCA]

• Removing unnecessary isPPC64 check
• fix formatting

[nemanjai]

LGTM other than the nit that can be addressed on the commit.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

2769–2770 ↗

(On Diff #343684)

The operand should be lined up with the first operand of the node it belongs to:

def : Pat<(v4f32 (PPCvecinsertelt v4f32:$vDi, (f32 (load iaddr:$rA)),
                                  i32:$rB)),

Similarly on other similar lines.

2771 ↗

(On Diff #343455)

We haven't done super well with keeping the lines in target description files to 80 lines, but we should still try to do so on new code.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasP9Altivec()) {
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8,  Legal);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
       setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
     }
 
-    if (Subtarget.isISA3_1())
+    if (Subtarget.isISA3_1() && Subtarget.isPPC64())
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
   }
 
   if (Subtarget.pairedVectorMemops()) {
     addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
     setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
     setOperationAction(ISD::STORE, MVT::v256i1, Custom);
   }
SDValue PPCTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
   SDLoc dl(Op);
   SDValue V1 = Op.getOperand(0);
   SDValue V2 = Op.getOperand(1);
   SDValue V3 = Op.getOperand(2);
 
   if (VT == MVT::v2f64 && C)
     return Op;
 
-  if (Subtarget.isISA3_1()) {
+  if (Subtarget.isISA3_1() && Subtarget.isPPC64()) {
     // On P10, we have legal lowering for constant and variable indices for
     // integer vectors.
     if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
         VT == MVT::v2i64)
       return DAG.getNode(PPCISD::VECINSERT, dl, VT, V1, V2, V3);
     // For f32 and f64 vectors, we have legal lowering for variable indices.
     // For f32 we also have legal lowering when the element is loaded from
     // memory.
     if (VT == MVT::v4f32 || VT == MVT::v2f64) {
       if (!C || (VT == MVT::v4f32 && dyn_cast<LoadSDNode>(V2)))
         return DAG.getNode(PPCISD::VECINSERT, dl, VT, V1, V2, V3);

llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P10
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P10
 
 ; Byte indexed
 
 define <16 x i8> @testByte(<16 x i8> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testByte:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    clrldi 4, 4, 60
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stbx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testByte:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 6, 28
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stbx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testByte:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    vinsblx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testByte:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    addi 5, 1, -16
+; CHECK-32-P10-NEXT:    clrlwi 3, 6, 28
+; CHECK-32-P10-NEXT:    stxv 34, -16(1)
+; CHECK-32-P10-NEXT:    stbx 4, 5, 3
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %conv = trunc i64 %b to i8
   %vecins = insertelement <16 x i8> %a, i8 %conv, i64 %idx
   ret <16 x i8> %vecins
 }
 
 ; Halfword indexed
 

 ; CHECK-32-LABEL: testHalf:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 6, 1, 28, 30
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    sthx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testHalf:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    slwi 4, 4, 1
+; CHECK-64-P10-NEXT:    vinshlx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testHalf:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    addi 5, 1, -16
+; CHECK-32-P10-NEXT:    rlwinm 3, 6, 1, 28, 30
+; CHECK-32-P10-NEXT:    stxv 34, -16(1)
+; CHECK-32-P10-NEXT:    sthx 4, 5, 3
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %conv = trunc i64 %b to i16
   %vecins = insertelement <8 x i16> %a, i16 %conv, i64 %idx
   ret <8 x i16> %vecins
 }
 
 ; Word indexed
 

 ; CHECK-32-LABEL: testWord:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 6, 2, 28, 29
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stwx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testWord:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    slwi 4, 4, 2
+; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testWord:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    addi 5, 1, -16
+; CHECK-32-P10-NEXT:    rlwinm 3, 6, 2, 28, 29
+; CHECK-32-P10-NEXT:    stxv 34, -16(1)
+; CHECK-32-P10-NEXT:    stwx 4, 5, 3
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %conv = trunc i64 %b to i32
   %vecins = insertelement <4 x i32> %a, i32 %conv, i64 %idx
   ret <4 x i32> %vecins
 }
 
 ; Word immediate
 
 define <4 x i32> @testWordImm(<4 x i32> %a, i64 %b) {
 ; CHECK-64-LABEL: testWordImm:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    mtfprwz 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 4
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 12
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testWordImm:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    mtfprwz 0, 4
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 4
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 12
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testWordImm:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    vinsw 2, 3, 4
+; CHECK-64-P10-NEXT:    vinsw 2, 3, 12
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testWordImm:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    mtfprwz 0, 4
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 4
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 12
+; CHECK-32-P10-NEXT:    blr
 entry:
   %conv = trunc i64 %b to i32
   %vecins = insertelement <4 x i32> %a, i32 %conv, i32 1
   %vecins2 = insertelement <4 x i32> %vecins, i32 %conv, i32 3
   ret <4 x i32> %vecins2
 }
 
 ; Doubleword indexed

 ; CHECK-32-NEXT:    addi 3, 5, 1
 ; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    lxv 0, -32(1)
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
 ; CHECK-32-NEXT:    stxv 0, -16(1)
 ; CHECK-32-NEXT:    stwx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDoubleword:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
+; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDoubleword:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    add 5, 6, 6
+; CHECK-32-P10-NEXT:    addi 7, 1, -32
+; CHECK-32-P10-NEXT:    stxv 34, -32(1)
+; CHECK-32-P10-NEXT:    rlwinm 6, 5, 2, 28, 29
+; CHECK-32-P10-NEXT:    stwx 3, 7, 6
+; CHECK-32-P10-NEXT:    addi 3, 5, 1
+; CHECK-32-P10-NEXT:    addi 5, 1, -16
+; CHECK-32-P10-NEXT:    lxv 0, -32(1)
+; CHECK-32-P10-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-P10-NEXT:    stxv 0, -16(1)
+; CHECK-32-P10-NEXT:    stwx 4, 5, 3
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <2 x i64> %a, i64 %b, i64 %idx
   ret <2 x i64> %vecins
 }
 
 ; Doubleword immediate
 
 define <2 x i64> @testDoublewordImm(<2 x i64> %a, i64 %b) {
 ; CHECK-64-LABEL: testDoublewordImm:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    mtfprd 0, 3
 ; CHECK-64-NEXT:    xxmrghd 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDoublewordImm:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    mtfprwz 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    mtfprwz 0, 4
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 12
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDoublewordImm:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    vinsd 2, 3, 8
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDoublewordImm:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    mtfprwz 0, 3
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 8
+; CHECK-32-P10-NEXT:    mtfprwz 0, 4
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 12
+; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <2 x i64> %a, i64 %b, i32 1
   ret <2 x i64> %vecins
 }
 
 define <2 x i64> @testDoublewordImm2(<2 x i64> %a, i64 %b) {
 ; CHECK-64-LABEL: testDoublewordImm2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    mtfprd 0, 3
 ; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDoublewordImm2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    mtfprwz 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-NEXT:    mtfprwz 0, 4
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 4
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDoublewordImm2:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    vinsd 2, 3, 0
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDoublewordImm2:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    mtfprwz 0, 3
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 0
+; CHECK-32-P10-NEXT:    mtfprwz 0, 4
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 4
+; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <2 x i64> %a, i64 %b, i32 0
   ret <2 x i64> %vecins
 }
 
 ; Float indexed
 
 define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {

 ; CHECK-32-LABEL: testFloat1:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    rlwinm 3, 4, 2, 28, 29
 ; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stfsx 1, 4, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testFloat1:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
+; CHECK-64-P10-NEXT:    extsw 3, 4
+; CHECK-64-P10-NEXT:    slwi 3, 3, 2
+; CHECK-64-P10-NEXT:    xxsldwi 0, 0, 0, 3
+; CHECK-64-P10-NEXT:    mffprwz 4, 0
+; CHECK-64-P10-NEXT:    vinswlx 2, 3, 4
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testFloat1:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    rlwinm 3, 4, 2, 28, 29
+; CHECK-32-P10-NEXT:    addi 4, 1, -16
+; CHECK-32-P10-NEXT:    stxv 34, -16(1)
+; CHECK-32-P10-NEXT:    stfsx 1, 4, 3
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 %idx1
   ret <4 x float> %vecins
 }
 
 define <4 x float> @testFloat2(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testFloat2:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-DAG:     lwz 6, 0(3)
-; CHECK-64-DAG:     rlwinm 4, 4, 2, 28, 29
-; CHECK-64-DAG:     addi 7, 1, -32
-; CHECK-64-DAG:     stxv 34, -32(1)
-; CHECK-64-DAG:     stwx 6, 7, 4
-; CHECK-64-DAG:     rlwinm 4, 5, 2, 28, 29
-; CHECK-64-DAG:     addi 5, 1, -16
-; CHECK-64-DAG:     lxv 0, -32(1)
-; CHECK-64-DAG:     lwz 3, 1(3)
-; CHECK-64-DAG:     stxv 0, -16(1)
-; CHECK-64-DAG:     stwx 3, 5, 4
-; CHECK-64-DAG:     lxv 34, -16(1)
+; CHECK-64-NEXT:    lwz 6, 0(3)
+; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 7, 1, -32
+; CHECK-64-NEXT:    stxv 34, -32(1)
+; CHECK-64-NEXT:    stwx 6, 7, 4
+; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
+; CHECK-64-NEXT:    addi 5, 1, -16
+; CHECK-64-NEXT:    lxv 0, -32(1)
+; CHECK-64-NEXT:    lwz 3, 1(3)
+; CHECK-64-NEXT:    stxv 0, -16(1)
+; CHECK-64-NEXT:    stwx 3, 5, 4
+; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloat2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lwz 6, 0(3)
 ; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
 ; CHECK-32-NEXT:    stwx 6, 7, 4
 ; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    lxv 0, -32(1)
 ; CHECK-32-NEXT:    lwz 3, 1(3)
 ; CHECK-32-NEXT:    stxv 0, -16(1)
 ; CHECK-32-NEXT:    stwx 3, 4, 5
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testFloat2:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    lwz 6, 0(3)
+; CHECK-64-P10-NEXT:    extsw 4, 4
+; CHECK-64-P10-NEXT:    lwz 3, 1(3)
+; CHECK-64-P10-NEXT:    slwi 4, 4, 2
+; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
+; CHECK-64-P10-NEXT:    extsw 4, 5
+; CHECK-64-P10-NEXT:    slwi 4, 4, 2
+; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testFloat2:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lwz 6, 0(3)
+; CHECK-32-P10-NEXT:    addi 7, 1, -32
+; CHECK-32-P10-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-32-P10-NEXT:    stxv 34, -32(1)
+; CHECK-32-P10-NEXT:    rlwinm 5, 5, 2, 28, 29
+; CHECK-32-P10-NEXT:    stwx 6, 7, 4
+; CHECK-32-P10-NEXT:    addi 4, 1, -16
+; CHECK-32-P10-NEXT:    lxv 0, -32(1)
+; CHECK-32-P10-NEXT:    lwz 3, 1(3)
+; CHECK-32-P10-NEXT:    stxv 0, -16(1)
+; CHECK-32-P10-NEXT:    stwx 3, 4, 5
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %0 = bitcast i8* %b to float*
   %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
   %1 = bitcast i8* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
   %3 = load float, float* %1, align 4
   %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
   ret <4 x float> %vecins2
 }
 
 define <4 x float> @testFloat3(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testFloat3:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-DAG:     lis 6, 1
-; CHECK-64-DAG:     rlwinm 4, 4, 2, 28, 29
-; CHECK-64-DAG:     addi 7, 1, -32
-; CHECK-64-DAG:     lwzx 6, 3, 6
-; CHECK-64-DAG:     stxv 34, -32(1)
-; CHECK-64-DAG:     stwx 6, 7, 4
-; CHECK-64-DAG:     li 4, 1
-; CHECK-64-DAG:     lxv 0, -32(1)
-; CHECK-64-DAG:     rldic 4, 4, 36, 27
-; CHECK-64-DAG:     lwzx 3, 3, 4
-; CHECK-64-DAG:     rlwinm 4, 5, 2, 28, 29
-; CHECK-64-DAG:     addi 5, 1, -16
-; CHECK-64-DAG:     stxv 0, -16(1)
-; CHECK-64-DAG:     stwx 3, 5, 4
-; CHECK-64-DAG:     lxv 34, -16(1)
+; CHECK-64-NEXT:    lis 6, 1
+; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 7, 1, -32
+; CHECK-64-NEXT:    lwzx 6, 3, 6
+; CHECK-64-NEXT:    stxv 34, -32(1)
+; CHECK-64-NEXT:    stwx 6, 7, 4
+; CHECK-64-NEXT:    li 4, 1
+; CHECK-64-NEXT:    lxv 0, -32(1)
+; CHECK-64-NEXT:    rldic 4, 4, 36, 27
+; CHECK-64-NEXT:    lwzx 3, 3, 4
+; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
+; CHECK-64-NEXT:    addi 5, 1, -16
+; CHECK-64-NEXT:    stxv 0, -16(1)
+; CHECK-64-NEXT:    stwx 3, 5, 4
+; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloat3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lis 6, 1
 ; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
 ; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
 ; CHECK-32-NEXT:    lwzx 6, 3, 6
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    stwx 6, 7, 4
 ; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    lxv 0, -32(1)
 ; CHECK-32-NEXT:    lwz 3, 0(3)
 ; CHECK-32-NEXT:    stxv 0, -16(1)
 ; CHECK-32-NEXT:    stwx 3, 4, 5
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testFloat3:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    plwz 6, 65536(3), 0
+; CHECK-64-P10-NEXT:    extsw 4, 4
+; CHECK-64-P10-NEXT:    slwi 4, 4, 2
+; CHECK-64-P10-NEXT:    vinswlx 2, 4, 6
+; CHECK-64-P10-NEXT:    li 4, 1
+; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
+; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
+; CHECK-64-P10-NEXT:    extsw 4, 5
+; CHECK-64-P10-NEXT:    slwi 4, 4, 2
+; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testFloat3:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lis 6, 1
+; CHECK-32-P10-NEXT:    addi 7, 1, -32
+; CHECK-32-P10-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-32-P10-NEXT:    rlwinm 5, 5, 2, 28, 29
+; CHECK-32-P10-NEXT:    lwzx 6, 3, 6
+; CHECK-32-P10-NEXT:    stxv 34, -32(1)
+; CHECK-32-P10-NEXT:    stwx 6, 7, 4
+; CHECK-32-P10-NEXT:    addi 4, 1, -16
+; CHECK-32-P10-NEXT:    lxv 0, -32(1)
+; CHECK-32-P10-NEXT:    lwz 3, 0(3)
+; CHECK-32-P10-NEXT:    stxv 0, -16(1)
+; CHECK-32-P10-NEXT:    stwx 3, 4, 5
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
   %0 = bitcast i8* %add.ptr to float*
   %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
   %1 = bitcast i8* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 %idx1
   %3 = load float, float* %1, align 4

 ;
 ; CHECK-32-LABEL: testFloatImm1:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    xscvdpspn 0, 1
 ; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testFloatImm1:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
+; CHECK-64-P10-NEXT:    xxsldwi 0, 0, 0, 3
+; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 0
+; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 8
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testFloatImm1:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    xscvdpspn 0, 1
+; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 0
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 8
+; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 0
   %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2
   ret <4 x float> %vecins1
 }
 
 define <4 x float> @testFloatImm2(<4 x float> %a, i32* %b) {
 ; CHECK-64-LABEL: testFloatImm2:

 ; CHECK-32-NEXT:    xscvdpspn 0, 0
 ; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-NEXT:    lfs 0, 4(3)
 ; CHECK-32-NEXT:    xscvdpspn 0, 0
 ; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testFloatImm2:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    lwz 4, 0(3)
+; CHECK-64-P10-NEXT:    lwz 3, 4(3)
+; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
+; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testFloatImm2:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lfs 0, 0(3)
+; CHECK-32-P10-NEXT:    xscvdpspn 0, 0
+; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 0
+; CHECK-32-P10-NEXT:    lfs 0, 4(3)
+; CHECK-32-P10-NEXT:    xscvdpspn 0, 0
+; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 8
+; CHECK-32-P10-NEXT:    blr
 entry:
   %0 = bitcast i32* %b to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 1
   %1 = bitcast i32* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 0
   %3 = load float, float* %1, align 4
   %vecins2 = insertelement <4 x float> %vecins, float %3, i32 2

 ; CHECK-32-NEXT:    xscvdpspn 0, 0
 ; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-NEXT:    lfs 0, 0(3)
 ; CHECK-32-NEXT:    xscvdpspn 0, 0
 ; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testFloatImm3:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    plwz 4, 262144(3), 0
+; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
+; CHECK-64-P10-NEXT:    li 4, 1
+; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
+; CHECK-64-P10-NEXT:    lwzx 3, 3, 4
+; CHECK-64-P10-NEXT:    vinsw 2, 3, 8
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testFloatImm3:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lis 4, 4
+; CHECK-32-P10-NEXT:    lfsx 0, 3, 4
+; CHECK-32-P10-NEXT:    xscvdpspn 0, 0
+; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 0
+; CHECK-32-P10-NEXT:    lfs 0, 0(3)
+; CHECK-32-P10-NEXT:    xscvdpspn 0, 0
+; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
+; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 8
+; CHECK-32-P10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
   %0 = bitcast i32* %add.ptr to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 68719476736
   %1 = bitcast i32* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 0
   %3 = load float, float* %1, align 4

 ; CHECK-32-LABEL: testDouble1:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 5, 3, 28, 28
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stfdx 1, 4, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDouble1:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    extsw 4, 4
+; CHECK-64-P10-NEXT:    mffprd 3, 1
+; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
+; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDouble1:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    addi 4, 1, -16
+; CHECK-32-P10-NEXT:    rlwinm 3, 5, 3, 28, 28
+; CHECK-32-P10-NEXT:    stxv 34, -16(1)
+; CHECK-32-P10-NEXT:    stfdx 1, 4, 3
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <2 x double> %a, double %b, i32 %idx1
   ret <2 x double> %vecins
 }
 
 define <2 x double> @testDouble2(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testDouble2:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-DAG:     ld 6, 0(3)
-; CHECK-64-DAG:     rlwinm 4, 4, 3, 28, 28
-; CHECK-64-DAG:     addi 7, 1, -32
-; CHECK-64-DAG:     stxv 34, -32(1)
-; CHECK-64-DAG:     stdx 6, 7, 4
-; CHECK-64-DAG:     li 4, 1
-; CHECK-64-DAG:     lxv 0, -32(1)
-; CHECK-64-DAG:     ldx 3, 3, 4
-; CHECK-64-DAG:     rlwinm 4, 5, 3, 28, 28
-; CHECK-64-DAG:     addi 5, 1, -16
-; CHECK-64-DAG:     stxv 0, -16(1)
-; CHECK-64-DAG:     stdx 3, 5, 4
-; CHECK-64-DAG:     lxv 34, -16(1)
+; CHECK-64-NEXT:    ld 6, 0(3)
+; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-64-NEXT:    addi 7, 1, -32
+; CHECK-64-NEXT:    stxv 34, -32(1)
+; CHECK-64-NEXT:    stdx 6, 7, 4
+; CHECK-64-NEXT:    li 4, 1
+; CHECK-64-NEXT:    lxv 0, -32(1)
+; CHECK-64-NEXT:    ldx 3, 3, 4
+; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
+; CHECK-64-NEXT:    addi 5, 1, -16
+; CHECK-64-NEXT:    stxv 0, -16(1)
+; CHECK-64-NEXT:    stdx 3, 5, 4
+; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDouble2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lfd 0, 0(3)
 ; CHECK-32-NEXT:    addi 6, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-NEXT:    stfdx 0, 6, 4
 ; CHECK-32-NEXT:    lxv 0, -32(1)
 ; CHECK-32-NEXT:    lfd 1, 1(3)
 ; CHECK-32-NEXT:    addi 3, 1, -16
 ; CHECK-32-NEXT:    stxv 0, -16(1)
 ; CHECK-32-NEXT:    stfdx 1, 3, 5
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDouble2:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    ld 6, 0(3)
+; CHECK-64-P10-NEXT:    extsw 4, 4
+; CHECK-64-P10-NEXT:    pld 3, 1(3), 0
+; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
+; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
+; CHECK-64-P10-NEXT:    extsw 4, 5
+; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
+; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDouble2:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lfd 0, 0(3)
+; CHECK-32-P10-NEXT:    addi 6, 1, -32
+; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-32-P10-NEXT:    stxv 34, -32(1)
+; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
+; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
+; CHECK-32-P10-NEXT:    lxv 0, -32(1)
+; CHECK-32-P10-NEXT:    lfd 1, 1(3)
+; CHECK-32-P10-NEXT:    addi 3, 1, -16
+; CHECK-32-P10-NEXT:    stxv 0, -16(1)
+; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %0 = bitcast i8* %b to double*
   %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 1
   %1 = bitcast i8* %add.ptr1 to double*
   %2 = load double, double* %0, align 8
   %vecins = insertelement <2 x double> %a, double %2, i32 %idx1
   %3 = load double, double* %1, align 8
   %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
   ret <2 x double> %vecins2
 }
 
 define <2 x double> @testDouble3(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testDouble3:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-DAG:     lis 6, 1
-; CHECK-64-DAG:     rlwinm 4, 4, 3, 28, 28
-; CHECK-64-DAG:     addi 7, 1, -32
-; CHECK-64-DAG:     ldx 6, 3, 6
-; CHECK-64-DAG:     stxv 34, -32(1)
-; CHECK-64-DAG:     stdx 6, 7, 4
-; CHECK-64-DAG:     li 4, 1
-; CHECK-64-DAG:     lxv 0, -32(1)
-; CHECK-64-DAG:     rldic 4, 4, 36, 27
-; CHECK-64-DAG:     ldx 3, 3, 4
-; CHECK-64-DAG:     rlwinm 4, 5, 3, 28, 28
-; CHECK-64-DAG:     addi 5, 1, -16
-; CHECK-64-DAG:     stxv 0, -16(1)
-; CHECK-64-DAG:     stdx 3, 5, 4
-; CHECK-64-DAG:     lxv 34, -16(1)
+; CHECK-64-NEXT:    lis 6, 1
+; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-64-NEXT:    addi 7, 1, -32
+; CHECK-64-NEXT:    ldx 6, 3, 6
+; CHECK-64-NEXT:    stxv 34, -32(1)
+; CHECK-64-NEXT:    stdx 6, 7, 4
+; CHECK-64-NEXT:    li 4, 1
+; CHECK-64-NEXT:    lxv 0, -32(1)
+; CHECK-64-NEXT:    rldic 4, 4, 36, 27
+; CHECK-64-NEXT:    ldx 3, 3, 4
+; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
+; CHECK-64-NEXT:    addi 5, 1, -16
+; CHECK-64-NEXT:    stxv 0, -16(1)
+; CHECK-64-NEXT:    stdx 3, 5, 4
+; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDouble3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lis 6, 1
 ; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
 ; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-NEXT:    lfdx 0, 3, 6
 ; CHECK-32-NEXT:    addi 6, 1, -32
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    stfdx 0, 6, 4
 ; CHECK-32-NEXT:    lxv 0, -32(1)
 ; CHECK-32-NEXT:    lfd 1, 0(3)
 ; CHECK-32-NEXT:    addi 3, 1, -16
 ; CHECK-32-NEXT:    stxv 0, -16(1)
 ; CHECK-32-NEXT:    stfdx 1, 3, 5
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDouble3:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    pld 6, 65536(3), 0
+; CHECK-64-P10-NEXT:    extsw 4, 4
+; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
+; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 6
+; CHECK-64-P10-NEXT:    li 4, 1
+; CHECK-64-P10-NEXT:    rldic 4, 4, 36, 27
+; CHECK-64-P10-NEXT:    ldx 3, 3, 4
+; CHECK-64-P10-NEXT:    extsw 4, 5
+; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
+; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDouble3:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lis 6, 1
+; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
+; CHECK-32-P10-NEXT:    lfdx 0, 3, 6
+; CHECK-32-P10-NEXT:    addi 6, 1, -32
+; CHECK-32-P10-NEXT:    stxv 34, -32(1)
+; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
+; CHECK-32-P10-NEXT:    lxv 0, -32(1)
+; CHECK-32-P10-NEXT:    lfd 1, 0(3)
+; CHECK-32-P10-NEXT:    addi 3, 1, -16
+; CHECK-32-P10-NEXT:    stxv 0, -16(1)
+; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
+; CHECK-32-P10-NEXT:    lxv 34, -16(1)
+; CHECK-32-P10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %b, i64 65536
   %0 = bitcast i8* %add.ptr to double*
   %add.ptr1 = getelementptr inbounds i8, i8* %b, i64 68719476736
   %1 = bitcast i8* %add.ptr1 to double*
   %2 = load double, double* %0, align 8
   %vecins = insertelement <2 x double> %a, double %2, i32 %idx1
   %3 = load double, double* %1, align 8

 ; CHECK-64-NEXT:    xxpermdi 34, 1, 34, 1
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDoubleImm1:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; CHECK-32-NEXT:    xxpermdi 34, 1, 34, 1
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDoubleImm1:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    # kill: def $f1 killed $f1 def $vsl1
+; CHECK-64-P10-NEXT:    xxpermdi 34, 1, 34, 1
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDoubleImm1:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    # kill: def $f1 killed $f1 def $vsl1
+; CHECK-32-P10-NEXT:    xxpermdi 34, 1, 34, 1
+; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <2 x double> %a, double %b, i32 0
   ret <2 x double> %vecins
 }
 
 define <2 x double> @testDoubleImm2(<2 x double> %a, i32* %b) {
 ; CHECK-64-LABEL: testDoubleImm2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lfd 0, 0(3)
 ; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDoubleImm2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lfd 0, 0(3)
 ; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDoubleImm2:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    lfd 0, 0(3)
+; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDoubleImm2:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lfd 0, 0(3)
+; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
+; CHECK-32-P10-NEXT:    blr
 entry:
   %0 = bitcast i32* %b to double*
   %1 = load double, double* %0, align 8
   %vecins = insertelement <2 x double> %a, double %1, i32 0
   ret <2 x double> %vecins
 }
 
 define <2 x double> @testDoubleImm3(<2 x double> %a, i32* %b) {
 ; CHECK-64-LABEL: testDoubleImm3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lfd 0, 4(3)
 ; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDoubleImm3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lfd 0, 4(3)
 ; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDoubleImm3:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    lfd 0, 4(3)
+; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDoubleImm3:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lfd 0, 4(3)
+; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
+; CHECK-32-P10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 1
   %0 = bitcast i32* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %vecins = insertelement <2 x double> %a, double %1, i32 0
   ret <2 x double> %vecins
 }
 
 define <2 x double> @testDoubleImm4(<2 x double> %a, i32* %b) {
 ; CHECK-64-LABEL: testDoubleImm4:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 4, 4
 ; CHECK-64-NEXT:    lfdx 0, 3, 4
 ; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDoubleImm4:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lis 4, 4
 ; CHECK-32-NEXT:    lfdx 0, 3, 4
 ; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDoubleImm4:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    lis 4, 4
+; CHECK-64-P10-NEXT:    lfdx 0, 3, 4
+; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDoubleImm4:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lis 4, 4
+; CHECK-32-P10-NEXT:    lfdx 0, 3, 4
+; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
+; CHECK-32-P10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
   %0 = bitcast i32* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %vecins = insertelement <2 x double> %a, double %1, i32 0
   ret <2 x double> %vecins
 }
 
 define <2 x double> @testDoubleImm5(<2 x double> %a, i32* %b) {
 ; CHECK-64-LABEL: testDoubleImm5:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    rldic 4, 4, 38, 25
 ; CHECK-64-NEXT:    lfdx 0, 3, 4
 ; CHECK-64-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDoubleImm5:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lfd 0, 0(3)
 ; CHECK-32-NEXT:    xxpermdi 34, 0, 34, 1
 ; CHECK-32-NEXT:    blr
+;
+; CHECK-64-P10-LABEL: testDoubleImm5:
+; CHECK-64-P10:       # %bb.0: # %entry
+; CHECK-64-P10-NEXT:    li 4, 1
+; CHECK-64-P10-NEXT:    rldic 4, 4, 38, 25
+; CHECK-64-P10-NEXT:    lfdx 0, 3, 4
+; CHECK-64-P10-NEXT:    xxpermdi 34, 0, 34, 1
+; CHECK-64-P10-NEXT:    blr
+;
+; CHECK-32-P10-LABEL: testDoubleImm5:
+; CHECK-32-P10:       # %bb.0: # %entry
+; CHECK-32-P10-NEXT:    lfd 0, 0(3)
+; CHECK-32-P10-NEXT:    xxpermdi 34, 0, 34, 1
+; CHECK-32-P10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 68719476736
   %0 = bitcast i32* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %vecins = insertelement <2 x double> %a, double %1, i32 0
   ret <2 x double> %vecins
 }