[AMDGPU] Serialize MFInfo::ScavengeFI

[sebastian-ne]

Summary

Serialize ScavengeFI from SIMachineFunctionInfo into yaml.

ScavengeFI is not used outside of the PrologEpilogInserter,
so this shouldn't change anything.

[arsenm]

The point that this is only used in PEI is interesting. That almost suggests it doesn't belong here at all but I'm not sure where else you would track it.

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir

352

This is rougher than I would hope. This isn't a simple integer, it's a frame index. I would hope there would be some syntax to indicate this, and some validation that it is a valid frame object. There's no frame info here at all. e.g. I would expect a string here that looks like a frame index as it appears in an operand

[sebastian-ne]

This is rougher than I would hope. This isn't a simple integer, it's a frame index. I would hope there would be some syntax to indicate this, and some validation that it is a valid frame object. There's no frame info here at all. e.g. I would expect a string here that looks like a frame index as it appears in an operand

Ah, I was already wondering why it felt so easy.
Now it uses the same form as in operands. The disadvantage is that a MachineFrameInfo is needed for serialization and deserialization.

[arsenm]

llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir

13 ↗

(On Diff #342012)

Can you also add a test where the stack reference does parse correctly, but there is no MachineFrameInfo?

13 ↗

(On Diff #342012)

Plus when there is frame info, but an out of bounds index

[sebastian-ne]

Add two tests to check invalid frame indices.

[arsenm]

llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir

4 ↗

(On Diff #342336)

This should emit a proper error, not just assert.

llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir

4 ↗

(On Diff #342336)

Ditto

[sebastian-ne]

Return error instead of failing assert for non-existing frame index.

I’m not quite sure how to create the SMDiagnostic. The resulting error message looks fine, so I hope this is ok.

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
   unsigned Occupancy = 0;
 
   StringValue ScratchRSrcReg = "$private_rsrc_reg";
   StringValue FrameOffsetReg = "$fp_reg";
   StringValue StackPtrOffsetReg = "$sp_reg";
 
   Optional<SIArgumentInfo> ArgInfo;
   SIMode Mode;
+  Optional<int> ScavengeFI;
 
   SIMachineFunctionInfo() = default;
   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
                         const TargetRegisterInfo &TRI);
 
   void mappingImpl(yaml::IO &YamlIO) override;
   ~SIMachineFunctionInfo() = default;
 };
YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
                        StringValue("$fp_reg"));
     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
                        StringValue("$sp_reg"));
     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
     YamlIO.mapOptional("highBitsOf32BitAddress",
                        MFI.HighBitsOf32BitAddress, 0u);
     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
+    YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
   }
 };
 
 } // end namespace yaml
 
 /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
 /// tells the hardware which interpolation parameters to load.
 class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
public:
   bool haveFreeLanesForSGPRSpill(const MachineFunction &MF,
                                  unsigned NumLane) const;
   bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
   bool reserveVGPRforSGPRSpills(MachineFunction &MF);
   bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR);
   void removeDeadFrameIndices(MachineFrameInfo &MFI);
 
   int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI);
+  Optional<int> getOptionalScavengeFI() const { return ScavengeFI; }
 
   bool hasCalculatedTID() const { return TIDReg != 0; };
   Register getTIDReg() const { return TIDReg; };
   void setTIDReg(Register Reg) { TIDReg = Reg; }
 
   unsigned getBytesInStackArgArea() const {
     return BytesInStackArgArea;
   }

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

: ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
       MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
       HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
       Occupancy(MFI.getOccupancy()),
       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
-      ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
-}
+      ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()),
+      ScavengeFI(MFI.getOptionalScavengeFI()) {}
 
 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
 }
 
 bool SIMachineFunctionInfo::initializeBaseYamlFields(
   const yaml::SIMachineFunctionInfo &YamlMFI) {
   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
   MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
   LDSSize = YamlMFI.LDSSize;
   DynLDSAlign = YamlMFI.DynLDSAlign;
   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
   Occupancy = YamlMFI.Occupancy;
   IsEntryFunction = YamlMFI.IsEntryFunction;
   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
   MemoryBound = YamlMFI.MemoryBound;
   WaveLimiter = YamlMFI.WaveLimiter;
   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;
+  ScavengeFI = YamlMFI.ScavengeFI;
   return false;
 }
 
 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
 bool SIMachineFunctionInfo::removeVGPRForSGPRSpill(Register ReservedVGPR,
                                                    MachineFunction &MF) {
   for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
     if (i->VGPR == ReservedVGPR) {

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll

+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=AFTER-PEI %s
+
+; Test that the ScavengeFI is serialized in the SIMachineFunctionInfo.
+
+; AFTER-PEI-LABEL: {{^}}name: scavenge_fi
+; AFTER-PEI: machineFunctionInfo:
+; AFTER-PEI-NEXT: explicitKernArgSize: 12
+; AFTER-PEI-NEXT: maxKernArgAlign: 8
+; AFTER-PEI-NEXT: ldsSize:         0
+; AFTER-PEI-NEXT: dynLDSAlign:     1
+; AFTER-PEI-NEXT: isEntryFunction: true
+; AFTER-PEI-NEXT: noSignedZerosFPMath: false
+; AFTER-PEI-NEXT: memoryBound:     false
+; AFTER-PEI-NEXT: waveLimiter:     false
+; AFTER-PEI-NEXT: hasSpilledSGPRs: true
+; AFTER-PEI-NEXT: hasSpilledVGPRs: false
+; AFTER-PEI-NEXT: scratchRSrcReg:  '$sgpr68_sgpr69_sgpr70_sgpr71'
+; AFTER-PEI-NEXT: frameOffsetReg:  '$fp_reg'
+; AFTER-PEI-NEXT: stackPtrOffsetReg: '$sgpr32'
+; AFTER-PEI-NEXT: argumentInfo:
+; AFTER-PEI-NEXT:   privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
+; AFTER-PEI-NEXT:   kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
+; AFTER-PEI-NEXT:   workGroupIDX:    { reg: '$sgpr6' }
+; AFTER-PEI-NEXT:   privateSegmentWaveByteOffset: { reg: '$sgpr7' }
+; AFTER-PEI-NEXT:   workItemIDX:     { reg: '$vgpr0' }
+; AFTER-PEI-NEXT: mode:
+; AFTER-PEI-NEXT:   ieee:            true
+; AFTER-PEI-NEXT:   dx10-clamp:      true
+; AFTER-PEI-NEXT:   fp32-input-denormals: true
+; AFTER-PEI-NEXT:   fp32-output-denormals: true
+; AFTER-PEI-NEXT:   fp64-fp16-input-denormals: true
+; AFTER-PEI-NEXT:   fp64-fp16-output-denormals: true
+; AFTER-PEI-NEXT: highBitsOf32BitAddress: 0
+; AFTER-PEI-NEXT: occupancy: 5
+; AFTER-PEI-NEXT: scavengeFI: -1
+; AFTER-PEI-NEXT: body:
+define amdgpu_kernel void @scavenge_fi(i32 addrspace(1)* %out, i32 %in) #0 {
+  %wide.sgpr0 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
+  %wide.sgpr1 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
+  %wide.sgpr2 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
+  %wide.sgpr3 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
+
+  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr0) #0
+  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr1) #0
+  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr2) #0
+  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr3) #0
+  ret void
+}
+
+attributes #0 = { nounwind }

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir

 machineFunctionInfo:
   occupancy: 3
 
 body:             |
   bb.0:
     S_ENDPGM 0
 
 ...
+
+---
+# ALL-LABEL: name: scavenge_fi
+
+# FULL: scavengeFI: 5
+
+# SIMPLE: scavengeFI: 5
+name: scavenge_fi
+machineFunctionInfo:
+  scavengeFI: 5
+
+body:             |
+  bb.0:
+    S_ENDPGM 0
+
+...