Add a test, dest register could be v0.
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[RISCV][MC] Mask load should not have VMConstraint. ClosedPublic Authored by khchen on Apr 20 2021, 1:27 AM.
Details Summary Add a test, dest register could be v0.
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Event TimelineHerald added subscribers: vkmr, frasercrmck, luismarques and 23 others. · View Herald TranscriptApr 20 2021, 1:27 AM This revision is now accepted and ready to land.Apr 20 2021, 1:42 AM Closed by commit rGad0fe5db2fa0: [RISCV][MC] Mask load should not have VMConstraint. (authored by khchen). · Explain WhyApr 21 2021, 12:22 AM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 339121 llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/load.s
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