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[RISCV] Implement the pseudo compare builtin.
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Authored by HsiangKai on Tue, Apr 20, 12:39 AM.

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HsiangKai created this revision.Tue, Apr 20, 12:39 AM
HsiangKai requested review of this revision.Tue, Apr 20, 12:40 AM
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Thinking about this more, I'd like to consider doing this in the backend specifically for the compares for a few reasons.

-vmsgt(u).vv intrinsic already selects vmslt(u).vv with swapped operands in the backend. This was needed for SEW=64 on RV32.
-Inconsistent that some compare IR intrinsics accept vector or scalar second argument, but some only support scalar.
-We can probably generate better code for masked vmsge(u).vx if we defer expansion to post register allocation.
-Unifies the compare intrinsic implementation in the frontend.

I just posted https://reviews.llvm.org/D100889 which should allow the frontend to treat all comparisons the same way. It also avoids using the long expansion for vmsge.vx

I just posted https://reviews.llvm.org/D100889 which should allow the frontend to treat all comparisons the same way. It also avoids using the long expansion for vmsge.vx

I will refine the patch based on D100925.

Use new defined intrinsics.

Update test cases.

This revision is now accepted and ready to land.Fri, Apr 23, 3:11 PM
This revision was automatically updated to reflect the committed changes.