[RISCV][test] Add a new test of addition

[benshi001]

This test will show how

; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -1097
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret

are optimized to

; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 1500
; RV64I-NEXT: addiw a0, a0, 1499
; RV64I-NEXT: ret

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/add-imm.ll

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a0, a0, 1500
 ; RV64I-NEXT:    addi a0, a0, 1499
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 2999
   ret i32 %1
 }
 
+define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
+; RV32I-LABEL: add32_sext_accept:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 1500
+; RV32I-NEXT:    addi a0, a0, 1499
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add32_sext_accept:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, -1097
+; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    ret
+  %1 = add i32 %a, 2999
+  ret i32 %1
+}
+
 define i64 @add64_accept(i64 %a) nounwind {
 ; RV32I-LABEL: add64_accept:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, a0, 1500
 ; RV32I-NEXT:    addi a2, a2, 1499
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2